1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt5682.h -- RT5682/RT5658 ALSA SoC audio driver 4 * 5 * Copyright 2018 Realtek Microelectronics 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #ifndef __RT5682_H__ 10 #define __RT5682_H__ 11 12 #include <sound/rt5682.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/soundwire/sdw.h> 18 #include <linux/soundwire/sdw_type.h> 19 20 #define DEVICE_ID 0x6530 21 22 /* Info */ 23 #define RT5682_RESET 0x0000 24 #define RT5682_VERSION_ID 0x00fd 25 #define RT5682_VENDOR_ID 0x00fe 26 #define RT5682_DEVICE_ID 0x00ff 27 /* I/O - Output */ 28 #define RT5682_HP_CTRL_1 0x0002 29 #define RT5682_HP_CTRL_2 0x0003 30 #define RT5682_HPL_GAIN 0x0005 31 #define RT5682_HPR_GAIN 0x0006 32 33 #define RT5682_I2C_CTRL 0x0008 34 35 /* I/O - Input */ 36 #define RT5682_CBJ_BST_CTRL 0x000b 37 #define RT5682_CBJ_CTRL_1 0x0010 38 #define RT5682_CBJ_CTRL_2 0x0011 39 #define RT5682_CBJ_CTRL_3 0x0012 40 #define RT5682_CBJ_CTRL_4 0x0013 41 #define RT5682_CBJ_CTRL_5 0x0014 42 #define RT5682_CBJ_CTRL_6 0x0015 43 #define RT5682_CBJ_CTRL_7 0x0016 44 /* I/O - ADC/DAC/DMIC */ 45 #define RT5682_DAC1_DIG_VOL 0x0019 46 #define RT5682_STO1_ADC_DIG_VOL 0x001c 47 #define RT5682_STO1_ADC_BOOST 0x001f 48 #define RT5682_HP_IMP_GAIN_1 0x0022 49 #define RT5682_HP_IMP_GAIN_2 0x0023 50 /* Mixer - D-D */ 51 #define RT5682_SIDETONE_CTRL 0x0024 52 #define RT5682_STO1_ADC_MIXER 0x0026 53 #define RT5682_AD_DA_MIXER 0x0029 54 #define RT5682_STO1_DAC_MIXER 0x002a 55 #define RT5682_A_DAC1_MUX 0x002b 56 #define RT5682_DIG_INF2_DATA 0x0030 57 /* Mixer - ADC */ 58 #define RT5682_REC_MIXER 0x003c 59 #define RT5682_CAL_REC 0x0044 60 #define RT5682_ALC_BACK_GAIN 0x0049 61 /* Power */ 62 #define RT5682_PWR_DIG_1 0x0061 63 #define RT5682_PWR_DIG_2 0x0062 64 #define RT5682_PWR_ANLG_1 0x0063 65 #define RT5682_PWR_ANLG_2 0x0064 66 #define RT5682_PWR_ANLG_3 0x0065 67 #define RT5682_PWR_MIXER 0x0066 68 #define RT5682_PWR_VOL 0x0067 69 /* Clock Detect */ 70 #define RT5682_CLK_DET 0x006b 71 /* Filter Auto Reset */ 72 #define RT5682_RESET_LPF_CTRL 0x006c 73 #define RT5682_RESET_HPF_CTRL 0x006d 74 /* DMIC */ 75 #define RT5682_DMIC_CTRL_1 0x006e 76 /* Format - ADC/DAC */ 77 #define RT5682_I2S1_SDP 0x0070 78 #define RT5682_I2S2_SDP 0x0071 79 #define RT5682_ADDA_CLK_1 0x0073 80 #define RT5682_ADDA_CLK_2 0x0074 81 #define RT5682_I2S1_F_DIV_CTRL_1 0x0075 82 #define RT5682_I2S1_F_DIV_CTRL_2 0x0076 83 /* Format - TDM Control */ 84 #define RT5682_TDM_CTRL 0x0079 85 #define RT5682_TDM_ADDA_CTRL_1 0x007a 86 #define RT5682_TDM_ADDA_CTRL_2 0x007b 87 #define RT5682_DATA_SEL_CTRL_1 0x007c 88 #define RT5682_TDM_TCON_CTRL 0x007e 89 /* Function - Analog */ 90 #define RT5682_GLB_CLK 0x0080 91 #define RT5682_PLL_CTRL_1 0x0081 92 #define RT5682_PLL_CTRL_2 0x0082 93 #define RT5682_PLL_TRACK_1 0x0083 94 #define RT5682_PLL_TRACK_2 0x0084 95 #define RT5682_PLL_TRACK_3 0x0085 96 #define RT5682_PLL_TRACK_4 0x0086 97 #define RT5682_PLL_TRACK_5 0x0087 98 #define RT5682_PLL_TRACK_6 0x0088 99 #define RT5682_PLL_TRACK_11 0x008c 100 #define RT5682_SDW_REF_CLK 0x008d 101 #define RT5682_DEPOP_1 0x008e 102 #define RT5682_DEPOP_2 0x008f 103 #define RT5682_HP_CHARGE_PUMP_1 0x0091 104 #define RT5682_HP_CHARGE_PUMP_2 0x0092 105 #define RT5682_MICBIAS_1 0x0093 106 #define RT5682_MICBIAS_2 0x0094 107 #define RT5682_PLL_TRACK_12 0x0098 108 #define RT5682_PLL_TRACK_14 0x009a 109 #define RT5682_PLL2_CTRL_1 0x009b 110 #define RT5682_PLL2_CTRL_2 0x009c 111 #define RT5682_PLL2_CTRL_3 0x009d 112 #define RT5682_PLL2_CTRL_4 0x009e 113 #define RT5682_RC_CLK_CTRL 0x009f 114 #define RT5682_I2S_M_CLK_CTRL_1 0x00a0 115 #define RT5682_I2S2_F_DIV_CTRL_1 0x00a3 116 #define RT5682_I2S2_F_DIV_CTRL_2 0x00a4 117 /* Function - Digital */ 118 #define RT5682_EQ_CTRL_1 0x00ae 119 #define RT5682_EQ_CTRL_2 0x00af 120 #define RT5682_IRQ_CTRL_1 0x00b6 121 #define RT5682_IRQ_CTRL_2 0x00b7 122 #define RT5682_IRQ_CTRL_3 0x00b8 123 #define RT5682_IRQ_CTRL_4 0x00b9 124 #define RT5682_INT_ST_1 0x00be 125 #define RT5682_GPIO_CTRL_1 0x00c0 126 #define RT5682_GPIO_CTRL_2 0x00c1 127 #define RT5682_GPIO_CTRL_3 0x00c2 128 #define RT5682_HP_AMP_DET_CTRL_1 0x00d0 129 #define RT5682_HP_AMP_DET_CTRL_2 0x00d1 130 #define RT5682_MID_HP_AMP_DET 0x00d2 131 #define RT5682_LOW_HP_AMP_DET 0x00d3 132 #define RT5682_DELAY_BUF_CTRL 0x00d4 133 #define RT5682_SV_ZCD_1 0x00d9 134 #define RT5682_SV_ZCD_2 0x00da 135 #define RT5682_IL_CMD_1 0x00db 136 #define RT5682_IL_CMD_2 0x00dc 137 #define RT5682_IL_CMD_3 0x00dd 138 #define RT5682_IL_CMD_4 0x00de 139 #define RT5682_IL_CMD_5 0x00df 140 #define RT5682_IL_CMD_6 0x00e0 141 #define RT5682_4BTN_IL_CMD_1 0x00e2 142 #define RT5682_4BTN_IL_CMD_2 0x00e3 143 #define RT5682_4BTN_IL_CMD_3 0x00e4 144 #define RT5682_4BTN_IL_CMD_4 0x00e5 145 #define RT5682_4BTN_IL_CMD_5 0x00e6 146 #define RT5682_4BTN_IL_CMD_6 0x00e7 147 #define RT5682_4BTN_IL_CMD_7 0x00e8 148 149 #define RT5682_ADC_STO1_HP_CTRL_1 0x00ea 150 #define RT5682_ADC_STO1_HP_CTRL_2 0x00eb 151 #define RT5682_AJD1_CTRL 0x00f0 152 #define RT5682_JD1_THD 0x00f1 153 #define RT5682_JD2_THD 0x00f2 154 #define RT5682_JD_CTRL_1 0x00f6 155 /* General Control */ 156 #define RT5682_DUMMY_1 0x00fa 157 #define RT5682_DUMMY_2 0x00fb 158 #define RT5682_DUMMY_3 0x00fc 159 160 #define RT5682_DAC_ADC_DIG_VOL1 0x0100 161 #define RT5682_BIAS_CUR_CTRL_2 0x010b 162 #define RT5682_BIAS_CUR_CTRL_3 0x010c 163 #define RT5682_BIAS_CUR_CTRL_4 0x010d 164 #define RT5682_BIAS_CUR_CTRL_5 0x010e 165 #define RT5682_BIAS_CUR_CTRL_6 0x010f 166 #define RT5682_BIAS_CUR_CTRL_7 0x0110 167 #define RT5682_BIAS_CUR_CTRL_8 0x0111 168 #define RT5682_BIAS_CUR_CTRL_9 0x0112 169 #define RT5682_BIAS_CUR_CTRL_10 0x0113 170 #define RT5682_VREF_REC_OP_FB_CAP_CTRL 0x0117 171 #define RT5682_CHARGE_PUMP_1 0x0125 172 #define RT5682_DIG_IN_CTRL_1 0x0132 173 #define RT5682_PAD_DRIVING_CTRL 0x0136 174 #define RT5682_SOFT_RAMP_DEPOP 0x0138 175 #define RT5682_CHOP_DAC 0x013a 176 #define RT5682_CHOP_ADC 0x013b 177 #define RT5682_CALIB_ADC_CTRL 0x013c 178 #define RT5682_VOL_TEST 0x013f 179 #define RT5682_SPKVDD_DET_STA 0x0142 180 #define RT5682_TEST_MODE_CTRL_1 0x0145 181 #define RT5682_TEST_MODE_CTRL_2 0x0146 182 #define RT5682_TEST_MODE_CTRL_3 0x0147 183 #define RT5682_TEST_MODE_CTRL_4 0x0148 184 #define RT5682_TEST_MODE_CTRL_5 0x0149 185 #define RT5682_PLL1_INTERNAL 0x0150 186 #define RT5682_PLL2_INTERNAL 0x0156 187 #define RT5682_STO_NG2_CTRL_1 0x0160 188 #define RT5682_STO_NG2_CTRL_2 0x0161 189 #define RT5682_STO_NG2_CTRL_3 0x0162 190 #define RT5682_STO_NG2_CTRL_4 0x0163 191 #define RT5682_STO_NG2_CTRL_5 0x0164 192 #define RT5682_STO_NG2_CTRL_6 0x0165 193 #define RT5682_STO_NG2_CTRL_7 0x0166 194 #define RT5682_STO_NG2_CTRL_8 0x0167 195 #define RT5682_STO_NG2_CTRL_9 0x0168 196 #define RT5682_STO_NG2_CTRL_10 0x0169 197 #define RT5682_STO1_DAC_SIL_DET 0x0190 198 #define RT5682_SIL_PSV_CTRL1 0x0194 199 #define RT5682_SIL_PSV_CTRL2 0x0195 200 #define RT5682_SIL_PSV_CTRL3 0x0197 201 #define RT5682_SIL_PSV_CTRL4 0x0198 202 #define RT5682_SIL_PSV_CTRL5 0x0199 203 #define RT5682_HP_IMP_SENS_CTRL_01 0x01af 204 #define RT5682_HP_IMP_SENS_CTRL_02 0x01b0 205 #define RT5682_HP_IMP_SENS_CTRL_03 0x01b1 206 #define RT5682_HP_IMP_SENS_CTRL_04 0x01b2 207 #define RT5682_HP_IMP_SENS_CTRL_05 0x01b3 208 #define RT5682_HP_IMP_SENS_CTRL_06 0x01b4 209 #define RT5682_HP_IMP_SENS_CTRL_07 0x01b5 210 #define RT5682_HP_IMP_SENS_CTRL_08 0x01b6 211 #define RT5682_HP_IMP_SENS_CTRL_09 0x01b7 212 #define RT5682_HP_IMP_SENS_CTRL_10 0x01b8 213 #define RT5682_HP_IMP_SENS_CTRL_11 0x01b9 214 #define RT5682_HP_IMP_SENS_CTRL_12 0x01ba 215 #define RT5682_HP_IMP_SENS_CTRL_13 0x01bb 216 #define RT5682_HP_IMP_SENS_CTRL_14 0x01bc 217 #define RT5682_HP_IMP_SENS_CTRL_15 0x01bd 218 #define RT5682_HP_IMP_SENS_CTRL_16 0x01be 219 #define RT5682_HP_IMP_SENS_CTRL_17 0x01bf 220 #define RT5682_HP_IMP_SENS_CTRL_18 0x01c0 221 #define RT5682_HP_IMP_SENS_CTRL_19 0x01c1 222 #define RT5682_HP_IMP_SENS_CTRL_20 0x01c2 223 #define RT5682_HP_IMP_SENS_CTRL_21 0x01c3 224 #define RT5682_HP_IMP_SENS_CTRL_22 0x01c4 225 #define RT5682_HP_IMP_SENS_CTRL_23 0x01c5 226 #define RT5682_HP_IMP_SENS_CTRL_24 0x01c6 227 #define RT5682_HP_IMP_SENS_CTRL_25 0x01c7 228 #define RT5682_HP_IMP_SENS_CTRL_26 0x01c8 229 #define RT5682_HP_IMP_SENS_CTRL_27 0x01c9 230 #define RT5682_HP_IMP_SENS_CTRL_28 0x01ca 231 #define RT5682_HP_IMP_SENS_CTRL_29 0x01cb 232 #define RT5682_HP_IMP_SENS_CTRL_30 0x01cc 233 #define RT5682_HP_IMP_SENS_CTRL_31 0x01cd 234 #define RT5682_HP_IMP_SENS_CTRL_32 0x01ce 235 #define RT5682_HP_IMP_SENS_CTRL_33 0x01cf 236 #define RT5682_HP_IMP_SENS_CTRL_34 0x01d0 237 #define RT5682_HP_IMP_SENS_CTRL_35 0x01d1 238 #define RT5682_HP_IMP_SENS_CTRL_36 0x01d2 239 #define RT5682_HP_IMP_SENS_CTRL_37 0x01d3 240 #define RT5682_HP_IMP_SENS_CTRL_38 0x01d4 241 #define RT5682_HP_IMP_SENS_CTRL_39 0x01d5 242 #define RT5682_HP_IMP_SENS_CTRL_40 0x01d6 243 #define RT5682_HP_IMP_SENS_CTRL_41 0x01d7 244 #define RT5682_HP_IMP_SENS_CTRL_42 0x01d8 245 #define RT5682_HP_IMP_SENS_CTRL_43 0x01d9 246 #define RT5682_HP_LOGIC_CTRL_1 0x01da 247 #define RT5682_HP_LOGIC_CTRL_2 0x01db 248 #define RT5682_HP_LOGIC_CTRL_3 0x01dc 249 #define RT5682_HP_CALIB_CTRL_1 0x01de 250 #define RT5682_HP_CALIB_CTRL_2 0x01df 251 #define RT5682_HP_CALIB_CTRL_3 0x01e0 252 #define RT5682_HP_CALIB_CTRL_4 0x01e1 253 #define RT5682_HP_CALIB_CTRL_5 0x01e2 254 #define RT5682_HP_CALIB_CTRL_6 0x01e3 255 #define RT5682_HP_CALIB_CTRL_7 0x01e4 256 #define RT5682_HP_CALIB_CTRL_9 0x01e6 257 #define RT5682_HP_CALIB_CTRL_10 0x01e7 258 #define RT5682_HP_CALIB_CTRL_11 0x01e8 259 #define RT5682_HP_CALIB_STA_1 0x01ea 260 #define RT5682_HP_CALIB_STA_2 0x01eb 261 #define RT5682_HP_CALIB_STA_3 0x01ec 262 #define RT5682_HP_CALIB_STA_4 0x01ed 263 #define RT5682_HP_CALIB_STA_5 0x01ee 264 #define RT5682_HP_CALIB_STA_6 0x01ef 265 #define RT5682_HP_CALIB_STA_7 0x01f0 266 #define RT5682_HP_CALIB_STA_8 0x01f1 267 #define RT5682_HP_CALIB_STA_9 0x01f2 268 #define RT5682_HP_CALIB_STA_10 0x01f3 269 #define RT5682_HP_CALIB_STA_11 0x01f4 270 #define RT5682_SAR_IL_CMD_1 0x0210 271 #define RT5682_SAR_IL_CMD_2 0x0211 272 #define RT5682_SAR_IL_CMD_3 0x0212 273 #define RT5682_SAR_IL_CMD_4 0x0213 274 #define RT5682_SAR_IL_CMD_5 0x0214 275 #define RT5682_SAR_IL_CMD_6 0x0215 276 #define RT5682_SAR_IL_CMD_7 0x0216 277 #define RT5682_SAR_IL_CMD_8 0x0217 278 #define RT5682_SAR_IL_CMD_9 0x0218 279 #define RT5682_SAR_IL_CMD_10 0x0219 280 #define RT5682_SAR_IL_CMD_11 0x021a 281 #define RT5682_SAR_IL_CMD_12 0x021b 282 #define RT5682_SAR_IL_CMD_13 0x021c 283 #define RT5682_EFUSE_CTRL_1 0x0250 284 #define RT5682_EFUSE_CTRL_2 0x0251 285 #define RT5682_EFUSE_CTRL_3 0x0252 286 #define RT5682_EFUSE_CTRL_4 0x0253 287 #define RT5682_EFUSE_CTRL_5 0x0254 288 #define RT5682_EFUSE_CTRL_6 0x0255 289 #define RT5682_EFUSE_CTRL_7 0x0256 290 #define RT5682_EFUSE_CTRL_8 0x0257 291 #define RT5682_EFUSE_CTRL_9 0x0258 292 #define RT5682_EFUSE_CTRL_10 0x0259 293 #define RT5682_EFUSE_CTRL_11 0x025a 294 #define RT5682_JD_TOP_VC_VTRL 0x0270 295 #define RT5682_DRC1_CTRL_0 0x02ff 296 #define RT5682_DRC1_CTRL_1 0x0300 297 #define RT5682_DRC1_CTRL_2 0x0301 298 #define RT5682_DRC1_CTRL_3 0x0302 299 #define RT5682_DRC1_CTRL_4 0x0303 300 #define RT5682_DRC1_CTRL_5 0x0304 301 #define RT5682_DRC1_CTRL_6 0x0305 302 #define RT5682_DRC1_HARD_LMT_CTRL_1 0x0306 303 #define RT5682_DRC1_HARD_LMT_CTRL_2 0x0307 304 #define RT5682_DRC1_PRIV_1 0x0310 305 #define RT5682_DRC1_PRIV_2 0x0311 306 #define RT5682_DRC1_PRIV_3 0x0312 307 #define RT5682_DRC1_PRIV_4 0x0313 308 #define RT5682_DRC1_PRIV_5 0x0314 309 #define RT5682_DRC1_PRIV_6 0x0315 310 #define RT5682_DRC1_PRIV_7 0x0316 311 #define RT5682_DRC1_PRIV_8 0x0317 312 #define RT5682_EQ_AUTO_RCV_CTRL1 0x03c0 313 #define RT5682_EQ_AUTO_RCV_CTRL2 0x03c1 314 #define RT5682_EQ_AUTO_RCV_CTRL3 0x03c2 315 #define RT5682_EQ_AUTO_RCV_CTRL4 0x03c3 316 #define RT5682_EQ_AUTO_RCV_CTRL5 0x03c4 317 #define RT5682_EQ_AUTO_RCV_CTRL6 0x03c5 318 #define RT5682_EQ_AUTO_RCV_CTRL7 0x03c6 319 #define RT5682_EQ_AUTO_RCV_CTRL8 0x03c7 320 #define RT5682_EQ_AUTO_RCV_CTRL9 0x03c8 321 #define RT5682_EQ_AUTO_RCV_CTRL10 0x03c9 322 #define RT5682_EQ_AUTO_RCV_CTRL11 0x03ca 323 #define RT5682_EQ_AUTO_RCV_CTRL12 0x03cb 324 #define RT5682_EQ_AUTO_RCV_CTRL13 0x03cc 325 #define RT5682_ADC_L_EQ_LPF1_A1 0x03d0 326 #define RT5682_R_EQ_LPF1_A1 0x03d1 327 #define RT5682_L_EQ_LPF1_H0 0x03d2 328 #define RT5682_R_EQ_LPF1_H0 0x03d3 329 #define RT5682_L_EQ_BPF1_A1 0x03d4 330 #define RT5682_R_EQ_BPF1_A1 0x03d5 331 #define RT5682_L_EQ_BPF1_A2 0x03d6 332 #define RT5682_R_EQ_BPF1_A2 0x03d7 333 #define RT5682_L_EQ_BPF1_H0 0x03d8 334 #define RT5682_R_EQ_BPF1_H0 0x03d9 335 #define RT5682_L_EQ_BPF2_A1 0x03da 336 #define RT5682_R_EQ_BPF2_A1 0x03db 337 #define RT5682_L_EQ_BPF2_A2 0x03dc 338 #define RT5682_R_EQ_BPF2_A2 0x03dd 339 #define RT5682_L_EQ_BPF2_H0 0x03de 340 #define RT5682_R_EQ_BPF2_H0 0x03df 341 #define RT5682_L_EQ_BPF3_A1 0x03e0 342 #define RT5682_R_EQ_BPF3_A1 0x03e1 343 #define RT5682_L_EQ_BPF3_A2 0x03e2 344 #define RT5682_R_EQ_BPF3_A2 0x03e3 345 #define RT5682_L_EQ_BPF3_H0 0x03e4 346 #define RT5682_R_EQ_BPF3_H0 0x03e5 347 #define RT5682_L_EQ_BPF4_A1 0x03e6 348 #define RT5682_R_EQ_BPF4_A1 0x03e7 349 #define RT5682_L_EQ_BPF4_A2 0x03e8 350 #define RT5682_R_EQ_BPF4_A2 0x03e9 351 #define RT5682_L_EQ_BPF4_H0 0x03ea 352 #define RT5682_R_EQ_BPF4_H0 0x03eb 353 #define RT5682_L_EQ_HPF1_A1 0x03ec 354 #define RT5682_R_EQ_HPF1_A1 0x03ed 355 #define RT5682_L_EQ_HPF1_H0 0x03ee 356 #define RT5682_R_EQ_HPF1_H0 0x03ef 357 #define RT5682_L_EQ_PRE_VOL 0x03f0 358 #define RT5682_R_EQ_PRE_VOL 0x03f1 359 #define RT5682_L_EQ_POST_VOL 0x03f2 360 #define RT5682_R_EQ_POST_VOL 0x03f3 361 #define RT5682_I2C_MODE 0xffff 362 363 364 /* global definition */ 365 #define RT5682_L_MUTE (0x1 << 15) 366 #define RT5682_L_MUTE_SFT 15 367 #define RT5682_VOL_L_MUTE (0x1 << 14) 368 #define RT5682_VOL_L_SFT 14 369 #define RT5682_R_MUTE (0x1 << 7) 370 #define RT5682_R_MUTE_SFT 7 371 #define RT5682_VOL_R_MUTE (0x1 << 6) 372 #define RT5682_VOL_R_SFT 6 373 #define RT5682_L_VOL_MASK (0x3f << 8) 374 #define RT5682_L_VOL_SFT 8 375 #define RT5682_R_VOL_MASK (0x3f) 376 #define RT5682_R_VOL_SFT 0 377 378 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ 379 #define RT5682_G_HP (0xf << 8) 380 #define RT5682_G_HP_SFT 8 381 #define RT5682_G_STO_DA_DMIX (0xf) 382 #define RT5682_G_STO_DA_SFT 0 383 384 /* CBJ Control (0x000b) */ 385 #define RT5682_BST_CBJ_MASK (0xf << 8) 386 #define RT5682_BST_CBJ_SFT 8 387 388 /* Embeeded Jack and Type Detection Control 1 (0x0010) */ 389 #define RT5682_EMB_JD_EN (0x1 << 15) 390 #define RT5682_EMB_JD_EN_SFT 15 391 #define RT5682_EMB_JD_RST (0x1 << 14) 392 #define RT5682_JD_MODE (0x1 << 13) 393 #define RT5682_JD_MODE_SFT 13 394 #define RT5682_DET_TYPE (0x1 << 12) 395 #define RT5682_DET_TYPE_SFT 12 396 #define RT5682_POLA_EXT_JD_MASK (0x1 << 11) 397 #define RT5682_POLA_EXT_JD_LOW (0x1 << 11) 398 #define RT5682_POLA_EXT_JD_HIGH (0x0 << 11) 399 #define RT5682_EXT_JD_DIG (0x1 << 9) 400 #define RT5682_POL_FAST_OFF_MASK (0x1 << 8) 401 #define RT5682_POL_FAST_OFF_HIGH (0x1 << 8) 402 #define RT5682_POL_FAST_OFF_LOW (0x0 << 8) 403 #define RT5682_FAST_OFF_MASK (0x1 << 7) 404 #define RT5682_FAST_OFF_EN (0x1 << 7) 405 #define RT5682_FAST_OFF_DIS (0x0 << 7) 406 #define RT5682_VREF_POW_MASK (0x1 << 6) 407 #define RT5682_VREF_POW_FSM (0x0 << 6) 408 #define RT5682_VREF_POW_REG (0x1 << 6) 409 #define RT5682_MB1_PATH_MASK (0x1 << 5) 410 #define RT5682_CTRL_MB1_REG (0x1 << 5) 411 #define RT5682_CTRL_MB1_FSM (0x0 << 5) 412 #define RT5682_MB2_PATH_MASK (0x1 << 4) 413 #define RT5682_CTRL_MB2_REG (0x1 << 4) 414 #define RT5682_CTRL_MB2_FSM (0x0 << 4) 415 #define RT5682_TRIG_JD_MASK (0x1 << 3) 416 #define RT5682_TRIG_JD_HIGH (0x1 << 3) 417 #define RT5682_TRIG_JD_LOW (0x0 << 3) 418 #define RT5682_MIC_CAP_MASK (0x1 << 1) 419 #define RT5682_MIC_CAP_HS (0x1 << 1) 420 #define RT5682_MIC_CAP_HP (0x0 << 1) 421 #define RT5682_MIC_CAP_SRC_MASK (0x1) 422 #define RT5682_MIC_CAP_SRC_REG (0x1) 423 #define RT5682_MIC_CAP_SRC_ANA (0x0) 424 425 /* Embeeded Jack and Type Detection Control 2 (0x0011) */ 426 #define RT5682_EXT_JD_SRC (0x7 << 4) 427 #define RT5682_EXT_JD_SRC_SFT 4 428 #define RT5682_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) 429 #define RT5682_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) 430 #define RT5682_EXT_JD_SRC_JDH (0x2 << 4) 431 #define RT5682_EXT_JD_SRC_JDL (0x3 << 4) 432 #define RT5682_EXT_JD_SRC_MANUAL (0x4 << 4) 433 #define RT5682_JACK_TYPE_MASK (0x3) 434 435 /* Combo Jack and Type Detection Control 3 (0x0012) */ 436 #define RT5682_CBJ_IN_BUF_EN (0x1 << 7) 437 438 /* Combo Jack and Type Detection Control 4 (0x0013) */ 439 #define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12) 440 #define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12) 441 #define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12) 442 #define RT5682_CBJ_JD_TEST_MASK (0x1 << 6) 443 #define RT5682_CBJ_JD_TEST_NORM (0x0 << 6) 444 #define RT5682_CBJ_JD_TEST_MODE (0x1 << 6) 445 446 /* DAC1 Digital Volume (0x0019) */ 447 #define RT5682_DAC_L1_VOL_MASK (0xff << 8) 448 #define RT5682_DAC_L1_VOL_SFT 8 449 #define RT5682_DAC_R1_VOL_MASK (0xff) 450 #define RT5682_DAC_R1_VOL_SFT 0 451 452 /* ADC Digital Volume Control (0x001c) */ 453 #define RT5682_ADC_L_VOL_MASK (0x7f << 8) 454 #define RT5682_ADC_L_VOL_SFT 8 455 #define RT5682_ADC_R_VOL_MASK (0x7f) 456 #define RT5682_ADC_R_VOL_SFT 0 457 458 /* Stereo1 ADC Boost Gain Control (0x001f) */ 459 #define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14) 460 #define RT5682_STO1_ADC_L_BST_SFT 14 461 #define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12) 462 #define RT5682_STO1_ADC_R_BST_SFT 12 463 464 /* Sidetone Control (0x0024) */ 465 #define RT5682_ST_SRC_SEL (0x1 << 8) 466 #define RT5682_ST_SRC_SFT 8 467 #define RT5682_ST_EN_MASK (0x1 << 6) 468 #define RT5682_ST_DIS (0x0 << 6) 469 #define RT5682_ST_EN (0x1 << 6) 470 #define RT5682_ST_EN_SFT 6 471 472 /* Stereo1 ADC Mixer Control (0x0026) */ 473 #define RT5682_M_STO1_ADC_L1 (0x1 << 15) 474 #define RT5682_M_STO1_ADC_L1_SFT 15 475 #define RT5682_M_STO1_ADC_L2 (0x1 << 14) 476 #define RT5682_M_STO1_ADC_L2_SFT 14 477 #define RT5682_STO1_ADC1L_SRC_MASK (0x1 << 13) 478 #define RT5682_STO1_ADC1L_SRC_SFT 13 479 #define RT5682_STO1_ADC1_SRC_ADC (0x1 << 13) 480 #define RT5682_STO1_ADC1_SRC_DACMIX (0x0 << 13) 481 #define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12) 482 #define RT5682_STO1_ADC2L_SRC_SFT 12 483 #define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10) 484 #define RT5682_STO1_ADCL_SRC_SFT 10 485 #define RT5682_STO1_DD_L_SRC_MASK (0x1 << 9) 486 #define RT5682_STO1_DD_L_SRC_SFT 9 487 #define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8) 488 #define RT5682_STO1_DMIC_SRC_SFT 8 489 #define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8) 490 #define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8) 491 #define RT5682_M_STO1_ADC_R1 (0x1 << 7) 492 #define RT5682_M_STO1_ADC_R1_SFT 7 493 #define RT5682_M_STO1_ADC_R2 (0x1 << 6) 494 #define RT5682_M_STO1_ADC_R2_SFT 6 495 #define RT5682_STO1_ADC1R_SRC_MASK (0x1 << 5) 496 #define RT5682_STO1_ADC1R_SRC_SFT 5 497 #define RT5682_STO1_ADC2R_SRC_MASK (0x1 << 4) 498 #define RT5682_STO1_ADC2R_SRC_SFT 4 499 #define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2) 500 #define RT5682_STO1_ADCR_SRC_SFT 2 501 502 /* ADC Mixer to DAC Mixer Control (0x0029) */ 503 #define RT5682_M_ADCMIX_L (0x1 << 15) 504 #define RT5682_M_ADCMIX_L_SFT 15 505 #define RT5682_M_DAC1_L (0x1 << 14) 506 #define RT5682_M_DAC1_L_SFT 14 507 #define RT5682_DAC1_R_SEL_MASK (0x1 << 10) 508 #define RT5682_DAC1_R_SEL_SFT 10 509 #define RT5682_DAC1_L_SEL_MASK (0x1 << 8) 510 #define RT5682_DAC1_L_SEL_SFT 8 511 #define RT5682_M_ADCMIX_R (0x1 << 7) 512 #define RT5682_M_ADCMIX_R_SFT 7 513 #define RT5682_M_DAC1_R (0x1 << 6) 514 #define RT5682_M_DAC1_R_SFT 6 515 516 /* Stereo1 DAC Mixer Control (0x002a) */ 517 #define RT5682_M_DAC_L1_STO_L (0x1 << 15) 518 #define RT5682_M_DAC_L1_STO_L_SFT 15 519 #define RT5682_G_DAC_L1_STO_L_MASK (0x1 << 14) 520 #define RT5682_G_DAC_L1_STO_L_SFT 14 521 #define RT5682_M_DAC_R1_STO_L (0x1 << 13) 522 #define RT5682_M_DAC_R1_STO_L_SFT 13 523 #define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12) 524 #define RT5682_G_DAC_R1_STO_L_SFT 12 525 #define RT5682_M_DAC_L1_STO_R (0x1 << 7) 526 #define RT5682_M_DAC_L1_STO_R_SFT 7 527 #define RT5682_G_DAC_L1_STO_R_MASK (0x1 << 6) 528 #define RT5682_G_DAC_L1_STO_R_SFT 6 529 #define RT5682_M_DAC_R1_STO_R (0x1 << 5) 530 #define RT5682_M_DAC_R1_STO_R_SFT 5 531 #define RT5682_G_DAC_R1_STO_R_MASK (0x1 << 4) 532 #define RT5682_G_DAC_R1_STO_R_SFT 4 533 534 /* Analog DAC1 Input Source Control (0x002b) */ 535 #define RT5682_M_ST_STO_L (0x1 << 9) 536 #define RT5682_M_ST_STO_L_SFT 9 537 #define RT5682_M_ST_STO_R (0x1 << 8) 538 #define RT5682_M_ST_STO_R_SFT 8 539 #define RT5682_DAC_L1_SRC_MASK (0x3 << 4) 540 #define RT5682_A_DACL1_SFT 4 541 #define RT5682_DAC_R1_SRC_MASK (0x3) 542 #define RT5682_A_DACR1_SFT 0 543 544 /* Digital Interface Data Control (0x0030) */ 545 #define RT5682_IF2_ADC_SEL_MASK (0x3 << 0) 546 #define RT5682_IF2_ADC_SEL_SFT 0 547 548 /* REC Left Mixer Control 2 (0x003c) */ 549 #define RT5682_G_CBJ_RM1_L (0x7 << 10) 550 #define RT5682_G_CBJ_RM1_L_SFT 10 551 #define RT5682_M_CBJ_RM1_L (0x1 << 7) 552 #define RT5682_M_CBJ_RM1_L_SFT 7 553 554 /* Power Management for Digital 1 (0x0061) */ 555 #define RT5682_PWR_I2S1 (0x1 << 15) 556 #define RT5682_PWR_I2S1_BIT 15 557 #define RT5682_PWR_I2S2 (0x1 << 14) 558 #define RT5682_PWR_I2S2_BIT 14 559 #define RT5682_PWR_DAC_L1 (0x1 << 11) 560 #define RT5682_PWR_DAC_L1_BIT 11 561 #define RT5682_PWR_DAC_R1 (0x1 << 10) 562 #define RT5682_PWR_DAC_R1_BIT 10 563 #define RT5682_PWR_LDO (0x1 << 8) 564 #define RT5682_PWR_LDO_BIT 8 565 #define RT5682_PWR_ADC_L1 (0x1 << 4) 566 #define RT5682_PWR_ADC_L1_BIT 4 567 #define RT5682_PWR_ADC_R1 (0x1 << 3) 568 #define RT5682_PWR_ADC_R1_BIT 3 569 #define RT5682_DIG_GATE_CTRL (0x1 << 0) 570 #define RT5682_DIG_GATE_CTRL_SFT 0 571 572 573 /* Power Management for Digital 2 (0x0062) */ 574 #define RT5682_PWR_ADC_S1F (0x1 << 15) 575 #define RT5682_PWR_ADC_S1F_BIT 15 576 #define RT5682_PWR_DAC_S1F (0x1 << 10) 577 #define RT5682_PWR_DAC_S1F_BIT 10 578 579 /* Power Management for Analog 1 (0x0063) */ 580 #define RT5682_PWR_VREF1 (0x1 << 15) 581 #define RT5682_PWR_VREF1_BIT 15 582 #define RT5682_PWR_FV1 (0x1 << 14) 583 #define RT5682_PWR_FV1_BIT 14 584 #define RT5682_PWR_VREF2 (0x1 << 13) 585 #define RT5682_PWR_VREF2_BIT 13 586 #define RT5682_PWR_FV2 (0x1 << 12) 587 #define RT5682_PWR_FV2_BIT 12 588 #define RT5682_LDO1_DBG_MASK (0x3 << 10) 589 #define RT5682_PWR_MB (0x1 << 9) 590 #define RT5682_PWR_MB_BIT 9 591 #define RT5682_PWR_BG (0x1 << 7) 592 #define RT5682_PWR_BG_BIT 7 593 #define RT5682_LDO1_BYPASS_MASK (0x1 << 6) 594 #define RT5682_LDO1_BYPASS (0x1 << 6) 595 #define RT5682_LDO1_NOT_BYPASS (0x0 << 6) 596 #define RT5682_PWR_MA_BIT 6 597 #define RT5682_LDO1_DVO_MASK (0x3 << 4) 598 #define RT5682_LDO1_DVO_09 (0x0 << 4) 599 #define RT5682_LDO1_DVO_10 (0x1 << 4) 600 #define RT5682_LDO1_DVO_12 (0x2 << 4) 601 #define RT5682_LDO1_DVO_14 (0x3 << 4) 602 #define RT5682_HP_DRIVER_MASK (0x3 << 2) 603 #define RT5682_HP_DRIVER_1X (0x0 << 2) 604 #define RT5682_HP_DRIVER_3X (0x1 << 2) 605 #define RT5682_HP_DRIVER_5X (0x3 << 2) 606 #define RT5682_PWR_HA_L (0x1 << 1) 607 #define RT5682_PWR_HA_L_BIT 1 608 #define RT5682_PWR_HA_R (0x1 << 0) 609 #define RT5682_PWR_HA_R_BIT 0 610 611 /* Power Management for Analog 2 (0x0064) */ 612 #define RT5682_PWR_MB1 (0x1 << 11) 613 #define RT5682_PWR_MB1_PWR_DOWN (0x0 << 11) 614 #define RT5682_PWR_MB1_BIT 11 615 #define RT5682_PWR_MB2 (0x1 << 10) 616 #define RT5682_PWR_MB2_PWR_DOWN (0x0 << 10) 617 #define RT5682_PWR_MB2_BIT 10 618 #define RT5682_PWR_JDH (0x1 << 3) 619 #define RT5682_PWR_JDH_BIT 3 620 #define RT5682_PWR_JDL (0x1 << 2) 621 #define RT5682_PWR_JDL_BIT 2 622 #define RT5682_PWR_RM1_L (0x1 << 1) 623 #define RT5682_PWR_RM1_L_BIT 1 624 625 /* Power Management for Analog 3 (0x0065) */ 626 #define RT5682_PWR_CBJ (0x1 << 9) 627 #define RT5682_PWR_CBJ_BIT 9 628 #define RT5682_PWR_PLL (0x1 << 6) 629 #define RT5682_PWR_PLL_BIT 6 630 #define RT5682_PWR_PLL2B (0x1 << 5) 631 #define RT5682_PWR_PLL2B_BIT 5 632 #define RT5682_PWR_PLL2F (0x1 << 4) 633 #define RT5682_PWR_PLL2F_BIT 4 634 #define RT5682_PWR_LDO2 (0x1 << 2) 635 #define RT5682_PWR_LDO2_BIT 2 636 #define RT5682_PWR_DET_SPKVDD (0x1 << 1) 637 #define RT5682_PWR_DET_SPKVDD_BIT 1 638 639 /* Power Management for Mixer (0x0066) */ 640 #define RT5682_PWR_STO1_DAC_L (0x1 << 5) 641 #define RT5682_PWR_STO1_DAC_L_BIT 5 642 #define RT5682_PWR_STO1_DAC_R (0x1 << 4) 643 #define RT5682_PWR_STO1_DAC_R_BIT 4 644 645 /* MCLK and System Clock Detection Control (0x006b) */ 646 #define RT5682_SYS_CLK_DET (0x1 << 15) 647 #define RT5682_SYS_CLK_DET_SFT 15 648 #define RT5682_PLL1_CLK_DET (0x1 << 14) 649 #define RT5682_PLL1_CLK_DET_SFT 14 650 #define RT5682_PLL2_CLK_DET (0x1 << 13) 651 #define RT5682_PLL2_CLK_DET_SFT 13 652 #define RT5682_POW_CLK_DET2_SFT 8 653 #define RT5682_POW_CLK_DET_SFT 0 654 655 /* Digital Microphone Control 1 (0x006e) */ 656 #define RT5682_DMIC_1_EN_MASK (0x1 << 15) 657 #define RT5682_DMIC_1_EN_SFT 15 658 #define RT5682_DMIC_1_DIS (0x0 << 15) 659 #define RT5682_DMIC_1_EN (0x1 << 15) 660 #define RT5682_FIFO_CLK_DIV_MASK (0x7 << 12) 661 #define RT5682_FIFO_CLK_DIV_2 (0x1 << 12) 662 #define RT5682_DMIC_1_DP_MASK (0x3 << 4) 663 #define RT5682_DMIC_1_DP_SFT 4 664 #define RT5682_DMIC_1_DP_GPIO2 (0x0 << 4) 665 #define RT5682_DMIC_1_DP_GPIO5 (0x1 << 4) 666 #define RT5682_DMIC_CLK_MASK (0xf << 0) 667 #define RT5682_DMIC_CLK_SFT 0 668 669 /* I2S1 Audio Serial Data Port Control (0x0070) */ 670 #define RT5682_SEL_ADCDAT_MASK (0x1 << 15) 671 #define RT5682_SEL_ADCDAT_OUT (0x0 << 15) 672 #define RT5682_SEL_ADCDAT_IN (0x1 << 15) 673 #define RT5682_SEL_ADCDAT_SFT 15 674 #define RT5682_I2S1_TX_CHL_MASK (0x7 << 12) 675 #define RT5682_I2S1_TX_CHL_SFT 12 676 #define RT5682_I2S1_TX_CHL_16 (0x0 << 12) 677 #define RT5682_I2S1_TX_CHL_20 (0x1 << 12) 678 #define RT5682_I2S1_TX_CHL_24 (0x2 << 12) 679 #define RT5682_I2S1_TX_CHL_32 (0x3 << 12) 680 #define RT5682_I2S1_TX_CHL_8 (0x4 << 12) 681 #define RT5682_I2S1_RX_CHL_MASK (0x7 << 8) 682 #define RT5682_I2S1_RX_CHL_SFT 8 683 #define RT5682_I2S1_RX_CHL_16 (0x0 << 8) 684 #define RT5682_I2S1_RX_CHL_20 (0x1 << 8) 685 #define RT5682_I2S1_RX_CHL_24 (0x2 << 8) 686 #define RT5682_I2S1_RX_CHL_32 (0x3 << 8) 687 #define RT5682_I2S1_RX_CHL_8 (0x4 << 8) 688 #define RT5682_I2S1_MONO_MASK (0x1 << 7) 689 #define RT5682_I2S1_MONO_EN (0x1 << 7) 690 #define RT5682_I2S1_MONO_DIS (0x0 << 7) 691 #define RT5682_I2S2_MONO_MASK (0x1 << 6) 692 #define RT5682_I2S2_MONO_EN (0x1 << 6) 693 #define RT5682_I2S2_MONO_DIS (0x0 << 6) 694 #define RT5682_I2S1_DL_MASK (0x7 << 4) 695 #define RT5682_I2S1_DL_SFT 4 696 #define RT5682_I2S1_DL_16 (0x0 << 4) 697 #define RT5682_I2S1_DL_20 (0x1 << 4) 698 #define RT5682_I2S1_DL_24 (0x2 << 4) 699 #define RT5682_I2S1_DL_32 (0x3 << 4) 700 #define RT5682_I2S1_DL_8 (0x4 << 4) 701 702 /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */ 703 #define RT5682_I2S2_MS_MASK (0x1 << 15) 704 #define RT5682_I2S2_MS_SFT 15 705 #define RT5682_I2S2_MS_M (0x0 << 15) 706 #define RT5682_I2S2_MS_S (0x1 << 15) 707 #define RT5682_I2S2_PIN_CFG_MASK (0x1 << 14) 708 #define RT5682_I2S2_PIN_CFG_SFT 14 709 #define RT5682_I2S2_CLK_SEL_MASK (0x1 << 11) 710 #define RT5682_I2S2_CLK_SEL_SFT 11 711 #define RT5682_I2S2_OUT_MASK (0x1 << 9) 712 #define RT5682_I2S2_OUT_SFT 9 713 #define RT5682_I2S2_OUT_UM (0x0 << 9) 714 #define RT5682_I2S2_OUT_M (0x1 << 9) 715 #define RT5682_I2S_BP_MASK (0x1 << 8) 716 #define RT5682_I2S_BP_SFT 8 717 #define RT5682_I2S_BP_NOR (0x0 << 8) 718 #define RT5682_I2S_BP_INV (0x1 << 8) 719 #define RT5682_I2S2_MONO_EN (0x1 << 6) 720 #define RT5682_I2S2_MONO_DIS (0x0 << 6) 721 #define RT5682_I2S2_DL_MASK (0x3 << 4) 722 #define RT5682_I2S2_DL_SFT 4 723 #define RT5682_I2S2_DL_16 (0x0 << 4) 724 #define RT5682_I2S2_DL_20 (0x1 << 4) 725 #define RT5682_I2S2_DL_24 (0x2 << 4) 726 #define RT5682_I2S2_DL_8 (0x3 << 4) 727 #define RT5682_I2S_DF_MASK (0x7) 728 #define RT5682_I2S_DF_SFT 0 729 #define RT5682_I2S_DF_I2S (0x0) 730 #define RT5682_I2S_DF_LEFT (0x1) 731 #define RT5682_I2S_DF_PCM_A (0x2) 732 #define RT5682_I2S_DF_PCM_B (0x3) 733 #define RT5682_I2S_DF_PCM_A_N (0x6) 734 #define RT5682_I2S_DF_PCM_B_N (0x7) 735 736 /* ADC/DAC Clock Control 1 (0x0073) */ 737 #define RT5682_ADC_OSR_MASK (0xf << 12) 738 #define RT5682_ADC_OSR_SFT 12 739 #define RT5682_ADC_OSR_D_1 (0x0 << 12) 740 #define RT5682_ADC_OSR_D_2 (0x1 << 12) 741 #define RT5682_ADC_OSR_D_4 (0x2 << 12) 742 #define RT5682_ADC_OSR_D_6 (0x3 << 12) 743 #define RT5682_ADC_OSR_D_8 (0x4 << 12) 744 #define RT5682_ADC_OSR_D_12 (0x5 << 12) 745 #define RT5682_ADC_OSR_D_16 (0x6 << 12) 746 #define RT5682_ADC_OSR_D_24 (0x7 << 12) 747 #define RT5682_ADC_OSR_D_32 (0x8 << 12) 748 #define RT5682_ADC_OSR_D_48 (0x9 << 12) 749 #define RT5682_I2S_M_DIV_MASK (0xf << 8) 750 #define RT5682_I2S_M_DIV_SFT 8 751 #define RT5682_I2S_M_D_1 (0x0 << 8) 752 #define RT5682_I2S_M_D_2 (0x1 << 8) 753 #define RT5682_I2S_M_D_3 (0x2 << 8) 754 #define RT5682_I2S_M_D_4 (0x3 << 8) 755 #define RT5682_I2S_M_D_6 (0x4 << 8) 756 #define RT5682_I2S_M_D_8 (0x5 << 8) 757 #define RT5682_I2S_M_D_12 (0x6 << 8) 758 #define RT5682_I2S_M_D_16 (0x7 << 8) 759 #define RT5682_I2S_M_D_24 (0x8 << 8) 760 #define RT5682_I2S_M_D_32 (0x9 << 8) 761 #define RT5682_I2S_M_D_48 (0x10 << 8) 762 #define RT5682_I2S_CLK_SRC_MASK (0x7 << 4) 763 #define RT5682_I2S_CLK_SRC_SFT 4 764 #define RT5682_I2S_CLK_SRC_MCLK (0x0 << 4) 765 #define RT5682_I2S_CLK_SRC_PLL1 (0x1 << 4) 766 #define RT5682_I2S_CLK_SRC_PLL2 (0x2 << 4) 767 #define RT5682_I2S_CLK_SRC_SDW (0x3 << 4) 768 #define RT5682_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */ 769 #define RT5682_DAC_OSR_MASK (0xf << 0) 770 #define RT5682_DAC_OSR_SFT 0 771 #define RT5682_DAC_OSR_D_1 (0x0 << 0) 772 #define RT5682_DAC_OSR_D_2 (0x1 << 0) 773 #define RT5682_DAC_OSR_D_4 (0x2 << 0) 774 #define RT5682_DAC_OSR_D_6 (0x3 << 0) 775 #define RT5682_DAC_OSR_D_8 (0x4 << 0) 776 #define RT5682_DAC_OSR_D_12 (0x5 << 0) 777 #define RT5682_DAC_OSR_D_16 (0x6 << 0) 778 #define RT5682_DAC_OSR_D_24 (0x7 << 0) 779 #define RT5682_DAC_OSR_D_32 (0x8 << 0) 780 #define RT5682_DAC_OSR_D_48 (0x9 << 0) 781 782 /* ADC/DAC Clock Control 2 (0x0074) */ 783 #define RT5682_I2S2_BCLK_MS2_MASK (0x1 << 11) 784 #define RT5682_I2S2_BCLK_MS2_SFT 11 785 #define RT5682_I2S2_BCLK_MS2_32 (0x0 << 11) 786 #define RT5682_I2S2_BCLK_MS2_64 (0x1 << 11) 787 788 789 /* TDM control 1 (0x0079) */ 790 #define RT5682_TDM_TX_CH_MASK (0x3 << 12) 791 #define RT5682_TDM_TX_CH_2 (0x0 << 12) 792 #define RT5682_TDM_TX_CH_4 (0x1 << 12) 793 #define RT5682_TDM_TX_CH_6 (0x2 << 12) 794 #define RT5682_TDM_TX_CH_8 (0x3 << 12) 795 #define RT5682_TDM_RX_CH_MASK (0x3 << 8) 796 #define RT5682_TDM_RX_CH_2 (0x0 << 8) 797 #define RT5682_TDM_RX_CH_4 (0x1 << 8) 798 #define RT5682_TDM_RX_CH_6 (0x2 << 8) 799 #define RT5682_TDM_RX_CH_8 (0x3 << 8) 800 #define RT5682_TDM_ADC_LCA_MASK (0xf << 4) 801 #define RT5682_TDM_ADC_LCA_SFT 4 802 #define RT5682_TDM_ADC_DL_SFT 0 803 804 /* TDM control 2 (0x007a) */ 805 #define RT5682_IF1_ADC1_SEL_SFT 14 806 #define RT5682_IF1_ADC2_SEL_SFT 12 807 #define RT5682_IF1_ADC3_SEL_SFT 10 808 #define RT5682_IF1_ADC4_SEL_SFT 8 809 #define RT5682_TDM_ADC_SEL_SFT 4 810 811 /* TDM control 3 (0x007b) */ 812 #define RT5682_TDM_EN (0x1 << 7) 813 814 /* TDM/I2S control (0x007e) */ 815 #define RT5682_TDM_S_BP_MASK (0x1 << 15) 816 #define RT5682_TDM_S_BP_SFT 15 817 #define RT5682_TDM_S_BP_NOR (0x0 << 15) 818 #define RT5682_TDM_S_BP_INV (0x1 << 15) 819 #define RT5682_TDM_S_LP_MASK (0x1 << 14) 820 #define RT5682_TDM_S_LP_SFT 14 821 #define RT5682_TDM_S_LP_NOR (0x0 << 14) 822 #define RT5682_TDM_S_LP_INV (0x1 << 14) 823 #define RT5682_TDM_DF_MASK (0x7 << 11) 824 #define RT5682_TDM_DF_SFT 11 825 #define RT5682_TDM_DF_I2S (0x0 << 11) 826 #define RT5682_TDM_DF_LEFT (0x1 << 11) 827 #define RT5682_TDM_DF_PCM_A (0x2 << 11) 828 #define RT5682_TDM_DF_PCM_B (0x3 << 11) 829 #define RT5682_TDM_DF_PCM_A_N (0x6 << 11) 830 #define RT5682_TDM_DF_PCM_B_N (0x7 << 11) 831 #define RT5682_TDM_BCLK_MS1_MASK (0x3 << 9) 832 #define RT5682_TDM_BCLK_MS1_SFT 9 833 #define RT5682_TDM_BCLK_MS1_32 (0x0 << 9) 834 #define RT5682_TDM_BCLK_MS1_64 (0x1 << 9) 835 #define RT5682_TDM_BCLK_MS1_128 (0x2 << 9) 836 #define RT5682_TDM_BCLK_MS1_256 (0x3 << 9) 837 #define RT5682_TDM_CL_MASK (0x3 << 4) 838 #define RT5682_TDM_CL_16 (0x0 << 4) 839 #define RT5682_TDM_CL_20 (0x1 << 4) 840 #define RT5682_TDM_CL_24 (0x2 << 4) 841 #define RT5682_TDM_CL_32 (0x3 << 4) 842 #define RT5682_TDM_M_BP_MASK (0x1 << 2) 843 #define RT5682_TDM_M_BP_SFT 2 844 #define RT5682_TDM_M_BP_NOR (0x0 << 2) 845 #define RT5682_TDM_M_BP_INV (0x1 << 2) 846 #define RT5682_TDM_M_LP_MASK (0x1 << 1) 847 #define RT5682_TDM_M_LP_SFT 1 848 #define RT5682_TDM_M_LP_NOR (0x0 << 1) 849 #define RT5682_TDM_M_LP_INV (0x1 << 1) 850 #define RT5682_TDM_MS_MASK (0x1 << 0) 851 #define RT5682_TDM_MS_SFT 0 852 #define RT5682_TDM_MS_S (0x0 << 0) 853 #define RT5682_TDM_MS_M (0x1 << 0) 854 855 /* Global Clock Control (0x0080) */ 856 #define RT5682_SCLK_SRC_MASK (0x7 << 13) 857 #define RT5682_SCLK_SRC_SFT 13 858 #define RT5682_SCLK_SRC_MCLK (0x0 << 13) 859 #define RT5682_SCLK_SRC_PLL1 (0x1 << 13) 860 #define RT5682_SCLK_SRC_PLL2 (0x2 << 13) 861 #define RT5682_SCLK_SRC_SDW (0x3 << 13) 862 #define RT5682_SCLK_SRC_RCCLK (0x4 << 13) 863 #define RT5682_PLL2_SRC_MASK (0x3 << 10) 864 #define RT5682_PLL2_SRC_SFT 10 865 #define RT5682_PLL2_SRC_MCLK (0x0 << 10) 866 #define RT5682_PLL2_SRC_BCLK1 (0x1 << 10) 867 #define RT5682_PLL2_SRC_SDW (0x2 << 10) 868 #define RT5682_PLL2_SRC_RC (0x3 << 10) 869 #define RT5682_PLL1_SRC_MASK (0x3 << 8) 870 #define RT5682_PLL1_SRC_SFT 8 871 #define RT5682_PLL1_SRC_MCLK (0x0 << 8) 872 #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8) 873 #define RT5682_PLL1_SRC_SDW (0x2 << 8) 874 #define RT5682_PLL1_SRC_RC (0x3 << 8) 875 876 877 878 #define RT5682_PLL_INP_MAX 40000000 879 #define RT5682_PLL_INP_MIN 256000 880 /* PLL M/N/K Code Control 1 (0x0081) */ 881 #define RT5682_PLL_N_MAX 0x001ff 882 #define RT5682_PLL_N_MASK (RT5682_PLL_N_MAX << 7) 883 #define RT5682_PLL_N_SFT 7 884 #define RT5682_PLL_K_MAX 0x001f 885 #define RT5682_PLL_K_MASK (RT5682_PLL_K_MAX) 886 #define RT5682_PLL_K_SFT 0 887 888 /* PLL M/N/K Code Control 2 (0x0082) */ 889 #define RT5682_PLL_M_MAX 0x00f 890 #define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12) 891 #define RT5682_PLL_M_SFT 12 892 #define RT5682_PLL_M_BP (0x1 << 11) 893 #define RT5682_PLL_M_BP_SFT 11 894 #define RT5682_PLL_K_BP (0x1 << 10) 895 #define RT5682_PLL_K_BP_SFT 10 896 #define RT5682_PLL_RST (0x1 << 1) 897 898 /* PLL tracking mode 1 (0x0083) */ 899 #define RT5682_DA_ASRC_MASK (0x1 << 13) 900 #define RT5682_DA_ASRC_SFT 13 901 #define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12) 902 #define RT5682_DAC_STO1_ASRC_SFT 12 903 #define RT5682_AD_ASRC_MASK (0x1 << 8) 904 #define RT5682_AD_ASRC_SFT 8 905 #define RT5682_AD_ASRC_SEL_MASK (0x1 << 4) 906 #define RT5682_AD_ASRC_SEL_SFT 4 907 #define RT5682_DMIC_ASRC_MASK (0x1 << 3) 908 #define RT5682_DMIC_ASRC_SFT 3 909 #define RT5682_ADC_STO1_ASRC_MASK (0x1 << 2) 910 #define RT5682_ADC_STO1_ASRC_SFT 2 911 #define RT5682_DA_ASRC_SEL_MASK (0x1 << 0) 912 #define RT5682_DA_ASRC_SEL_SFT 0 913 914 /* PLL tracking mode 2 3 (0x0084)(0x0085)*/ 915 #define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12) 916 #define RT5682_FILTER_CLK_SEL_SFT 12 917 #define RT5682_FILTER_CLK_DIV_MASK (0xf << 8) 918 #define RT5682_FILTER_CLK_DIV_SFT 8 919 920 /* ASRC Control 4 (0x0086) */ 921 #define RT5682_ASRCIN_FTK_N1_MASK (0x3 << 14) 922 #define RT5682_ASRCIN_FTK_N1_SFT 14 923 #define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12) 924 #define RT5682_ASRCIN_FTK_N2_SFT 12 925 #define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8) 926 #define RT5682_ASRCIN_FTK_M1_SFT 8 927 #define RT5682_ASRCIN_FTK_M2_MASK (0x7 << 4) 928 #define RT5682_ASRCIN_FTK_M2_SFT 4 929 930 /* SoundWire reference clk (0x008d) */ 931 #define RT5682_PLL2_OUT_MASK (0x1 << 8) 932 #define RT5682_PLL2_OUT_98M (0x0 << 8) 933 #define RT5682_PLL2_OUT_49M (0x1 << 8) 934 #define RT5682_SDW_REF_2_MASK (0xf << 4) 935 #define RT5682_SDW_REF_2_SFT 4 936 #define RT5682_SDW_REF_2_48K (0x0 << 4) 937 #define RT5682_SDW_REF_2_96K (0x1 << 4) 938 #define RT5682_SDW_REF_2_192K (0x2 << 4) 939 #define RT5682_SDW_REF_2_32K (0x3 << 4) 940 #define RT5682_SDW_REF_2_24K (0x4 << 4) 941 #define RT5682_SDW_REF_2_16K (0x5 << 4) 942 #define RT5682_SDW_REF_2_12K (0x6 << 4) 943 #define RT5682_SDW_REF_2_8K (0x7 << 4) 944 #define RT5682_SDW_REF_2_44K (0x8 << 4) 945 #define RT5682_SDW_REF_2_88K (0x9 << 4) 946 #define RT5682_SDW_REF_2_176K (0xa << 4) 947 #define RT5682_SDW_REF_2_353K (0xb << 4) 948 #define RT5682_SDW_REF_2_22K (0xc << 4) 949 #define RT5682_SDW_REF_2_384K (0xd << 4) 950 #define RT5682_SDW_REF_2_11K (0xe << 4) 951 #define RT5682_SDW_REF_1_MASK (0xf << 0) 952 #define RT5682_SDW_REF_1_SFT 0 953 #define RT5682_SDW_REF_1_48K (0x0 << 0) 954 #define RT5682_SDW_REF_1_96K (0x1 << 0) 955 #define RT5682_SDW_REF_1_192K (0x2 << 0) 956 #define RT5682_SDW_REF_1_32K (0x3 << 0) 957 #define RT5682_SDW_REF_1_24K (0x4 << 0) 958 #define RT5682_SDW_REF_1_16K (0x5 << 0) 959 #define RT5682_SDW_REF_1_12K (0x6 << 0) 960 #define RT5682_SDW_REF_1_8K (0x7 << 0) 961 #define RT5682_SDW_REF_1_44K (0x8 << 0) 962 #define RT5682_SDW_REF_1_88K (0x9 << 0) 963 #define RT5682_SDW_REF_1_176K (0xa << 0) 964 #define RT5682_SDW_REF_1_353K (0xb << 0) 965 #define RT5682_SDW_REF_1_22K (0xc << 0) 966 #define RT5682_SDW_REF_1_384K (0xd << 0) 967 #define RT5682_SDW_REF_1_11K (0xe << 0) 968 969 /* Depop Mode Control 1 (0x008e) */ 970 #define RT5682_PUMP_EN (0x1 << 3) 971 #define RT5682_PUMP_EN_SFT 3 972 #define RT5682_CAPLESS_EN (0x1 << 0) 973 #define RT5682_CAPLESS_EN_SFT 0 974 975 /* Depop Mode Control 2 (0x8f) */ 976 #define RT5682_RAMP_MASK (0x1 << 12) 977 #define RT5682_RAMP_SFT 12 978 #define RT5682_RAMP_DIS (0x0 << 12) 979 #define RT5682_RAMP_EN (0x1 << 12) 980 #define RT5682_BPS_MASK (0x1 << 11) 981 #define RT5682_BPS_SFT 11 982 #define RT5682_BPS_DIS (0x0 << 11) 983 #define RT5682_BPS_EN (0x1 << 11) 984 #define RT5682_FAST_UPDN_MASK (0x1 << 10) 985 #define RT5682_FAST_UPDN_SFT 10 986 #define RT5682_FAST_UPDN_DIS (0x0 << 10) 987 #define RT5682_FAST_UPDN_EN (0x1 << 10) 988 #define RT5682_VLO_MASK (0x1 << 7) 989 #define RT5682_VLO_SFT 7 990 #define RT5682_VLO_3V (0x0 << 7) 991 #define RT5682_VLO_33V (0x1 << 7) 992 993 /* HPOUT charge pump 1 (0x0091) */ 994 #define RT5682_OSW_L_MASK (0x1 << 11) 995 #define RT5682_OSW_L_SFT 11 996 #define RT5682_OSW_L_DIS (0x0 << 11) 997 #define RT5682_OSW_L_EN (0x1 << 11) 998 #define RT5682_OSW_R_MASK (0x1 << 10) 999 #define RT5682_OSW_R_SFT 10 1000 #define RT5682_OSW_R_DIS (0x0 << 10) 1001 #define RT5682_OSW_R_EN (0x1 << 10) 1002 #define RT5682_PM_HP_MASK (0x3 << 8) 1003 #define RT5682_PM_HP_SFT 8 1004 #define RT5682_PM_HP_LV (0x0 << 8) 1005 #define RT5682_PM_HP_MV (0x1 << 8) 1006 #define RT5682_PM_HP_HV (0x2 << 8) 1007 #define RT5682_IB_HP_MASK (0x3 << 6) 1008 #define RT5682_IB_HP_SFT 6 1009 #define RT5682_IB_HP_125IL (0x0 << 6) 1010 #define RT5682_IB_HP_25IL (0x1 << 6) 1011 #define RT5682_IB_HP_5IL (0x2 << 6) 1012 #define RT5682_IB_HP_1IL (0x3 << 6) 1013 1014 /* Micbias Control1 (0x93) */ 1015 #define RT5682_MIC1_OV_MASK (0x3 << 14) 1016 #define RT5682_MIC1_OV_SFT 14 1017 #define RT5682_MIC1_OV_2V7 (0x0 << 14) 1018 #define RT5682_MIC1_OV_2V4 (0x1 << 14) 1019 #define RT5682_MIC1_OV_2V25 (0x3 << 14) 1020 #define RT5682_MIC1_OV_1V8 (0x4 << 14) 1021 #define RT5682_MIC1_CLK_MASK (0x1 << 13) 1022 #define RT5682_MIC1_CLK_SFT 13 1023 #define RT5682_MIC1_CLK_DIS (0x0 << 13) 1024 #define RT5682_MIC1_CLK_EN (0x1 << 13) 1025 #define RT5682_MIC1_OVCD_MASK (0x1 << 12) 1026 #define RT5682_MIC1_OVCD_SFT 12 1027 #define RT5682_MIC1_OVCD_DIS (0x0 << 12) 1028 #define RT5682_MIC1_OVCD_EN (0x1 << 12) 1029 #define RT5682_MIC1_OVTH_MASK (0x3 << 10) 1030 #define RT5682_MIC1_OVTH_SFT 10 1031 #define RT5682_MIC1_OVTH_768UA (0x0 << 10) 1032 #define RT5682_MIC1_OVTH_960UA (0x1 << 10) 1033 #define RT5682_MIC1_OVTH_1152UA (0x2 << 10) 1034 #define RT5682_MIC1_OVTH_1960UA (0x3 << 10) 1035 #define RT5682_MIC2_OV_MASK (0x3 << 8) 1036 #define RT5682_MIC2_OV_SFT 8 1037 #define RT5682_MIC2_OV_2V7 (0x0 << 8) 1038 #define RT5682_MIC2_OV_2V4 (0x1 << 8) 1039 #define RT5682_MIC2_OV_2V25 (0x3 << 8) 1040 #define RT5682_MIC2_OV_1V8 (0x4 << 8) 1041 #define RT5682_MIC2_CLK_MASK (0x1 << 7) 1042 #define RT5682_MIC2_CLK_SFT 7 1043 #define RT5682_MIC2_CLK_DIS (0x0 << 7) 1044 #define RT5682_MIC2_CLK_EN (0x1 << 7) 1045 #define RT5682_MIC2_OVTH_MASK (0x3 << 4) 1046 #define RT5682_MIC2_OVTH_SFT 4 1047 #define RT5682_MIC2_OVTH_768UA (0x0 << 4) 1048 #define RT5682_MIC2_OVTH_960UA (0x1 << 4) 1049 #define RT5682_MIC2_OVTH_1152UA (0x2 << 4) 1050 #define RT5682_MIC2_OVTH_1960UA (0x3 << 4) 1051 #define RT5682_PWR_MB_MASK (0x1 << 3) 1052 #define RT5682_PWR_MB_SFT 3 1053 #define RT5682_PWR_MB_PD (0x0 << 3) 1054 #define RT5682_PWR_MB_PU (0x1 << 3) 1055 1056 /* Micbias Control2 (0x0094) */ 1057 #define RT5682_PWR_CLK25M_MASK (0x1 << 9) 1058 #define RT5682_PWR_CLK25M_SFT 9 1059 #define RT5682_PWR_CLK25M_PD (0x0 << 9) 1060 #define RT5682_PWR_CLK25M_PU (0x1 << 9) 1061 #define RT5682_PWR_CLK1M_MASK (0x1 << 8) 1062 #define RT5682_PWR_CLK1M_SFT 8 1063 #define RT5682_PWR_CLK1M_PD (0x0 << 8) 1064 #define RT5682_PWR_CLK1M_PU (0x1 << 8) 1065 1066 /* PLL2 M/N/K Code Control 1 (0x009b) */ 1067 #define RT5682_PLL2F_K_MASK (0x1f << 8) 1068 #define RT5682_PLL2F_K_SFT 8 1069 #define RT5682_PLL2B_K_MASK (0xf << 4) 1070 #define RT5682_PLL2B_K_SFT 4 1071 #define RT5682_PLL2B_M_MASK (0xf << 0) 1072 1073 /* PLL2 M/N/K Code Control 2 (0x009c) */ 1074 #define RT5682_PLL2F_M_MASK (0x3f << 8) 1075 #define RT5682_PLL2F_M_SFT 8 1076 #define RT5682_PLL2B_N_MASK (0x3f << 0) 1077 1078 /* PLL2 M/N/K Code Control 2 (0x009d) */ 1079 #define RT5682_PLL2F_N_MASK (0x7f << 8) 1080 #define RT5682_PLL2F_N_SFT 8 1081 1082 /* PLL2 M/N/K Code Control 2 (0x009e) */ 1083 #define RT5682_PLL2B_SEL_PS_MASK (0x1 << 13) 1084 #define RT5682_PLL2B_SEL_PS_SFT 13 1085 #define RT5682_PLL2B_PS_BYP_MASK (0x1 << 12) 1086 #define RT5682_PLL2B_PS_BYP_SFT 12 1087 #define RT5682_PLL2B_M_BP_MASK (0x1 << 11) 1088 #define RT5682_PLL2B_M_BP_SFT 11 1089 #define RT5682_PLL2F_M_BP_MASK (0x1 << 7) 1090 #define RT5682_PLL2F_M_BP_SFT 7 1091 1092 /* RC Clock Control (0x009f) */ 1093 #define RT5682_POW_IRQ (0x1 << 15) 1094 #define RT5682_POW_JDH (0x1 << 14) 1095 #define RT5682_POW_JDL (0x1 << 13) 1096 #define RT5682_POW_ANA (0x1 << 12) 1097 1098 /* I2S Master Mode Clock Control 1 (0x00a0) */ 1099 #define RT5682_CLK_SRC_MCLK (0x0) 1100 #define RT5682_CLK_SRC_PLL1 (0x1) 1101 #define RT5682_CLK_SRC_PLL2 (0x2) 1102 #define RT5682_CLK_SRC_SDW (0x3) 1103 #define RT5682_CLK_SRC_RCCLK (0x4) 1104 #define RT5682_I2S_PD_1 (0x0) 1105 #define RT5682_I2S_PD_2 (0x1) 1106 #define RT5682_I2S_PD_3 (0x2) 1107 #define RT5682_I2S_PD_4 (0x3) 1108 #define RT5682_I2S_PD_6 (0x4) 1109 #define RT5682_I2S_PD_8 (0x5) 1110 #define RT5682_I2S_PD_12 (0x6) 1111 #define RT5682_I2S_PD_16 (0x7) 1112 #define RT5682_I2S_PD_24 (0x8) 1113 #define RT5682_I2S_PD_32 (0x9) 1114 #define RT5682_I2S_PD_48 (0xa) 1115 #define RT5682_I2S2_SRC_MASK (0x3 << 4) 1116 #define RT5682_I2S2_SRC_SFT 4 1117 #define RT5682_I2S2_M_PD_MASK (0xf << 0) 1118 #define RT5682_I2S2_M_PD_SFT 0 1119 1120 /* IRQ Control 1 (0x00b6) */ 1121 #define RT5682_JD1_PULSE_EN_MASK (0x1 << 10) 1122 #define RT5682_JD1_PULSE_EN_SFT 10 1123 #define RT5682_JD1_PULSE_DIS (0x0 << 10) 1124 #define RT5682_JD1_PULSE_EN (0x1 << 10) 1125 1126 /* IRQ Control 2 (0x00b7) */ 1127 #define RT5682_JD1_EN_MASK (0x1 << 15) 1128 #define RT5682_JD1_EN_SFT 15 1129 #define RT5682_JD1_DIS (0x0 << 15) 1130 #define RT5682_JD1_EN (0x1 << 15) 1131 #define RT5682_JD1_POL_MASK (0x1 << 13) 1132 #define RT5682_JD1_POL_NOR (0x0 << 13) 1133 #define RT5682_JD1_POL_INV (0x1 << 13) 1134 #define RT5682_JD1_IRQ_MASK (0x1 << 10) 1135 #define RT5682_JD1_IRQ_LEV (0x0 << 10) 1136 #define RT5682_JD1_IRQ_PUL (0x1 << 10) 1137 1138 /* IRQ Control 3 (0x00b8) */ 1139 #define RT5682_IL_IRQ_MASK (0x1 << 7) 1140 #define RT5682_IL_IRQ_DIS (0x0 << 7) 1141 #define RT5682_IL_IRQ_EN (0x1 << 7) 1142 #define RT5682_IL_IRQ_TYPE_MASK (0x1 << 4) 1143 #define RT5682_IL_IRQ_LEV (0x0 << 4) 1144 #define RT5682_IL_IRQ_PUL (0x1 << 4) 1145 1146 /* GPIO Control 1 (0x00c0) */ 1147 #define RT5682_GP1_PIN_MASK (0x3 << 14) 1148 #define RT5682_GP1_PIN_SFT 14 1149 #define RT5682_GP1_PIN_GPIO1 (0x0 << 14) 1150 #define RT5682_GP1_PIN_IRQ (0x1 << 14) 1151 #define RT5682_GP1_PIN_DMIC_CLK (0x2 << 14) 1152 #define RT5682_GP2_PIN_MASK (0x3 << 12) 1153 #define RT5682_GP2_PIN_SFT 12 1154 #define RT5682_GP2_PIN_GPIO2 (0x0 << 12) 1155 #define RT5682_GP2_PIN_LRCK2 (0x1 << 12) 1156 #define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12) 1157 #define RT5682_GP3_PIN_MASK (0x3 << 10) 1158 #define RT5682_GP3_PIN_SFT 10 1159 #define RT5682_GP3_PIN_GPIO3 (0x0 << 10) 1160 #define RT5682_GP3_PIN_BCLK2 (0x1 << 10) 1161 #define RT5682_GP3_PIN_DMIC_CLK (0x2 << 10) 1162 #define RT5682_GP4_PIN_MASK (0x3 << 8) 1163 #define RT5682_GP4_PIN_SFT 8 1164 #define RT5682_GP4_PIN_GPIO4 (0x0 << 8) 1165 #define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8) 1166 #define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8) 1167 #define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8) 1168 #define RT5682_GP5_PIN_MASK (0x3 << 6) 1169 #define RT5682_GP5_PIN_SFT 6 1170 #define RT5682_GP5_PIN_GPIO5 (0x0 << 6) 1171 #define RT5682_GP5_PIN_DACDAT1 (0x1 << 6) 1172 #define RT5682_GP5_PIN_DMIC_SDA (0x2 << 6) 1173 #define RT5682_GP6_PIN_MASK (0x1 << 5) 1174 #define RT5682_GP6_PIN_SFT 5 1175 #define RT5682_GP6_PIN_GPIO6 (0x0 << 5) 1176 #define RT5682_GP6_PIN_LRCK1 (0x1 << 5) 1177 1178 /* GPIO Control 2 (0x00c1)*/ 1179 #define RT5682_GP1_PF_MASK (0x1 << 15) 1180 #define RT5682_GP1_PF_IN (0x0 << 15) 1181 #define RT5682_GP1_PF_OUT (0x1 << 15) 1182 #define RT5682_GP1_OUT_MASK (0x1 << 14) 1183 #define RT5682_GP1_OUT_L (0x0 << 14) 1184 #define RT5682_GP1_OUT_H (0x1 << 14) 1185 #define RT5682_GP2_PF_MASK (0x1 << 13) 1186 #define RT5682_GP2_PF_IN (0x0 << 13) 1187 #define RT5682_GP2_PF_OUT (0x1 << 13) 1188 #define RT5682_GP2_OUT_MASK (0x1 << 12) 1189 #define RT5682_GP2_OUT_L (0x0 << 12) 1190 #define RT5682_GP2_OUT_H (0x1 << 12) 1191 #define RT5682_GP3_PF_MASK (0x1 << 11) 1192 #define RT5682_GP3_PF_IN (0x0 << 11) 1193 #define RT5682_GP3_PF_OUT (0x1 << 11) 1194 #define RT5682_GP3_OUT_MASK (0x1 << 10) 1195 #define RT5682_GP3_OUT_L (0x0 << 10) 1196 #define RT5682_GP3_OUT_H (0x1 << 10) 1197 #define RT5682_GP4_PF_MASK (0x1 << 9) 1198 #define RT5682_GP4_PF_IN (0x0 << 9) 1199 #define RT5682_GP4_PF_OUT (0x1 << 9) 1200 #define RT5682_GP4_OUT_MASK (0x1 << 8) 1201 #define RT5682_GP4_OUT_L (0x0 << 8) 1202 #define RT5682_GP4_OUT_H (0x1 << 8) 1203 #define RT5682_GP5_PF_MASK (0x1 << 7) 1204 #define RT5682_GP5_PF_IN (0x0 << 7) 1205 #define RT5682_GP5_PF_OUT (0x1 << 7) 1206 #define RT5682_GP5_OUT_MASK (0x1 << 6) 1207 #define RT5682_GP5_OUT_L (0x0 << 6) 1208 #define RT5682_GP5_OUT_H (0x1 << 6) 1209 #define RT5682_GP6_PF_MASK (0x1 << 5) 1210 #define RT5682_GP6_PF_IN (0x0 << 5) 1211 #define RT5682_GP6_PF_OUT (0x1 << 5) 1212 #define RT5682_GP6_OUT_MASK (0x1 << 4) 1213 #define RT5682_GP6_OUT_L (0x0 << 4) 1214 #define RT5682_GP6_OUT_H (0x1 << 4) 1215 1216 1217 /* GPIO Status (0x00c2) */ 1218 #define RT5682_GP6_STA (0x1 << 6) 1219 #define RT5682_GP5_STA (0x1 << 5) 1220 #define RT5682_GP4_STA (0x1 << 4) 1221 #define RT5682_GP3_STA (0x1 << 3) 1222 #define RT5682_GP2_STA (0x1 << 2) 1223 #define RT5682_GP1_STA (0x1 << 1) 1224 1225 /* Soft volume and zero cross control 1 (0x00d9) */ 1226 #define RT5682_SV_MASK (0x1 << 15) 1227 #define RT5682_SV_SFT 15 1228 #define RT5682_SV_DIS (0x0 << 15) 1229 #define RT5682_SV_EN (0x1 << 15) 1230 #define RT5682_ZCD_MASK (0x1 << 10) 1231 #define RT5682_ZCD_SFT 10 1232 #define RT5682_ZCD_PD (0x0 << 10) 1233 #define RT5682_ZCD_PU (0x1 << 10) 1234 #define RT5682_SV_DLY_MASK (0xf) 1235 #define RT5682_SV_DLY_SFT 0 1236 1237 /* Soft volume and zero cross control 2 (0x00da) */ 1238 #define RT5682_ZCD_BST1_CBJ_MASK (0x1 << 7) 1239 #define RT5682_ZCD_BST1_CBJ_SFT 7 1240 #define RT5682_ZCD_BST1_CBJ_DIS (0x0 << 7) 1241 #define RT5682_ZCD_BST1_CBJ_EN (0x1 << 7) 1242 #define RT5682_ZCD_RECMIX_MASK (0x1) 1243 #define RT5682_ZCD_RECMIX_SFT 0 1244 #define RT5682_ZCD_RECMIX_DIS (0x0) 1245 #define RT5682_ZCD_RECMIX_EN (0x1) 1246 1247 /* 4 Button Inline Command Control 2 (0x00e3) */ 1248 #define RT5682_4BTN_IL_MASK (0x1 << 15) 1249 #define RT5682_4BTN_IL_EN (0x1 << 15) 1250 #define RT5682_4BTN_IL_DIS (0x0 << 15) 1251 #define RT5682_4BTN_IL_RST_MASK (0x1 << 14) 1252 #define RT5682_4BTN_IL_NOR (0x1 << 14) 1253 #define RT5682_4BTN_IL_RST (0x0 << 14) 1254 1255 /* Analog JD Control (0x00f0) */ 1256 #define RT5682_JDH_RS_MASK (0x1 << 4) 1257 #define RT5682_JDH_NO_PLUG (0x1 << 4) 1258 #define RT5682_JDH_PLUG (0x0 << 4) 1259 1260 /* Bias current control 8 (0x0111) */ 1261 #define RT5682_HPA_CP_BIAS_CTRL_MASK (0x3 << 2) 1262 #define RT5682_HPA_CP_BIAS_2UA (0x0 << 2) 1263 #define RT5682_HPA_CP_BIAS_3UA (0x1 << 2) 1264 #define RT5682_HPA_CP_BIAS_4UA (0x2 << 2) 1265 #define RT5682_HPA_CP_BIAS_6UA (0x3 << 2) 1266 1267 /* Charge Pump Internal Register1 (0x0125) */ 1268 #define RT5682_CP_CLK_HP_MASK (0x3 << 4) 1269 #define RT5682_CP_CLK_HP_100KHZ (0x0 << 4) 1270 #define RT5682_CP_CLK_HP_200KHZ (0x1 << 4) 1271 #define RT5682_CP_CLK_HP_300KHZ (0x2 << 4) 1272 #define RT5682_CP_CLK_HP_600KHZ (0x3 << 4) 1273 1274 /* Pad Driving Control (0x0136) */ 1275 #define RT5682_PAD_DRV_GP1_MASK (0x3 << 14) 1276 #define RT5682_PAD_DRV_GP1_SFT 14 1277 #define RT5682_PAD_DRV_GP2_MASK (0x3 << 12) 1278 #define RT5682_PAD_DRV_GP2_SFT 12 1279 #define RT5682_PAD_DRV_GP3_MASK (0x3 << 10) 1280 #define RT5682_PAD_DRV_GP3_SFT 10 1281 #define RT5682_PAD_DRV_GP4_MASK (0x3 << 8) 1282 #define RT5682_PAD_DRV_GP4_SFT 8 1283 #define RT5682_PAD_DRV_GP5_MASK (0x3 << 6) 1284 #define RT5682_PAD_DRV_GP5_SFT 6 1285 #define RT5682_PAD_DRV_GP6_MASK (0x3 << 4) 1286 #define RT5682_PAD_DRV_GP6_SFT 4 1287 1288 /* Chopper and Clock control for DAC (0x013a)*/ 1289 #define RT5682_CKXEN_DAC1_MASK (0x1 << 13) 1290 #define RT5682_CKXEN_DAC1_SFT 13 1291 #define RT5682_CKGEN_DAC1_MASK (0x1 << 12) 1292 #define RT5682_CKGEN_DAC1_SFT 12 1293 1294 /* Chopper and Clock control for ADC (0x013b)*/ 1295 #define RT5682_CKXEN_ADC1_MASK (0x1 << 13) 1296 #define RT5682_CKXEN_ADC1_SFT 13 1297 #define RT5682_CKGEN_ADC1_MASK (0x1 << 12) 1298 #define RT5682_CKGEN_ADC1_SFT 12 1299 1300 /* Volume test (0x013f)*/ 1301 #define RT5682_SEL_CLK_VOL_MASK (0x1 << 15) 1302 #define RT5682_SEL_CLK_VOL_EN (0x1 << 15) 1303 #define RT5682_SEL_CLK_VOL_DIS (0x0 << 15) 1304 1305 /* Test Mode Control 1 (0x0145) */ 1306 #define RT5682_AD2DA_LB_MASK (0x1 << 10) 1307 #define RT5682_AD2DA_LB_SFT 10 1308 1309 /* Stereo Noise Gate Control 1 (0x0160) */ 1310 #define RT5682_NG2_EN_MASK (0x1 << 15) 1311 #define RT5682_NG2_EN (0x1 << 15) 1312 #define RT5682_NG2_DIS (0x0 << 15) 1313 1314 /* Stereo1 DAC Silence Detection Control (0x0190) */ 1315 #define RT5682_DEB_STO_DAC_MASK (0x7 << 4) 1316 #define RT5682_DEB_80_MS (0x0 << 4) 1317 1318 /* SAR ADC Inline Command Control 1 (0x0210) */ 1319 #define RT5682_SAR_BUTT_DET_MASK (0x1 << 15) 1320 #define RT5682_SAR_BUTT_DET_EN (0x1 << 15) 1321 #define RT5682_SAR_BUTT_DET_DIS (0x0 << 15) 1322 #define RT5682_SAR_BUTDET_MODE_MASK (0x1 << 14) 1323 #define RT5682_SAR_BUTDET_POW_SAV (0x1 << 14) 1324 #define RT5682_SAR_BUTDET_POW_NORM (0x0 << 14) 1325 #define RT5682_SAR_BUTDET_RST_MASK (0x1 << 13) 1326 #define RT5682_SAR_BUTDET_RST_NORMAL (0x1 << 13) 1327 #define RT5682_SAR_BUTDET_RST (0x0 << 13) 1328 #define RT5682_SAR_POW_MASK (0x1 << 12) 1329 #define RT5682_SAR_POW_EN (0x1 << 12) 1330 #define RT5682_SAR_POW_DIS (0x0 << 12) 1331 #define RT5682_SAR_RST_MASK (0x1 << 11) 1332 #define RT5682_SAR_RST_NORMAL (0x1 << 11) 1333 #define RT5682_SAR_RST (0x0 << 11) 1334 #define RT5682_SAR_BYPASS_MASK (0x1 << 10) 1335 #define RT5682_SAR_BYPASS_EN (0x1 << 10) 1336 #define RT5682_SAR_BYPASS_DIS (0x0 << 10) 1337 #define RT5682_SAR_SEL_MB1_MASK (0x1 << 9) 1338 #define RT5682_SAR_SEL_MB1_SEL (0x1 << 9) 1339 #define RT5682_SAR_SEL_MB1_NOSEL (0x0 << 9) 1340 #define RT5682_SAR_SEL_MB2_MASK (0x1 << 8) 1341 #define RT5682_SAR_SEL_MB2_SEL (0x1 << 8) 1342 #define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8) 1343 #define RT5682_SAR_SEL_MODE_MASK (0x1 << 7) 1344 #define RT5682_SAR_SEL_MODE_CMP (0x1 << 7) 1345 #define RT5682_SAR_SEL_MODE_ADC (0x0 << 7) 1346 #define RT5682_SAR_SEL_MB1_MB2_MASK (0x1 << 5) 1347 #define RT5682_SAR_SEL_MB1_MB2_AUTO (0x1 << 5) 1348 #define RT5682_SAR_SEL_MB1_MB2_MANU (0x0 << 5) 1349 #define RT5682_SAR_SEL_SIGNAL_MASK (0x1 << 4) 1350 #define RT5682_SAR_SEL_SIGNAL_AUTO (0x1 << 4) 1351 #define RT5682_SAR_SEL_SIGNAL_MANU (0x0 << 4) 1352 1353 /* SAR ADC Inline Command Control 13 (0x021c) */ 1354 #define RT5682_SAR_SOUR_MASK (0x3f) 1355 #define RT5682_SAR_SOUR_BTN (0x3f) 1356 #define RT5682_SAR_SOUR_TYPE (0x0) 1357 1358 /* soundwire timeout */ 1359 #define RT5682_PROBE_TIMEOUT 5000 1360 1361 1362 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 1363 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1364 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1365 1366 /* System Clock Source */ 1367 enum { 1368 RT5682_SCLK_S_MCLK, 1369 RT5682_SCLK_S_PLL1, 1370 RT5682_SCLK_S_PLL2, 1371 RT5682_SCLK_S_RCCLK, 1372 }; 1373 1374 /* PLL Source */ 1375 enum { 1376 RT5682_PLL1_S_MCLK, 1377 RT5682_PLL1_S_BCLK1, 1378 RT5682_PLL1_S_RCCLK, 1379 RT5682_PLL2_S_MCLK, 1380 }; 1381 1382 enum { 1383 RT5682_PLL1, 1384 RT5682_PLL2, 1385 RT5682_PLLS, 1386 }; 1387 1388 enum { 1389 RT5682_AIF1, 1390 RT5682_AIF2, 1391 RT5682_SDW, 1392 RT5682_AIFS 1393 }; 1394 1395 /* filter mask */ 1396 enum { 1397 RT5682_DA_STEREO1_FILTER = 0x1, 1398 RT5682_AD_STEREO1_FILTER = (0x1 << 1), 1399 }; 1400 1401 enum { 1402 RT5682_CLK_SEL_SYS, 1403 RT5682_CLK_SEL_I2S1_ASRC, 1404 RT5682_CLK_SEL_I2S2_ASRC, 1405 }; 1406 1407 #define RT5682_NUM_SUPPLIES 3 1408 1409 struct rt5682_priv { 1410 struct snd_soc_component *component; 1411 struct rt5682_platform_data pdata; 1412 struct regmap *regmap; 1413 struct regmap *sdw_regmap; 1414 struct snd_soc_jack *hs_jack; 1415 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; 1416 struct delayed_work jack_detect_work; 1417 struct delayed_work jd_check_work; 1418 struct mutex disable_irq_lock; /* imp-def irq lock protection */ 1419 bool disable_irq; 1420 struct mutex calibrate_mutex; 1421 struct sdw_slave *slave; 1422 enum sdw_slave_status status; 1423 struct sdw_bus_params params; 1424 bool hw_init; 1425 bool first_hw_init; 1426 bool is_sdw; 1427 1428 #ifdef CONFIG_COMMON_CLK 1429 struct clk_hw dai_clks_hw[RT5682_DAI_NUM_CLKS]; 1430 struct clk *mclk; 1431 #endif 1432 1433 int sysclk; 1434 int sysclk_src; 1435 int lrck[RT5682_AIFS]; 1436 int bclk[RT5682_AIFS]; 1437 int master[RT5682_AIFS]; 1438 1439 int pll_src[RT5682_PLLS]; 1440 int pll_in[RT5682_PLLS]; 1441 int pll_out[RT5682_PLLS]; 1442 1443 int jack_type; 1444 int irq_work_delay_time; 1445 }; 1446 1447 extern const char *rt5682_supply_names[RT5682_NUM_SUPPLIES]; 1448 1449 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 1450 unsigned int filter_mask, unsigned int clk_src); 1451 1452 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev); 1453 1454 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert); 1455 void rt5682_jack_detect_handler(struct work_struct *work); 1456 1457 bool rt5682_volatile_register(struct device *dev, unsigned int reg); 1458 bool rt5682_readable_register(struct device *dev, unsigned int reg); 1459 1460 int rt5682_register_component(struct device *dev); 1461 void rt5682_calibrate(struct rt5682_priv *rt5682); 1462 void rt5682_reset(struct rt5682_priv *rt5682); 1463 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev); 1464 1465 #define RT5682_REG_NUM 318 1466 extern const struct reg_default rt5682_reg[RT5682_REG_NUM]; 1467 1468 extern const struct snd_soc_dai_ops rt5682_aif1_dai_ops; 1469 extern const struct snd_soc_dai_ops rt5682_aif2_dai_ops; 1470 extern const struct snd_soc_component_driver rt5682_soc_component_dev; 1471 1472 #endif /* __RT5682_H__ */ 1473