1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682.c -- RT5682 ALSA SoC audio component driver 4 // 5 // Copyright 2018 Realtek Semiconductor Corp. 6 // Author: Bard Liao <bardliao@realtek.com> 7 // 8 9 #include <linux/cleanup.h> 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/pm.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/acpi.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/mutex.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/rt5682.h> 30 31 #include "rl6231.h" 32 #include "rt5682.h" 33 34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38 "DBVDD", 39 "LDO1-IN", 40 }; 41 EXPORT_SYMBOL_GPL(rt5682_supply_names); 42 43 static const struct reg_sequence patch_list[] = { 44 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 45 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 46 {RT5682_I2C_CTRL, 0x000f}, 47 {RT5682_PLL2_INTERNAL, 0x8266}, 48 {RT5682_SAR_IL_CMD_1, 0x22b7}, 49 {RT5682_SAR_IL_CMD_3, 0x0365}, 50 {RT5682_SAR_IL_CMD_6, 0x0110}, 51 {RT5682_CHARGE_PUMP_1, 0x0210}, 52 {RT5682_HP_LOGIC_CTRL_2, 0x0007}, 53 {RT5682_SAR_IL_CMD_2, 0xac00}, 54 {RT5682_CBJ_CTRL_7, 0x0104}, 55 }; 56 57 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 58 { 59 int ret; 60 61 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 62 ARRAY_SIZE(patch_list)); 63 if (ret) 64 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 65 } 66 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 67 68 const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 69 {0x0002, 0x8080}, 70 {0x0003, 0x8000}, 71 {0x0005, 0x0000}, 72 {0x0006, 0x0000}, 73 {0x0008, 0x800f}, 74 {0x000b, 0x0000}, 75 {0x0010, 0x4040}, 76 {0x0011, 0x0000}, 77 {0x0012, 0x1404}, 78 {0x0013, 0x1000}, 79 {0x0014, 0xa00a}, 80 {0x0015, 0x0404}, 81 {0x0016, 0x0404}, 82 {0x0019, 0xafaf}, 83 {0x001c, 0x2f2f}, 84 {0x001f, 0x0000}, 85 {0x0022, 0x5757}, 86 {0x0023, 0x0039}, 87 {0x0024, 0x000b}, 88 {0x0026, 0xc0c4}, 89 {0x0029, 0x8080}, 90 {0x002a, 0xa0a0}, 91 {0x002b, 0x0300}, 92 {0x0030, 0x0000}, 93 {0x003c, 0x0080}, 94 {0x0044, 0x0c0c}, 95 {0x0049, 0x0000}, 96 {0x0061, 0x0000}, 97 {0x0062, 0x0000}, 98 {0x0063, 0x003f}, 99 {0x0064, 0x0000}, 100 {0x0065, 0x0000}, 101 {0x0066, 0x0030}, 102 {0x0067, 0x0000}, 103 {0x006b, 0x0000}, 104 {0x006c, 0x0000}, 105 {0x006d, 0x2200}, 106 {0x006e, 0x0a10}, 107 {0x0070, 0x8000}, 108 {0x0071, 0x8000}, 109 {0x0073, 0x0000}, 110 {0x0074, 0x0000}, 111 {0x0075, 0x0002}, 112 {0x0076, 0x0001}, 113 {0x0079, 0x0000}, 114 {0x007a, 0x0000}, 115 {0x007b, 0x0000}, 116 {0x007c, 0x0100}, 117 {0x007e, 0x0000}, 118 {0x0080, 0x0000}, 119 {0x0081, 0x0000}, 120 {0x0082, 0x0000}, 121 {0x0083, 0x0000}, 122 {0x0084, 0x0000}, 123 {0x0085, 0x0000}, 124 {0x0086, 0x0005}, 125 {0x0087, 0x0000}, 126 {0x0088, 0x0000}, 127 {0x008c, 0x0003}, 128 {0x008d, 0x0000}, 129 {0x008e, 0x0060}, 130 {0x008f, 0x1000}, 131 {0x0091, 0x0c26}, 132 {0x0092, 0x0073}, 133 {0x0093, 0x0000}, 134 {0x0094, 0x0080}, 135 {0x0098, 0x0000}, 136 {0x009a, 0x0000}, 137 {0x009b, 0x0000}, 138 {0x009c, 0x0000}, 139 {0x009d, 0x0000}, 140 {0x009e, 0x100c}, 141 {0x009f, 0x0000}, 142 {0x00a0, 0x0000}, 143 {0x00a3, 0x0002}, 144 {0x00a4, 0x0001}, 145 {0x00ae, 0x2040}, 146 {0x00af, 0x0000}, 147 {0x00b6, 0x0000}, 148 {0x00b7, 0x0000}, 149 {0x00b8, 0x0000}, 150 {0x00b9, 0x0002}, 151 {0x00be, 0x0000}, 152 {0x00c0, 0x0160}, 153 {0x00c1, 0x82a0}, 154 {0x00c2, 0x0000}, 155 {0x00d0, 0x0000}, 156 {0x00d1, 0x2244}, 157 {0x00d2, 0x3300}, 158 {0x00d3, 0x2200}, 159 {0x00d4, 0x0000}, 160 {0x00d9, 0x0009}, 161 {0x00da, 0x0000}, 162 {0x00db, 0x0000}, 163 {0x00dc, 0x00c0}, 164 {0x00dd, 0x2220}, 165 {0x00de, 0x3131}, 166 {0x00df, 0x3131}, 167 {0x00e0, 0x3131}, 168 {0x00e2, 0x0000}, 169 {0x00e3, 0x4000}, 170 {0x00e4, 0x0aa0}, 171 {0x00e5, 0x3131}, 172 {0x00e6, 0x3131}, 173 {0x00e7, 0x3131}, 174 {0x00e8, 0x3131}, 175 {0x00ea, 0xb320}, 176 {0x00eb, 0x0000}, 177 {0x00f0, 0x0000}, 178 {0x00f1, 0x00d0}, 179 {0x00f2, 0x00d0}, 180 {0x00f6, 0x0000}, 181 {0x00fa, 0x0000}, 182 {0x00fb, 0x0000}, 183 {0x00fc, 0x0000}, 184 {0x00fd, 0x0000}, 185 {0x00fe, 0x10ec}, 186 {0x00ff, 0x6530}, 187 {0x0100, 0xa0a0}, 188 {0x010b, 0x0000}, 189 {0x010c, 0xae00}, 190 {0x010d, 0xaaa0}, 191 {0x010e, 0x8aa2}, 192 {0x010f, 0x02a2}, 193 {0x0110, 0xc000}, 194 {0x0111, 0x04a2}, 195 {0x0112, 0x2800}, 196 {0x0113, 0x0000}, 197 {0x0117, 0x0100}, 198 {0x0125, 0x0410}, 199 {0x0132, 0x6026}, 200 {0x0136, 0x5555}, 201 {0x0138, 0x3700}, 202 {0x013a, 0x2000}, 203 {0x013b, 0x2000}, 204 {0x013c, 0x2005}, 205 {0x013f, 0x0000}, 206 {0x0142, 0x0000}, 207 {0x0145, 0x0002}, 208 {0x0146, 0x0000}, 209 {0x0147, 0x0000}, 210 {0x0148, 0x0000}, 211 {0x0149, 0x0000}, 212 {0x0150, 0x79a1}, 213 {0x0156, 0xaaaa}, 214 {0x0160, 0x4ec0}, 215 {0x0161, 0x0080}, 216 {0x0162, 0x0200}, 217 {0x0163, 0x0800}, 218 {0x0164, 0x0000}, 219 {0x0165, 0x0000}, 220 {0x0166, 0x0000}, 221 {0x0167, 0x000f}, 222 {0x0168, 0x000f}, 223 {0x0169, 0x0021}, 224 {0x0190, 0x413d}, 225 {0x0194, 0x0000}, 226 {0x0195, 0x0000}, 227 {0x0197, 0x0022}, 228 {0x0198, 0x0000}, 229 {0x0199, 0x0000}, 230 {0x01af, 0x0000}, 231 {0x01b0, 0x0400}, 232 {0x01b1, 0x0000}, 233 {0x01b2, 0x0000}, 234 {0x01b3, 0x0000}, 235 {0x01b4, 0x0000}, 236 {0x01b5, 0x0000}, 237 {0x01b6, 0x01c3}, 238 {0x01b7, 0x02a0}, 239 {0x01b8, 0x03e9}, 240 {0x01b9, 0x1389}, 241 {0x01ba, 0xc351}, 242 {0x01bb, 0x0009}, 243 {0x01bc, 0x0018}, 244 {0x01bd, 0x002a}, 245 {0x01be, 0x004c}, 246 {0x01bf, 0x0097}, 247 {0x01c0, 0x433d}, 248 {0x01c2, 0x0000}, 249 {0x01c3, 0x0000}, 250 {0x01c4, 0x0000}, 251 {0x01c5, 0x0000}, 252 {0x01c6, 0x0000}, 253 {0x01c7, 0x0000}, 254 {0x01c8, 0x40af}, 255 {0x01c9, 0x0702}, 256 {0x01ca, 0x0000}, 257 {0x01cb, 0x0000}, 258 {0x01cc, 0x5757}, 259 {0x01cd, 0x5757}, 260 {0x01ce, 0x5757}, 261 {0x01cf, 0x5757}, 262 {0x01d0, 0x5757}, 263 {0x01d1, 0x5757}, 264 {0x01d2, 0x5757}, 265 {0x01d3, 0x5757}, 266 {0x01d4, 0x5757}, 267 {0x01d5, 0x5757}, 268 {0x01d6, 0x0000}, 269 {0x01d7, 0x0008}, 270 {0x01d8, 0x0029}, 271 {0x01d9, 0x3333}, 272 {0x01da, 0x0000}, 273 {0x01db, 0x0004}, 274 {0x01dc, 0x0000}, 275 {0x01de, 0x7c00}, 276 {0x01df, 0x0320}, 277 {0x01e0, 0x06a1}, 278 {0x01e1, 0x0000}, 279 {0x01e2, 0x0000}, 280 {0x01e3, 0x0000}, 281 {0x01e4, 0x0000}, 282 {0x01e6, 0x0001}, 283 {0x01e7, 0x0000}, 284 {0x01e8, 0x0000}, 285 {0x01ea, 0x0000}, 286 {0x01eb, 0x0000}, 287 {0x01ec, 0x0000}, 288 {0x01ed, 0x0000}, 289 {0x01ee, 0x0000}, 290 {0x01ef, 0x0000}, 291 {0x01f0, 0x0000}, 292 {0x01f1, 0x0000}, 293 {0x01f2, 0x0000}, 294 {0x01f3, 0x0000}, 295 {0x01f4, 0x0000}, 296 {0x0210, 0x6297}, 297 {0x0211, 0xa005}, 298 {0x0212, 0x824c}, 299 {0x0213, 0xf7ff}, 300 {0x0214, 0xf24c}, 301 {0x0215, 0x0102}, 302 {0x0216, 0x00a3}, 303 {0x0217, 0x0048}, 304 {0x0218, 0xa2c0}, 305 {0x0219, 0x0400}, 306 {0x021a, 0x00c8}, 307 {0x021b, 0x00c0}, 308 {0x021c, 0x0000}, 309 {0x0250, 0x4500}, 310 {0x0251, 0x40b3}, 311 {0x0252, 0x0000}, 312 {0x0253, 0x0000}, 313 {0x0254, 0x0000}, 314 {0x0255, 0x0000}, 315 {0x0256, 0x0000}, 316 {0x0257, 0x0000}, 317 {0x0258, 0x0000}, 318 {0x0259, 0x0000}, 319 {0x025a, 0x0005}, 320 {0x0270, 0x0000}, 321 {0x02ff, 0x0110}, 322 {0x0300, 0x001f}, 323 {0x0301, 0x032c}, 324 {0x0302, 0x5f21}, 325 {0x0303, 0x4000}, 326 {0x0304, 0x4000}, 327 {0x0305, 0x06d5}, 328 {0x0306, 0x8000}, 329 {0x0307, 0x0700}, 330 {0x0310, 0x4560}, 331 {0x0311, 0xa4a8}, 332 {0x0312, 0x7418}, 333 {0x0313, 0x0000}, 334 {0x0314, 0x0006}, 335 {0x0315, 0xffff}, 336 {0x0316, 0xc400}, 337 {0x0317, 0x0000}, 338 {0x03c0, 0x7e00}, 339 {0x03c1, 0x8000}, 340 {0x03c2, 0x8000}, 341 {0x03c3, 0x8000}, 342 {0x03c4, 0x8000}, 343 {0x03c5, 0x8000}, 344 {0x03c6, 0x8000}, 345 {0x03c7, 0x8000}, 346 {0x03c8, 0x8000}, 347 {0x03c9, 0x8000}, 348 {0x03ca, 0x8000}, 349 {0x03cb, 0x8000}, 350 {0x03cc, 0x8000}, 351 {0x03d0, 0x0000}, 352 {0x03d1, 0x0000}, 353 {0x03d2, 0x0000}, 354 {0x03d3, 0x0000}, 355 {0x03d4, 0x2000}, 356 {0x03d5, 0x2000}, 357 {0x03d6, 0x0000}, 358 {0x03d7, 0x0000}, 359 {0x03d8, 0x2000}, 360 {0x03d9, 0x2000}, 361 {0x03da, 0x2000}, 362 {0x03db, 0x2000}, 363 {0x03dc, 0x0000}, 364 {0x03dd, 0x0000}, 365 {0x03de, 0x0000}, 366 {0x03df, 0x2000}, 367 {0x03e0, 0x0000}, 368 {0x03e1, 0x0000}, 369 {0x03e2, 0x0000}, 370 {0x03e3, 0x0000}, 371 {0x03e4, 0x0000}, 372 {0x03e5, 0x0000}, 373 {0x03e6, 0x0000}, 374 {0x03e7, 0x0000}, 375 {0x03e8, 0x0000}, 376 {0x03e9, 0x0000}, 377 {0x03ea, 0x0000}, 378 {0x03eb, 0x0000}, 379 {0x03ec, 0x0000}, 380 {0x03ed, 0x0000}, 381 {0x03ee, 0x0000}, 382 {0x03ef, 0x0000}, 383 {0x03f0, 0x0800}, 384 {0x03f1, 0x0800}, 385 {0x03f2, 0x0800}, 386 {0x03f3, 0x0800}, 387 }; 388 EXPORT_SYMBOL_GPL(rt5682_reg); 389 390 bool rt5682_volatile_register(struct device *dev, unsigned int reg) 391 { 392 switch (reg) { 393 case RT5682_RESET: 394 case RT5682_CBJ_CTRL_2: 395 case RT5682_INT_ST_1: 396 case RT5682_4BTN_IL_CMD_1: 397 case RT5682_AJD1_CTRL: 398 case RT5682_HP_CALIB_CTRL_1: 399 case RT5682_INT_DEVICE_ID: 400 case RT5682_DEVICE_ID: 401 case RT5682_I2C_MODE: 402 case RT5682_HP_CALIB_CTRL_10: 403 case RT5682_EFUSE_CTRL_2: 404 case RT5682_JD_TOP_VC_VTRL: 405 case RT5682_HP_IMP_SENS_CTRL_19: 406 case RT5682_IL_CMD_1: 407 case RT5682_SAR_IL_CMD_2: 408 case RT5682_SAR_IL_CMD_4: 409 case RT5682_SAR_IL_CMD_10: 410 case RT5682_SAR_IL_CMD_11: 411 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 412 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 413 return true; 414 default: 415 return false; 416 } 417 } 418 EXPORT_SYMBOL_GPL(rt5682_volatile_register); 419 420 bool rt5682_readable_register(struct device *dev, unsigned int reg) 421 { 422 switch (reg) { 423 case RT5682_RESET: 424 case RT5682_INT_DEVICE_ID: 425 case RT5682_VERSION_ID: 426 case RT5682_VENDOR_ID: 427 case RT5682_DEVICE_ID: 428 case RT5682_HP_CTRL_1: 429 case RT5682_HP_CTRL_2: 430 case RT5682_HPL_GAIN: 431 case RT5682_HPR_GAIN: 432 case RT5682_I2C_CTRL: 433 case RT5682_CBJ_BST_CTRL: 434 case RT5682_CBJ_CTRL_1: 435 case RT5682_CBJ_CTRL_2: 436 case RT5682_CBJ_CTRL_3: 437 case RT5682_CBJ_CTRL_4: 438 case RT5682_CBJ_CTRL_5: 439 case RT5682_CBJ_CTRL_6: 440 case RT5682_CBJ_CTRL_7: 441 case RT5682_DAC1_DIG_VOL: 442 case RT5682_STO1_ADC_DIG_VOL: 443 case RT5682_STO1_ADC_BOOST: 444 case RT5682_HP_IMP_GAIN_1: 445 case RT5682_HP_IMP_GAIN_2: 446 case RT5682_SIDETONE_CTRL: 447 case RT5682_STO1_ADC_MIXER: 448 case RT5682_AD_DA_MIXER: 449 case RT5682_STO1_DAC_MIXER: 450 case RT5682_A_DAC1_MUX: 451 case RT5682_DIG_INF2_DATA: 452 case RT5682_REC_MIXER: 453 case RT5682_CAL_REC: 454 case RT5682_ALC_BACK_GAIN: 455 case RT5682_PWR_DIG_1: 456 case RT5682_PWR_DIG_2: 457 case RT5682_PWR_ANLG_1: 458 case RT5682_PWR_ANLG_2: 459 case RT5682_PWR_ANLG_3: 460 case RT5682_PWR_MIXER: 461 case RT5682_PWR_VOL: 462 case RT5682_CLK_DET: 463 case RT5682_RESET_LPF_CTRL: 464 case RT5682_RESET_HPF_CTRL: 465 case RT5682_DMIC_CTRL_1: 466 case RT5682_I2S1_SDP: 467 case RT5682_I2S2_SDP: 468 case RT5682_ADDA_CLK_1: 469 case RT5682_ADDA_CLK_2: 470 case RT5682_I2S1_F_DIV_CTRL_1: 471 case RT5682_I2S1_F_DIV_CTRL_2: 472 case RT5682_TDM_CTRL: 473 case RT5682_TDM_ADDA_CTRL_1: 474 case RT5682_TDM_ADDA_CTRL_2: 475 case RT5682_DATA_SEL_CTRL_1: 476 case RT5682_TDM_TCON_CTRL: 477 case RT5682_GLB_CLK: 478 case RT5682_PLL_CTRL_1: 479 case RT5682_PLL_CTRL_2: 480 case RT5682_PLL_TRACK_1: 481 case RT5682_PLL_TRACK_2: 482 case RT5682_PLL_TRACK_3: 483 case RT5682_PLL_TRACK_4: 484 case RT5682_PLL_TRACK_5: 485 case RT5682_PLL_TRACK_6: 486 case RT5682_PLL_TRACK_11: 487 case RT5682_SDW_REF_CLK: 488 case RT5682_DEPOP_1: 489 case RT5682_DEPOP_2: 490 case RT5682_HP_CHARGE_PUMP_1: 491 case RT5682_HP_CHARGE_PUMP_2: 492 case RT5682_MICBIAS_1: 493 case RT5682_MICBIAS_2: 494 case RT5682_PLL_TRACK_12: 495 case RT5682_PLL_TRACK_14: 496 case RT5682_PLL2_CTRL_1: 497 case RT5682_PLL2_CTRL_2: 498 case RT5682_PLL2_CTRL_3: 499 case RT5682_PLL2_CTRL_4: 500 case RT5682_RC_CLK_CTRL: 501 case RT5682_I2S_M_CLK_CTRL_1: 502 case RT5682_I2S2_F_DIV_CTRL_1: 503 case RT5682_I2S2_F_DIV_CTRL_2: 504 case RT5682_EQ_CTRL_1: 505 case RT5682_EQ_CTRL_2: 506 case RT5682_IRQ_CTRL_1: 507 case RT5682_IRQ_CTRL_2: 508 case RT5682_IRQ_CTRL_3: 509 case RT5682_IRQ_CTRL_4: 510 case RT5682_INT_ST_1: 511 case RT5682_GPIO_CTRL_1: 512 case RT5682_GPIO_CTRL_2: 513 case RT5682_GPIO_CTRL_3: 514 case RT5682_HP_AMP_DET_CTRL_1: 515 case RT5682_HP_AMP_DET_CTRL_2: 516 case RT5682_MID_HP_AMP_DET: 517 case RT5682_LOW_HP_AMP_DET: 518 case RT5682_DELAY_BUF_CTRL: 519 case RT5682_SV_ZCD_1: 520 case RT5682_SV_ZCD_2: 521 case RT5682_IL_CMD_1: 522 case RT5682_IL_CMD_2: 523 case RT5682_IL_CMD_3: 524 case RT5682_IL_CMD_4: 525 case RT5682_IL_CMD_5: 526 case RT5682_IL_CMD_6: 527 case RT5682_4BTN_IL_CMD_1: 528 case RT5682_4BTN_IL_CMD_2: 529 case RT5682_4BTN_IL_CMD_3: 530 case RT5682_4BTN_IL_CMD_4: 531 case RT5682_4BTN_IL_CMD_5: 532 case RT5682_4BTN_IL_CMD_6: 533 case RT5682_4BTN_IL_CMD_7: 534 case RT5682_ADC_STO1_HP_CTRL_1: 535 case RT5682_ADC_STO1_HP_CTRL_2: 536 case RT5682_AJD1_CTRL: 537 case RT5682_JD1_THD: 538 case RT5682_JD2_THD: 539 case RT5682_JD_CTRL_1: 540 case RT5682_DUMMY_1: 541 case RT5682_DUMMY_2: 542 case RT5682_DUMMY_3: 543 case RT5682_DAC_ADC_DIG_VOL1: 544 case RT5682_BIAS_CUR_CTRL_2: 545 case RT5682_BIAS_CUR_CTRL_3: 546 case RT5682_BIAS_CUR_CTRL_4: 547 case RT5682_BIAS_CUR_CTRL_5: 548 case RT5682_BIAS_CUR_CTRL_6: 549 case RT5682_BIAS_CUR_CTRL_7: 550 case RT5682_BIAS_CUR_CTRL_8: 551 case RT5682_BIAS_CUR_CTRL_9: 552 case RT5682_BIAS_CUR_CTRL_10: 553 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 554 case RT5682_CHARGE_PUMP_1: 555 case RT5682_DIG_IN_CTRL_1: 556 case RT5682_PAD_DRIVING_CTRL: 557 case RT5682_SOFT_RAMP_DEPOP: 558 case RT5682_CHOP_DAC: 559 case RT5682_CHOP_ADC: 560 case RT5682_CALIB_ADC_CTRL: 561 case RT5682_VOL_TEST: 562 case RT5682_SPKVDD_DET_STA: 563 case RT5682_TEST_MODE_CTRL_1: 564 case RT5682_TEST_MODE_CTRL_2: 565 case RT5682_TEST_MODE_CTRL_3: 566 case RT5682_TEST_MODE_CTRL_4: 567 case RT5682_TEST_MODE_CTRL_5: 568 case RT5682_PLL1_INTERNAL: 569 case RT5682_PLL2_INTERNAL: 570 case RT5682_STO_NG2_CTRL_1: 571 case RT5682_STO_NG2_CTRL_2: 572 case RT5682_STO_NG2_CTRL_3: 573 case RT5682_STO_NG2_CTRL_4: 574 case RT5682_STO_NG2_CTRL_5: 575 case RT5682_STO_NG2_CTRL_6: 576 case RT5682_STO_NG2_CTRL_7: 577 case RT5682_STO_NG2_CTRL_8: 578 case RT5682_STO_NG2_CTRL_9: 579 case RT5682_STO_NG2_CTRL_10: 580 case RT5682_STO1_DAC_SIL_DET: 581 case RT5682_SIL_PSV_CTRL1: 582 case RT5682_SIL_PSV_CTRL2: 583 case RT5682_SIL_PSV_CTRL3: 584 case RT5682_SIL_PSV_CTRL4: 585 case RT5682_SIL_PSV_CTRL5: 586 case RT5682_HP_IMP_SENS_CTRL_01: 587 case RT5682_HP_IMP_SENS_CTRL_02: 588 case RT5682_HP_IMP_SENS_CTRL_03: 589 case RT5682_HP_IMP_SENS_CTRL_04: 590 case RT5682_HP_IMP_SENS_CTRL_05: 591 case RT5682_HP_IMP_SENS_CTRL_06: 592 case RT5682_HP_IMP_SENS_CTRL_07: 593 case RT5682_HP_IMP_SENS_CTRL_08: 594 case RT5682_HP_IMP_SENS_CTRL_09: 595 case RT5682_HP_IMP_SENS_CTRL_10: 596 case RT5682_HP_IMP_SENS_CTRL_11: 597 case RT5682_HP_IMP_SENS_CTRL_12: 598 case RT5682_HP_IMP_SENS_CTRL_13: 599 case RT5682_HP_IMP_SENS_CTRL_14: 600 case RT5682_HP_IMP_SENS_CTRL_15: 601 case RT5682_HP_IMP_SENS_CTRL_16: 602 case RT5682_HP_IMP_SENS_CTRL_17: 603 case RT5682_HP_IMP_SENS_CTRL_18: 604 case RT5682_HP_IMP_SENS_CTRL_19: 605 case RT5682_HP_IMP_SENS_CTRL_20: 606 case RT5682_HP_IMP_SENS_CTRL_21: 607 case RT5682_HP_IMP_SENS_CTRL_22: 608 case RT5682_HP_IMP_SENS_CTRL_23: 609 case RT5682_HP_IMP_SENS_CTRL_24: 610 case RT5682_HP_IMP_SENS_CTRL_25: 611 case RT5682_HP_IMP_SENS_CTRL_26: 612 case RT5682_HP_IMP_SENS_CTRL_27: 613 case RT5682_HP_IMP_SENS_CTRL_28: 614 case RT5682_HP_IMP_SENS_CTRL_29: 615 case RT5682_HP_IMP_SENS_CTRL_30: 616 case RT5682_HP_IMP_SENS_CTRL_31: 617 case RT5682_HP_IMP_SENS_CTRL_32: 618 case RT5682_HP_IMP_SENS_CTRL_33: 619 case RT5682_HP_IMP_SENS_CTRL_34: 620 case RT5682_HP_IMP_SENS_CTRL_35: 621 case RT5682_HP_IMP_SENS_CTRL_36: 622 case RT5682_HP_IMP_SENS_CTRL_37: 623 case RT5682_HP_IMP_SENS_CTRL_38: 624 case RT5682_HP_IMP_SENS_CTRL_39: 625 case RT5682_HP_IMP_SENS_CTRL_40: 626 case RT5682_HP_IMP_SENS_CTRL_41: 627 case RT5682_HP_IMP_SENS_CTRL_42: 628 case RT5682_HP_IMP_SENS_CTRL_43: 629 case RT5682_HP_LOGIC_CTRL_1: 630 case RT5682_HP_LOGIC_CTRL_2: 631 case RT5682_HP_LOGIC_CTRL_3: 632 case RT5682_HP_CALIB_CTRL_1: 633 case RT5682_HP_CALIB_CTRL_2: 634 case RT5682_HP_CALIB_CTRL_3: 635 case RT5682_HP_CALIB_CTRL_4: 636 case RT5682_HP_CALIB_CTRL_5: 637 case RT5682_HP_CALIB_CTRL_6: 638 case RT5682_HP_CALIB_CTRL_7: 639 case RT5682_HP_CALIB_CTRL_9: 640 case RT5682_HP_CALIB_CTRL_10: 641 case RT5682_HP_CALIB_CTRL_11: 642 case RT5682_HP_CALIB_STA_1: 643 case RT5682_HP_CALIB_STA_2: 644 case RT5682_HP_CALIB_STA_3: 645 case RT5682_HP_CALIB_STA_4: 646 case RT5682_HP_CALIB_STA_5: 647 case RT5682_HP_CALIB_STA_6: 648 case RT5682_HP_CALIB_STA_7: 649 case RT5682_HP_CALIB_STA_8: 650 case RT5682_HP_CALIB_STA_9: 651 case RT5682_HP_CALIB_STA_10: 652 case RT5682_HP_CALIB_STA_11: 653 case RT5682_SAR_IL_CMD_1: 654 case RT5682_SAR_IL_CMD_2: 655 case RT5682_SAR_IL_CMD_3: 656 case RT5682_SAR_IL_CMD_4: 657 case RT5682_SAR_IL_CMD_5: 658 case RT5682_SAR_IL_CMD_6: 659 case RT5682_SAR_IL_CMD_7: 660 case RT5682_SAR_IL_CMD_8: 661 case RT5682_SAR_IL_CMD_9: 662 case RT5682_SAR_IL_CMD_10: 663 case RT5682_SAR_IL_CMD_11: 664 case RT5682_SAR_IL_CMD_12: 665 case RT5682_SAR_IL_CMD_13: 666 case RT5682_EFUSE_CTRL_1: 667 case RT5682_EFUSE_CTRL_2: 668 case RT5682_EFUSE_CTRL_3: 669 case RT5682_EFUSE_CTRL_4: 670 case RT5682_EFUSE_CTRL_5: 671 case RT5682_EFUSE_CTRL_6: 672 case RT5682_EFUSE_CTRL_7: 673 case RT5682_EFUSE_CTRL_8: 674 case RT5682_EFUSE_CTRL_9: 675 case RT5682_EFUSE_CTRL_10: 676 case RT5682_EFUSE_CTRL_11: 677 case RT5682_JD_TOP_VC_VTRL: 678 case RT5682_DRC1_CTRL_0: 679 case RT5682_DRC1_CTRL_1: 680 case RT5682_DRC1_CTRL_2: 681 case RT5682_DRC1_CTRL_3: 682 case RT5682_DRC1_CTRL_4: 683 case RT5682_DRC1_CTRL_5: 684 case RT5682_DRC1_CTRL_6: 685 case RT5682_DRC1_HARD_LMT_CTRL_1: 686 case RT5682_DRC1_HARD_LMT_CTRL_2: 687 case RT5682_DRC1_PRIV_1: 688 case RT5682_DRC1_PRIV_2: 689 case RT5682_DRC1_PRIV_3: 690 case RT5682_DRC1_PRIV_4: 691 case RT5682_DRC1_PRIV_5: 692 case RT5682_DRC1_PRIV_6: 693 case RT5682_DRC1_PRIV_7: 694 case RT5682_DRC1_PRIV_8: 695 case RT5682_EQ_AUTO_RCV_CTRL1: 696 case RT5682_EQ_AUTO_RCV_CTRL2: 697 case RT5682_EQ_AUTO_RCV_CTRL3: 698 case RT5682_EQ_AUTO_RCV_CTRL4: 699 case RT5682_EQ_AUTO_RCV_CTRL5: 700 case RT5682_EQ_AUTO_RCV_CTRL6: 701 case RT5682_EQ_AUTO_RCV_CTRL7: 702 case RT5682_EQ_AUTO_RCV_CTRL8: 703 case RT5682_EQ_AUTO_RCV_CTRL9: 704 case RT5682_EQ_AUTO_RCV_CTRL10: 705 case RT5682_EQ_AUTO_RCV_CTRL11: 706 case RT5682_EQ_AUTO_RCV_CTRL12: 707 case RT5682_EQ_AUTO_RCV_CTRL13: 708 case RT5682_ADC_L_EQ_LPF1_A1: 709 case RT5682_R_EQ_LPF1_A1: 710 case RT5682_L_EQ_LPF1_H0: 711 case RT5682_R_EQ_LPF1_H0: 712 case RT5682_L_EQ_BPF1_A1: 713 case RT5682_R_EQ_BPF1_A1: 714 case RT5682_L_EQ_BPF1_A2: 715 case RT5682_R_EQ_BPF1_A2: 716 case RT5682_L_EQ_BPF1_H0: 717 case RT5682_R_EQ_BPF1_H0: 718 case RT5682_L_EQ_BPF2_A1: 719 case RT5682_R_EQ_BPF2_A1: 720 case RT5682_L_EQ_BPF2_A2: 721 case RT5682_R_EQ_BPF2_A2: 722 case RT5682_L_EQ_BPF2_H0: 723 case RT5682_R_EQ_BPF2_H0: 724 case RT5682_L_EQ_BPF3_A1: 725 case RT5682_R_EQ_BPF3_A1: 726 case RT5682_L_EQ_BPF3_A2: 727 case RT5682_R_EQ_BPF3_A2: 728 case RT5682_L_EQ_BPF3_H0: 729 case RT5682_R_EQ_BPF3_H0: 730 case RT5682_L_EQ_BPF4_A1: 731 case RT5682_R_EQ_BPF4_A1: 732 case RT5682_L_EQ_BPF4_A2: 733 case RT5682_R_EQ_BPF4_A2: 734 case RT5682_L_EQ_BPF4_H0: 735 case RT5682_R_EQ_BPF4_H0: 736 case RT5682_L_EQ_HPF1_A1: 737 case RT5682_R_EQ_HPF1_A1: 738 case RT5682_L_EQ_HPF1_H0: 739 case RT5682_R_EQ_HPF1_H0: 740 case RT5682_L_EQ_PRE_VOL: 741 case RT5682_R_EQ_PRE_VOL: 742 case RT5682_L_EQ_POST_VOL: 743 case RT5682_R_EQ_POST_VOL: 744 case RT5682_I2C_MODE: 745 return true; 746 default: 747 return false; 748 } 749 } 750 EXPORT_SYMBOL_GPL(rt5682_readable_register); 751 752 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 753 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 754 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 755 756 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 757 static const DECLARE_TLV_DB_RANGE(bst_tlv, 758 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 759 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 760 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 761 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 762 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 763 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 764 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 765 ); 766 767 /* Interface data select */ 768 static const char * const rt5682_data_select[] = { 769 "L/R", "R/L", "L/L", "R/R" 770 }; 771 772 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 773 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 774 775 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 776 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 777 778 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 779 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 780 781 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 782 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 783 784 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 785 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 786 787 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 788 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 789 790 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 791 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 792 793 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 794 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 795 796 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 797 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 798 799 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 800 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 801 802 static const char * const rt5682_dac_select[] = { 803 "IF1", "SOUND" 804 }; 805 806 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 807 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 808 809 static const struct snd_kcontrol_new rt5682_dac_l_mux = 810 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 811 812 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 813 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 814 815 static const struct snd_kcontrol_new rt5682_dac_r_mux = 816 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 817 818 void rt5682_reset(struct rt5682_priv *rt5682) 819 { 820 regmap_write(rt5682->regmap, RT5682_RESET, 0); 821 if (!rt5682->is_sdw) 822 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 823 } 824 EXPORT_SYMBOL_GPL(rt5682_reset); 825 826 /** 827 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 828 * @component: SoC audio component device. 829 * @filter_mask: mask of filters. 830 * @clk_src: clock source 831 * 832 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 833 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 834 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 835 * ASRC function will track i2s clock and generate a corresponding system clock 836 * for codec. This function provides an API to select the clock source for a 837 * set of filters specified by the mask. And the component driver will turn on 838 * ASRC for these filters if ASRC is selected as their clock source. 839 */ 840 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 841 unsigned int filter_mask, unsigned int clk_src) 842 { 843 switch (clk_src) { 844 case RT5682_CLK_SEL_SYS: 845 case RT5682_CLK_SEL_I2S1_ASRC: 846 case RT5682_CLK_SEL_I2S2_ASRC: 847 break; 848 849 default: 850 return -EINVAL; 851 } 852 853 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 854 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 855 RT5682_FILTER_CLK_SEL_MASK, 856 clk_src << RT5682_FILTER_CLK_SEL_SFT); 857 } 858 859 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 860 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 861 RT5682_FILTER_CLK_SEL_MASK, 862 clk_src << RT5682_FILTER_CLK_SEL_SFT); 863 } 864 865 return 0; 866 } 867 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 868 869 static int rt5682_button_detect(struct snd_soc_component *component) 870 { 871 int btn_type, val; 872 873 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1); 874 btn_type = val & 0xfff0; 875 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 876 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 877 snd_soc_component_update_bits(component, 878 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 879 880 return btn_type; 881 } 882 883 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 884 bool enable) 885 { 886 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 887 888 if (enable) { 889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 890 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 891 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 892 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 893 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 894 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 895 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 896 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 897 if (rt5682->is_sdw) 898 snd_soc_component_update_bits(component, 899 RT5682_IRQ_CTRL_3, 900 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 901 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 902 else 903 snd_soc_component_update_bits(component, 904 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 905 RT5682_IL_IRQ_EN); 906 } else { 907 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 908 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 909 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 910 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 911 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 912 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 913 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 914 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 915 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 916 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 917 } 918 } 919 920 /** 921 * rt5682_headset_detect - Detect headset. 922 * @component: SoC audio component device. 923 * @jack_insert: Jack insert or not. 924 * 925 * Detect whether is headset or not when jack inserted. 926 * 927 * Returns detect status. 928 */ 929 static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 930 { 931 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 932 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 933 unsigned int val, count; 934 935 if (jack_insert) { 936 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 937 RT5682_PWR_VREF2 | RT5682_PWR_MB, 938 RT5682_PWR_VREF2 | RT5682_PWR_MB); 939 snd_soc_component_update_bits(component, 940 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 941 usleep_range(15000, 20000); 942 snd_soc_component_update_bits(component, 943 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 944 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 945 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 946 snd_soc_component_update_bits(component, 947 RT5682_HP_CHARGE_PUMP_1, 948 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 949 rt5682_enable_push_button_irq(component, false); 950 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 951 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 952 usleep_range(55000, 60000); 953 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 954 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 955 956 count = 0; 957 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2) 958 & RT5682_JACK_TYPE_MASK; 959 while (val == 0 && count < 50) { 960 usleep_range(10000, 15000); 961 val = snd_soc_component_read(component, 962 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 963 count++; 964 } 965 966 switch (val) { 967 case 0x1: 968 case 0x2: 969 rt5682->jack_type = SND_JACK_HEADSET; 970 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 971 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN); 972 rt5682_enable_push_button_irq(component, true); 973 break; 974 default: 975 rt5682->jack_type = SND_JACK_HEADPHONE; 976 break; 977 } 978 979 snd_soc_component_update_bits(component, 980 RT5682_HP_CHARGE_PUMP_1, 981 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 982 RT5682_OSW_L_EN | RT5682_OSW_R_EN); 983 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 984 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 985 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 986 } else { 987 rt5682_enable_push_button_irq(component, false); 988 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 989 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 990 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") && 991 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 992 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 993 snd_soc_component_update_bits(component, 994 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 995 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") && 996 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 997 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 998 snd_soc_component_update_bits(component, 999 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1000 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 1001 RT5682_PWR_CBJ, 0); 1002 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 1003 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 1004 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 1005 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 1006 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS); 1007 1008 rt5682->jack_type = 0; 1009 } 1010 1011 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 1012 return rt5682->jack_type; 1013 } 1014 1015 static int rt5682_set_jack_detect(struct snd_soc_component *component, 1016 struct snd_soc_jack *hs_jack, void *data) 1017 { 1018 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1019 1020 rt5682->hs_jack = hs_jack; 1021 1022 if (rt5682->is_sdw && !rt5682->first_hw_init) 1023 return 0; 1024 1025 if (!hs_jack) { 1026 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1027 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1028 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1029 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1030 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1031 1032 return 0; 1033 } 1034 1035 if (!rt5682->is_sdw) { 1036 switch (rt5682->pdata.jd_src) { 1037 case RT5682_JD1: 1038 snd_soc_component_update_bits(component, 1039 RT5682_CBJ_CTRL_5, 0x0700, 0x0600); 1040 snd_soc_component_update_bits(component, 1041 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1042 RT5682_EXT_JD_SRC_MANUAL); 1043 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1044 0xd142); 1045 snd_soc_component_update_bits(component, 1046 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1047 RT5682_CBJ_IN_BUF_EN); 1048 snd_soc_component_update_bits(component, 1049 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1050 RT5682_SAR_POW_EN); 1051 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1052 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1053 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1054 RT5682_POW_IRQ | RT5682_POW_JDH | 1055 RT5682_POW_ANA, RT5682_POW_IRQ | 1056 RT5682_POW_JDH | RT5682_POW_ANA); 1057 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1058 RT5682_PWR_JDH, RT5682_PWR_JDH); 1059 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1060 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1061 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1062 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1063 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1064 rt5682->pdata.btndet_delay)); 1065 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1066 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1067 rt5682->pdata.btndet_delay)); 1068 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1069 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1070 rt5682->pdata.btndet_delay)); 1071 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1072 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1073 rt5682->pdata.btndet_delay)); 1074 mod_delayed_work(system_power_efficient_wq, 1075 &rt5682->jack_detect_work, 1076 msecs_to_jiffies(250)); 1077 break; 1078 1079 case RT5682_JD_NULL: 1080 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1081 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1082 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1083 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1084 break; 1085 1086 default: 1087 dev_warn(component->dev, "Wrong JD source\n"); 1088 break; 1089 } 1090 } 1091 1092 return 0; 1093 } 1094 1095 void rt5682_jack_detect_handler(struct work_struct *work) 1096 { 1097 struct rt5682_priv *rt5682 = 1098 container_of(work, struct rt5682_priv, jack_detect_work.work); 1099 struct snd_soc_dapm_context *dapm; 1100 int val, btn_type; 1101 1102 if (!rt5682->component || 1103 !snd_soc_card_is_instantiated(rt5682->component->card)) { 1104 /* card not yet ready, try later */ 1105 mod_delayed_work(system_power_efficient_wq, 1106 &rt5682->jack_detect_work, msecs_to_jiffies(15)); 1107 return; 1108 } 1109 1110 if (rt5682->is_sdw) { 1111 if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) { 1112 dev_dbg(&rt5682->slave->dev, 1113 "%s: parent device is pm_runtime_status_suspended, skipping jack detection\n", 1114 __func__); 1115 return; 1116 } 1117 } 1118 1119 dapm = snd_soc_component_to_dapm(rt5682->component); 1120 1121 snd_soc_dapm_mutex_lock(dapm); 1122 mutex_lock(&rt5682->calibrate_mutex); 1123 1124 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) 1125 & RT5682_JDH_RS_MASK; 1126 if (!val) { 1127 /* jack in */ 1128 if (rt5682->jack_type == 0) { 1129 /* jack was out, report jack type */ 1130 rt5682->jack_type = 1131 rt5682_headset_detect(rt5682->component, 1); 1132 rt5682->irq_work_delay_time = 0; 1133 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == 1134 SND_JACK_HEADSET) { 1135 /* jack is already in, report button event */ 1136 rt5682->jack_type = SND_JACK_HEADSET; 1137 btn_type = rt5682_button_detect(rt5682->component); 1138 /** 1139 * rt5682 can report three kinds of button behavior, 1140 * one click, double click and hold. However, 1141 * currently we will report button pressed/released 1142 * event. So all the three button behaviors are 1143 * treated as button pressed. 1144 */ 1145 switch (btn_type) { 1146 case 0x8000: 1147 case 0x4000: 1148 case 0x2000: 1149 rt5682->jack_type |= SND_JACK_BTN_0; 1150 break; 1151 case 0x1000: 1152 case 0x0800: 1153 case 0x0400: 1154 rt5682->jack_type |= SND_JACK_BTN_1; 1155 break; 1156 case 0x0200: 1157 case 0x0100: 1158 case 0x0080: 1159 rt5682->jack_type |= SND_JACK_BTN_2; 1160 break; 1161 case 0x0040: 1162 case 0x0020: 1163 case 0x0010: 1164 rt5682->jack_type |= SND_JACK_BTN_3; 1165 break; 1166 case 0x0000: /* unpressed */ 1167 break; 1168 default: 1169 dev_err(rt5682->component->dev, 1170 "Unexpected button code 0x%04x\n", 1171 btn_type); 1172 break; 1173 } 1174 } 1175 } else { 1176 /* jack out */ 1177 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1178 rt5682->irq_work_delay_time = 50; 1179 } 1180 1181 mutex_unlock(&rt5682->calibrate_mutex); 1182 snd_soc_dapm_mutex_unlock(dapm); 1183 1184 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1185 SND_JACK_HEADSET | 1186 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1187 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1188 1189 if (!rt5682->is_sdw) { 1190 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1191 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1192 schedule_delayed_work(&rt5682->jd_check_work, 0); 1193 else 1194 cancel_delayed_work_sync(&rt5682->jd_check_work); 1195 } 1196 } 1197 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1198 1199 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1200 /* DAC Digital Volume */ 1201 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1202 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1203 1204 /* IN Boost Volume */ 1205 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1206 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1207 1208 /* ADC Digital Volume Control */ 1209 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1210 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1211 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1212 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1213 1214 /* ADC Boost Volume Control */ 1215 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1216 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1217 3, 0, adc_bst_tlv), 1218 }; 1219 1220 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1221 int target, const int div[], int size) 1222 { 1223 int i; 1224 1225 if (rt5682->sysclk < target) { 1226 dev_err(rt5682->component->dev, 1227 "sysclk rate %d is too low\n", rt5682->sysclk); 1228 return 0; 1229 } 1230 1231 for (i = 0; i < size - 1; i++) { 1232 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1233 if (target * div[i] == rt5682->sysclk) 1234 return i; 1235 if (target * div[i + 1] > rt5682->sysclk) { 1236 dev_dbg(rt5682->component->dev, 1237 "can't find div for sysclk %d\n", 1238 rt5682->sysclk); 1239 return i; 1240 } 1241 } 1242 1243 if (target * div[i] < rt5682->sysclk) 1244 dev_err(rt5682->component->dev, 1245 "sysclk rate %d is too high\n", rt5682->sysclk); 1246 1247 return size - 1; 1248 } 1249 1250 /** 1251 * set_dmic_clk - Set parameter of dmic. 1252 * 1253 * @w: DAPM widget. 1254 * @kcontrol: The kcontrol of this widget. 1255 * @event: Event id. 1256 * 1257 * Choose dmic clock between 1MHz and 3MHz. 1258 * It is better for clock to approximate 3MHz. 1259 */ 1260 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1261 struct snd_kcontrol *kcontrol, int event) 1262 { 1263 struct snd_soc_component *component = 1264 snd_soc_dapm_to_component(w->dapm); 1265 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1266 int idx, dmic_clk_rate = 3072000; 1267 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1268 1269 if (rt5682->pdata.dmic_clk_rate) 1270 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1271 1272 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1273 1274 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1275 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1276 1277 return 0; 1278 } 1279 1280 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1281 struct snd_kcontrol *kcontrol, int event) 1282 { 1283 struct snd_soc_component *component = 1284 snd_soc_dapm_to_component(w->dapm); 1285 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1286 int ref, val, reg, idx; 1287 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1288 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1289 1290 if (rt5682->is_sdw) 1291 return 0; 1292 1293 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) & 1294 RT5682_GP4_PIN_MASK; 1295 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1296 val == RT5682_GP4_PIN_ADCDAT2) 1297 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1298 else 1299 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1300 1301 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1302 1303 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1304 reg = RT5682_PLL_TRACK_3; 1305 else 1306 reg = RT5682_PLL_TRACK_2; 1307 1308 snd_soc_component_update_bits(component, reg, 1309 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1310 1311 /* select over sample rate */ 1312 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1313 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1314 break; 1315 } 1316 1317 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1318 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1319 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1320 1321 return 0; 1322 } 1323 1324 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1325 struct snd_soc_dapm_widget *sink) 1326 { 1327 unsigned int val; 1328 struct snd_soc_component *component = 1329 snd_soc_dapm_to_component(w->dapm); 1330 1331 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1332 val &= RT5682_SCLK_SRC_MASK; 1333 if (val == RT5682_SCLK_SRC_PLL1) 1334 return 1; 1335 else 1336 return 0; 1337 } 1338 1339 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1340 struct snd_soc_dapm_widget *sink) 1341 { 1342 unsigned int val; 1343 struct snd_soc_component *component = 1344 snd_soc_dapm_to_component(w->dapm); 1345 1346 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1347 val &= RT5682_SCLK_SRC_MASK; 1348 if (val == RT5682_SCLK_SRC_PLL2) 1349 return 1; 1350 else 1351 return 0; 1352 } 1353 1354 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1355 struct snd_soc_dapm_widget *sink) 1356 { 1357 unsigned int reg, shift, val; 1358 struct snd_soc_component *component = 1359 snd_soc_dapm_to_component(w->dapm); 1360 1361 switch (w->shift) { 1362 case RT5682_ADC_STO1_ASRC_SFT: 1363 reg = RT5682_PLL_TRACK_3; 1364 shift = RT5682_FILTER_CLK_SEL_SFT; 1365 break; 1366 case RT5682_DAC_STO1_ASRC_SFT: 1367 reg = RT5682_PLL_TRACK_2; 1368 shift = RT5682_FILTER_CLK_SEL_SFT; 1369 break; 1370 default: 1371 return 0; 1372 } 1373 1374 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1375 switch (val) { 1376 case RT5682_CLK_SEL_I2S1_ASRC: 1377 case RT5682_CLK_SEL_I2S2_ASRC: 1378 return 1; 1379 default: 1380 return 0; 1381 } 1382 } 1383 1384 /* Digital Mixer */ 1385 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1386 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1387 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1388 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1389 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1390 }; 1391 1392 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1393 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1394 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1395 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1396 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1397 }; 1398 1399 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1400 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1401 RT5682_M_ADCMIX_L_SFT, 1, 1), 1402 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1403 RT5682_M_DAC1_L_SFT, 1, 1), 1404 }; 1405 1406 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1407 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1408 RT5682_M_ADCMIX_R_SFT, 1, 1), 1409 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1410 RT5682_M_DAC1_R_SFT, 1, 1), 1411 }; 1412 1413 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1414 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1415 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1416 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1417 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1418 }; 1419 1420 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1421 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1422 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1423 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1424 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1425 }; 1426 1427 /* Analog Input Mixer */ 1428 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1429 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1430 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1431 }; 1432 1433 /* STO1 ADC1 Source */ 1434 /* MX-26 [13] [5] */ 1435 static const char * const rt5682_sto1_adc1_src[] = { 1436 "DAC MIX", "ADC" 1437 }; 1438 1439 static SOC_ENUM_SINGLE_DECL( 1440 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1441 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1442 1443 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1444 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1445 1446 static SOC_ENUM_SINGLE_DECL( 1447 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1448 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1449 1450 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1451 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1452 1453 /* STO1 ADC Source */ 1454 /* MX-26 [11:10] [3:2] */ 1455 static const char * const rt5682_sto1_adc_src[] = { 1456 "ADC1 L", "ADC1 R" 1457 }; 1458 1459 static SOC_ENUM_SINGLE_DECL( 1460 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1461 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1462 1463 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1464 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1465 1466 static SOC_ENUM_SINGLE_DECL( 1467 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1468 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1469 1470 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1471 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1472 1473 /* STO1 ADC2 Source */ 1474 /* MX-26 [12] [4] */ 1475 static const char * const rt5682_sto1_adc2_src[] = { 1476 "DAC MIX", "DMIC" 1477 }; 1478 1479 static SOC_ENUM_SINGLE_DECL( 1480 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1481 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1482 1483 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1484 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1485 1486 static SOC_ENUM_SINGLE_DECL( 1487 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1488 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1489 1490 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1491 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1492 1493 /* MX-79 [6:4] I2S1 ADC data location */ 1494 static const unsigned int rt5682_if1_adc_slot_values[] = { 1495 0, 1496 2, 1497 4, 1498 6, 1499 }; 1500 1501 static const char * const rt5682_if1_adc_slot_src[] = { 1502 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1503 }; 1504 1505 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1506 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1507 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1508 1509 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1510 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1511 1512 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1513 /* MX-2B [4], MX-2B [0]*/ 1514 static const char * const rt5682_alg_dac1_src[] = { 1515 "Stereo1 DAC Mixer", "DAC1" 1516 }; 1517 1518 static SOC_ENUM_SINGLE_DECL( 1519 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1520 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1521 1522 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1523 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1524 1525 static SOC_ENUM_SINGLE_DECL( 1526 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1527 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1528 1529 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1530 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1531 1532 /* Out Switch */ 1533 static const struct snd_kcontrol_new hpol_switch = 1534 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1535 RT5682_L_MUTE_SFT, 1, 1); 1536 static const struct snd_kcontrol_new hpor_switch = 1537 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1538 RT5682_R_MUTE_SFT, 1, 1); 1539 1540 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1541 struct snd_kcontrol *kcontrol, int event) 1542 { 1543 struct snd_soc_component *component = 1544 snd_soc_dapm_to_component(w->dapm); 1545 1546 switch (event) { 1547 case SND_SOC_DAPM_PRE_PMU: 1548 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1549 RT5682_HP_C2_DAC_AMP_MUTE, 0); 1550 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2, 1551 RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG); 1552 snd_soc_component_update_bits(component, 1553 RT5682_DEPOP_1, 0x60, 0x60); 1554 snd_soc_component_update_bits(component, 1555 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1556 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1557 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 1558 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN); 1559 usleep_range(5000, 10000); 1560 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1561 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L); 1562 break; 1563 1564 case SND_SOC_DAPM_POST_PMD: 1565 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1566 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0); 1567 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1568 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M); 1569 snd_soc_component_update_bits(component, 1570 RT5682_DEPOP_1, 0x60, 0x0); 1571 snd_soc_component_update_bits(component, 1572 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1573 break; 1574 } 1575 1576 return 0; 1577 } 1578 1579 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1580 struct snd_kcontrol *kcontrol, int event) 1581 { 1582 struct snd_soc_component *component = 1583 snd_soc_dapm_to_component(w->dapm); 1584 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1585 unsigned int delay = 50, val; 1586 1587 if (rt5682->pdata.dmic_delay) 1588 delay = rt5682->pdata.dmic_delay; 1589 1590 switch (event) { 1591 case SND_SOC_DAPM_POST_PMU: 1592 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1593 val &= RT5682_SCLK_SRC_MASK; 1594 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2) 1595 snd_soc_component_update_bits(component, 1596 RT5682_PWR_ANLG_1, 1597 RT5682_PWR_VREF2 | RT5682_PWR_MB, 1598 RT5682_PWR_VREF2 | RT5682_PWR_MB); 1599 1600 /*Add delay to avoid pop noise*/ 1601 msleep(delay); 1602 break; 1603 1604 case SND_SOC_DAPM_POST_PMD: 1605 if (!rt5682->jack_type) { 1606 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1607 snd_soc_component_update_bits(component, 1608 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 1609 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1610 snd_soc_component_update_bits(component, 1611 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1612 } 1613 break; 1614 } 1615 1616 return 0; 1617 } 1618 1619 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1620 struct snd_kcontrol *kcontrol, int event) 1621 { 1622 struct snd_soc_component *component = 1623 snd_soc_dapm_to_component(w->dapm); 1624 1625 switch (event) { 1626 case SND_SOC_DAPM_PRE_PMU: 1627 switch (w->shift) { 1628 case RT5682_PWR_VREF1_BIT: 1629 snd_soc_component_update_bits(component, 1630 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1631 break; 1632 1633 case RT5682_PWR_VREF2_BIT: 1634 snd_soc_component_update_bits(component, 1635 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1636 break; 1637 } 1638 break; 1639 1640 case SND_SOC_DAPM_POST_PMU: 1641 usleep_range(15000, 20000); 1642 switch (w->shift) { 1643 case RT5682_PWR_VREF1_BIT: 1644 snd_soc_component_update_bits(component, 1645 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1646 RT5682_PWR_FV1); 1647 break; 1648 1649 case RT5682_PWR_VREF2_BIT: 1650 snd_soc_component_update_bits(component, 1651 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1652 RT5682_PWR_FV2); 1653 break; 1654 } 1655 break; 1656 } 1657 1658 return 0; 1659 } 1660 1661 static const unsigned int rt5682_adcdat_pin_values[] = { 1662 1, 1663 3, 1664 }; 1665 1666 static const char * const rt5682_adcdat_pin_select[] = { 1667 "ADCDAT1", 1668 "ADCDAT2", 1669 }; 1670 1671 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1672 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1673 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1674 1675 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1676 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1677 1678 static const unsigned int rt5682_hpo_sig_out_values[] = { 1679 2, 1680 7, 1681 }; 1682 1683 static const char * const rt5682_hpo_sig_out_mode[] = { 1684 "Legacy", 1685 "OneBit", 1686 }; 1687 1688 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum, 1689 RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK, 1690 rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values); 1691 1692 static const struct snd_kcontrol_new rt5682_hpo_sig_demux = 1693 SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum); 1694 1695 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1696 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1697 0, NULL, 0), 1698 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1699 0, NULL, 0), 1700 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1701 0, NULL, 0), 1702 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1703 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1704 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1705 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1706 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1707 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1708 1709 /* ASRC */ 1710 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1711 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1712 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1713 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1714 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1715 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1716 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1717 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1718 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1719 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1720 1721 /* Input Side */ 1722 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1723 0, NULL, 0), 1724 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1725 0, NULL, 0), 1726 1727 /* Input Lines */ 1728 SND_SOC_DAPM_INPUT("DMIC L1"), 1729 SND_SOC_DAPM_INPUT("DMIC R1"), 1730 1731 SND_SOC_DAPM_INPUT("IN1P"), 1732 1733 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1734 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1735 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1736 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, 1737 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1738 1739 /* Boost */ 1740 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1741 0, 0, NULL, 0), 1742 1743 /* REC Mixer */ 1744 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1745 ARRAY_SIZE(rt5682_rec1_l_mix)), 1746 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1747 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1748 1749 /* ADCs */ 1750 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1751 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1752 1753 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1754 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1755 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1756 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1757 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1758 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1759 1760 /* ADC Mux */ 1761 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1762 &rt5682_sto1_adc1l_mux), 1763 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1764 &rt5682_sto1_adc1r_mux), 1765 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1766 &rt5682_sto1_adc2l_mux), 1767 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1768 &rt5682_sto1_adc2r_mux), 1769 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1770 &rt5682_sto1_adcl_mux), 1771 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1772 &rt5682_sto1_adcr_mux), 1773 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1774 &rt5682_if1_adc_slot_mux), 1775 1776 /* ADC Mixer */ 1777 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1778 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1779 SND_SOC_DAPM_PRE_PMU), 1780 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1781 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1782 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1783 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1784 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1785 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1786 1787 /* ADC PGA */ 1788 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1789 1790 /* Digital Interface */ 1791 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1792 0, NULL, 0), 1793 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1794 0, NULL, 0), 1795 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1796 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1797 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1798 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1799 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1800 1801 /* Digital Interface Select */ 1802 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1803 &rt5682_if1_01_adc_swap_mux), 1804 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1805 &rt5682_if1_23_adc_swap_mux), 1806 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1807 &rt5682_if1_45_adc_swap_mux), 1808 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1809 &rt5682_if1_67_adc_swap_mux), 1810 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1811 &rt5682_if2_adc_swap_mux), 1812 1813 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1814 &rt5682_adcdat_pin_ctrl), 1815 1816 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1817 &rt5682_dac_l_mux), 1818 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1819 &rt5682_dac_r_mux), 1820 1821 /* Audio Interface */ 1822 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1823 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1824 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1825 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1826 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1827 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1828 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1829 1830 /* Output Side */ 1831 /* DAC mixer before sound effect */ 1832 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1833 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1834 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1835 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1836 1837 /* DAC channel Mux */ 1838 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1839 &rt5682_alg_dac_l1_mux), 1840 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1841 &rt5682_alg_dac_r1_mux), 1842 1843 /* DAC Mixer */ 1844 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1845 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1846 SND_SOC_DAPM_PRE_PMU), 1847 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1848 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1849 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1850 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1851 1852 /* DACs */ 1853 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1854 RT5682_PWR_DAC_L1_BIT, 0), 1855 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1856 RT5682_PWR_DAC_R1_BIT, 0), 1857 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1858 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1859 1860 /* HPO */ 1861 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1862 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1863 1864 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1865 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1866 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1867 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1868 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1869 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1870 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1871 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1872 1873 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1874 &hpol_switch), 1875 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1876 &hpor_switch), 1877 1878 SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0), 1879 SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0), 1880 SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux), 1881 1882 /* CLK DET */ 1883 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1884 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1885 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1886 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1887 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1888 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1889 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1890 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1891 1892 /* Output Lines */ 1893 SND_SOC_DAPM_OUTPUT("HPOL"), 1894 SND_SOC_DAPM_OUTPUT("HPOR"), 1895 }; 1896 1897 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1898 /*PLL*/ 1899 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1900 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1901 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1902 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1903 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1904 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1905 1906 /*ASRC*/ 1907 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1908 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1909 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1910 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1911 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1912 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1913 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1914 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1915 1916 /*Vref*/ 1917 {"MICBIAS1", NULL, "Vref1"}, 1918 {"MICBIAS2", NULL, "Vref1"}, 1919 1920 {"CLKDET SYS", NULL, "CLKDET"}, 1921 1922 {"BST1 CBJ", NULL, "IN1P"}, 1923 1924 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1925 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1926 1927 {"ADC1 L", NULL, "RECMIX1L"}, 1928 {"ADC1 L", NULL, "ADC1 L Power"}, 1929 {"ADC1 L", NULL, "ADC1 clock"}, 1930 1931 {"DMIC L1", NULL, "DMIC CLK"}, 1932 {"DMIC L1", NULL, "DMIC1 Power"}, 1933 {"DMIC R1", NULL, "DMIC CLK"}, 1934 {"DMIC R1", NULL, "DMIC1 Power"}, 1935 {"DMIC CLK", NULL, "DMIC ASRC"}, 1936 1937 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1938 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1939 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1940 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1941 1942 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1943 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1944 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1945 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1946 1947 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1948 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1949 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1950 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1951 1952 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1953 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1954 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1955 1956 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1957 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1958 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1959 1960 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1961 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1962 1963 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1964 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1965 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1966 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1967 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1968 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1969 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1970 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1971 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1972 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1973 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1974 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1975 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1976 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1977 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1978 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1979 1980 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1981 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1982 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1983 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1984 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1985 {"AIF1TX", NULL, "I2S1"}, 1986 {"AIF1TX", NULL, "ADCDAT Mux"}, 1987 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1988 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1989 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1990 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1991 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1992 {"AIF2TX", NULL, "ADCDAT Mux"}, 1993 1994 {"SDWTX", NULL, "PLL2B"}, 1995 {"SDWTX", NULL, "PLL2F"}, 1996 {"SDWTX", NULL, "ADCDAT Mux"}, 1997 1998 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1999 {"IF1 DAC1 L", NULL, "I2S1"}, 2000 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 2001 {"IF1 DAC1 R", NULL, "AIF1RX"}, 2002 {"IF1 DAC1 R", NULL, "I2S1"}, 2003 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 2004 2005 {"SOUND DAC L", NULL, "SDWRX"}, 2006 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 2007 {"SOUND DAC L", NULL, "PLL2B"}, 2008 {"SOUND DAC L", NULL, "PLL2F"}, 2009 {"SOUND DAC R", NULL, "SDWRX"}, 2010 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 2011 {"SOUND DAC R", NULL, "PLL2B"}, 2012 {"SOUND DAC R", NULL, "PLL2F"}, 2013 2014 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 2015 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 2016 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 2017 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 2018 2019 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 2020 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 2021 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 2022 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 2023 2024 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 2025 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 2026 2027 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 2028 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 2029 2030 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 2031 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 2032 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 2033 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 2034 2035 {"DAC L1", NULL, "DAC L1 Source"}, 2036 {"DAC R1", NULL, "DAC R1 Source"}, 2037 2038 {"DAC L1", NULL, "DAC 1 Clock"}, 2039 {"DAC R1", NULL, "DAC 1 Clock"}, 2040 2041 {"HP Amp", NULL, "DAC L1"}, 2042 {"HP Amp", NULL, "DAC R1"}, 2043 {"HP Amp", NULL, "HP Amp L"}, 2044 {"HP Amp", NULL, "HP Amp R"}, 2045 {"HP Amp", NULL, "Capless"}, 2046 {"HP Amp", NULL, "Charge Pump"}, 2047 {"HP Amp", NULL, "CLKDET SYS"}, 2048 {"HP Amp", NULL, "Vref1"}, 2049 2050 {"HPO Signal Demux", NULL, "HP Amp"}, 2051 2052 {"HPO Legacy", "Legacy", "HPO Signal Demux"}, 2053 {"HPO OneBit", "OneBit", "HPO Signal Demux"}, 2054 2055 {"HPOL Playback", "Switch", "HPO Legacy"}, 2056 {"HPOR Playback", "Switch", "HPO Legacy"}, 2057 2058 {"HPOL", NULL, "HPOL Playback"}, 2059 {"HPOR", NULL, "HPOR Playback"}, 2060 {"HPOL", NULL, "HPO OneBit"}, 2061 {"HPOR", NULL, "HPO OneBit"}, 2062 }; 2063 2064 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2065 unsigned int rx_mask, int slots, int slot_width) 2066 { 2067 struct snd_soc_component *component = dai->component; 2068 unsigned int cl, val = 0; 2069 2070 if (tx_mask || rx_mask) 2071 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2072 RT5682_TDM_EN, RT5682_TDM_EN); 2073 else 2074 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2075 RT5682_TDM_EN, 0); 2076 2077 switch (slots) { 2078 case 4: 2079 val |= RT5682_TDM_TX_CH_4; 2080 val |= RT5682_TDM_RX_CH_4; 2081 break; 2082 case 6: 2083 val |= RT5682_TDM_TX_CH_6; 2084 val |= RT5682_TDM_RX_CH_6; 2085 break; 2086 case 8: 2087 val |= RT5682_TDM_TX_CH_8; 2088 val |= RT5682_TDM_RX_CH_8; 2089 break; 2090 case 2: 2091 break; 2092 default: 2093 return -EINVAL; 2094 } 2095 2096 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2097 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2098 2099 switch (slot_width) { 2100 case 8: 2101 if (tx_mask || rx_mask) 2102 return -EINVAL; 2103 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2104 break; 2105 case 16: 2106 val = RT5682_TDM_CL_16; 2107 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2108 break; 2109 case 20: 2110 val = RT5682_TDM_CL_20; 2111 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2112 break; 2113 case 24: 2114 val = RT5682_TDM_CL_24; 2115 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2116 break; 2117 case 32: 2118 val = RT5682_TDM_CL_32; 2119 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2120 break; 2121 default: 2122 return -EINVAL; 2123 } 2124 2125 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2126 RT5682_TDM_CL_MASK, val); 2127 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2128 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2129 2130 return 0; 2131 } 2132 2133 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2134 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2135 { 2136 struct snd_soc_component *component = dai->component; 2137 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2138 unsigned int len_1 = 0, len_2 = 0; 2139 int pre_div, frame_size; 2140 2141 rt5682->lrck[dai->id] = params_rate(params); 2142 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2143 2144 frame_size = snd_soc_params_to_frame_size(params); 2145 if (frame_size < 0) { 2146 dev_err(component->dev, "Unsupported frame size: %d\n", 2147 frame_size); 2148 return -EINVAL; 2149 } 2150 2151 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2152 rt5682->lrck[dai->id], pre_div, dai->id); 2153 2154 switch (params_width(params)) { 2155 case 16: 2156 break; 2157 case 20: 2158 len_1 |= RT5682_I2S1_DL_20; 2159 len_2 |= RT5682_I2S2_DL_20; 2160 break; 2161 case 24: 2162 len_1 |= RT5682_I2S1_DL_24; 2163 len_2 |= RT5682_I2S2_DL_24; 2164 break; 2165 case 32: 2166 len_1 |= RT5682_I2S1_DL_32; 2167 len_2 |= RT5682_I2S2_DL_24; 2168 break; 2169 case 8: 2170 len_1 |= RT5682_I2S2_DL_8; 2171 len_2 |= RT5682_I2S2_DL_8; 2172 break; 2173 default: 2174 return -EINVAL; 2175 } 2176 2177 switch (dai->id) { 2178 case RT5682_AIF1: 2179 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2180 RT5682_I2S1_DL_MASK, len_1); 2181 if (rt5682->master[RT5682_AIF1]) { 2182 snd_soc_component_update_bits(component, 2183 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2184 RT5682_I2S_CLK_SRC_MASK, 2185 pre_div << RT5682_I2S_M_DIV_SFT | 2186 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2187 } 2188 if (params_channels(params) == 1) /* mono mode */ 2189 snd_soc_component_update_bits(component, 2190 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2191 RT5682_I2S1_MONO_EN); 2192 else 2193 snd_soc_component_update_bits(component, 2194 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2195 RT5682_I2S1_MONO_DIS); 2196 break; 2197 case RT5682_AIF2: 2198 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2199 RT5682_I2S2_DL_MASK, len_2); 2200 if (rt5682->master[RT5682_AIF2]) { 2201 snd_soc_component_update_bits(component, 2202 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2203 pre_div << RT5682_I2S2_M_PD_SFT); 2204 } 2205 if (params_channels(params) == 1) /* mono mode */ 2206 snd_soc_component_update_bits(component, 2207 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2208 RT5682_I2S2_MONO_EN); 2209 else 2210 snd_soc_component_update_bits(component, 2211 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2212 RT5682_I2S2_MONO_DIS); 2213 break; 2214 default: 2215 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2216 return -EINVAL; 2217 } 2218 2219 return 0; 2220 } 2221 2222 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2223 { 2224 struct snd_soc_component *component = dai->component; 2225 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2226 unsigned int reg_val = 0, tdm_ctrl = 0; 2227 2228 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2229 case SND_SOC_DAIFMT_CBP_CFP: 2230 rt5682->master[dai->id] = 1; 2231 break; 2232 case SND_SOC_DAIFMT_CBC_CFC: 2233 rt5682->master[dai->id] = 0; 2234 break; 2235 default: 2236 return -EINVAL; 2237 } 2238 2239 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2240 case SND_SOC_DAIFMT_NB_NF: 2241 break; 2242 case SND_SOC_DAIFMT_IB_NF: 2243 reg_val |= RT5682_I2S_BP_INV; 2244 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2245 break; 2246 case SND_SOC_DAIFMT_NB_IF: 2247 if (dai->id == RT5682_AIF1) 2248 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2249 else 2250 return -EINVAL; 2251 break; 2252 case SND_SOC_DAIFMT_IB_IF: 2253 if (dai->id == RT5682_AIF1) 2254 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2255 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2256 else 2257 return -EINVAL; 2258 break; 2259 default: 2260 return -EINVAL; 2261 } 2262 2263 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2264 case SND_SOC_DAIFMT_I2S: 2265 break; 2266 case SND_SOC_DAIFMT_LEFT_J: 2267 reg_val |= RT5682_I2S_DF_LEFT; 2268 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2269 break; 2270 case SND_SOC_DAIFMT_DSP_A: 2271 reg_val |= RT5682_I2S_DF_PCM_A; 2272 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2273 break; 2274 case SND_SOC_DAIFMT_DSP_B: 2275 reg_val |= RT5682_I2S_DF_PCM_B; 2276 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2277 break; 2278 default: 2279 return -EINVAL; 2280 } 2281 2282 switch (dai->id) { 2283 case RT5682_AIF1: 2284 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2285 RT5682_I2S_DF_MASK, reg_val); 2286 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2287 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2288 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2289 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2290 tdm_ctrl | rt5682->master[dai->id]); 2291 break; 2292 case RT5682_AIF2: 2293 if (rt5682->master[dai->id] == 0) 2294 reg_val |= RT5682_I2S2_MS_S; 2295 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2296 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2297 RT5682_I2S_DF_MASK, reg_val); 2298 break; 2299 default: 2300 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2301 return -EINVAL; 2302 } 2303 return 0; 2304 } 2305 2306 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2307 int clk_id, int source, unsigned int freq, int dir) 2308 { 2309 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2310 unsigned int reg_val = 0, src = 0; 2311 2312 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2313 return 0; 2314 2315 switch (clk_id) { 2316 case RT5682_SCLK_S_MCLK: 2317 reg_val |= RT5682_SCLK_SRC_MCLK; 2318 src = RT5682_CLK_SRC_MCLK; 2319 break; 2320 case RT5682_SCLK_S_PLL1: 2321 reg_val |= RT5682_SCLK_SRC_PLL1; 2322 src = RT5682_CLK_SRC_PLL1; 2323 break; 2324 case RT5682_SCLK_S_PLL2: 2325 reg_val |= RT5682_SCLK_SRC_PLL2; 2326 src = RT5682_CLK_SRC_PLL2; 2327 break; 2328 case RT5682_SCLK_S_RCCLK: 2329 reg_val |= RT5682_SCLK_SRC_RCCLK; 2330 src = RT5682_CLK_SRC_RCCLK; 2331 break; 2332 default: 2333 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2334 return -EINVAL; 2335 } 2336 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2337 RT5682_SCLK_SRC_MASK, reg_val); 2338 2339 if (rt5682->master[RT5682_AIF2]) { 2340 snd_soc_component_update_bits(component, 2341 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2342 src << RT5682_I2S2_SRC_SFT); 2343 } 2344 2345 rt5682->sysclk = freq; 2346 rt5682->sysclk_src = clk_id; 2347 2348 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2349 freq, clk_id); 2350 2351 return 0; 2352 } 2353 2354 static int rt5682_set_component_pll(struct snd_soc_component *component, 2355 int pll_id, int source, unsigned int freq_in, 2356 unsigned int freq_out) 2357 { 2358 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2359 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2360 unsigned int pll2_fout1, pll2_ps_val; 2361 int ret; 2362 2363 if (source == rt5682->pll_src[pll_id] && 2364 freq_in == rt5682->pll_in[pll_id] && 2365 freq_out == rt5682->pll_out[pll_id]) 2366 return 0; 2367 2368 if (!freq_in || !freq_out) { 2369 dev_dbg(component->dev, "PLL disabled\n"); 2370 2371 rt5682->pll_in[pll_id] = 0; 2372 rt5682->pll_out[pll_id] = 0; 2373 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2374 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2375 return 0; 2376 } 2377 2378 if (pll_id == RT5682_PLL2) { 2379 switch (source) { 2380 case RT5682_PLL2_S_MCLK: 2381 snd_soc_component_update_bits(component, 2382 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2383 RT5682_PLL2_SRC_MCLK); 2384 break; 2385 default: 2386 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2387 source); 2388 return -EINVAL; 2389 } 2390 2391 /** 2392 * PLL2 concatenates 2 PLL units. 2393 * We suggest the Fout of the front PLL is 3.84MHz. 2394 */ 2395 pll2_fout1 = 3840000; 2396 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2397 if (ret < 0) { 2398 dev_err(component->dev, "Unsupported input clock %d\n", 2399 freq_in); 2400 return ret; 2401 } 2402 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2403 freq_in, pll2_fout1, 2404 pll2f_code.m_bp, 2405 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2406 pll2f_code.n_code, pll2f_code.k_code); 2407 2408 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2409 if (ret < 0) { 2410 dev_err(component->dev, "Unsupported input clock %d\n", 2411 pll2_fout1); 2412 return ret; 2413 } 2414 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2415 pll2_fout1, freq_out, 2416 pll2b_code.m_bp, 2417 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2418 pll2b_code.n_code, pll2b_code.k_code); 2419 2420 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2421 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2422 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2423 pll2b_code.m_code); 2424 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2425 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2426 pll2b_code.n_code); 2427 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2428 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2429 2430 if (freq_out == 22579200) 2431 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 2432 else 2433 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 2434 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2435 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 2436 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2437 pll2_ps_val | 2438 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2439 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2440 0xf); 2441 } else { 2442 switch (source) { 2443 case RT5682_PLL1_S_MCLK: 2444 snd_soc_component_update_bits(component, 2445 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2446 RT5682_PLL1_SRC_MCLK); 2447 break; 2448 case RT5682_PLL1_S_BCLK1: 2449 snd_soc_component_update_bits(component, 2450 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2451 RT5682_PLL1_SRC_BCLK1); 2452 break; 2453 default: 2454 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2455 source); 2456 return -EINVAL; 2457 } 2458 2459 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2460 if (ret < 0) { 2461 dev_err(component->dev, "Unsupported input clock %d\n", 2462 freq_in); 2463 return ret; 2464 } 2465 2466 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2467 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2468 pll_code.n_code, pll_code.k_code); 2469 2470 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2471 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code); 2472 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2473 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) | 2474 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST)); 2475 } 2476 2477 rt5682->pll_in[pll_id] = freq_in; 2478 rt5682->pll_out[pll_id] = freq_out; 2479 rt5682->pll_src[pll_id] = source; 2480 2481 return 0; 2482 } 2483 2484 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2485 { 2486 struct snd_soc_component *component = dai->component; 2487 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2488 2489 rt5682->bclk[dai->id] = ratio; 2490 2491 switch (ratio) { 2492 case 256: 2493 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2494 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2495 break; 2496 case 128: 2497 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2498 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2499 break; 2500 case 64: 2501 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2502 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2503 break; 2504 case 32: 2505 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2506 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2507 break; 2508 default: 2509 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2510 return -EINVAL; 2511 } 2512 2513 return 0; 2514 } 2515 2516 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2517 { 2518 struct snd_soc_component *component = dai->component; 2519 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2520 2521 rt5682->bclk[dai->id] = ratio; 2522 2523 switch (ratio) { 2524 case 64: 2525 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2526 RT5682_I2S2_BCLK_MS2_MASK, 2527 RT5682_I2S2_BCLK_MS2_64); 2528 break; 2529 case 32: 2530 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2531 RT5682_I2S2_BCLK_MS2_MASK, 2532 RT5682_I2S2_BCLK_MS2_32); 2533 break; 2534 default: 2535 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2536 return -EINVAL; 2537 } 2538 2539 return 0; 2540 } 2541 2542 static int rt5682_set_bias_level(struct snd_soc_component *component, 2543 enum snd_soc_bias_level level) 2544 { 2545 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2546 2547 switch (level) { 2548 case SND_SOC_BIAS_PREPARE: 2549 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2550 RT5682_PWR_BG, RT5682_PWR_BG); 2551 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2552 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2553 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2554 break; 2555 2556 case SND_SOC_BIAS_STANDBY: 2557 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2558 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2559 break; 2560 case SND_SOC_BIAS_OFF: 2561 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2562 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2563 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2564 RT5682_PWR_BG, 0); 2565 break; 2566 case SND_SOC_BIAS_ON: 2567 break; 2568 } 2569 2570 return 0; 2571 } 2572 2573 #ifdef CONFIG_COMMON_CLK 2574 #define CLK_PLL2_FIN 48000000 2575 #define CLK_48 48000 2576 #define CLK_44 44100 2577 2578 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2579 { 2580 if (!rt5682->master[RT5682_AIF1]) { 2581 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n"); 2582 return false; 2583 } 2584 return true; 2585 } 2586 2587 static int rt5682_wclk_prepare(struct clk_hw *hw) 2588 { 2589 struct rt5682_priv *rt5682 = 2590 container_of(hw, struct rt5682_priv, 2591 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2592 struct snd_soc_component *component; 2593 struct snd_soc_dapm_context *dapm; 2594 2595 if (!rt5682_clk_check(rt5682)) 2596 return -EINVAL; 2597 2598 component = rt5682->component; 2599 dapm = snd_soc_component_to_dapm(component); 2600 2601 snd_soc_dapm_mutex_lock(dapm); 2602 2603 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2604 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2605 RT5682_PWR_MB, RT5682_PWR_MB); 2606 2607 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2608 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2609 RT5682_PWR_VREF2 | RT5682_PWR_FV2, 2610 RT5682_PWR_VREF2); 2611 usleep_range(55000, 60000); 2612 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2613 RT5682_PWR_FV2, RT5682_PWR_FV2); 2614 2615 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2616 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2617 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2618 snd_soc_dapm_sync_unlocked(dapm); 2619 2620 snd_soc_dapm_mutex_unlock(dapm); 2621 2622 return 0; 2623 } 2624 2625 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2626 { 2627 struct rt5682_priv *rt5682 = 2628 container_of(hw, struct rt5682_priv, 2629 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2630 struct snd_soc_component *component; 2631 struct snd_soc_dapm_context *dapm; 2632 2633 if (!rt5682_clk_check(rt5682)) 2634 return; 2635 2636 component = rt5682->component; 2637 dapm = snd_soc_component_to_dapm(component); 2638 2639 snd_soc_dapm_mutex_lock(dapm); 2640 2641 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2642 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2643 if (!rt5682->jack_type) 2644 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2645 RT5682_PWR_VREF2 | RT5682_PWR_FV2 | 2646 RT5682_PWR_MB, 0); 2647 2648 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2649 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2650 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2651 snd_soc_dapm_sync_unlocked(dapm); 2652 2653 snd_soc_dapm_mutex_unlock(dapm); 2654 } 2655 2656 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2657 unsigned long parent_rate) 2658 { 2659 struct rt5682_priv *rt5682 = 2660 container_of(hw, struct rt5682_priv, 2661 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2662 const char * const clk_name = clk_hw_get_name(hw); 2663 2664 if (!rt5682_clk_check(rt5682)) 2665 return 0; 2666 /* 2667 * Only accept to set wclk rate to 44.1k or 48kHz. 2668 */ 2669 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && 2670 rt5682->lrck[RT5682_AIF1] != CLK_44) { 2671 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2672 __func__, clk_name, CLK_44, CLK_48); 2673 return 0; 2674 } 2675 2676 return rt5682->lrck[RT5682_AIF1]; 2677 } 2678 2679 static int rt5682_wclk_determine_rate(struct clk_hw *hw, 2680 struct clk_rate_request *req) 2681 { 2682 struct rt5682_priv *rt5682 = 2683 container_of(hw, struct rt5682_priv, 2684 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2685 const char * const clk_name = clk_hw_get_name(hw); 2686 2687 if (!rt5682_clk_check(rt5682)) 2688 return -EINVAL; 2689 /* 2690 * Only accept to set wclk rate to 44.1k or 48kHz. 2691 * It will force to 48kHz if not both. 2692 */ 2693 if (req->rate != CLK_48 && req->rate != CLK_44) { 2694 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2695 __func__, clk_name, CLK_44, CLK_48); 2696 req->rate = CLK_48; 2697 } 2698 2699 return 0; 2700 } 2701 2702 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2703 unsigned long parent_rate) 2704 { 2705 struct rt5682_priv *rt5682 = 2706 container_of(hw, struct rt5682_priv, 2707 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2708 struct snd_soc_component *component; 2709 struct clk_hw *parent_hw; 2710 const char * const clk_name = clk_hw_get_name(hw); 2711 int pre_div; 2712 unsigned int clk_pll2_out; 2713 2714 if (!rt5682_clk_check(rt5682)) 2715 return -EINVAL; 2716 2717 component = rt5682->component; 2718 2719 /* 2720 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2721 * it is fixed or set to 48MHz before setting wclk rate. It's a 2722 * temporary limitation. Only accept 48MHz clk as the clk provider. 2723 * 2724 * It will set the codec anyway by assuming mclk is 48MHz. 2725 */ 2726 parent_hw = clk_hw_get_parent(hw); 2727 if (!parent_hw) 2728 dev_warn(rt5682->i2c_dev, 2729 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2730 CLK_PLL2_FIN); 2731 2732 if (parent_rate != CLK_PLL2_FIN) 2733 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n", 2734 clk_name, CLK_PLL2_FIN); 2735 2736 /* 2737 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2738 * PLL2 is needed. 2739 */ 2740 clk_pll2_out = rate * 512; 2741 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2742 CLK_PLL2_FIN, clk_pll2_out); 2743 2744 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2745 clk_pll2_out, SND_SOC_CLOCK_IN); 2746 2747 rt5682->lrck[RT5682_AIF1] = rate; 2748 2749 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2750 2751 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2752 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2753 pre_div << RT5682_I2S_M_DIV_SFT | 2754 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2755 2756 return 0; 2757 } 2758 2759 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2760 unsigned long parent_rate) 2761 { 2762 struct rt5682_priv *rt5682 = 2763 container_of(hw, struct rt5682_priv, 2764 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2765 unsigned int bclks_per_wclk; 2766 2767 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk); 2768 2769 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2770 case RT5682_TDM_BCLK_MS1_256: 2771 return parent_rate * 256; 2772 case RT5682_TDM_BCLK_MS1_128: 2773 return parent_rate * 128; 2774 case RT5682_TDM_BCLK_MS1_64: 2775 return parent_rate * 64; 2776 case RT5682_TDM_BCLK_MS1_32: 2777 return parent_rate * 32; 2778 default: 2779 return 0; 2780 } 2781 } 2782 2783 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2784 unsigned long parent_rate) 2785 { 2786 unsigned long factor; 2787 2788 factor = rate / parent_rate; 2789 if (factor < 64) 2790 return 32; 2791 else if (factor < 128) 2792 return 64; 2793 else if (factor < 256) 2794 return 128; 2795 else 2796 return 256; 2797 } 2798 2799 static int rt5682_bclk_determine_rate(struct clk_hw *hw, 2800 struct clk_rate_request *req) 2801 { 2802 struct rt5682_priv *rt5682 = 2803 container_of(hw, struct rt5682_priv, 2804 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2805 unsigned long factor; 2806 2807 if (!req->best_parent_rate || !rt5682_clk_check(rt5682)) 2808 return -EINVAL; 2809 2810 /* 2811 * BCLK rates are set as a multiplier of WCLK in HW. 2812 * We don't allow changing the parent WCLK. We just do 2813 * some rounding down based on the parent WCLK rate 2814 * and find the appropriate multiplier of BCLK to 2815 * get the rounded down BCLK value. 2816 */ 2817 factor = rt5682_bclk_get_factor(req->rate, req->best_parent_rate); 2818 2819 req->rate = req->best_parent_rate * factor; 2820 2821 return 0; 2822 } 2823 2824 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2825 unsigned long parent_rate) 2826 { 2827 struct rt5682_priv *rt5682 = 2828 container_of(hw, struct rt5682_priv, 2829 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2830 struct snd_soc_component *component; 2831 struct snd_soc_dai *dai; 2832 unsigned long factor; 2833 2834 if (!rt5682_clk_check(rt5682)) 2835 return -EINVAL; 2836 2837 component = rt5682->component; 2838 2839 factor = rt5682_bclk_get_factor(rate, parent_rate); 2840 2841 for_each_component_dais(component, dai) 2842 if (dai->id == RT5682_AIF1) 2843 return rt5682_set_bclk1_ratio(dai, factor); 2844 2845 dev_err(rt5682->i2c_dev, "dai %d not found in component\n", 2846 RT5682_AIF1); 2847 return -ENODEV; 2848 } 2849 2850 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2851 [RT5682_DAI_WCLK_IDX] = { 2852 .prepare = rt5682_wclk_prepare, 2853 .unprepare = rt5682_wclk_unprepare, 2854 .recalc_rate = rt5682_wclk_recalc_rate, 2855 .determine_rate = rt5682_wclk_determine_rate, 2856 .set_rate = rt5682_wclk_set_rate, 2857 }, 2858 [RT5682_DAI_BCLK_IDX] = { 2859 .recalc_rate = rt5682_bclk_recalc_rate, 2860 .determine_rate = rt5682_bclk_determine_rate, 2861 .set_rate = rt5682_bclk_set_rate, 2862 }, 2863 }; 2864 2865 int rt5682_register_dai_clks(struct rt5682_priv *rt5682) 2866 { 2867 struct device *dev = rt5682->i2c_dev; 2868 struct rt5682_platform_data *pdata = &rt5682->pdata; 2869 struct clk_hw *dai_clk_hw; 2870 int i, ret; 2871 2872 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2873 struct clk_init_data init = { }; 2874 const struct clk_hw *parent; 2875 2876 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2877 2878 switch (i) { 2879 case RT5682_DAI_WCLK_IDX: 2880 /* Make MCLK the parent of WCLK */ 2881 if (rt5682->mclk) { 2882 parent = __clk_get_hw(rt5682->mclk); 2883 init.parent_hws = &parent; 2884 init.num_parents = 1; 2885 } 2886 break; 2887 case RT5682_DAI_BCLK_IDX: 2888 /* Make WCLK the parent of BCLK */ 2889 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]; 2890 init.parent_hws = &parent; 2891 init.num_parents = 1; 2892 break; 2893 default: 2894 dev_err(dev, "Invalid clock index\n"); 2895 return -EINVAL; 2896 } 2897 2898 init.name = pdata->dai_clk_names[i]; 2899 init.ops = &rt5682_dai_clk_ops[i]; 2900 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2901 dai_clk_hw->init = &init; 2902 2903 ret = devm_clk_hw_register(dev, dai_clk_hw); 2904 if (ret) { 2905 dev_warn(dev, "Failed to register %s: %d\n", 2906 init.name, ret); 2907 return ret; 2908 } 2909 2910 if (dev->of_node) { 2911 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2912 dai_clk_hw); 2913 if (ret) 2914 return ret; 2915 } else { 2916 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2917 init.name, 2918 dev_name(dev)); 2919 if (ret) 2920 return ret; 2921 } 2922 } 2923 2924 return 0; 2925 } 2926 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks); 2927 #endif /* CONFIG_COMMON_CLK */ 2928 2929 static int rt5682_probe(struct snd_soc_component *component) 2930 { 2931 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2932 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2933 int ret; 2934 2935 rt5682->component = component; 2936 2937 if (rt5682->is_sdw) { 2938 ret = sdw_slave_wait_for_init(rt5682->slave, RT5682_PROBE_TIMEOUT); 2939 if (ret) 2940 return ret; 2941 } 2942 2943 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2944 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2945 snd_soc_dapm_sync(dapm); 2946 return 0; 2947 } 2948 2949 static void rt5682_remove(struct snd_soc_component *component) 2950 { 2951 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2952 2953 rt5682_reset(rt5682); 2954 } 2955 2956 #ifdef CONFIG_PM 2957 static int rt5682_suspend(struct snd_soc_component *component) 2958 { 2959 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2960 unsigned int val; 2961 2962 if (rt5682->is_sdw) 2963 return 0; 2964 2965 if (rt5682->irq) 2966 disable_irq(rt5682->irq); 2967 2968 cancel_delayed_work_sync(&rt5682->jack_detect_work); 2969 cancel_delayed_work_sync(&rt5682->jd_check_work); 2970 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 2971 val = snd_soc_component_read(component, 2972 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 2973 2974 switch (val) { 2975 case 0x1: 2976 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2977 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2978 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL); 2979 break; 2980 case 0x2: 2981 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2982 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2983 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL); 2984 break; 2985 default: 2986 break; 2987 } 2988 2989 /* enter SAR ADC power saving mode */ 2990 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2991 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK | 2992 RT5682_SAR_SEL_MB1_MB2_MASK, 0); 2993 usleep_range(5000, 6000); 2994 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 2995 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 2996 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG); 2997 usleep_range(10000, 12000); 2998 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2999 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK, 3000 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV); 3001 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1, 3002 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 3003 } 3004 3005 regcache_cache_only(rt5682->regmap, true); 3006 regcache_mark_dirty(rt5682->regmap); 3007 return 0; 3008 } 3009 3010 static int rt5682_resume(struct snd_soc_component *component) 3011 { 3012 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 3013 3014 if (rt5682->is_sdw) 3015 return 0; 3016 3017 regcache_cache_only(rt5682->regmap, false); 3018 regcache_sync(rt5682->regmap); 3019 3020 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 3021 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 3022 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK, 3023 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO); 3024 usleep_range(5000, 6000); 3025 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 3026 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 3027 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM); 3028 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 3029 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 3030 } 3031 3032 rt5682->jack_type = 0; 3033 mod_delayed_work(system_power_efficient_wq, 3034 &rt5682->jack_detect_work, msecs_to_jiffies(0)); 3035 3036 if (rt5682->irq) 3037 enable_irq(rt5682->irq); 3038 3039 return 0; 3040 } 3041 #else 3042 #define rt5682_suspend NULL 3043 #define rt5682_resume NULL 3044 #endif 3045 3046 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 3047 .hw_params = rt5682_hw_params, 3048 .set_fmt = rt5682_set_dai_fmt, 3049 .set_tdm_slot = rt5682_set_tdm_slot, 3050 .set_bclk_ratio = rt5682_set_bclk1_ratio, 3051 }; 3052 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 3053 3054 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 3055 .hw_params = rt5682_hw_params, 3056 .set_fmt = rt5682_set_dai_fmt, 3057 .set_bclk_ratio = rt5682_set_bclk2_ratio, 3058 }; 3059 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 3060 3061 const struct snd_soc_component_driver rt5682_soc_component_dev = { 3062 .probe = rt5682_probe, 3063 .remove = rt5682_remove, 3064 .suspend = rt5682_suspend, 3065 .resume = rt5682_resume, 3066 .set_bias_level = rt5682_set_bias_level, 3067 .controls = rt5682_snd_controls, 3068 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 3069 .dapm_widgets = rt5682_dapm_widgets, 3070 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 3071 .dapm_routes = rt5682_dapm_routes, 3072 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 3073 .set_sysclk = rt5682_set_component_sysclk, 3074 .set_pll = rt5682_set_component_pll, 3075 .set_jack = rt5682_set_jack_detect, 3076 .use_pmdown_time = 1, 3077 .endianness = 1, 3078 }; 3079 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 3080 3081 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 3082 { 3083 3084 device_property_read_u32(dev, "realtek,dmic1-data-pin", 3085 &rt5682->pdata.dmic1_data_pin); 3086 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 3087 &rt5682->pdata.dmic1_clk_pin); 3088 device_property_read_u32(dev, "realtek,jd-src", 3089 &rt5682->pdata.jd_src); 3090 device_property_read_u32(dev, "realtek,btndet-delay", 3091 &rt5682->pdata.btndet_delay); 3092 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 3093 &rt5682->pdata.dmic_clk_rate); 3094 device_property_read_u32(dev, "realtek,dmic-delay-ms", 3095 &rt5682->pdata.dmic_delay); 3096 3097 if (device_property_read_string_array(dev, "clock-output-names", 3098 rt5682->pdata.dai_clk_names, 3099 RT5682_DAI_NUM_CLKS) < 0) 3100 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 3101 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 3102 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 3103 3104 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, 3105 "realtek,dmic-clk-driving-high"); 3106 3107 return 0; 3108 } 3109 EXPORT_SYMBOL_GPL(rt5682_parse_dt); 3110 3111 int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev) 3112 { 3113 rt5682->ldo1_en = devm_gpiod_get_optional(dev, 3114 "realtek,ldo1-en", 3115 GPIOD_OUT_HIGH); 3116 if (IS_ERR(rt5682->ldo1_en)) { 3117 dev_err(dev, "Fail gpio request ldo1_en\n"); 3118 return PTR_ERR(rt5682->ldo1_en); 3119 } 3120 3121 return 0; 3122 } 3123 EXPORT_SYMBOL_GPL(rt5682_get_ldo1); 3124 3125 void rt5682_calibrate(struct rt5682_priv *rt5682) 3126 { 3127 int value, count; 3128 3129 guard(mutex)(&rt5682->calibrate_mutex); 3130 3131 rt5682_reset(rt5682); 3132 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3133 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3134 usleep_range(15000, 20000); 3135 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3136 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3137 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3138 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3139 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3140 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3141 if (rt5682->ve_ic) 3142 regmap_write(rt5682->regmap, RT5682_CHOP_ADC, 0x7005); 3143 else 3144 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3145 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3146 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3147 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3148 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3149 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3150 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3151 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3152 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3153 3154 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3155 3156 for (count = 0; count < 60; count++) { 3157 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3158 if (!(value & 0x8000)) 3159 break; 3160 3161 usleep_range(10000, 10005); 3162 } 3163 3164 if (count >= 60) 3165 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 3166 3167 /* restore settings */ 3168 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); 3169 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3170 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3171 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3172 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3173 if (rt5682->ve_ic) 3174 regmap_write(rt5682->regmap, RT5682_CHOP_ADC, 0x2005); 3175 else 3176 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3177 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3178 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); 3179 } 3180 EXPORT_SYMBOL_GPL(rt5682_calibrate); 3181 3182 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3183 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3184 MODULE_LICENSE("GPL v2"); 3185