1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5677.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #include <linux/cleanup.h> 10 #include <linux/bits.h> 11 #include <linux/delay.h> 12 #include <linux/firmware.h> 13 #include <linux/fs.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqdomain.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm.h> 23 #include <linux/property.h> 24 #include <linux/regmap.h> 25 #include <linux/spi/spi.h> 26 #include <linux/workqueue.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 35 #include "rl6231.h" 36 #include "rt5677.h" 37 #include "rt5677-spi.h" 38 39 #define RT5677_DEVICE_ID 0x6327 40 41 /* Register controlling boot vector */ 42 #define RT5677_DSP_BOOT_VECTOR 0x1801f090 43 #define RT5677_MODEL_ADDR 0x5FFC9800 44 45 #define RT5677_PR_RANGE_BASE (0xff + 1) 46 #define RT5677_PR_SPACING 0x100 47 48 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 49 50 static const struct regmap_range_cfg rt5677_ranges[] = { 51 { 52 .name = "PR", 53 .range_min = RT5677_PR_BASE, 54 .range_max = RT5677_PR_BASE + 0xfd, 55 .selector_reg = RT5677_PRIV_INDEX, 56 .selector_mask = 0xff, 57 .selector_shift = 0x0, 58 .window_start = RT5677_PRIV_DATA, 59 .window_len = 0x1, 60 }, 61 }; 62 63 static const struct reg_sequence init_list[] = { 64 {RT5677_ASRC_12, 0x0018}, 65 {RT5677_PR_BASE + 0x3d, 0x364d}, 66 {RT5677_PR_BASE + 0x17, 0x4fc0}, 67 {RT5677_PR_BASE + 0x13, 0x0312}, 68 {RT5677_PR_BASE + 0x1e, 0x0000}, 69 {RT5677_PR_BASE + 0x12, 0x0eaa}, 70 {RT5677_PR_BASE + 0x14, 0x018a}, 71 {RT5677_PR_BASE + 0x15, 0x0490}, 72 {RT5677_PR_BASE + 0x38, 0x0f71}, 73 {RT5677_PR_BASE + 0x39, 0x0f71}, 74 }; 75 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 76 77 static const struct reg_default rt5677_reg[] = { 78 {RT5677_RESET , 0x0000}, 79 {RT5677_LOUT1 , 0xa800}, 80 {RT5677_IN1 , 0x0000}, 81 {RT5677_MICBIAS , 0x0000}, 82 {RT5677_SLIMBUS_PARAM , 0x0000}, 83 {RT5677_SLIMBUS_RX , 0x0000}, 84 {RT5677_SLIMBUS_CTRL , 0x0000}, 85 {RT5677_SIDETONE_CTRL , 0x000b}, 86 {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, 87 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, 88 {RT5677_DAC4_DIG_VOL , 0xafaf}, 89 {RT5677_DAC3_DIG_VOL , 0xafaf}, 90 {RT5677_DAC1_DIG_VOL , 0xafaf}, 91 {RT5677_DAC2_DIG_VOL , 0xafaf}, 92 {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, 93 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, 94 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, 95 {RT5677_STO1_2_ADC_BST , 0x0000}, 96 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, 97 {RT5677_ADC_BST_CTRL2 , 0x0000}, 98 {RT5677_STO3_4_ADC_BST , 0x0000}, 99 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, 100 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, 101 {RT5677_STO4_ADC_MIXER , 0xd4c0}, 102 {RT5677_STO3_ADC_MIXER , 0xd4c0}, 103 {RT5677_STO2_ADC_MIXER , 0xd4c0}, 104 {RT5677_STO1_ADC_MIXER , 0xd4c0}, 105 {RT5677_MONO_ADC_MIXER , 0xd4d1}, 106 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, 107 {RT5677_STO1_DAC_MIXER , 0xaaaa}, 108 {RT5677_MONO_DAC_MIXER , 0xaaaa}, 109 {RT5677_DD1_MIXER , 0xaaaa}, 110 {RT5677_DD2_MIXER , 0xaaaa}, 111 {RT5677_IF3_DATA , 0x0000}, 112 {RT5677_IF4_DATA , 0x0000}, 113 {RT5677_PDM_OUT_CTRL , 0x8888}, 114 {RT5677_PDM_DATA_CTRL1 , 0x0000}, 115 {RT5677_PDM_DATA_CTRL2 , 0x0000}, 116 {RT5677_PDM1_DATA_CTRL2 , 0x0000}, 117 {RT5677_PDM1_DATA_CTRL3 , 0x0000}, 118 {RT5677_PDM1_DATA_CTRL4 , 0x0000}, 119 {RT5677_PDM2_DATA_CTRL2 , 0x0000}, 120 {RT5677_PDM2_DATA_CTRL3 , 0x0000}, 121 {RT5677_PDM2_DATA_CTRL4 , 0x0000}, 122 {RT5677_TDM1_CTRL1 , 0x0300}, 123 {RT5677_TDM1_CTRL2 , 0x0000}, 124 {RT5677_TDM1_CTRL3 , 0x4000}, 125 {RT5677_TDM1_CTRL4 , 0x0123}, 126 {RT5677_TDM1_CTRL5 , 0x4567}, 127 {RT5677_TDM2_CTRL1 , 0x0300}, 128 {RT5677_TDM2_CTRL2 , 0x0000}, 129 {RT5677_TDM2_CTRL3 , 0x4000}, 130 {RT5677_TDM2_CTRL4 , 0x0123}, 131 {RT5677_TDM2_CTRL5 , 0x4567}, 132 {RT5677_I2C_MASTER_CTRL1 , 0x0001}, 133 {RT5677_I2C_MASTER_CTRL2 , 0x0000}, 134 {RT5677_I2C_MASTER_CTRL3 , 0x0000}, 135 {RT5677_I2C_MASTER_CTRL4 , 0x0000}, 136 {RT5677_I2C_MASTER_CTRL5 , 0x0000}, 137 {RT5677_I2C_MASTER_CTRL6 , 0x0000}, 138 {RT5677_I2C_MASTER_CTRL7 , 0x0000}, 139 {RT5677_I2C_MASTER_CTRL8 , 0x0000}, 140 {RT5677_DMIC_CTRL1 , 0x1505}, 141 {RT5677_DMIC_CTRL2 , 0x0055}, 142 {RT5677_HAP_GENE_CTRL1 , 0x0111}, 143 {RT5677_HAP_GENE_CTRL2 , 0x0064}, 144 {RT5677_HAP_GENE_CTRL3 , 0xef0e}, 145 {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, 146 {RT5677_HAP_GENE_CTRL5 , 0xef0e}, 147 {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, 148 {RT5677_HAP_GENE_CTRL7 , 0xef0e}, 149 {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, 150 {RT5677_HAP_GENE_CTRL9 , 0xf000}, 151 {RT5677_HAP_GENE_CTRL10 , 0x0000}, 152 {RT5677_PWR_DIG1 , 0x0000}, 153 {RT5677_PWR_DIG2 , 0x0000}, 154 {RT5677_PWR_ANLG1 , 0x0055}, 155 {RT5677_PWR_ANLG2 , 0x0000}, 156 {RT5677_PWR_DSP1 , 0x0001}, 157 {RT5677_PWR_DSP_ST , 0x0000}, 158 {RT5677_PWR_DSP2 , 0x0000}, 159 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, 160 {RT5677_PRIV_INDEX , 0x0000}, 161 {RT5677_PRIV_DATA , 0x0000}, 162 {RT5677_I2S4_SDP , 0x8000}, 163 {RT5677_I2S1_SDP , 0x8000}, 164 {RT5677_I2S2_SDP , 0x8000}, 165 {RT5677_I2S3_SDP , 0x8000}, 166 {RT5677_CLK_TREE_CTRL1 , 0x1111}, 167 {RT5677_CLK_TREE_CTRL2 , 0x1111}, 168 {RT5677_CLK_TREE_CTRL3 , 0x0000}, 169 {RT5677_PLL1_CTRL1 , 0x0000}, 170 {RT5677_PLL1_CTRL2 , 0x0000}, 171 {RT5677_PLL2_CTRL1 , 0x0c60}, 172 {RT5677_PLL2_CTRL2 , 0x2000}, 173 {RT5677_GLB_CLK1 , 0x0000}, 174 {RT5677_GLB_CLK2 , 0x0000}, 175 {RT5677_ASRC_1 , 0x0000}, 176 {RT5677_ASRC_2 , 0x0000}, 177 {RT5677_ASRC_3 , 0x0000}, 178 {RT5677_ASRC_4 , 0x0000}, 179 {RT5677_ASRC_5 , 0x0000}, 180 {RT5677_ASRC_6 , 0x0000}, 181 {RT5677_ASRC_7 , 0x0000}, 182 {RT5677_ASRC_8 , 0x0000}, 183 {RT5677_ASRC_9 , 0x0000}, 184 {RT5677_ASRC_10 , 0x0000}, 185 {RT5677_ASRC_11 , 0x0000}, 186 {RT5677_ASRC_12 , 0x0018}, 187 {RT5677_ASRC_13 , 0x0000}, 188 {RT5677_ASRC_14 , 0x0000}, 189 {RT5677_ASRC_15 , 0x0000}, 190 {RT5677_ASRC_16 , 0x0000}, 191 {RT5677_ASRC_17 , 0x0000}, 192 {RT5677_ASRC_18 , 0x0000}, 193 {RT5677_ASRC_19 , 0x0000}, 194 {RT5677_ASRC_20 , 0x0000}, 195 {RT5677_ASRC_21 , 0x000c}, 196 {RT5677_ASRC_22 , 0x0000}, 197 {RT5677_ASRC_23 , 0x0000}, 198 {RT5677_VAD_CTRL1 , 0x2184}, 199 {RT5677_VAD_CTRL2 , 0x010a}, 200 {RT5677_VAD_CTRL3 , 0x0aea}, 201 {RT5677_VAD_CTRL4 , 0x000c}, 202 {RT5677_VAD_CTRL5 , 0x0000}, 203 {RT5677_DSP_INB_CTRL1 , 0x0000}, 204 {RT5677_DSP_INB_CTRL2 , 0x0000}, 205 {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, 206 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, 207 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, 208 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, 209 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, 210 {RT5677_ADC_EQ_CTRL1 , 0x6000}, 211 {RT5677_ADC_EQ_CTRL2 , 0x0000}, 212 {RT5677_EQ_CTRL1 , 0xc000}, 213 {RT5677_EQ_CTRL2 , 0x0000}, 214 {RT5677_EQ_CTRL3 , 0x0000}, 215 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, 216 {RT5677_JD_CTRL1 , 0x0000}, 217 {RT5677_JD_CTRL2 , 0x0000}, 218 {RT5677_JD_CTRL3 , 0x0000}, 219 {RT5677_IRQ_CTRL1 , 0x0000}, 220 {RT5677_IRQ_CTRL2 , 0x0000}, 221 {RT5677_GPIO_ST , 0x0000}, 222 {RT5677_GPIO_CTRL1 , 0x0000}, 223 {RT5677_GPIO_CTRL2 , 0x0000}, 224 {RT5677_GPIO_CTRL3 , 0x0000}, 225 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, 226 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, 227 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, 228 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, 229 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, 230 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, 231 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, 232 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, 233 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, 234 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, 235 {RT5677_MB_DRC_CTRL1 , 0x0f20}, 236 {RT5677_DRC1_CTRL1 , 0x001f}, 237 {RT5677_DRC1_CTRL2 , 0x020c}, 238 {RT5677_DRC1_CTRL3 , 0x1f00}, 239 {RT5677_DRC1_CTRL4 , 0x0000}, 240 {RT5677_DRC1_CTRL5 , 0x0000}, 241 {RT5677_DRC1_CTRL6 , 0x0029}, 242 {RT5677_DRC2_CTRL1 , 0x001f}, 243 {RT5677_DRC2_CTRL2 , 0x020c}, 244 {RT5677_DRC2_CTRL3 , 0x1f00}, 245 {RT5677_DRC2_CTRL4 , 0x0000}, 246 {RT5677_DRC2_CTRL5 , 0x0000}, 247 {RT5677_DRC2_CTRL6 , 0x0029}, 248 {RT5677_DRC1_HL_CTRL1 , 0x8000}, 249 {RT5677_DRC1_HL_CTRL2 , 0x0200}, 250 {RT5677_DRC2_HL_CTRL1 , 0x8000}, 251 {RT5677_DRC2_HL_CTRL2 , 0x0200}, 252 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, 253 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, 254 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, 255 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, 256 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, 257 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, 258 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, 259 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, 260 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, 261 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, 262 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, 263 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, 264 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, 265 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, 266 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, 267 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, 268 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, 269 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, 270 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, 271 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, 272 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, 273 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, 274 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, 275 {RT5677_DIG_MISC , 0x0000}, 276 {RT5677_GEN_CTRL1 , 0x0000}, 277 {RT5677_GEN_CTRL2 , 0x0000}, 278 {RT5677_VENDOR_ID , 0x0000}, 279 {RT5677_VENDOR_ID1 , 0x10ec}, 280 {RT5677_VENDOR_ID2 , 0x6327}, 281 }; 282 283 static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 284 { 285 int i; 286 287 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 288 if (reg >= rt5677_ranges[i].range_min && 289 reg <= rt5677_ranges[i].range_max) { 290 return true; 291 } 292 } 293 294 switch (reg) { 295 case RT5677_RESET: 296 case RT5677_SLIMBUS_PARAM: 297 case RT5677_PDM_DATA_CTRL1: 298 case RT5677_PDM_DATA_CTRL2: 299 case RT5677_PDM1_DATA_CTRL4: 300 case RT5677_PDM2_DATA_CTRL4: 301 case RT5677_I2C_MASTER_CTRL1: 302 case RT5677_I2C_MASTER_CTRL7: 303 case RT5677_I2C_MASTER_CTRL8: 304 case RT5677_HAP_GENE_CTRL2: 305 case RT5677_PWR_ANLG2: /* Modified by DSP firmware */ 306 case RT5677_PWR_DSP_ST: 307 case RT5677_PRIV_DATA: 308 case RT5677_ASRC_22: 309 case RT5677_ASRC_23: 310 case RT5677_VAD_CTRL5: 311 case RT5677_ADC_EQ_CTRL1: 312 case RT5677_EQ_CTRL1: 313 case RT5677_IRQ_CTRL1: 314 case RT5677_IRQ_CTRL2: 315 case RT5677_GPIO_ST: 316 case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */ 317 case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */ 318 case RT5677_DSP_INB1_SRC_CTRL4: 319 case RT5677_DSP_INB2_SRC_CTRL4: 320 case RT5677_DSP_INB3_SRC_CTRL4: 321 case RT5677_DSP_OUTB1_SRC_CTRL4: 322 case RT5677_DSP_OUTB2_SRC_CTRL4: 323 case RT5677_VENDOR_ID: 324 case RT5677_VENDOR_ID1: 325 case RT5677_VENDOR_ID2: 326 return true; 327 default: 328 return false; 329 } 330 } 331 332 static bool rt5677_readable_register(struct device *dev, unsigned int reg) 333 { 334 int i; 335 336 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 337 if (reg >= rt5677_ranges[i].range_min && 338 reg <= rt5677_ranges[i].range_max) { 339 return true; 340 } 341 } 342 343 switch (reg) { 344 case RT5677_RESET: 345 case RT5677_LOUT1: 346 case RT5677_IN1: 347 case RT5677_MICBIAS: 348 case RT5677_SLIMBUS_PARAM: 349 case RT5677_SLIMBUS_RX: 350 case RT5677_SLIMBUS_CTRL: 351 case RT5677_SIDETONE_CTRL: 352 case RT5677_ANA_DAC1_2_3_SRC: 353 case RT5677_IF_DSP_DAC3_4_MIXER: 354 case RT5677_DAC4_DIG_VOL: 355 case RT5677_DAC3_DIG_VOL: 356 case RT5677_DAC1_DIG_VOL: 357 case RT5677_DAC2_DIG_VOL: 358 case RT5677_IF_DSP_DAC2_MIXER: 359 case RT5677_STO1_ADC_DIG_VOL: 360 case RT5677_MONO_ADC_DIG_VOL: 361 case RT5677_STO1_2_ADC_BST: 362 case RT5677_STO2_ADC_DIG_VOL: 363 case RT5677_ADC_BST_CTRL2: 364 case RT5677_STO3_4_ADC_BST: 365 case RT5677_STO3_ADC_DIG_VOL: 366 case RT5677_STO4_ADC_DIG_VOL: 367 case RT5677_STO4_ADC_MIXER: 368 case RT5677_STO3_ADC_MIXER: 369 case RT5677_STO2_ADC_MIXER: 370 case RT5677_STO1_ADC_MIXER: 371 case RT5677_MONO_ADC_MIXER: 372 case RT5677_ADC_IF_DSP_DAC1_MIXER: 373 case RT5677_STO1_DAC_MIXER: 374 case RT5677_MONO_DAC_MIXER: 375 case RT5677_DD1_MIXER: 376 case RT5677_DD2_MIXER: 377 case RT5677_IF3_DATA: 378 case RT5677_IF4_DATA: 379 case RT5677_PDM_OUT_CTRL: 380 case RT5677_PDM_DATA_CTRL1: 381 case RT5677_PDM_DATA_CTRL2: 382 case RT5677_PDM1_DATA_CTRL2: 383 case RT5677_PDM1_DATA_CTRL3: 384 case RT5677_PDM1_DATA_CTRL4: 385 case RT5677_PDM2_DATA_CTRL2: 386 case RT5677_PDM2_DATA_CTRL3: 387 case RT5677_PDM2_DATA_CTRL4: 388 case RT5677_TDM1_CTRL1: 389 case RT5677_TDM1_CTRL2: 390 case RT5677_TDM1_CTRL3: 391 case RT5677_TDM1_CTRL4: 392 case RT5677_TDM1_CTRL5: 393 case RT5677_TDM2_CTRL1: 394 case RT5677_TDM2_CTRL2: 395 case RT5677_TDM2_CTRL3: 396 case RT5677_TDM2_CTRL4: 397 case RT5677_TDM2_CTRL5: 398 case RT5677_I2C_MASTER_CTRL1: 399 case RT5677_I2C_MASTER_CTRL2: 400 case RT5677_I2C_MASTER_CTRL3: 401 case RT5677_I2C_MASTER_CTRL4: 402 case RT5677_I2C_MASTER_CTRL5: 403 case RT5677_I2C_MASTER_CTRL6: 404 case RT5677_I2C_MASTER_CTRL7: 405 case RT5677_I2C_MASTER_CTRL8: 406 case RT5677_DMIC_CTRL1: 407 case RT5677_DMIC_CTRL2: 408 case RT5677_HAP_GENE_CTRL1: 409 case RT5677_HAP_GENE_CTRL2: 410 case RT5677_HAP_GENE_CTRL3: 411 case RT5677_HAP_GENE_CTRL4: 412 case RT5677_HAP_GENE_CTRL5: 413 case RT5677_HAP_GENE_CTRL6: 414 case RT5677_HAP_GENE_CTRL7: 415 case RT5677_HAP_GENE_CTRL8: 416 case RT5677_HAP_GENE_CTRL9: 417 case RT5677_HAP_GENE_CTRL10: 418 case RT5677_PWR_DIG1: 419 case RT5677_PWR_DIG2: 420 case RT5677_PWR_ANLG1: 421 case RT5677_PWR_ANLG2: 422 case RT5677_PWR_DSP1: 423 case RT5677_PWR_DSP_ST: 424 case RT5677_PWR_DSP2: 425 case RT5677_ADC_DAC_HPF_CTRL1: 426 case RT5677_PRIV_INDEX: 427 case RT5677_PRIV_DATA: 428 case RT5677_I2S4_SDP: 429 case RT5677_I2S1_SDP: 430 case RT5677_I2S2_SDP: 431 case RT5677_I2S3_SDP: 432 case RT5677_CLK_TREE_CTRL1: 433 case RT5677_CLK_TREE_CTRL2: 434 case RT5677_CLK_TREE_CTRL3: 435 case RT5677_PLL1_CTRL1: 436 case RT5677_PLL1_CTRL2: 437 case RT5677_PLL2_CTRL1: 438 case RT5677_PLL2_CTRL2: 439 case RT5677_GLB_CLK1: 440 case RT5677_GLB_CLK2: 441 case RT5677_ASRC_1: 442 case RT5677_ASRC_2: 443 case RT5677_ASRC_3: 444 case RT5677_ASRC_4: 445 case RT5677_ASRC_5: 446 case RT5677_ASRC_6: 447 case RT5677_ASRC_7: 448 case RT5677_ASRC_8: 449 case RT5677_ASRC_9: 450 case RT5677_ASRC_10: 451 case RT5677_ASRC_11: 452 case RT5677_ASRC_12: 453 case RT5677_ASRC_13: 454 case RT5677_ASRC_14: 455 case RT5677_ASRC_15: 456 case RT5677_ASRC_16: 457 case RT5677_ASRC_17: 458 case RT5677_ASRC_18: 459 case RT5677_ASRC_19: 460 case RT5677_ASRC_20: 461 case RT5677_ASRC_21: 462 case RT5677_ASRC_22: 463 case RT5677_ASRC_23: 464 case RT5677_VAD_CTRL1: 465 case RT5677_VAD_CTRL2: 466 case RT5677_VAD_CTRL3: 467 case RT5677_VAD_CTRL4: 468 case RT5677_VAD_CTRL5: 469 case RT5677_DSP_INB_CTRL1: 470 case RT5677_DSP_INB_CTRL2: 471 case RT5677_DSP_IN_OUTB_CTRL: 472 case RT5677_DSP_OUTB0_1_DIG_VOL: 473 case RT5677_DSP_OUTB2_3_DIG_VOL: 474 case RT5677_DSP_OUTB4_5_DIG_VOL: 475 case RT5677_DSP_OUTB6_7_DIG_VOL: 476 case RT5677_ADC_EQ_CTRL1: 477 case RT5677_ADC_EQ_CTRL2: 478 case RT5677_EQ_CTRL1: 479 case RT5677_EQ_CTRL2: 480 case RT5677_EQ_CTRL3: 481 case RT5677_SOFT_VOL_ZERO_CROSS1: 482 case RT5677_JD_CTRL1: 483 case RT5677_JD_CTRL2: 484 case RT5677_JD_CTRL3: 485 case RT5677_IRQ_CTRL1: 486 case RT5677_IRQ_CTRL2: 487 case RT5677_GPIO_ST: 488 case RT5677_GPIO_CTRL1: 489 case RT5677_GPIO_CTRL2: 490 case RT5677_GPIO_CTRL3: 491 case RT5677_STO1_ADC_HI_FILTER1: 492 case RT5677_STO1_ADC_HI_FILTER2: 493 case RT5677_MONO_ADC_HI_FILTER1: 494 case RT5677_MONO_ADC_HI_FILTER2: 495 case RT5677_STO2_ADC_HI_FILTER1: 496 case RT5677_STO2_ADC_HI_FILTER2: 497 case RT5677_STO3_ADC_HI_FILTER1: 498 case RT5677_STO3_ADC_HI_FILTER2: 499 case RT5677_STO4_ADC_HI_FILTER1: 500 case RT5677_STO4_ADC_HI_FILTER2: 501 case RT5677_MB_DRC_CTRL1: 502 case RT5677_DRC1_CTRL1: 503 case RT5677_DRC1_CTRL2: 504 case RT5677_DRC1_CTRL3: 505 case RT5677_DRC1_CTRL4: 506 case RT5677_DRC1_CTRL5: 507 case RT5677_DRC1_CTRL6: 508 case RT5677_DRC2_CTRL1: 509 case RT5677_DRC2_CTRL2: 510 case RT5677_DRC2_CTRL3: 511 case RT5677_DRC2_CTRL4: 512 case RT5677_DRC2_CTRL5: 513 case RT5677_DRC2_CTRL6: 514 case RT5677_DRC1_HL_CTRL1: 515 case RT5677_DRC1_HL_CTRL2: 516 case RT5677_DRC2_HL_CTRL1: 517 case RT5677_DRC2_HL_CTRL2: 518 case RT5677_DSP_INB1_SRC_CTRL1: 519 case RT5677_DSP_INB1_SRC_CTRL2: 520 case RT5677_DSP_INB1_SRC_CTRL3: 521 case RT5677_DSP_INB1_SRC_CTRL4: 522 case RT5677_DSP_INB2_SRC_CTRL1: 523 case RT5677_DSP_INB2_SRC_CTRL2: 524 case RT5677_DSP_INB2_SRC_CTRL3: 525 case RT5677_DSP_INB2_SRC_CTRL4: 526 case RT5677_DSP_INB3_SRC_CTRL1: 527 case RT5677_DSP_INB3_SRC_CTRL2: 528 case RT5677_DSP_INB3_SRC_CTRL3: 529 case RT5677_DSP_INB3_SRC_CTRL4: 530 case RT5677_DSP_OUTB1_SRC_CTRL1: 531 case RT5677_DSP_OUTB1_SRC_CTRL2: 532 case RT5677_DSP_OUTB1_SRC_CTRL3: 533 case RT5677_DSP_OUTB1_SRC_CTRL4: 534 case RT5677_DSP_OUTB2_SRC_CTRL1: 535 case RT5677_DSP_OUTB2_SRC_CTRL2: 536 case RT5677_DSP_OUTB2_SRC_CTRL3: 537 case RT5677_DSP_OUTB2_SRC_CTRL4: 538 case RT5677_DSP_OUTB_0123_MIXER_CTRL: 539 case RT5677_DSP_OUTB_45_MIXER_CTRL: 540 case RT5677_DSP_OUTB_67_MIXER_CTRL: 541 case RT5677_DIG_MISC: 542 case RT5677_GEN_CTRL1: 543 case RT5677_GEN_CTRL2: 544 case RT5677_VENDOR_ID: 545 case RT5677_VENDOR_ID1: 546 case RT5677_VENDOR_ID2: 547 return true; 548 default: 549 return false; 550 } 551 } 552 553 /** 554 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. 555 * @rt5677: Private Data. 556 * @addr: Address index. 557 * @value: Address data. 558 * @opcode: opcode value 559 * 560 * Returns 0 for success or negative error code. 561 */ 562 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, 563 unsigned int addr, unsigned int value, unsigned int opcode) 564 { 565 struct snd_soc_component *component = rt5677->component; 566 int ret; 567 568 guard(mutex)(&rt5677->dsp_cmd_lock); 569 570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 571 addr >> 16); 572 if (ret < 0) { 573 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 574 return ret; 575 } 576 577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 578 addr & 0xffff); 579 if (ret < 0) { 580 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 581 return ret; 582 } 583 584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, 585 value >> 16); 586 if (ret < 0) { 587 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); 588 return ret; 589 } 590 591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, 592 value & 0xffff); 593 if (ret < 0) { 594 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); 595 return ret; 596 } 597 598 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 599 opcode); 600 if (ret < 0) { 601 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 602 return ret; 603 } 604 605 return ret; 606 } 607 608 /** 609 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. 610 * @rt5677: Private Data. 611 * @addr: Address index. 612 * @value: Address data. 613 * 614 * 615 * Returns 0 for success or negative error code. 616 */ 617 static int rt5677_dsp_mode_i2c_read_addr( 618 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) 619 { 620 struct snd_soc_component *component = rt5677->component; 621 int ret; 622 unsigned int msb, lsb; 623 624 guard(mutex)(&rt5677->dsp_cmd_lock); 625 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 627 addr >> 16); 628 if (ret < 0) { 629 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 630 return ret; 631 } 632 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 634 addr & 0xffff); 635 if (ret < 0) { 636 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 637 return ret; 638 } 639 640 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 641 0x0002); 642 if (ret < 0) { 643 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 644 return ret; 645 } 646 647 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); 648 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); 649 *value = (msb << 16) | lsb; 650 651 return ret; 652 } 653 654 /** 655 * rt5677_dsp_mode_i2c_write - Write register on DSP mode. 656 * @rt5677: Private Data. 657 * @reg: Register index. 658 * @value: Register data. 659 * 660 * 661 * Returns 0 for success or negative error code. 662 */ 663 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, 664 unsigned int reg, unsigned int value) 665 { 666 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, 667 value, 0x0001); 668 } 669 670 /** 671 * rt5677_dsp_mode_i2c_read - Read register on DSP mode. 672 * @rt5677: Private Data 673 * @reg: Register index. 674 * @value: Register data. 675 * 676 * 677 * Returns 0 for success or negative error code. 678 */ 679 static int rt5677_dsp_mode_i2c_read( 680 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) 681 { 682 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, 683 value); 684 685 *value &= 0xffff; 686 687 return ret; 688 } 689 690 static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on) 691 { 692 if (on) { 693 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 694 RT5677_PWR_DSP, RT5677_PWR_DSP); 695 rt5677->is_dsp_mode = true; 696 } else { 697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 698 RT5677_PWR_DSP, 0x0); 699 rt5677->is_dsp_mode = false; 700 } 701 } 702 703 static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677) 704 { 705 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt5677->component); 706 /* Force dapm to sync before we enable the 707 * DSP to prevent write corruption 708 */ 709 snd_soc_dapm_sync(dapm); 710 711 /* DMIC1 power = enabled 712 * DMIC CLK = 256 * fs / 12 713 */ 714 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 715 RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT); 716 717 /* I2S pre divide 2 = /6 (clk_sys2) */ 718 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 719 RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6); 720 721 /* DSP Clock = MCLK1 (bypassed PLL2) */ 722 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, 723 RT5677_DSP_CLK_SRC_BYPASS); 724 725 /* SAD Threshold1 */ 726 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f); 727 /* SAD Threshold2 */ 728 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5); 729 /* SAD Sample Rate Converter = Up 6 (8K to 48K) 730 * SAD Output Sample Rate = Same as I2S 731 * SAD Threshold3 732 */ 733 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4, 734 RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK | 735 RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT); 736 /* Minimum frame level within a pre-determined duration = 32 frames 737 * Bypass ADPCM Encoder/Decoder = Bypass ADPCM 738 * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable 739 * SAD Buffer Over-Writing = enable 740 * SAD Buffer Pop Mode Control = disable 741 * SAD Buffer Push Mode Control = enable 742 * SAD Detector Control = enable 743 * SAD Function Control = enable 744 * SAD Function Reset = normal 745 */ 746 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 747 RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE | 748 RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH | 749 RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC | 750 RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT); 751 752 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it 753 * is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save 754 * power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack 755 * Detection" for more info. 756 */ 757 758 /* Private register, no doc */ 759 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, 760 0x0f00, 0x0100); 761 762 /* LDO2 output = 1.2V 763 * LDO1 output = 1.2V (LDO_IN = 1.8V) 764 */ 765 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 766 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 767 5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT); 768 769 /* Codec core power = power on 770 * LDO1 power = power on 771 */ 772 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 773 RT5677_PWR_CORE | RT5677_PWR_LDO1, 774 RT5677_PWR_CORE | RT5677_PWR_LDO1); 775 776 /* Isolation for DCVDD4 = normal (set during probe) 777 * Isolation for DCVDD2 = normal (set during probe) 778 * Isolation for DSP = normal 779 * Isolation for Band 0~7 = disable 780 * Isolation for InBound 4~10 and OutBound 4~10 = disable 781 */ 782 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 783 RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO | 784 RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO | 785 RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO | 786 RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO | 787 RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO | 788 RT5677_PWR_MLT_ISO); 789 790 /* System Band 0~7 = power on 791 * InBound 4~10 and OutBound 4~10 = power on 792 * DSP = power on 793 * DSP CPU = stop (will be set to "run" after firmware loaded) 794 */ 795 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 796 RT5677_PWR_SR7 | RT5677_PWR_SR6 | 797 RT5677_PWR_SR5 | RT5677_PWR_SR4 | 798 RT5677_PWR_SR3 | RT5677_PWR_SR2 | 799 RT5677_PWR_SR1 | RT5677_PWR_SR0 | 800 RT5677_PWR_MLT | RT5677_PWR_DSP | 801 RT5677_PWR_DSP_CPU); 802 803 return 0; 804 } 805 806 static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf, 807 unsigned int len) 808 { 809 struct snd_soc_component *component = rt5677->component; 810 Elf32_Ehdr *elf_hdr; 811 Elf32_Phdr *pr_hdr; 812 Elf32_Half i; 813 int ret = 0; 814 815 if (!buf || (len < sizeof(Elf32_Ehdr))) 816 return -ENOMEM; 817 818 elf_hdr = (Elf32_Ehdr *)buf; 819 #ifndef EM_XTENSA 820 #define EM_XTENSA 94 821 #endif 822 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1)) 823 dev_err(component->dev, "Wrong ELF header prefix\n"); 824 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr)) 825 dev_err(component->dev, "Wrong ELF header size\n"); 826 if (elf_hdr->e_machine != EM_XTENSA) 827 dev_err(component->dev, "Wrong DSP code file\n"); 828 829 if (len < elf_hdr->e_phoff) 830 return -ENOMEM; 831 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff); 832 for (i = 0; i < elf_hdr->e_phnum; i++) { 833 /* TODO: handle p_memsz != p_filesz */ 834 if (pr_hdr->p_paddr && pr_hdr->p_filesz) { 835 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n", 836 pr_hdr->p_filesz, pr_hdr->p_paddr); 837 838 ret = rt5677_spi_write(pr_hdr->p_paddr, 839 buf + pr_hdr->p_offset, 840 pr_hdr->p_filesz); 841 if (ret) 842 dev_err(component->dev, "Load firmware failed %d\n", 843 ret); 844 } 845 pr_hdr++; 846 } 847 return ret; 848 } 849 850 static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677) 851 { 852 struct device *dev = rt5677->component->dev; 853 int ret; 854 855 /* Load dsp firmware from rt5677_elf_vad file */ 856 const struct firmware *fwp __free(firmware) = NULL; 857 ret = request_firmware(&fwp, "rt5677_elf_vad", dev); 858 if (ret) { 859 dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret); 860 return ret; 861 } 862 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size); 863 864 return rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size); 865 } 866 867 static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on) 868 { 869 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 870 rt5677->dsp_vad_en_request = on; 871 rt5677->dsp_vad_en = on; 872 873 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) 874 return -ENXIO; 875 876 schedule_delayed_work(&rt5677->dsp_work, 0); 877 return 0; 878 } 879 880 static void rt5677_dsp_work(struct work_struct *work) 881 { 882 struct rt5677_priv *rt5677 = 883 container_of(work, struct rt5677_priv, dsp_work.work); 884 static bool activity; 885 bool enable = rt5677->dsp_vad_en; 886 int i, val; 887 888 889 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", 890 enable, activity); 891 892 if (enable && !activity) { 893 activity = true; 894 895 /* Before a hotword is detected, GPIO1 pin is configured as IRQ 896 * output so that jack detect works. When a hotword is detected, 897 * the DSP firmware configures the GPIO1 pin as GPIO1 and 898 * drives a 1. rt5677_irq() is called after a rising edge on 899 * the GPIO1 pin, due to either jack detect event or hotword 900 * event, or both. All possible events are checked and handled 901 * in rt5677_irq() where GPIO1 pin is configured back to IRQ 902 * output if a hotword is detected. 903 */ 904 905 rt5677_set_vad_source(rt5677); 906 rt5677_set_dsp_mode(rt5677, true); 907 908 #define RT5677_BOOT_RETRY 20 909 for (i = 0; i < RT5677_BOOT_RETRY; i++) { 910 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val); 911 if (val == 0x3ff) 912 break; 913 udelay(500); 914 } 915 if (i == RT5677_BOOT_RETRY && val != 0x3ff) { 916 dev_err(rt5677->component->dev, "DSP Boot Timed Out!"); 917 return; 918 } 919 920 /* Boot the firmware from IRAM instead of SRAM0. */ 921 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 922 0x0009, 0x0003); 923 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 924 0x0019, 0x0003); 925 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 926 0x0009, 0x0003); 927 928 rt5677_load_dsp_from_file(rt5677); 929 930 /* Set DSP CPU to Run */ 931 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 932 RT5677_PWR_DSP_CPU, 0x0); 933 } else if (!enable && activity) { 934 activity = false; 935 936 /* Don't turn off the DSP while handling irqs */ 937 scoped_guard(mutex, &rt5677->irq_lock) { 938 /* Set DSP CPU to Stop */ 939 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 940 RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU); 941 942 rt5677_set_dsp_mode(rt5677, false); 943 944 /* Disable and clear VAD interrupt */ 945 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); 946 947 /* Set GPIO1 pin back to be IRQ output for jack detect */ 948 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 949 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 950 } 951 } 952 } 953 954 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 955 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 956 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 957 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 958 959 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 960 static const DECLARE_TLV_DB_RANGE(bst_tlv, 961 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 962 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 963 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 964 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 965 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 966 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 967 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 968 ); 969 970 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, 971 struct snd_ctl_elem_value *ucontrol) 972 { 973 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 974 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 975 976 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request; 977 978 return 0; 979 } 980 981 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, 982 struct snd_ctl_elem_value *ucontrol) 983 { 984 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 985 986 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]); 987 988 return 0; 989 } 990 991 static const struct snd_kcontrol_new rt5677_snd_controls[] = { 992 /* OUTPUT Control */ 993 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 994 RT5677_LOUT1_L_MUTE_SFT, 1, 1), 995 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, 996 RT5677_LOUT2_L_MUTE_SFT, 1, 1), 997 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, 998 RT5677_LOUT3_L_MUTE_SFT, 1, 1), 999 1000 /* DAC Digital Volume */ 1001 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 1002 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1003 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 1004 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1005 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 1006 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1007 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 1008 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1009 1010 /* IN1/IN2 Control */ 1011 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 1012 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), 1013 1014 /* ADC Digital Volume Control */ 1015 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, 1016 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1017 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, 1018 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1019 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, 1020 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1021 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, 1022 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1023 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, 1024 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1025 1026 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 1027 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1028 adc_vol_tlv), 1029 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 1030 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1031 adc_vol_tlv), 1032 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 1033 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1034 adc_vol_tlv), 1035 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 1036 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1037 adc_vol_tlv), 1038 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 1039 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, 1040 adc_vol_tlv), 1041 1042 /* Sidetone Control */ 1043 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, 1044 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), 1045 1046 /* ADC Boost Volume Control */ 1047 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1048 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 1049 adc_bst_tlv), 1050 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1051 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 1052 adc_bst_tlv), 1053 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1054 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 1055 adc_bst_tlv), 1056 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1057 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 1058 adc_bst_tlv), 1059 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 1060 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 1061 adc_bst_tlv), 1062 1063 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, 1064 rt5677_dsp_vad_get, rt5677_dsp_vad_put), 1065 }; 1066 1067 /** 1068 * set_dmic_clk - Set parameter of dmic. 1069 * 1070 * @w: DAPM widget. 1071 * @kcontrol: The kcontrol of this widget. 1072 * @event: Event id. 1073 * 1074 * Choose dmic clock between 1MHz and 3MHz. 1075 * It is better for clock to approximate 3MHz. 1076 */ 1077 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1078 struct snd_kcontrol *kcontrol, int event) 1079 { 1080 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1081 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1082 int idx, rate; 1083 1084 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, 1085 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT); 1086 idx = rl6231_calc_dmic_clk(rate); 1087 if (idx < 0) 1088 dev_err(component->dev, "Failed to set DMIC clock\n"); 1089 else 1090 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 1091 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); 1092 return idx; 1093 } 1094 1095 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 1096 struct snd_soc_dapm_widget *sink) 1097 { 1098 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1099 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1100 unsigned int val; 1101 1102 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); 1103 val &= RT5677_SCLK_SRC_MASK; 1104 if (val == RT5677_SCLK_SRC_PLL1) 1105 return 1; 1106 else 1107 return 0; 1108 } 1109 1110 static int is_using_asrc(struct snd_soc_dapm_widget *source, 1111 struct snd_soc_dapm_widget *sink) 1112 { 1113 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1114 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1115 unsigned int reg, shift, val; 1116 1117 if (source->reg == RT5677_ASRC_1) { 1118 switch (source->shift) { 1119 case 12: 1120 reg = RT5677_ASRC_4; 1121 shift = 0; 1122 break; 1123 case 13: 1124 reg = RT5677_ASRC_4; 1125 shift = 4; 1126 break; 1127 case 14: 1128 reg = RT5677_ASRC_4; 1129 shift = 8; 1130 break; 1131 case 15: 1132 reg = RT5677_ASRC_4; 1133 shift = 12; 1134 break; 1135 default: 1136 return 0; 1137 } 1138 } else { 1139 switch (source->shift) { 1140 case 0: 1141 reg = RT5677_ASRC_6; 1142 shift = 8; 1143 break; 1144 case 1: 1145 reg = RT5677_ASRC_6; 1146 shift = 12; 1147 break; 1148 case 2: 1149 reg = RT5677_ASRC_5; 1150 shift = 0; 1151 break; 1152 case 3: 1153 reg = RT5677_ASRC_5; 1154 shift = 4; 1155 break; 1156 case 4: 1157 reg = RT5677_ASRC_5; 1158 shift = 8; 1159 break; 1160 case 5: 1161 reg = RT5677_ASRC_5; 1162 shift = 12; 1163 break; 1164 case 12: 1165 reg = RT5677_ASRC_3; 1166 shift = 0; 1167 break; 1168 case 13: 1169 reg = RT5677_ASRC_3; 1170 shift = 4; 1171 break; 1172 case 14: 1173 reg = RT5677_ASRC_3; 1174 shift = 12; 1175 break; 1176 default: 1177 return 0; 1178 } 1179 } 1180 1181 regmap_read(rt5677->regmap, reg, &val); 1182 val = (val >> shift) & 0xf; 1183 1184 switch (val) { 1185 case 1 ... 6: 1186 return 1; 1187 default: 1188 return 0; 1189 } 1190 1191 } 1192 1193 static int can_use_asrc(struct snd_soc_dapm_widget *source, 1194 struct snd_soc_dapm_widget *sink) 1195 { 1196 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1197 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1198 1199 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) 1200 return 1; 1201 1202 return 0; 1203 } 1204 1205 /** 1206 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters 1207 * @component: SoC audio component device. 1208 * @filter_mask: mask of filters. 1209 * @clk_src: clock source 1210 * 1211 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can 1212 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1213 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1214 * ASRC function will track i2s clock and generate a corresponding system clock 1215 * for codec. This function provides an API to select the clock source for a 1216 * set of filters specified by the mask. And the codec driver will turn on ASRC 1217 * for these filters if ASRC is selected as their clock source. 1218 */ 1219 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component, 1220 unsigned int filter_mask, unsigned int clk_src) 1221 { 1222 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1223 unsigned int asrc3_mask = 0, asrc3_value = 0; 1224 unsigned int asrc4_mask = 0, asrc4_value = 0; 1225 unsigned int asrc5_mask = 0, asrc5_value = 0; 1226 unsigned int asrc6_mask = 0, asrc6_value = 0; 1227 unsigned int asrc7_mask = 0, asrc7_value = 0; 1228 unsigned int asrc8_mask = 0, asrc8_value = 0; 1229 1230 switch (clk_src) { 1231 case RT5677_CLK_SEL_SYS: 1232 case RT5677_CLK_SEL_I2S1_ASRC: 1233 case RT5677_CLK_SEL_I2S2_ASRC: 1234 case RT5677_CLK_SEL_I2S3_ASRC: 1235 case RT5677_CLK_SEL_I2S4_ASRC: 1236 case RT5677_CLK_SEL_I2S5_ASRC: 1237 case RT5677_CLK_SEL_I2S6_ASRC: 1238 case RT5677_CLK_SEL_SYS2: 1239 case RT5677_CLK_SEL_SYS3: 1240 case RT5677_CLK_SEL_SYS4: 1241 case RT5677_CLK_SEL_SYS5: 1242 case RT5677_CLK_SEL_SYS6: 1243 case RT5677_CLK_SEL_SYS7: 1244 break; 1245 1246 default: 1247 return -EINVAL; 1248 } 1249 1250 /* ASRC 3 */ 1251 if (filter_mask & RT5677_DA_STEREO_FILTER) { 1252 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK; 1253 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK) 1254 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT); 1255 } 1256 1257 if (filter_mask & RT5677_DA_MONO2_L_FILTER) { 1258 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK; 1259 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK) 1260 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT); 1261 } 1262 1263 if (filter_mask & RT5677_DA_MONO2_R_FILTER) { 1264 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK; 1265 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK) 1266 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT); 1267 } 1268 1269 if (asrc3_mask) 1270 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, 1271 asrc3_value); 1272 1273 /* ASRC 4 */ 1274 if (filter_mask & RT5677_DA_MONO3_L_FILTER) { 1275 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK; 1276 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK) 1277 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT); 1278 } 1279 1280 if (filter_mask & RT5677_DA_MONO3_R_FILTER) { 1281 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK; 1282 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK) 1283 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT); 1284 } 1285 1286 if (filter_mask & RT5677_DA_MONO4_L_FILTER) { 1287 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK; 1288 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK) 1289 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT); 1290 } 1291 1292 if (filter_mask & RT5677_DA_MONO4_R_FILTER) { 1293 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK; 1294 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK) 1295 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT); 1296 } 1297 1298 if (asrc4_mask) 1299 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, 1300 asrc4_value); 1301 1302 /* ASRC 5 */ 1303 if (filter_mask & RT5677_AD_STEREO1_FILTER) { 1304 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK; 1305 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK) 1306 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT); 1307 } 1308 1309 if (filter_mask & RT5677_AD_STEREO2_FILTER) { 1310 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK; 1311 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK) 1312 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT); 1313 } 1314 1315 if (filter_mask & RT5677_AD_STEREO3_FILTER) { 1316 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK; 1317 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK) 1318 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT); 1319 } 1320 1321 if (filter_mask & RT5677_AD_STEREO4_FILTER) { 1322 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK; 1323 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK) 1324 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT); 1325 } 1326 1327 if (asrc5_mask) 1328 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, 1329 asrc5_value); 1330 1331 /* ASRC 6 */ 1332 if (filter_mask & RT5677_AD_MONO_L_FILTER) { 1333 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK; 1334 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK) 1335 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT); 1336 } 1337 1338 if (filter_mask & RT5677_AD_MONO_R_FILTER) { 1339 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK; 1340 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK) 1341 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT); 1342 } 1343 1344 if (asrc6_mask) 1345 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, 1346 asrc6_value); 1347 1348 /* ASRC 7 */ 1349 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) { 1350 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK; 1351 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK) 1352 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT); 1353 } 1354 1355 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) { 1356 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK; 1357 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK) 1358 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT); 1359 } 1360 1361 if (asrc7_mask) 1362 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, 1363 asrc7_value); 1364 1365 /* ASRC 8 */ 1366 if (filter_mask & RT5677_I2S1_SOURCE) { 1367 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK; 1368 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK) 1369 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); 1370 } 1371 1372 if (filter_mask & RT5677_I2S2_SOURCE) { 1373 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK; 1374 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK) 1375 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); 1376 } 1377 1378 if (filter_mask & RT5677_I2S3_SOURCE) { 1379 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK; 1380 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK) 1381 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); 1382 } 1383 1384 if (filter_mask & RT5677_I2S4_SOURCE) { 1385 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK; 1386 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK) 1387 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); 1388 } 1389 1390 if (asrc8_mask) 1391 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, 1392 asrc8_value); 1393 1394 return 0; 1395 } 1396 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src); 1397 1398 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source, 1399 struct snd_soc_dapm_widget *sink) 1400 { 1401 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1402 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1403 unsigned int asrc_setting; 1404 1405 switch (source->shift) { 1406 case 11: 1407 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1408 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >> 1409 RT5677_AD_STO1_CLK_SEL_SFT; 1410 break; 1411 1412 case 10: 1413 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1414 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >> 1415 RT5677_AD_STO2_CLK_SEL_SFT; 1416 break; 1417 1418 case 9: 1419 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1420 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >> 1421 RT5677_AD_STO3_CLK_SEL_SFT; 1422 break; 1423 1424 case 8: 1425 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1426 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >> 1427 RT5677_AD_STO4_CLK_SEL_SFT; 1428 break; 1429 1430 case 7: 1431 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1432 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >> 1433 RT5677_AD_MONOL_CLK_SEL_SFT; 1434 break; 1435 1436 case 6: 1437 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1438 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >> 1439 RT5677_AD_MONOR_CLK_SEL_SFT; 1440 break; 1441 1442 default: 1443 return 0; 1444 } 1445 1446 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC && 1447 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC) 1448 return 1; 1449 1450 return 0; 1451 } 1452 1453 /* Digital Mixer */ 1454 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 1455 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1456 RT5677_M_STO1_ADC_L1_SFT, 1, 1), 1457 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1458 RT5677_M_STO1_ADC_L2_SFT, 1, 1), 1459 }; 1460 1461 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { 1462 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1463 RT5677_M_STO1_ADC_R1_SFT, 1, 1), 1464 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1465 RT5677_M_STO1_ADC_R2_SFT, 1, 1), 1466 }; 1467 1468 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { 1469 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1470 RT5677_M_STO2_ADC_L1_SFT, 1, 1), 1471 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1472 RT5677_M_STO2_ADC_L2_SFT, 1, 1), 1473 }; 1474 1475 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { 1476 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1477 RT5677_M_STO2_ADC_R1_SFT, 1, 1), 1478 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1479 RT5677_M_STO2_ADC_R2_SFT, 1, 1), 1480 }; 1481 1482 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { 1483 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1484 RT5677_M_STO3_ADC_L1_SFT, 1, 1), 1485 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1486 RT5677_M_STO3_ADC_L2_SFT, 1, 1), 1487 }; 1488 1489 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { 1490 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1491 RT5677_M_STO3_ADC_R1_SFT, 1, 1), 1492 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1493 RT5677_M_STO3_ADC_R2_SFT, 1, 1), 1494 }; 1495 1496 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { 1497 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1498 RT5677_M_STO4_ADC_L1_SFT, 1, 1), 1499 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1500 RT5677_M_STO4_ADC_L2_SFT, 1, 1), 1501 }; 1502 1503 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { 1504 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1505 RT5677_M_STO4_ADC_R1_SFT, 1, 1), 1506 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1507 RT5677_M_STO4_ADC_R2_SFT, 1, 1), 1508 }; 1509 1510 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { 1511 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1512 RT5677_M_MONO_ADC_L1_SFT, 1, 1), 1513 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1514 RT5677_M_MONO_ADC_L2_SFT, 1, 1), 1515 }; 1516 1517 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { 1518 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1519 RT5677_M_MONO_ADC_R1_SFT, 1, 1), 1520 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1521 RT5677_M_MONO_ADC_R2_SFT, 1, 1), 1522 }; 1523 1524 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { 1525 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1526 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), 1527 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1528 RT5677_M_DAC1_L_SFT, 1, 1), 1529 }; 1530 1531 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { 1532 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1533 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), 1534 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1535 RT5677_M_DAC1_R_SFT, 1, 1), 1536 }; 1537 1538 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { 1539 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER, 1540 RT5677_M_ST_DAC1_L_SFT, 1, 1), 1541 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1542 RT5677_M_DAC1_L_STO_L_SFT, 1, 1), 1543 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, 1544 RT5677_M_DAC2_L_STO_L_SFT, 1, 1), 1545 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1546 RT5677_M_DAC1_R_STO_L_SFT, 1, 1), 1547 }; 1548 1549 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { 1550 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER, 1551 RT5677_M_ST_DAC1_R_SFT, 1, 1), 1552 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1553 RT5677_M_DAC1_R_STO_R_SFT, 1, 1), 1554 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, 1555 RT5677_M_DAC2_R_STO_R_SFT, 1, 1), 1556 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1557 RT5677_M_DAC1_L_STO_R_SFT, 1, 1), 1558 }; 1559 1560 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { 1561 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER, 1562 RT5677_M_ST_DAC2_L_SFT, 1, 1), 1563 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, 1564 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), 1565 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1566 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), 1567 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1568 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), 1569 }; 1570 1571 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { 1572 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER, 1573 RT5677_M_ST_DAC2_R_SFT, 1, 1), 1574 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, 1575 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), 1576 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1577 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), 1578 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1579 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), 1580 }; 1581 1582 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { 1583 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, 1584 RT5677_M_STO_L_DD1_L_SFT, 1, 1), 1585 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, 1586 RT5677_M_MONO_L_DD1_L_SFT, 1, 1), 1587 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1588 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), 1589 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1590 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), 1591 }; 1592 1593 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { 1594 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, 1595 RT5677_M_STO_R_DD1_R_SFT, 1, 1), 1596 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, 1597 RT5677_M_MONO_R_DD1_R_SFT, 1, 1), 1598 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1599 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), 1600 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1601 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), 1602 }; 1603 1604 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { 1605 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, 1606 RT5677_M_STO_L_DD2_L_SFT, 1, 1), 1607 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, 1608 RT5677_M_MONO_L_DD2_L_SFT, 1, 1), 1609 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1610 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), 1611 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1612 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), 1613 }; 1614 1615 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { 1616 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, 1617 RT5677_M_STO_R_DD2_R_SFT, 1, 1), 1618 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, 1619 RT5677_M_MONO_R_DD2_R_SFT, 1, 1), 1620 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1621 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), 1622 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1623 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), 1624 }; 1625 1626 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { 1627 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1628 RT5677_DSP_IB_01_H_SFT, 1, 1), 1629 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1630 RT5677_DSP_IB_23_H_SFT, 1, 1), 1631 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1632 RT5677_DSP_IB_45_H_SFT, 1, 1), 1633 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1634 RT5677_DSP_IB_6_H_SFT, 1, 1), 1635 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1636 RT5677_DSP_IB_7_H_SFT, 1, 1), 1637 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1638 RT5677_DSP_IB_8_H_SFT, 1, 1), 1639 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1640 RT5677_DSP_IB_9_H_SFT, 1, 1), 1641 }; 1642 1643 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { 1644 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1645 RT5677_DSP_IB_01_L_SFT, 1, 1), 1646 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1647 RT5677_DSP_IB_23_L_SFT, 1, 1), 1648 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1649 RT5677_DSP_IB_45_L_SFT, 1, 1), 1650 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1651 RT5677_DSP_IB_6_L_SFT, 1, 1), 1652 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1653 RT5677_DSP_IB_7_L_SFT, 1, 1), 1654 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1655 RT5677_DSP_IB_8_L_SFT, 1, 1), 1656 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1657 RT5677_DSP_IB_9_L_SFT, 1, 1), 1658 }; 1659 1660 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { 1661 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1662 RT5677_DSP_IB_01_H_SFT, 1, 1), 1663 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1664 RT5677_DSP_IB_23_H_SFT, 1, 1), 1665 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1666 RT5677_DSP_IB_45_H_SFT, 1, 1), 1667 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1668 RT5677_DSP_IB_6_H_SFT, 1, 1), 1669 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1670 RT5677_DSP_IB_7_H_SFT, 1, 1), 1671 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1672 RT5677_DSP_IB_8_H_SFT, 1, 1), 1673 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1674 RT5677_DSP_IB_9_H_SFT, 1, 1), 1675 }; 1676 1677 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { 1678 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1679 RT5677_DSP_IB_01_L_SFT, 1, 1), 1680 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1681 RT5677_DSP_IB_23_L_SFT, 1, 1), 1682 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1683 RT5677_DSP_IB_45_L_SFT, 1, 1), 1684 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1685 RT5677_DSP_IB_6_L_SFT, 1, 1), 1686 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1687 RT5677_DSP_IB_7_L_SFT, 1, 1), 1688 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1689 RT5677_DSP_IB_8_L_SFT, 1, 1), 1690 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1691 RT5677_DSP_IB_9_L_SFT, 1, 1), 1692 }; 1693 1694 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { 1695 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1696 RT5677_DSP_IB_01_H_SFT, 1, 1), 1697 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1698 RT5677_DSP_IB_23_H_SFT, 1, 1), 1699 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1700 RT5677_DSP_IB_45_H_SFT, 1, 1), 1701 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1702 RT5677_DSP_IB_6_H_SFT, 1, 1), 1703 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1704 RT5677_DSP_IB_7_H_SFT, 1, 1), 1705 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1706 RT5677_DSP_IB_8_H_SFT, 1, 1), 1707 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1708 RT5677_DSP_IB_9_H_SFT, 1, 1), 1709 }; 1710 1711 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { 1712 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1713 RT5677_DSP_IB_01_L_SFT, 1, 1), 1714 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1715 RT5677_DSP_IB_23_L_SFT, 1, 1), 1716 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1717 RT5677_DSP_IB_45_L_SFT, 1, 1), 1718 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1719 RT5677_DSP_IB_6_L_SFT, 1, 1), 1720 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1721 RT5677_DSP_IB_7_L_SFT, 1, 1), 1722 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1723 RT5677_DSP_IB_8_L_SFT, 1, 1), 1724 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1725 RT5677_DSP_IB_9_L_SFT, 1, 1), 1726 }; 1727 1728 1729 /* Mux */ 1730 /* DAC1 L/R Source */ /* MX-29 [10:8] */ 1731 static const char * const rt5677_dac1_src[] = { 1732 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 1733 "OB 01" 1734 }; 1735 1736 static SOC_ENUM_SINGLE_DECL( 1737 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1738 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 1739 1740 static const struct snd_kcontrol_new rt5677_dac1_mux = 1741 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); 1742 1743 /* ADDA1 L/R Source */ /* MX-29 [1:0] */ 1744 static const char * const rt5677_adda1_src[] = { 1745 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 1746 }; 1747 1748 static SOC_ENUM_SINGLE_DECL( 1749 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1750 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 1751 1752 static const struct snd_kcontrol_new rt5677_adda1_mux = 1753 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); 1754 1755 1756 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ 1757 static const char * const rt5677_dac2l_src[] = { 1758 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 1759 "OB 2", 1760 }; 1761 1762 static SOC_ENUM_SINGLE_DECL( 1763 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, 1764 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 1765 1766 static const struct snd_kcontrol_new rt5677_dac2_l_mux = 1767 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); 1768 1769 static const char * const rt5677_dac2r_src[] = { 1770 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 1771 "OB 3", "Haptic Generator", "VAD ADC" 1772 }; 1773 1774 static SOC_ENUM_SINGLE_DECL( 1775 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, 1776 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 1777 1778 static const struct snd_kcontrol_new rt5677_dac2_r_mux = 1779 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); 1780 1781 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ 1782 static const char * const rt5677_dac3l_src[] = { 1783 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 1784 "SLB DAC 4", "OB 4" 1785 }; 1786 1787 static SOC_ENUM_SINGLE_DECL( 1788 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1789 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1790 1791 static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1792 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); 1793 1794 static const char * const rt5677_dac3r_src[] = { 1795 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1796 "SLB DAC 5", "OB 5" 1797 }; 1798 1799 static SOC_ENUM_SINGLE_DECL( 1800 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1801 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1802 1803 static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1804 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); 1805 1806 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ 1807 static const char * const rt5677_dac4l_src[] = { 1808 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1809 "SLB DAC 6", "OB 6" 1810 }; 1811 1812 static SOC_ENUM_SINGLE_DECL( 1813 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1814 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1815 1816 static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1817 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); 1818 1819 static const char * const rt5677_dac4r_src[] = { 1820 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1821 "SLB DAC 7", "OB 7" 1822 }; 1823 1824 static SOC_ENUM_SINGLE_DECL( 1825 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1826 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1827 1828 static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1829 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); 1830 1831 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1832 static const char * const rt5677_iob_bypass_src[] = { 1833 "Bypass", "Pass SRC" 1834 }; 1835 1836 static SOC_ENUM_SINGLE_DECL( 1837 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1838 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1839 1840 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1841 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); 1842 1843 static SOC_ENUM_SINGLE_DECL( 1844 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1845 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1846 1847 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1848 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); 1849 1850 static SOC_ENUM_SINGLE_DECL( 1851 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1852 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1853 1854 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1855 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); 1856 1857 static SOC_ENUM_SINGLE_DECL( 1858 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1859 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1860 1861 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1862 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); 1863 1864 static SOC_ENUM_SINGLE_DECL( 1865 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1866 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1867 1868 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1869 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1870 1871 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1872 static const char * const rt5677_stereo_adc2_src[] = { 1873 "DD MIX1", "DMIC", "Stereo DAC MIX" 1874 }; 1875 1876 static SOC_ENUM_SINGLE_DECL( 1877 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, 1878 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1879 1880 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1881 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); 1882 1883 static SOC_ENUM_SINGLE_DECL( 1884 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1885 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1886 1887 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1888 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); 1889 1890 static SOC_ENUM_SINGLE_DECL( 1891 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1892 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1893 1894 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1895 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); 1896 1897 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1898 static const char * const rt5677_dmic_src[] = { 1899 "DMIC1", "DMIC2", "DMIC3", "DMIC4" 1900 }; 1901 1902 static SOC_ENUM_SINGLE_DECL( 1903 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, 1904 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1905 1906 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1907 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); 1908 1909 static SOC_ENUM_SINGLE_DECL( 1910 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1911 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1912 1913 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1914 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); 1915 1916 static SOC_ENUM_SINGLE_DECL( 1917 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1918 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1919 1920 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1921 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); 1922 1923 static SOC_ENUM_SINGLE_DECL( 1924 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1925 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1926 1927 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1928 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); 1929 1930 static SOC_ENUM_SINGLE_DECL( 1931 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1932 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1933 1934 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1935 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); 1936 1937 static SOC_ENUM_SINGLE_DECL( 1938 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1939 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1940 1941 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1942 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); 1943 1944 /* Stereo2 ADC Source */ /* MX-26 [0] */ 1945 static const char * const rt5677_stereo2_adc_lr_src[] = { 1946 "L", "LR" 1947 }; 1948 1949 static SOC_ENUM_SINGLE_DECL( 1950 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, 1951 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1952 1953 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1954 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1955 1956 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1957 static const char * const rt5677_stereo_adc1_src[] = { 1958 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1959 }; 1960 1961 static SOC_ENUM_SINGLE_DECL( 1962 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, 1963 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1964 1965 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1966 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); 1967 1968 static SOC_ENUM_SINGLE_DECL( 1969 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1970 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1971 1972 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1973 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); 1974 1975 static SOC_ENUM_SINGLE_DECL( 1976 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1977 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1978 1979 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1980 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); 1981 1982 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ 1983 static const char * const rt5677_mono_adc2_l_src[] = { 1984 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1985 }; 1986 1987 static SOC_ENUM_SINGLE_DECL( 1988 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, 1989 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 1990 1991 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 1992 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); 1993 1994 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ 1995 static const char * const rt5677_mono_adc1_l_src[] = { 1996 "DD MIX1L", "ADC1", "MONO DAC MIXL" 1997 }; 1998 1999 static SOC_ENUM_SINGLE_DECL( 2000 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, 2001 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 2002 2003 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 2004 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); 2005 2006 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ 2007 static const char * const rt5677_mono_adc2_r_src[] = { 2008 "DD MIX1R", "DMIC", "MONO DAC MIXR" 2009 }; 2010 2011 static SOC_ENUM_SINGLE_DECL( 2012 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, 2013 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 2014 2015 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 2016 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); 2017 2018 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ 2019 static const char * const rt5677_mono_adc1_r_src[] = { 2020 "DD MIX1R", "ADC2", "MONO DAC MIXR" 2021 }; 2022 2023 static SOC_ENUM_SINGLE_DECL( 2024 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, 2025 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 2026 2027 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 2028 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); 2029 2030 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 2031 static const char * const rt5677_stereo4_adc2_src[] = { 2032 "DD MIX1", "DMIC", "DD MIX2" 2033 }; 2034 2035 static SOC_ENUM_SINGLE_DECL( 2036 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, 2037 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 2038 2039 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 2040 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); 2041 2042 2043 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 2044 static const char * const rt5677_stereo4_adc1_src[] = { 2045 "DD MIX1", "ADC1/2", "DD MIX2" 2046 }; 2047 2048 static SOC_ENUM_SINGLE_DECL( 2049 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, 2050 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 2051 2052 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 2053 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); 2054 2055 /* InBound0/1 Source */ /* MX-A3 [14:12] */ 2056 static const char * const rt5677_inbound01_src[] = { 2057 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", 2058 "VAD ADC/DAC1 FS" 2059 }; 2060 2061 static SOC_ENUM_SINGLE_DECL( 2062 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, 2063 RT5677_IB01_SRC_SFT, rt5677_inbound01_src); 2064 2065 static const struct snd_kcontrol_new rt5677_ib01_src_mux = 2066 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); 2067 2068 /* InBound2/3 Source */ /* MX-A3 [10:8] */ 2069 static const char * const rt5677_inbound23_src[] = { 2070 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", 2071 "DAC1 FS", "IF4 DAC" 2072 }; 2073 2074 static SOC_ENUM_SINGLE_DECL( 2075 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, 2076 RT5677_IB23_SRC_SFT, rt5677_inbound23_src); 2077 2078 static const struct snd_kcontrol_new rt5677_ib23_src_mux = 2079 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); 2080 2081 /* InBound4/5 Source */ /* MX-A3 [6:4] */ 2082 static const char * const rt5677_inbound45_src[] = { 2083 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", 2084 "IF3 DAC" 2085 }; 2086 2087 static SOC_ENUM_SINGLE_DECL( 2088 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, 2089 RT5677_IB45_SRC_SFT, rt5677_inbound45_src); 2090 2091 static const struct snd_kcontrol_new rt5677_ib45_src_mux = 2092 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); 2093 2094 /* InBound6 Source */ /* MX-A3 [2:0] */ 2095 static const char * const rt5677_inbound6_src[] = { 2096 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", 2097 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" 2098 }; 2099 2100 static SOC_ENUM_SINGLE_DECL( 2101 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, 2102 RT5677_IB6_SRC_SFT, rt5677_inbound6_src); 2103 2104 static const struct snd_kcontrol_new rt5677_ib6_src_mux = 2105 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); 2106 2107 /* InBound7 Source */ /* MX-A4 [14:12] */ 2108 static const char * const rt5677_inbound7_src[] = { 2109 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", 2110 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" 2111 }; 2112 2113 static SOC_ENUM_SINGLE_DECL( 2114 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, 2115 RT5677_IB7_SRC_SFT, rt5677_inbound7_src); 2116 2117 static const struct snd_kcontrol_new rt5677_ib7_src_mux = 2118 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); 2119 2120 /* InBound8 Source */ /* MX-A4 [10:8] */ 2121 static const char * const rt5677_inbound8_src[] = { 2122 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", 2123 "MONO ADC MIX L", "DACL1 FS" 2124 }; 2125 2126 static SOC_ENUM_SINGLE_DECL( 2127 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, 2128 RT5677_IB8_SRC_SFT, rt5677_inbound8_src); 2129 2130 static const struct snd_kcontrol_new rt5677_ib8_src_mux = 2131 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); 2132 2133 /* InBound9 Source */ /* MX-A4 [6:4] */ 2134 static const char * const rt5677_inbound9_src[] = { 2135 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", 2136 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" 2137 }; 2138 2139 static SOC_ENUM_SINGLE_DECL( 2140 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, 2141 RT5677_IB9_SRC_SFT, rt5677_inbound9_src); 2142 2143 static const struct snd_kcontrol_new rt5677_ib9_src_mux = 2144 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); 2145 2146 /* VAD Source */ /* MX-9F [6:4] */ 2147 static const char * const rt5677_vad_src[] = { 2148 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", 2149 "STO3 ADC MIX L" 2150 }; 2151 2152 static SOC_ENUM_SINGLE_DECL( 2153 rt5677_vad_enum, RT5677_VAD_CTRL4, 2154 RT5677_VAD_SRC_SFT, rt5677_vad_src); 2155 2156 static const struct snd_kcontrol_new rt5677_vad_src_mux = 2157 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); 2158 2159 /* Sidetone Source */ /* MX-13 [11:9] */ 2160 static const char * const rt5677_sidetone_src[] = { 2161 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" 2162 }; 2163 2164 static SOC_ENUM_SINGLE_DECL( 2165 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, 2166 RT5677_ST_SEL_SFT, rt5677_sidetone_src); 2167 2168 static const struct snd_kcontrol_new rt5677_sidetone_mux = 2169 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); 2170 2171 /* DAC1/2 Source */ /* MX-15 [1:0] */ 2172 static const char * const rt5677_dac12_src[] = { 2173 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2174 }; 2175 2176 static SOC_ENUM_SINGLE_DECL( 2177 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, 2178 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); 2179 2180 static const struct snd_kcontrol_new rt5677_dac12_mux = 2181 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); 2182 2183 /* DAC3 Source */ /* MX-15 [5:4] */ 2184 static const char * const rt5677_dac3_src[] = { 2185 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" 2186 }; 2187 2188 static SOC_ENUM_SINGLE_DECL( 2189 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, 2190 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); 2191 2192 static const struct snd_kcontrol_new rt5677_dac3_mux = 2193 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 2194 2195 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 2196 static const char * const rt5677_pdm_src[] = { 2197 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2198 }; 2199 2200 static SOC_ENUM_SINGLE_DECL( 2201 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, 2202 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 2203 2204 static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 2205 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); 2206 2207 static SOC_ENUM_SINGLE_DECL( 2208 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 2209 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 2210 2211 static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 2212 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); 2213 2214 static SOC_ENUM_SINGLE_DECL( 2215 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 2216 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 2217 2218 static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 2219 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); 2220 2221 static SOC_ENUM_SINGLE_DECL( 2222 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 2223 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 2224 2225 static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 2226 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 2227 2228 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ 2229 static const char * const rt5677_if12_adc1_src[] = { 2230 "STO1 ADC MIX", "OB01", "VAD ADC" 2231 }; 2232 2233 static SOC_ENUM_SINGLE_DECL( 2234 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, 2235 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 2236 2237 static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 2238 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); 2239 2240 static SOC_ENUM_SINGLE_DECL( 2241 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 2242 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 2243 2244 static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 2245 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); 2246 2247 static SOC_ENUM_SINGLE_DECL( 2248 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 2249 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 2250 2251 static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 2252 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); 2253 2254 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 2255 static const char * const rt5677_if12_adc2_src[] = { 2256 "STO2 ADC MIX", "OB23" 2257 }; 2258 2259 static SOC_ENUM_SINGLE_DECL( 2260 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, 2261 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 2262 2263 static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 2264 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); 2265 2266 static SOC_ENUM_SINGLE_DECL( 2267 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 2268 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 2269 2270 static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 2271 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); 2272 2273 static SOC_ENUM_SINGLE_DECL( 2274 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 2275 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 2276 2277 static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 2278 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); 2279 2280 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 2281 static const char * const rt5677_if12_adc3_src[] = { 2282 "STO3 ADC MIX", "MONO ADC MIX", "OB45" 2283 }; 2284 2285 static SOC_ENUM_SINGLE_DECL( 2286 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, 2287 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 2288 2289 static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 2290 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); 2291 2292 static SOC_ENUM_SINGLE_DECL( 2293 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 2294 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 2295 2296 static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 2297 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); 2298 2299 static SOC_ENUM_SINGLE_DECL( 2300 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 2301 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 2302 2303 static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 2304 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 2305 2306 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 2307 static const char * const rt5677_if12_adc4_src[] = { 2308 "STO4 ADC MIX", "OB67", "OB01" 2309 }; 2310 2311 static SOC_ENUM_SINGLE_DECL( 2312 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, 2313 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 2314 2315 static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 2316 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); 2317 2318 static SOC_ENUM_SINGLE_DECL( 2319 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 2320 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 2321 2322 static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 2323 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); 2324 2325 static SOC_ENUM_SINGLE_DECL( 2326 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 2327 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 2328 2329 static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 2330 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 2331 2332 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ 2333 static const char * const rt5677_if34_adc_src[] = { 2334 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 2335 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 2336 }; 2337 2338 static SOC_ENUM_SINGLE_DECL( 2339 rt5677_if3_adc_enum, RT5677_IF3_DATA, 2340 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 2341 2342 static const struct snd_kcontrol_new rt5677_if3_adc_mux = 2343 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); 2344 2345 static SOC_ENUM_SINGLE_DECL( 2346 rt5677_if4_adc_enum, RT5677_IF4_DATA, 2347 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 2348 2349 static const struct snd_kcontrol_new rt5677_if4_adc_mux = 2350 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 2351 2352 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ 2353 static const char * const rt5677_if12_adc_swap_src[] = { 2354 "L/R", "R/L", "L/L", "R/R" 2355 }; 2356 2357 static SOC_ENUM_SINGLE_DECL( 2358 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, 2359 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); 2360 2361 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = 2362 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); 2363 2364 static SOC_ENUM_SINGLE_DECL( 2365 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, 2366 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2367 2368 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = 2369 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); 2370 2371 static SOC_ENUM_SINGLE_DECL( 2372 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, 2373 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2374 2375 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = 2376 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); 2377 2378 static SOC_ENUM_SINGLE_DECL( 2379 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, 2380 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2381 2382 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = 2383 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); 2384 2385 static SOC_ENUM_SINGLE_DECL( 2386 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, 2387 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2388 2389 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = 2390 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); 2391 2392 static SOC_ENUM_SINGLE_DECL( 2393 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, 2394 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2395 2396 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = 2397 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); 2398 2399 static SOC_ENUM_SINGLE_DECL( 2400 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, 2401 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2402 2403 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = 2404 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); 2405 2406 static SOC_ENUM_SINGLE_DECL( 2407 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, 2408 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2409 2410 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = 2411 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); 2412 2413 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ 2414 static const char * const rt5677_if1_adc_tdm_swap_src[] = { 2415 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2416 "3/1/2/4", "3/4/1/2" 2417 }; 2418 2419 static SOC_ENUM_SINGLE_DECL( 2420 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, 2421 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); 2422 2423 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = 2424 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); 2425 2426 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ 2427 static const char * const rt5677_if2_adc_tdm_swap_src[] = { 2428 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2429 "2/3/1/4", "3/4/1/2" 2430 }; 2431 2432 static SOC_ENUM_SINGLE_DECL( 2433 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, 2434 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); 2435 2436 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = 2437 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); 2438 2439 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] 2440 MX-3F[14:12][10:8][6:4][2:0] 2441 MX-43[14:12][10:8][6:4][2:0] 2442 MX-44[14:12][10:8][6:4][2:0] */ 2443 static const char * const rt5677_if12_dac_tdm_sel_src[] = { 2444 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 2445 }; 2446 2447 static SOC_ENUM_SINGLE_DECL( 2448 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, 2449 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2450 2451 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = 2452 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); 2453 2454 static SOC_ENUM_SINGLE_DECL( 2455 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, 2456 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2457 2458 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = 2459 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); 2460 2461 static SOC_ENUM_SINGLE_DECL( 2462 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, 2463 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2464 2465 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = 2466 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); 2467 2468 static SOC_ENUM_SINGLE_DECL( 2469 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, 2470 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2471 2472 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = 2473 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); 2474 2475 static SOC_ENUM_SINGLE_DECL( 2476 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, 2477 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2478 2479 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = 2480 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); 2481 2482 static SOC_ENUM_SINGLE_DECL( 2483 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, 2484 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2485 2486 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = 2487 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); 2488 2489 static SOC_ENUM_SINGLE_DECL( 2490 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, 2491 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2492 2493 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = 2494 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); 2495 2496 static SOC_ENUM_SINGLE_DECL( 2497 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, 2498 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2499 2500 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = 2501 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); 2502 2503 static SOC_ENUM_SINGLE_DECL( 2504 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, 2505 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2506 2507 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = 2508 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); 2509 2510 static SOC_ENUM_SINGLE_DECL( 2511 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, 2512 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2513 2514 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = 2515 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); 2516 2517 static SOC_ENUM_SINGLE_DECL( 2518 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, 2519 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2520 2521 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = 2522 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); 2523 2524 static SOC_ENUM_SINGLE_DECL( 2525 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, 2526 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2527 2528 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = 2529 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); 2530 2531 static SOC_ENUM_SINGLE_DECL( 2532 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, 2533 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2534 2535 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = 2536 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); 2537 2538 static SOC_ENUM_SINGLE_DECL( 2539 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, 2540 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2541 2542 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = 2543 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); 2544 2545 static SOC_ENUM_SINGLE_DECL( 2546 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, 2547 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2548 2549 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = 2550 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); 2551 2552 static SOC_ENUM_SINGLE_DECL( 2553 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, 2554 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2555 2556 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = 2557 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); 2558 2559 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2560 struct snd_kcontrol *kcontrol, int event) 2561 { 2562 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2563 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2564 2565 switch (event) { 2566 case SND_SOC_DAPM_POST_PMU: 2567 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2568 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); 2569 break; 2570 2571 case SND_SOC_DAPM_PRE_PMD: 2572 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2573 RT5677_PWR_BST1_P, 0); 2574 break; 2575 2576 default: 2577 return 0; 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, 2584 struct snd_kcontrol *kcontrol, int event) 2585 { 2586 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2587 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2588 2589 switch (event) { 2590 case SND_SOC_DAPM_POST_PMU: 2591 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2592 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); 2593 break; 2594 2595 case SND_SOC_DAPM_PRE_PMD: 2596 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2597 RT5677_PWR_BST2_P, 0); 2598 break; 2599 2600 default: 2601 return 0; 2602 } 2603 2604 return 0; 2605 } 2606 2607 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, 2608 struct snd_kcontrol *kcontrol, int event) 2609 { 2610 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2611 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2612 2613 switch (event) { 2614 case SND_SOC_DAPM_PRE_PMU: 2615 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); 2616 break; 2617 2618 case SND_SOC_DAPM_POST_PMU: 2619 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); 2620 break; 2621 2622 default: 2623 return 0; 2624 } 2625 2626 return 0; 2627 } 2628 2629 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, 2630 struct snd_kcontrol *kcontrol, int event) 2631 { 2632 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2633 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2634 2635 switch (event) { 2636 case SND_SOC_DAPM_PRE_PMU: 2637 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); 2638 break; 2639 2640 case SND_SOC_DAPM_POST_PMU: 2641 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); 2642 break; 2643 2644 default: 2645 return 0; 2646 } 2647 2648 return 0; 2649 } 2650 2651 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, 2652 struct snd_kcontrol *kcontrol, int event) 2653 { 2654 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2655 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2656 2657 switch (event) { 2658 case SND_SOC_DAPM_POST_PMU: 2659 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2660 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2661 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 2662 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 2663 break; 2664 2665 case SND_SOC_DAPM_PRE_PMD: 2666 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2667 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2668 RT5677_PWR_CLK_MB, 0); 2669 break; 2670 2671 default: 2672 return 0; 2673 } 2674 2675 return 0; 2676 } 2677 2678 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, 2679 struct snd_kcontrol *kcontrol, int event) 2680 { 2681 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2682 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2683 unsigned int value; 2684 2685 switch (event) { 2686 case SND_SOC_DAPM_PRE_PMU: 2687 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); 2688 if (value & RT5677_IF1_ADC_CTRL_MASK) 2689 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 2690 RT5677_IF1_ADC_MODE_MASK, 2691 RT5677_IF1_ADC_MODE_TDM); 2692 break; 2693 2694 default: 2695 return 0; 2696 } 2697 2698 return 0; 2699 } 2700 2701 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, 2702 struct snd_kcontrol *kcontrol, int event) 2703 { 2704 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2705 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2706 unsigned int value; 2707 2708 switch (event) { 2709 case SND_SOC_DAPM_PRE_PMU: 2710 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); 2711 if (value & RT5677_IF2_ADC_CTRL_MASK) 2712 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 2713 RT5677_IF2_ADC_MODE_MASK, 2714 RT5677_IF2_ADC_MODE_TDM); 2715 break; 2716 2717 default: 2718 return 0; 2719 } 2720 2721 return 0; 2722 } 2723 2724 static int rt5677_vref_event(struct snd_soc_dapm_widget *w, 2725 struct snd_kcontrol *kcontrol, int event) 2726 { 2727 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2728 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2729 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2730 2731 switch (event) { 2732 case SND_SOC_DAPM_POST_PMU: 2733 if (snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_ON && 2734 !rt5677->is_vref_slow) { 2735 mdelay(20); 2736 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 2737 RT5677_PWR_FV1 | RT5677_PWR_FV2, 2738 RT5677_PWR_FV1 | RT5677_PWR_FV2); 2739 rt5677->is_vref_slow = true; 2740 } 2741 break; 2742 2743 default: 2744 return 0; 2745 } 2746 2747 return 0; 2748 } 2749 2750 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w, 2751 struct snd_kcontrol *kcontrol, int event) 2752 { 2753 switch (event) { 2754 case SND_SOC_DAPM_POST_PMU: 2755 msleep(50); 2756 break; 2757 2758 default: 2759 return 0; 2760 } 2761 2762 return 0; 2763 } 2764 2765 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2766 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2767 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | 2768 SND_SOC_DAPM_POST_PMU), 2769 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, 2770 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | 2771 SND_SOC_DAPM_POST_PMU), 2772 2773 /* ASRC */ 2774 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0), 2775 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0), 2776 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0), 2777 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0), 2778 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, 2779 rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU), 2780 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL, 2781 0), 2782 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL, 2783 0), 2784 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL, 2785 0), 2786 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL, 2787 0), 2788 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL, 2789 0), 2790 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL, 2791 0), 2792 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL, 2793 0), 2794 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL, 2795 0), 2796 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL, 2797 0), 2798 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL, 2799 0), 2800 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL, 2801 0), 2802 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL, 2803 0), 2804 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0), 2805 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0), 2806 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0), 2807 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0), 2808 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL, 2809 0), 2810 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL, 2811 0), 2812 2813 /* Input Side */ 2814 /* micbias */ 2815 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 2816 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | 2817 SND_SOC_DAPM_POST_PMU), 2818 2819 /* Input Lines */ 2820 SND_SOC_DAPM_INPUT("DMIC L1"), 2821 SND_SOC_DAPM_INPUT("DMIC R1"), 2822 SND_SOC_DAPM_INPUT("DMIC L2"), 2823 SND_SOC_DAPM_INPUT("DMIC R2"), 2824 SND_SOC_DAPM_INPUT("DMIC L3"), 2825 SND_SOC_DAPM_INPUT("DMIC R3"), 2826 SND_SOC_DAPM_INPUT("DMIC L4"), 2827 SND_SOC_DAPM_INPUT("DMIC R4"), 2828 2829 SND_SOC_DAPM_INPUT("IN1P"), 2830 SND_SOC_DAPM_INPUT("IN1N"), 2831 SND_SOC_DAPM_INPUT("IN2P"), 2832 SND_SOC_DAPM_INPUT("IN2N"), 2833 2834 SND_SOC_DAPM_INPUT("Haptic Generator"), 2835 2836 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2837 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2838 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2839 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2840 2841 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, 2842 RT5677_DMIC_1_EN_SFT, 0, NULL, 0), 2843 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, 2844 RT5677_DMIC_2_EN_SFT, 0, NULL, 0), 2845 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, 2846 RT5677_DMIC_3_EN_SFT, 0, NULL, 0), 2847 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, 2848 RT5677_DMIC_4_EN_SFT, 0, NULL, 0), 2849 2850 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2851 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2852 2853 /* Boost */ 2854 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, 2855 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, 2856 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2857 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, 2858 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, 2859 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2860 2861 /* ADCs */ 2862 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 2863 0, 0), 2864 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 2865 0, 0), 2866 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), 2867 2868 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, 2869 RT5677_PWR_ADC_L_BIT, 0, NULL, 0), 2870 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, 2871 RT5677_PWR_ADC_R_BIT, 0, NULL, 0), 2872 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, 2873 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), 2874 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, 2875 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), 2876 2877 /* ADC Mux */ 2878 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2879 &rt5677_sto1_dmic_mux), 2880 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2881 &rt5677_sto1_adc1_mux), 2882 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2883 &rt5677_sto1_adc2_mux), 2884 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 2885 &rt5677_sto2_dmic_mux), 2886 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2887 &rt5677_sto2_adc1_mux), 2888 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2889 &rt5677_sto2_adc2_mux), 2890 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, 2891 &rt5677_sto2_adc_lr_mux), 2892 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, 2893 &rt5677_sto3_dmic_mux), 2894 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2895 &rt5677_sto3_adc1_mux), 2896 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2897 &rt5677_sto3_adc2_mux), 2898 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, 2899 &rt5677_sto4_dmic_mux), 2900 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2901 &rt5677_sto4_adc1_mux), 2902 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2903 &rt5677_sto4_adc2_mux), 2904 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2905 &rt5677_mono_dmic_l_mux), 2906 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2907 &rt5677_mono_dmic_r_mux), 2908 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, 2909 &rt5677_mono_adc2_l_mux), 2910 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, 2911 &rt5677_mono_adc1_l_mux), 2912 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, 2913 &rt5677_mono_adc1_r_mux), 2914 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, 2915 &rt5677_mono_adc2_r_mux), 2916 2917 /* ADC Mixer */ 2918 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, 2919 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), 2920 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, 2921 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), 2922 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, 2923 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), 2924 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, 2925 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), 2926 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2927 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), 2928 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2929 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), 2930 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 2931 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), 2932 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 2933 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), 2934 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, 2935 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), 2936 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, 2937 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), 2938 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, 2939 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), 2940 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, 2941 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), 2942 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, 2943 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2944 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2945 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), 2946 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, 2947 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2948 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2949 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), 2950 2951 /* ADC PGA */ 2952 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2953 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2954 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2955 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2956 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2957 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2958 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2959 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2960 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2961 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2962 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2963 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2964 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2965 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2966 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2967 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2968 2969 /* DSP */ 2970 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2971 &rt5677_ib9_src_mux), 2972 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, 2973 &rt5677_ib8_src_mux), 2974 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, 2975 &rt5677_ib7_src_mux), 2976 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, 2977 &rt5677_ib6_src_mux), 2978 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, 2979 &rt5677_ib45_src_mux), 2980 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, 2981 &rt5677_ib23_src_mux), 2982 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, 2983 &rt5677_ib01_src_mux), 2984 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, 2985 &rt5677_ib45_bypass_src_mux), 2986 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2987 &rt5677_ib23_bypass_src_mux), 2988 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2989 &rt5677_ib01_bypass_src_mux), 2990 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2991 &rt5677_ob23_bypass_src_mux), 2992 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2993 &rt5677_ob01_bypass_src_mux), 2994 2995 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), 2996 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), 2997 2998 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), 2999 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), 3000 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), 3001 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), 3002 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), 3003 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), 3004 3005 /* Digital Interface */ 3006 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, 3007 RT5677_PWR_I2S1_BIT, 0, NULL, 0), 3008 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3009 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3010 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3011 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3012 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3013 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3014 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3015 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3016 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3017 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3018 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3019 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3020 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3021 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3022 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3023 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3024 3025 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, 3026 RT5677_PWR_I2S2_BIT, 0, NULL, 0), 3027 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3028 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3029 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3030 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3031 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3032 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3033 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3034 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3035 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3036 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3037 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3038 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3039 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3040 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3041 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3042 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3043 3044 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, 3045 RT5677_PWR_I2S3_BIT, 0, NULL, 0), 3046 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3047 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3048 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3049 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3050 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3051 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3052 3053 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, 3054 RT5677_PWR_I2S4_BIT, 0, NULL, 0), 3055 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3056 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3057 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3058 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3059 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3060 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3061 3062 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, 3063 RT5677_PWR_SLB_BIT, 0, NULL, 0), 3064 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3065 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3066 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3067 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3068 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3069 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3070 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3071 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3072 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3073 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3074 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3075 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3076 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3077 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3078 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3079 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3080 3081 /* Digital Interface Select */ 3082 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3083 &rt5677_if1_adc1_mux), 3084 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3085 &rt5677_if1_adc2_mux), 3086 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3087 &rt5677_if1_adc3_mux), 3088 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3089 &rt5677_if1_adc4_mux), 3090 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3091 &rt5677_if1_adc1_swap_mux), 3092 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3093 &rt5677_if1_adc2_swap_mux), 3094 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3095 &rt5677_if1_adc3_swap_mux), 3096 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3097 &rt5677_if1_adc4_swap_mux), 3098 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3099 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, 3100 SND_SOC_DAPM_PRE_PMU), 3101 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3102 &rt5677_if2_adc1_mux), 3103 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3104 &rt5677_if2_adc2_mux), 3105 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3106 &rt5677_if2_adc3_mux), 3107 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3108 &rt5677_if2_adc4_mux), 3109 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3110 &rt5677_if2_adc1_swap_mux), 3111 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3112 &rt5677_if2_adc2_swap_mux), 3113 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3114 &rt5677_if2_adc3_swap_mux), 3115 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3116 &rt5677_if2_adc4_swap_mux), 3117 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3118 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, 3119 SND_SOC_DAPM_PRE_PMU), 3120 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 3121 &rt5677_if3_adc_mux), 3122 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 3123 &rt5677_if4_adc_mux), 3124 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, 3125 &rt5677_slb_adc1_mux), 3126 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, 3127 &rt5677_slb_adc2_mux), 3128 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, 3129 &rt5677_slb_adc3_mux), 3130 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 3131 &rt5677_slb_adc4_mux), 3132 3133 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3134 &rt5677_if1_dac0_tdm_sel_mux), 3135 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3136 &rt5677_if1_dac1_tdm_sel_mux), 3137 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3138 &rt5677_if1_dac2_tdm_sel_mux), 3139 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3140 &rt5677_if1_dac3_tdm_sel_mux), 3141 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3142 &rt5677_if1_dac4_tdm_sel_mux), 3143 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3144 &rt5677_if1_dac5_tdm_sel_mux), 3145 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3146 &rt5677_if1_dac6_tdm_sel_mux), 3147 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3148 &rt5677_if1_dac7_tdm_sel_mux), 3149 3150 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3151 &rt5677_if2_dac0_tdm_sel_mux), 3152 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3153 &rt5677_if2_dac1_tdm_sel_mux), 3154 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3155 &rt5677_if2_dac2_tdm_sel_mux), 3156 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3157 &rt5677_if2_dac3_tdm_sel_mux), 3158 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3159 &rt5677_if2_dac4_tdm_sel_mux), 3160 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3161 &rt5677_if2_dac5_tdm_sel_mux), 3162 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3163 &rt5677_if2_dac6_tdm_sel_mux), 3164 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3165 &rt5677_if2_dac7_tdm_sel_mux), 3166 3167 /* Audio Interface */ 3168 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 3169 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 3170 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 3171 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 3172 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 3173 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 3174 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), 3175 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), 3176 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), 3177 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), 3178 SND_SOC_DAPM_AIF_OUT("DSPTX", "DSP Buffer", 0, SND_SOC_NOPM, 0, 0), 3179 3180 /* Sidetone Mux */ 3181 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, 3182 &rt5677_sidetone_mux), 3183 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, 3184 RT5677_ST_EN_SFT, 0, NULL, 0), 3185 3186 /* VAD Mux*/ 3187 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, 3188 &rt5677_vad_src_mux), 3189 3190 /* Tensilica DSP */ 3191 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 3192 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, 3193 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), 3194 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, 3195 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), 3196 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, 3197 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), 3198 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, 3199 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), 3200 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, 3201 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), 3202 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, 3203 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 3204 3205 /* Output Side */ 3206 /* DAC mixer before sound effect */ 3207 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 3208 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 3209 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 3210 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), 3211 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), 3212 3213 /* DAC Mux */ 3214 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, 3215 &rt5677_dac1_mux), 3216 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, 3217 &rt5677_adda1_mux), 3218 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, 3219 &rt5677_dac12_mux), 3220 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, 3221 &rt5677_dac3_mux), 3222 3223 /* DAC2 channel Mux */ 3224 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, 3225 &rt5677_dac2_l_mux), 3226 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, 3227 &rt5677_dac2_r_mux), 3228 3229 /* DAC3 channel Mux */ 3230 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, 3231 &rt5677_dac3_l_mux), 3232 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, 3233 &rt5677_dac3_r_mux), 3234 3235 /* DAC4 channel Mux */ 3236 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, 3237 &rt5677_dac4_l_mux), 3238 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, 3239 &rt5677_dac4_r_mux), 3240 3241 /* DAC Mixer */ 3242 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, 3243 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event, 3244 SND_SOC_DAPM_POST_PMU), 3245 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2, 3246 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event, 3247 SND_SOC_DAPM_POST_PMU), 3248 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2, 3249 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event, 3250 SND_SOC_DAPM_POST_PMU), 3251 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2, 3252 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event, 3253 SND_SOC_DAPM_POST_PMU), 3254 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2, 3255 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event, 3256 SND_SOC_DAPM_POST_PMU), 3257 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2, 3258 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event, 3259 SND_SOC_DAPM_POST_PMU), 3260 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2, 3261 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event, 3262 SND_SOC_DAPM_POST_PMU), 3263 3264 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 3265 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), 3266 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 3267 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), 3268 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 3269 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), 3270 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 3271 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), 3272 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, 3273 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), 3274 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, 3275 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), 3276 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, 3277 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), 3278 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, 3279 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), 3280 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3281 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3282 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3283 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3284 3285 /* DACs */ 3286 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, 3287 RT5677_PWR_DAC1_BIT, 0), 3288 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, 3289 RT5677_PWR_DAC2_BIT, 0), 3290 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, 3291 RT5677_PWR_DAC3_BIT, 0), 3292 3293 /* PDM */ 3294 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, 3295 RT5677_PWR_PDM1_BIT, 0, NULL, 0), 3296 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, 3297 RT5677_PWR_PDM2_BIT, 0, NULL, 0), 3298 3299 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, 3300 1, &rt5677_pdm1_l_mux), 3301 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, 3302 1, &rt5677_pdm1_r_mux), 3303 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, 3304 1, &rt5677_pdm2_l_mux), 3305 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 3306 1, &rt5677_pdm2_r_mux), 3307 3308 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 3309 0, NULL, 0), 3310 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 3311 0, NULL, 0), 3312 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 3313 0, NULL, 0), 3314 3315 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, 3316 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3317 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, 3318 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3319 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, 3320 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3321 3322 /* Output Lines */ 3323 SND_SOC_DAPM_OUTPUT("LOUT1"), 3324 SND_SOC_DAPM_OUTPUT("LOUT2"), 3325 SND_SOC_DAPM_OUTPUT("LOUT3"), 3326 SND_SOC_DAPM_OUTPUT("PDM1L"), 3327 SND_SOC_DAPM_OUTPUT("PDM1R"), 3328 SND_SOC_DAPM_OUTPUT("PDM2L"), 3329 SND_SOC_DAPM_OUTPUT("PDM2R"), 3330 3331 SND_SOC_DAPM_POST("vref", rt5677_vref_event), 3332 }; 3333 3334 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 3335 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc }, 3336 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc }, 3337 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc }, 3338 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc }, 3339 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc }, 3340 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc }, 3341 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc}, 3342 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc}, 3343 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc}, 3344 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc}, 3345 3346 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 3347 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc }, 3348 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc }, 3349 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc }, 3350 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc }, 3351 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc }, 3352 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc }, 3353 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 3354 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc }, 3355 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc }, 3356 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc }, 3357 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 3358 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 3359 3360 { "DMIC1", NULL, "DMIC L1" }, 3361 { "DMIC1", NULL, "DMIC R1" }, 3362 { "DMIC2", NULL, "DMIC L2" }, 3363 { "DMIC2", NULL, "DMIC R2" }, 3364 { "DMIC3", NULL, "DMIC L3" }, 3365 { "DMIC3", NULL, "DMIC R3" }, 3366 { "DMIC4", NULL, "DMIC L4" }, 3367 { "DMIC4", NULL, "DMIC R4" }, 3368 3369 { "DMIC L1", NULL, "DMIC CLK" }, 3370 { "DMIC R1", NULL, "DMIC CLK" }, 3371 { "DMIC L2", NULL, "DMIC CLK" }, 3372 { "DMIC R2", NULL, "DMIC CLK" }, 3373 { "DMIC L3", NULL, "DMIC CLK" }, 3374 { "DMIC R3", NULL, "DMIC CLK" }, 3375 { "DMIC L4", NULL, "DMIC CLK" }, 3376 { "DMIC R4", NULL, "DMIC CLK" }, 3377 3378 { "DMIC L1", NULL, "DMIC1 power" }, 3379 { "DMIC R1", NULL, "DMIC1 power" }, 3380 { "DMIC L3", NULL, "DMIC3 power" }, 3381 { "DMIC R3", NULL, "DMIC3 power" }, 3382 { "DMIC L4", NULL, "DMIC4 power" }, 3383 { "DMIC R4", NULL, "DMIC4 power" }, 3384 3385 { "BST1", NULL, "IN1P" }, 3386 { "BST1", NULL, "IN1N" }, 3387 { "BST2", NULL, "IN2P" }, 3388 { "BST2", NULL, "IN2N" }, 3389 3390 { "IN1P", NULL, "MICBIAS1" }, 3391 { "IN1N", NULL, "MICBIAS1" }, 3392 { "IN2P", NULL, "MICBIAS1" }, 3393 { "IN2N", NULL, "MICBIAS1" }, 3394 3395 { "ADC 1", NULL, "BST1" }, 3396 { "ADC 1", NULL, "ADC 1 power" }, 3397 { "ADC 1", NULL, "ADC1 clock" }, 3398 { "ADC 2", NULL, "BST2" }, 3399 { "ADC 2", NULL, "ADC 2 power" }, 3400 { "ADC 2", NULL, "ADC2 clock" }, 3401 3402 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 3403 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 3404 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, 3405 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, 3406 3407 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 3408 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 3409 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, 3410 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, 3411 3412 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, 3413 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, 3414 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, 3415 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, 3416 3417 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, 3418 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, 3419 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, 3420 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, 3421 3422 { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, 3423 { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, 3424 { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, 3425 { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, 3426 3427 { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, 3428 { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, 3429 { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, 3430 { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, 3431 3432 { "ADC 1_2", NULL, "ADC 1" }, 3433 { "ADC 1_2", NULL, "ADC 2" }, 3434 3435 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3436 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3437 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3438 3439 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3440 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 3441 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3442 3443 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3444 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3445 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3446 3447 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3448 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, 3449 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3450 3451 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3452 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3453 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3454 3455 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3456 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3457 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3458 3459 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3460 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3461 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, 3462 3463 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3464 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3465 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, 3466 3467 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, 3468 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, 3469 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3470 3471 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, 3472 { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, 3473 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3474 3475 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, 3476 { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, 3477 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3478 3479 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, 3480 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, 3481 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3482 3483 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3484 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3485 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3486 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3487 3488 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 3489 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 3490 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 3491 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 3492 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3493 3494 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 3495 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 3496 3497 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3498 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3499 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3500 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3501 3502 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, 3503 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, 3504 3505 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, 3506 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, 3507 3508 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, 3509 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, 3510 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 3511 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, 3512 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3513 3514 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 3515 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 3516 3517 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3518 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3519 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3520 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3521 3522 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, 3523 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, 3524 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, 3525 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, 3526 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3527 3528 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, 3529 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, 3530 3531 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3532 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3533 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3534 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3535 3536 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, 3537 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, 3538 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, 3539 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, 3540 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3541 3542 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, 3543 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, 3544 3545 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, 3546 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, 3547 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 3548 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3549 3550 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, 3551 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, 3552 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 3553 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3554 3555 { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, 3556 { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, 3557 3558 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3559 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3560 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3561 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3562 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3563 3564 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3565 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3566 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3567 3568 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3569 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3570 3571 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3572 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3573 { "IF1 ADC3 Mux", "OB45", "OB45" }, 3574 3575 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3576 { "IF1 ADC4 Mux", "OB67", "OB67" }, 3577 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3578 3579 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, 3580 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, 3581 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, 3582 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, 3583 3584 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, 3585 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, 3586 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, 3587 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, 3588 3589 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, 3590 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, 3591 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, 3592 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, 3593 3594 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, 3595 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, 3596 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, 3597 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, 3598 3599 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, 3600 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, 3601 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, 3602 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, 3603 3604 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, 3605 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, 3606 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, 3607 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, 3608 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, 3609 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, 3610 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, 3611 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, 3612 3613 { "AIF1TX", NULL, "I2S1" }, 3614 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, 3615 3616 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3617 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3618 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3619 3620 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3621 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3622 3623 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3624 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3625 { "IF2 ADC3 Mux", "OB45", "OB45" }, 3626 3627 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3628 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3629 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3630 3631 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, 3632 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, 3633 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, 3634 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, 3635 3636 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, 3637 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, 3638 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, 3639 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, 3640 3641 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, 3642 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, 3643 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, 3644 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, 3645 3646 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, 3647 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, 3648 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, 3649 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, 3650 3651 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, 3652 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, 3653 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, 3654 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, 3655 3656 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, 3657 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, 3658 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, 3659 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, 3660 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, 3661 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, 3662 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, 3663 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, 3664 3665 { "AIF2TX", NULL, "I2S2" }, 3666 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, 3667 3668 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3669 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3670 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3671 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3672 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3673 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3674 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3675 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3676 3677 { "AIF3TX", NULL, "I2S3" }, 3678 { "AIF3TX", NULL, "IF3 ADC Mux" }, 3679 3680 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3681 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3682 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3683 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3684 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3685 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3686 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3687 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3688 3689 { "AIF4TX", NULL, "I2S4" }, 3690 { "AIF4TX", NULL, "IF4 ADC Mux" }, 3691 3692 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3693 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3694 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3695 3696 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3697 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3698 3699 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3700 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3701 { "SLB ADC3 Mux", "OB45", "OB45" }, 3702 3703 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3704 { "SLB ADC4 Mux", "OB67", "OB67" }, 3705 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3706 3707 { "SLBTX", NULL, "SLB" }, 3708 { "SLBTX", NULL, "SLB ADC1 Mux" }, 3709 { "SLBTX", NULL, "SLB ADC2 Mux" }, 3710 { "SLBTX", NULL, "SLB ADC3 Mux" }, 3711 { "SLBTX", NULL, "SLB ADC4 Mux" }, 3712 3713 { "DSPTX", NULL, "IB01 Bypass Mux" }, 3714 3715 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3716 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3717 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, 3718 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3719 /* The IB01 Mux controls the source for InBound0 and InBound1. 3720 * When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to 3721 * InBound0 and "DAC1 FS" goes to InBound1. "VAD ADC" is used for 3722 * hotwording. "DAC1 FS" is not used currently. 3723 * 3724 * Creating a common widget node for "VAD ADC" + "DAC1 FS" and 3725 * connecting the common widget to IB01 Mux causes the issue where 3726 * there is an active path going from system playback -> "DAC1 FS" -> 3727 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses 3728 * DAPM. Therefore "DAC1 FS" is ignored for now. 3729 */ 3730 { "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" }, 3731 3732 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, 3733 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, 3734 3735 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, 3736 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, 3737 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, 3738 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3739 { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, 3740 { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, 3741 3742 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, 3743 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, 3744 3745 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, 3746 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, 3747 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, 3748 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3749 { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, 3750 3751 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, 3752 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, 3753 3754 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 3755 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 3756 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, 3757 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3758 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, 3759 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3760 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3761 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3762 3763 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 3764 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 3765 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, 3766 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3767 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, 3768 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3769 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3770 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3771 3772 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3773 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3774 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3775 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3776 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3777 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, 3778 3779 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3780 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3781 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3782 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3783 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3784 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, 3785 { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, 3786 3787 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3788 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3789 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3790 { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, 3791 { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, 3792 { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, 3793 { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, 3794 3795 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3796 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3797 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3798 { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, 3799 { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, 3800 { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, 3801 { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, 3802 3803 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3804 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3805 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3806 { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, 3807 { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, 3808 { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, 3809 { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, 3810 3811 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3812 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3813 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3814 { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, 3815 { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, 3816 { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, 3817 { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, 3818 3819 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3820 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3821 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3822 { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, 3823 { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, 3824 { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, 3825 { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, 3826 3827 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3828 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3829 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3830 { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, 3831 { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, 3832 { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, 3833 { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, 3834 3835 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, 3836 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, 3837 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, 3838 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, 3839 3840 { "OutBound2", NULL, "OB23 Bypass Mux" }, 3841 { "OutBound3", NULL, "OB23 Bypass Mux" }, 3842 { "OutBound4", NULL, "OB4 MIX" }, 3843 { "OutBound5", NULL, "OB5 MIX" }, 3844 { "OutBound6", NULL, "OB6 MIX" }, 3845 { "OutBound7", NULL, "OB7 MIX" }, 3846 3847 { "OB45", NULL, "OutBound4" }, 3848 { "OB45", NULL, "OutBound5" }, 3849 { "OB67", NULL, "OutBound6" }, 3850 { "OB67", NULL, "OutBound7" }, 3851 3852 { "IF1 DAC0", NULL, "AIF1RX" }, 3853 { "IF1 DAC1", NULL, "AIF1RX" }, 3854 { "IF1 DAC2", NULL, "AIF1RX" }, 3855 { "IF1 DAC3", NULL, "AIF1RX" }, 3856 { "IF1 DAC4", NULL, "AIF1RX" }, 3857 { "IF1 DAC5", NULL, "AIF1RX" }, 3858 { "IF1 DAC6", NULL, "AIF1RX" }, 3859 { "IF1 DAC7", NULL, "AIF1RX" }, 3860 { "IF1 DAC0", NULL, "I2S1" }, 3861 { "IF1 DAC1", NULL, "I2S1" }, 3862 { "IF1 DAC2", NULL, "I2S1" }, 3863 { "IF1 DAC3", NULL, "I2S1" }, 3864 { "IF1 DAC4", NULL, "I2S1" }, 3865 { "IF1 DAC5", NULL, "I2S1" }, 3866 { "IF1 DAC6", NULL, "I2S1" }, 3867 { "IF1 DAC7", NULL, "I2S1" }, 3868 3869 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, 3870 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, 3871 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, 3872 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, 3873 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, 3874 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, 3875 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, 3876 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, 3877 3878 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, 3879 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, 3880 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, 3881 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, 3882 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, 3883 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, 3884 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, 3885 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, 3886 3887 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, 3888 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, 3889 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, 3890 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, 3891 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, 3892 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, 3893 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, 3894 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, 3895 3896 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, 3897 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, 3898 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, 3899 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, 3900 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, 3901 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, 3902 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, 3903 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, 3904 3905 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, 3906 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, 3907 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, 3908 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, 3909 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, 3910 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, 3911 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, 3912 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, 3913 3914 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, 3915 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, 3916 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, 3917 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, 3918 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, 3919 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, 3920 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, 3921 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, 3922 3923 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, 3924 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, 3925 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, 3926 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, 3927 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, 3928 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, 3929 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, 3930 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, 3931 3932 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, 3933 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, 3934 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, 3935 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, 3936 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, 3937 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, 3938 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, 3939 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, 3940 3941 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, 3942 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, 3943 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, 3944 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, 3945 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, 3946 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, 3947 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, 3948 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, 3949 3950 { "IF2 DAC0", NULL, "AIF2RX" }, 3951 { "IF2 DAC1", NULL, "AIF2RX" }, 3952 { "IF2 DAC2", NULL, "AIF2RX" }, 3953 { "IF2 DAC3", NULL, "AIF2RX" }, 3954 { "IF2 DAC4", NULL, "AIF2RX" }, 3955 { "IF2 DAC5", NULL, "AIF2RX" }, 3956 { "IF2 DAC6", NULL, "AIF2RX" }, 3957 { "IF2 DAC7", NULL, "AIF2RX" }, 3958 { "IF2 DAC0", NULL, "I2S2" }, 3959 { "IF2 DAC1", NULL, "I2S2" }, 3960 { "IF2 DAC2", NULL, "I2S2" }, 3961 { "IF2 DAC3", NULL, "I2S2" }, 3962 { "IF2 DAC4", NULL, "I2S2" }, 3963 { "IF2 DAC5", NULL, "I2S2" }, 3964 { "IF2 DAC6", NULL, "I2S2" }, 3965 { "IF2 DAC7", NULL, "I2S2" }, 3966 3967 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, 3968 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, 3969 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, 3970 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, 3971 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, 3972 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, 3973 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, 3974 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, 3975 3976 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, 3977 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, 3978 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, 3979 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, 3980 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, 3981 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, 3982 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, 3983 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, 3984 3985 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, 3986 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, 3987 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, 3988 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, 3989 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, 3990 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, 3991 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, 3992 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, 3993 3994 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, 3995 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, 3996 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, 3997 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, 3998 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, 3999 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, 4000 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, 4001 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, 4002 4003 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, 4004 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, 4005 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, 4006 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, 4007 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, 4008 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, 4009 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, 4010 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, 4011 4012 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, 4013 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, 4014 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, 4015 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, 4016 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, 4017 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, 4018 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, 4019 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, 4020 4021 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, 4022 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, 4023 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, 4024 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, 4025 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, 4026 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, 4027 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, 4028 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, 4029 4030 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, 4031 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, 4032 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, 4033 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, 4034 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, 4035 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, 4036 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, 4037 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, 4038 4039 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, 4040 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, 4041 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, 4042 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, 4043 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, 4044 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, 4045 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, 4046 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, 4047 4048 { "IF3 DAC", NULL, "AIF3RX" }, 4049 { "IF3 DAC", NULL, "I2S3" }, 4050 4051 { "IF4 DAC", NULL, "AIF4RX" }, 4052 { "IF4 DAC", NULL, "I2S4" }, 4053 4054 { "IF3 DAC L", NULL, "IF3 DAC" }, 4055 { "IF3 DAC R", NULL, "IF3 DAC" }, 4056 4057 { "IF4 DAC L", NULL, "IF4 DAC" }, 4058 { "IF4 DAC R", NULL, "IF4 DAC" }, 4059 4060 { "SLB DAC0", NULL, "SLBRX" }, 4061 { "SLB DAC1", NULL, "SLBRX" }, 4062 { "SLB DAC2", NULL, "SLBRX" }, 4063 { "SLB DAC3", NULL, "SLBRX" }, 4064 { "SLB DAC4", NULL, "SLBRX" }, 4065 { "SLB DAC5", NULL, "SLBRX" }, 4066 { "SLB DAC6", NULL, "SLBRX" }, 4067 { "SLB DAC7", NULL, "SLBRX" }, 4068 { "SLB DAC0", NULL, "SLB" }, 4069 { "SLB DAC1", NULL, "SLB" }, 4070 { "SLB DAC2", NULL, "SLB" }, 4071 { "SLB DAC3", NULL, "SLB" }, 4072 { "SLB DAC4", NULL, "SLB" }, 4073 { "SLB DAC5", NULL, "SLB" }, 4074 { "SLB DAC6", NULL, "SLB" }, 4075 { "SLB DAC7", NULL, "SLB" }, 4076 4077 { "SLB DAC01", NULL, "SLB DAC0" }, 4078 { "SLB DAC01", NULL, "SLB DAC1" }, 4079 { "SLB DAC23", NULL, "SLB DAC2" }, 4080 { "SLB DAC23", NULL, "SLB DAC3" }, 4081 { "SLB DAC45", NULL, "SLB DAC4" }, 4082 { "SLB DAC45", NULL, "SLB DAC5" }, 4083 { "SLB DAC67", NULL, "SLB DAC6" }, 4084 { "SLB DAC67", NULL, "SLB DAC7" }, 4085 4086 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 4087 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 4088 { "ADDA1 Mux", "OB 67", "OB67" }, 4089 4090 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, 4091 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, 4092 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, 4093 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, 4094 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, 4095 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, 4096 4097 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, 4098 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, 4099 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, 4100 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, 4101 4102 { "DAC1 FS", NULL, "DAC1 MIXL" }, 4103 { "DAC1 FS", NULL, "DAC1 MIXR" }, 4104 4105 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" }, 4106 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" }, 4107 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4108 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4109 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, 4110 { "DAC2 L Mux", "OB 2", "OutBound2" }, 4111 4112 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" }, 4113 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" }, 4114 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4115 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4116 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, 4117 { "DAC2 R Mux", "OB 3", "OutBound3" }, 4118 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, 4119 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, 4120 4121 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" }, 4122 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" }, 4123 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4124 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4125 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, 4126 { "DAC3 L Mux", "OB 4", "OutBound4" }, 4127 4128 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" }, 4129 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" }, 4130 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4131 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4132 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, 4133 { "DAC3 R Mux", "OB 5", "OutBound5" }, 4134 4135 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 4136 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 4137 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4138 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4139 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, 4140 { "DAC4 L Mux", "OB 6", "OutBound6" }, 4141 4142 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 4143 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 4144 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4145 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4146 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, 4147 { "DAC4 R Mux", "OB 7", "OutBound7" }, 4148 4149 { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, 4150 { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, 4151 { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, 4152 { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, 4153 { "Sidetone Mux", "ADC1", "ADC 1" }, 4154 { "Sidetone Mux", "ADC2", "ADC 2" }, 4155 { "Sidetone Mux", NULL, "Sidetone Power" }, 4156 4157 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4158 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4159 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4160 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, 4161 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 4162 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4163 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4164 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4165 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, 4166 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 4167 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 4168 4169 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4170 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4171 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4172 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, 4173 { "Mono DAC MIXL", NULL, "dac mono2 left filter" }, 4174 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4175 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4176 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4177 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4178 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, 4179 { "Mono DAC MIXR", NULL, "dac mono2 right filter" }, 4180 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4181 4182 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4183 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4184 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, 4185 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, 4186 { "DD1 MIXL", NULL, "dac mono3 left filter" }, 4187 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4188 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4189 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4190 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, 4191 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, 4192 { "DD1 MIXR", NULL, "dac mono3 right filter" }, 4193 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4194 4195 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4196 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4197 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, 4198 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, 4199 { "DD2 MIXL", NULL, "dac mono4 left filter" }, 4200 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4201 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4202 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4203 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, 4204 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, 4205 { "DD2 MIXR", NULL, "dac mono4 right filter" }, 4206 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4207 4208 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, 4209 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, 4210 { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, 4211 { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, 4212 { "DD1 MIX", NULL, "DD1 MIXL" }, 4213 { "DD1 MIX", NULL, "DD1 MIXR" }, 4214 { "DD2 MIX", NULL, "DD2 MIXL" }, 4215 { "DD2 MIX", NULL, "DD2 MIXR" }, 4216 4217 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, 4218 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, 4219 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, 4220 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, 4221 4222 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 4223 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 4224 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, 4225 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, 4226 4227 { "DAC 1", NULL, "DAC12 SRC Mux" }, 4228 { "DAC 2", NULL, "DAC12 SRC Mux" }, 4229 { "DAC 3", NULL, "DAC3 SRC Mux" }, 4230 4231 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4232 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4233 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, 4234 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, 4235 { "PDM1 L Mux", NULL, "PDM1 Power" }, 4236 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4237 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4238 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, 4239 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, 4240 { "PDM1 R Mux", NULL, "PDM1 Power" }, 4241 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4242 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4243 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, 4244 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, 4245 { "PDM2 L Mux", NULL, "PDM2 Power" }, 4246 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4247 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4248 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, 4249 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, 4250 { "PDM2 R Mux", NULL, "PDM2 Power" }, 4251 4252 { "LOUT1 amp", NULL, "DAC 1" }, 4253 { "LOUT2 amp", NULL, "DAC 2" }, 4254 { "LOUT3 amp", NULL, "DAC 3" }, 4255 4256 { "LOUT1 vref", NULL, "LOUT1 amp" }, 4257 { "LOUT2 vref", NULL, "LOUT2 amp" }, 4258 { "LOUT3 vref", NULL, "LOUT3 amp" }, 4259 4260 { "LOUT1", NULL, "LOUT1 vref" }, 4261 { "LOUT2", NULL, "LOUT2 vref" }, 4262 { "LOUT3", NULL, "LOUT3 vref" }, 4263 4264 { "PDM1L", NULL, "PDM1 L Mux" }, 4265 { "PDM1R", NULL, "PDM1 R Mux" }, 4266 { "PDM2L", NULL, "PDM2 L Mux" }, 4267 { "PDM2R", NULL, "PDM2 R Mux" }, 4268 }; 4269 4270 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { 4271 { "DMIC L2", NULL, "DMIC1 power" }, 4272 { "DMIC R2", NULL, "DMIC1 power" }, 4273 }; 4274 4275 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { 4276 { "DMIC L2", NULL, "DMIC2 power" }, 4277 { "DMIC R2", NULL, "DMIC2 power" }, 4278 }; 4279 4280 static int rt5677_hw_params(struct snd_pcm_substream *substream, 4281 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 4282 { 4283 struct snd_soc_component *component = dai->component; 4284 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4285 unsigned int val_len = 0, val_clk, mask_clk; 4286 int pre_div, bclk_ms, frame_size; 4287 4288 rt5677->lrck[dai->id] = params_rate(params); 4289 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 4290 if (pre_div < 0) { 4291 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", 4292 rt5677->sysclk, rt5677->lrck[dai->id]); 4293 return -EINVAL; 4294 } 4295 frame_size = snd_soc_params_to_frame_size(params); 4296 if (frame_size < 0) { 4297 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 4298 return -EINVAL; 4299 } 4300 bclk_ms = frame_size > 32; 4301 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); 4302 4303 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 4304 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); 4305 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 4306 bclk_ms, pre_div, dai->id); 4307 4308 switch (params_width(params)) { 4309 case 16: 4310 break; 4311 case 20: 4312 val_len |= RT5677_I2S_DL_20; 4313 break; 4314 case 24: 4315 val_len |= RT5677_I2S_DL_24; 4316 break; 4317 case 8: 4318 val_len |= RT5677_I2S_DL_8; 4319 break; 4320 default: 4321 return -EINVAL; 4322 } 4323 4324 switch (dai->id) { 4325 case RT5677_AIF1: 4326 mask_clk = RT5677_I2S_PD1_MASK; 4327 val_clk = pre_div << RT5677_I2S_PD1_SFT; 4328 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4329 RT5677_I2S_DL_MASK, val_len); 4330 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4331 mask_clk, val_clk); 4332 break; 4333 case RT5677_AIF2: 4334 mask_clk = RT5677_I2S_PD2_MASK; 4335 val_clk = pre_div << RT5677_I2S_PD2_SFT; 4336 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4337 RT5677_I2S_DL_MASK, val_len); 4338 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4339 mask_clk, val_clk); 4340 break; 4341 case RT5677_AIF3: 4342 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; 4343 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | 4344 pre_div << RT5677_I2S_PD3_SFT; 4345 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4346 RT5677_I2S_DL_MASK, val_len); 4347 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4348 mask_clk, val_clk); 4349 break; 4350 case RT5677_AIF4: 4351 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; 4352 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | 4353 pre_div << RT5677_I2S_PD4_SFT; 4354 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4355 RT5677_I2S_DL_MASK, val_len); 4356 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4357 mask_clk, val_clk); 4358 break; 4359 default: 4360 break; 4361 } 4362 4363 return 0; 4364 } 4365 4366 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 4367 { 4368 struct snd_soc_component *component = dai->component; 4369 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4370 unsigned int reg_val = 0; 4371 4372 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 4373 case SND_SOC_DAIFMT_CBP_CFP: 4374 rt5677->master[dai->id] = 1; 4375 break; 4376 case SND_SOC_DAIFMT_CBC_CFC: 4377 reg_val |= RT5677_I2S_MS_S; 4378 rt5677->master[dai->id] = 0; 4379 break; 4380 default: 4381 return -EINVAL; 4382 } 4383 4384 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 4385 case SND_SOC_DAIFMT_NB_NF: 4386 break; 4387 case SND_SOC_DAIFMT_IB_NF: 4388 reg_val |= RT5677_I2S_BP_INV; 4389 break; 4390 default: 4391 return -EINVAL; 4392 } 4393 4394 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 4395 case SND_SOC_DAIFMT_I2S: 4396 break; 4397 case SND_SOC_DAIFMT_LEFT_J: 4398 reg_val |= RT5677_I2S_DF_LEFT; 4399 break; 4400 case SND_SOC_DAIFMT_DSP_A: 4401 reg_val |= RT5677_I2S_DF_PCM_A; 4402 break; 4403 case SND_SOC_DAIFMT_DSP_B: 4404 reg_val |= RT5677_I2S_DF_PCM_B; 4405 break; 4406 default: 4407 return -EINVAL; 4408 } 4409 4410 switch (dai->id) { 4411 case RT5677_AIF1: 4412 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4413 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4414 RT5677_I2S_DF_MASK, reg_val); 4415 break; 4416 case RT5677_AIF2: 4417 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4418 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4419 RT5677_I2S_DF_MASK, reg_val); 4420 break; 4421 case RT5677_AIF3: 4422 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4423 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4424 RT5677_I2S_DF_MASK, reg_val); 4425 break; 4426 case RT5677_AIF4: 4427 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4428 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4429 RT5677_I2S_DF_MASK, reg_val); 4430 break; 4431 default: 4432 break; 4433 } 4434 4435 4436 return 0; 4437 } 4438 4439 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, 4440 int clk_id, unsigned int freq, int dir) 4441 { 4442 struct snd_soc_component *component = dai->component; 4443 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4444 unsigned int reg_val = 0; 4445 4446 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) 4447 return 0; 4448 4449 switch (clk_id) { 4450 case RT5677_SCLK_S_MCLK: 4451 reg_val |= RT5677_SCLK_SRC_MCLK; 4452 break; 4453 case RT5677_SCLK_S_PLL1: 4454 reg_val |= RT5677_SCLK_SRC_PLL1; 4455 break; 4456 case RT5677_SCLK_S_RCCLK: 4457 reg_val |= RT5677_SCLK_SRC_RCCLK; 4458 break; 4459 default: 4460 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 4461 return -EINVAL; 4462 } 4463 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4464 RT5677_SCLK_SRC_MASK, reg_val); 4465 rt5677->sysclk = freq; 4466 rt5677->sysclk_src = clk_id; 4467 4468 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 4469 4470 return 0; 4471 } 4472 4473 /** 4474 * rt5677_pll_calc - Calcualte PLL M/N/K code. 4475 * @freq_in: external clock provided to codec. 4476 * @freq_out: target clock which codec works on. 4477 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. 4478 * 4479 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. 4480 * 4481 * Returns 0 for success or negative error code. 4482 */ 4483 static int rt5677_pll_calc(const unsigned int freq_in, 4484 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 4485 { 4486 if (RT5677_PLL_INP_MIN > freq_in) 4487 return -EINVAL; 4488 4489 return rl6231_pll_calc(freq_in, freq_out, pll_code); 4490 } 4491 4492 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 4493 unsigned int freq_in, unsigned int freq_out) 4494 { 4495 struct snd_soc_component *component = dai->component; 4496 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4497 struct rl6231_pll_code pll_code; 4498 int ret; 4499 4500 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 4501 freq_out == rt5677->pll_out) 4502 return 0; 4503 4504 if (!freq_in || !freq_out) { 4505 dev_dbg(component->dev, "PLL disabled\n"); 4506 4507 rt5677->pll_in = 0; 4508 rt5677->pll_out = 0; 4509 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4510 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); 4511 return 0; 4512 } 4513 4514 switch (source) { 4515 case RT5677_PLL1_S_MCLK: 4516 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4517 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); 4518 break; 4519 case RT5677_PLL1_S_BCLK1: 4520 case RT5677_PLL1_S_BCLK2: 4521 case RT5677_PLL1_S_BCLK3: 4522 case RT5677_PLL1_S_BCLK4: 4523 switch (dai->id) { 4524 case RT5677_AIF1: 4525 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4526 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); 4527 break; 4528 case RT5677_AIF2: 4529 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4530 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); 4531 break; 4532 case RT5677_AIF3: 4533 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4534 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); 4535 break; 4536 case RT5677_AIF4: 4537 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4538 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); 4539 break; 4540 default: 4541 break; 4542 } 4543 break; 4544 default: 4545 dev_err(component->dev, "Unknown PLL source %d\n", source); 4546 return -EINVAL; 4547 } 4548 4549 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); 4550 if (ret < 0) { 4551 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 4552 return ret; 4553 } 4554 4555 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", 4556 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 4557 pll_code.n_code, pll_code.k_code); 4558 4559 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 4560 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); 4561 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 4562 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT) | 4563 (pll_code.m_bp << RT5677_PLL_M_BP_SFT)); 4564 4565 rt5677->pll_in = freq_in; 4566 rt5677->pll_out = freq_out; 4567 rt5677->pll_src = source; 4568 4569 return 0; 4570 } 4571 4572 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 4573 unsigned int rx_mask, int slots, int slot_width) 4574 { 4575 struct snd_soc_component *component = dai->component; 4576 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4577 unsigned int val = 0, slot_width_25 = 0; 4578 4579 if (rx_mask || tx_mask) 4580 val |= (1 << 12); 4581 4582 switch (slots) { 4583 case 4: 4584 val |= (1 << 10); 4585 break; 4586 case 6: 4587 val |= (2 << 10); 4588 break; 4589 case 8: 4590 val |= (3 << 10); 4591 break; 4592 case 2: 4593 default: 4594 break; 4595 } 4596 4597 switch (slot_width) { 4598 case 20: 4599 val |= (1 << 8); 4600 break; 4601 case 25: 4602 slot_width_25 = 0x8080; 4603 fallthrough; 4604 case 24: 4605 val |= (2 << 8); 4606 break; 4607 case 32: 4608 val |= (3 << 8); 4609 break; 4610 case 16: 4611 default: 4612 break; 4613 } 4614 4615 switch (dai->id) { 4616 case RT5677_AIF1: 4617 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, 4618 val); 4619 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, 4620 slot_width_25); 4621 break; 4622 case RT5677_AIF2: 4623 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, 4624 val); 4625 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, 4626 slot_width_25); 4627 break; 4628 default: 4629 break; 4630 } 4631 4632 return 0; 4633 } 4634 4635 static int rt5677_set_bias_level(struct snd_soc_component *component, 4636 enum snd_soc_bias_level level) 4637 { 4638 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4639 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 4640 enum snd_soc_bias_level prev_bias = snd_soc_dapm_get_bias_level(dapm); 4641 4642 switch (level) { 4643 case SND_SOC_BIAS_ON: 4644 break; 4645 4646 case SND_SOC_BIAS_PREPARE: 4647 if (prev_bias == SND_SOC_BIAS_STANDBY) { 4648 4649 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4650 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 4651 5 << RT5677_LDO1_SEL_SFT | 4652 5 << RT5677_LDO2_SEL_SFT); 4653 regmap_update_bits(rt5677->regmap, 4654 RT5677_PR_BASE + RT5677_BIAS_CUR4, 4655 0x0f00, 0x0f00); 4656 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4657 RT5677_PWR_FV1 | RT5677_PWR_FV2 | 4658 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4659 RT5677_PWR_BG | RT5677_PWR_VREF2, 4660 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4661 RT5677_PWR_BG | RT5677_PWR_VREF2); 4662 rt5677->is_vref_slow = false; 4663 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4664 RT5677_PWR_CORE, RT5677_PWR_CORE); 4665 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4666 0x1, 0x1); 4667 } 4668 break; 4669 4670 case SND_SOC_BIAS_STANDBY: 4671 if (prev_bias == SND_SOC_BIAS_OFF && 4672 rt5677->dsp_vad_en_request) { 4673 /* Re-enable the DSP if it was turned off at suspend */ 4674 rt5677->dsp_vad_en = true; 4675 /* The delay is to wait for MCLK */ 4676 schedule_delayed_work(&rt5677->dsp_work, 4677 msecs_to_jiffies(1000)); 4678 } 4679 break; 4680 4681 case SND_SOC_BIAS_OFF: 4682 flush_delayed_work(&rt5677->dsp_work); 4683 if (rt5677->is_dsp_mode) { 4684 /* Turn off the DSP before suspend */ 4685 rt5677->dsp_vad_en = false; 4686 schedule_delayed_work(&rt5677->dsp_work, 0); 4687 flush_delayed_work(&rt5677->dsp_work); 4688 } 4689 4690 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 4691 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 4692 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 4693 2 << RT5677_LDO1_SEL_SFT | 4694 2 << RT5677_LDO2_SEL_SFT); 4695 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4696 RT5677_PWR_CORE, 0); 4697 regmap_update_bits(rt5677->regmap, 4698 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4699 4700 if (rt5677->dsp_vad_en) 4701 rt5677_set_dsp_vad(component, true); 4702 break; 4703 4704 default: 4705 break; 4706 } 4707 4708 return 0; 4709 } 4710 4711 static int rt5677_update_gpio_bits(struct rt5677_priv *rt5677, unsigned offset, int m, int v) 4712 { 4713 unsigned int bank = offset / 5; 4714 unsigned int shift = (offset % 5) * 3; 4715 unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2; 4716 4717 return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift); 4718 } 4719 4720 #ifdef CONFIG_GPIOLIB 4721 static int rt5677_gpio_set(struct gpio_chip *chip, unsigned int offset, 4722 int value) 4723 { 4724 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4725 int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO; 4726 int m = RT5677_GPIOx_OUT_MASK; 4727 4728 return rt5677_update_gpio_bits(rt5677, offset, m, level); 4729 } 4730 4731 static int rt5677_gpio_direction_out(struct gpio_chip *chip, 4732 unsigned offset, int value) 4733 { 4734 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4735 int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO; 4736 int m = RT5677_GPIOx_DIR_MASK | RT5677_GPIOx_OUT_MASK; 4737 int v = RT5677_GPIOx_DIR_OUT | level; 4738 4739 return rt5677_update_gpio_bits(rt5677, offset, m, v); 4740 } 4741 4742 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) 4743 { 4744 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4745 int value, ret; 4746 4747 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); 4748 if (ret < 0) 4749 return ret; 4750 4751 return (value & (0x1 << offset)) >> offset; 4752 } 4753 4754 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 4755 { 4756 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4757 int m = RT5677_GPIOx_DIR_MASK; 4758 int v = RT5677_GPIOx_DIR_IN; 4759 4760 return rt5677_update_gpio_bits(rt5677, offset, m, v); 4761 } 4762 4763 static int rt5677_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 4764 { 4765 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4766 unsigned int shift = RT5677_GPIOx_DIR_SFT + (offset % 5) * 3; 4767 unsigned int bank = offset / 5; 4768 unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2; 4769 int ret; 4770 4771 ret = regmap_test_bits(rt5677->regmap, reg, BIT(shift)); 4772 if (ret < 0) 4773 return ret; 4774 4775 return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 4776 } 4777 4778 /* 4779 * Configures the GPIO as 4780 * 0 - floating 4781 * 1 - pull down 4782 * 2 - pull up 4783 */ 4784 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4785 int value) 4786 { 4787 int shift; 4788 4789 switch (offset) { 4790 case RT5677_GPIO1 ... RT5677_GPIO2: 4791 shift = 2 * (1 - offset); 4792 regmap_update_bits(rt5677->regmap, 4793 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, 4794 0x3 << shift, 4795 (value & 0x3) << shift); 4796 break; 4797 4798 case RT5677_GPIO3 ... RT5677_GPIO6: 4799 shift = 2 * (9 - offset); 4800 regmap_update_bits(rt5677->regmap, 4801 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, 4802 0x3 << shift, 4803 (value & 0x3) << shift); 4804 break; 4805 4806 default: 4807 break; 4808 } 4809 } 4810 4811 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) 4812 { 4813 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4814 int irq; 4815 4816 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || 4817 (rt5677->pdata.jd1_gpio == 2 && 4818 offset == RT5677_GPIO2) || 4819 (rt5677->pdata.jd1_gpio == 3 && 4820 offset == RT5677_GPIO3)) { 4821 irq = RT5677_IRQ_JD1; 4822 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || 4823 (rt5677->pdata.jd2_gpio == 2 && 4824 offset == RT5677_GPIO5) || 4825 (rt5677->pdata.jd2_gpio == 3 && 4826 offset == RT5677_GPIO6)) { 4827 irq = RT5677_IRQ_JD2; 4828 } else if ((rt5677->pdata.jd3_gpio == 1 && 4829 offset == RT5677_GPIO4) || 4830 (rt5677->pdata.jd3_gpio == 2 && 4831 offset == RT5677_GPIO5) || 4832 (rt5677->pdata.jd3_gpio == 3 && 4833 offset == RT5677_GPIO6)) { 4834 irq = RT5677_IRQ_JD3; 4835 } else { 4836 return -ENXIO; 4837 } 4838 4839 return irq_create_mapping(rt5677->domain, irq); 4840 } 4841 4842 static const struct gpio_chip rt5677_template_chip = { 4843 .label = RT5677_DRV_NAME, 4844 .owner = THIS_MODULE, 4845 .get_direction = rt5677_gpio_get_direction, 4846 .direction_output = rt5677_gpio_direction_out, 4847 .set = rt5677_gpio_set, 4848 .direction_input = rt5677_gpio_direction_in, 4849 .get = rt5677_gpio_get, 4850 .to_irq = rt5677_to_irq, 4851 .can_sleep = 1, 4852 }; 4853 4854 static void rt5677_init_gpio(struct i2c_client *i2c) 4855 { 4856 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4857 int ret; 4858 4859 rt5677->gpio_chip = rt5677_template_chip; 4860 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; 4861 rt5677->gpio_chip.parent = &i2c->dev; 4862 rt5677->gpio_chip.base = -1; 4863 4864 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); 4865 if (ret != 0) 4866 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); 4867 } 4868 4869 static void rt5677_free_gpio(struct i2c_client *i2c) 4870 { 4871 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4872 4873 gpiochip_remove(&rt5677->gpio_chip); 4874 } 4875 #else 4876 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4877 int value) 4878 { 4879 } 4880 4881 static void rt5677_init_gpio(struct i2c_client *i2c) 4882 { 4883 } 4884 4885 static void rt5677_free_gpio(struct i2c_client *i2c) 4886 { 4887 } 4888 #endif 4889 4890 static int rt5677_probe(struct snd_soc_component *component) 4891 { 4892 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 4893 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4894 int i; 4895 4896 rt5677->component = component; 4897 4898 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4899 snd_soc_dapm_add_routes(dapm, 4900 rt5677_dmic2_clk_2, 4901 ARRAY_SIZE(rt5677_dmic2_clk_2)); 4902 } else { /*use dmic1 clock by default*/ 4903 snd_soc_dapm_add_routes(dapm, 4904 rt5677_dmic2_clk_1, 4905 ARRAY_SIZE(rt5677_dmic2_clk_1)); 4906 } 4907 4908 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF); 4909 4910 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4911 ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020); 4912 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 4913 RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO); 4914 4915 for (i = 0; i < RT5677_GPIO_NUM; i++) 4916 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); 4917 4918 mutex_init(&rt5677->dsp_cmd_lock); 4919 mutex_init(&rt5677->dsp_pri_lock); 4920 4921 return 0; 4922 } 4923 4924 static void rt5677_remove(struct snd_soc_component *component) 4925 { 4926 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4927 4928 cancel_delayed_work_sync(&rt5677->dsp_work); 4929 4930 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4931 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4932 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4933 } 4934 4935 #ifdef CONFIG_PM 4936 static int rt5677_suspend(struct snd_soc_component *component) 4937 { 4938 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4939 4940 if (rt5677->irq) { 4941 cancel_delayed_work_sync(&rt5677->resume_irq_check); 4942 disable_irq(rt5677->irq); 4943 } 4944 4945 if (!rt5677->dsp_vad_en) { 4946 regcache_cache_only(rt5677->regmap, true); 4947 regcache_mark_dirty(rt5677->regmap); 4948 4949 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4950 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4951 } 4952 4953 return 0; 4954 } 4955 4956 static int rt5677_resume(struct snd_soc_component *component) 4957 { 4958 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4959 4960 if (!rt5677->dsp_vad_en) { 4961 rt5677->pll_src = 0; 4962 rt5677->pll_in = 0; 4963 rt5677->pll_out = 0; 4964 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); 4965 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 4966 if (rt5677->pow_ldo2 || rt5677->reset_pin) 4967 msleep(10); 4968 4969 regcache_cache_only(rt5677->regmap, false); 4970 regcache_sync(rt5677->regmap); 4971 } 4972 4973 if (rt5677->irq) { 4974 enable_irq(rt5677->irq); 4975 schedule_delayed_work(&rt5677->resume_irq_check, 0); 4976 } 4977 4978 return 0; 4979 } 4980 #else 4981 #define rt5677_suspend NULL 4982 #define rt5677_resume NULL 4983 #endif 4984 4985 static int rt5677_read(void *context, unsigned int reg, unsigned int *val) 4986 { 4987 struct i2c_client *client = context; 4988 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4989 4990 if (rt5677->is_dsp_mode) { 4991 if (reg > 0xff) { 4992 scoped_guard(mutex, &rt5677->dsp_pri_lock) { 4993 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4994 reg & 0xff); 4995 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); 4996 } 4997 } else { 4998 rt5677_dsp_mode_i2c_read(rt5677, reg, val); 4999 } 5000 } else { 5001 regmap_read(rt5677->regmap_physical, reg, val); 5002 } 5003 5004 return 0; 5005 } 5006 5007 static int rt5677_write(void *context, unsigned int reg, unsigned int val) 5008 { 5009 struct i2c_client *client = context; 5010 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 5011 5012 if (rt5677->is_dsp_mode) { 5013 if (reg > 0xff) { 5014 scoped_guard(mutex, &rt5677->dsp_pri_lock) { 5015 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 5016 reg & 0xff); 5017 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, 5018 val); 5019 } 5020 } else { 5021 rt5677_dsp_mode_i2c_write(rt5677, reg, val); 5022 } 5023 } else { 5024 regmap_write(rt5677->regmap_physical, reg, val); 5025 } 5026 5027 return 0; 5028 } 5029 5030 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 5031 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 5032 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 5033 5034 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = { 5035 .hw_params = rt5677_hw_params, 5036 .set_fmt = rt5677_set_dai_fmt, 5037 .set_sysclk = rt5677_set_dai_sysclk, 5038 .set_pll = rt5677_set_dai_pll, 5039 .set_tdm_slot = rt5677_set_tdm_slot, 5040 }; 5041 5042 static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = { 5043 .set_sysclk = rt5677_set_dai_sysclk, 5044 .set_pll = rt5677_set_dai_pll, 5045 }; 5046 5047 static struct snd_soc_dai_driver rt5677_dai[] = { 5048 { 5049 .name = "rt5677-aif1", 5050 .id = RT5677_AIF1, 5051 .playback = { 5052 .stream_name = "AIF1 Playback", 5053 .channels_min = 1, 5054 .channels_max = 2, 5055 .rates = RT5677_STEREO_RATES, 5056 .formats = RT5677_FORMATS, 5057 }, 5058 .capture = { 5059 .stream_name = "AIF1 Capture", 5060 .channels_min = 1, 5061 .channels_max = 2, 5062 .rates = RT5677_STEREO_RATES, 5063 .formats = RT5677_FORMATS, 5064 }, 5065 .ops = &rt5677_aif_dai_ops, 5066 }, 5067 { 5068 .name = "rt5677-aif2", 5069 .id = RT5677_AIF2, 5070 .playback = { 5071 .stream_name = "AIF2 Playback", 5072 .channels_min = 1, 5073 .channels_max = 2, 5074 .rates = RT5677_STEREO_RATES, 5075 .formats = RT5677_FORMATS, 5076 }, 5077 .capture = { 5078 .stream_name = "AIF2 Capture", 5079 .channels_min = 1, 5080 .channels_max = 2, 5081 .rates = RT5677_STEREO_RATES, 5082 .formats = RT5677_FORMATS, 5083 }, 5084 .ops = &rt5677_aif_dai_ops, 5085 }, 5086 { 5087 .name = "rt5677-aif3", 5088 .id = RT5677_AIF3, 5089 .playback = { 5090 .stream_name = "AIF3 Playback", 5091 .channels_min = 1, 5092 .channels_max = 2, 5093 .rates = RT5677_STEREO_RATES, 5094 .formats = RT5677_FORMATS, 5095 }, 5096 .capture = { 5097 .stream_name = "AIF3 Capture", 5098 .channels_min = 1, 5099 .channels_max = 2, 5100 .rates = RT5677_STEREO_RATES, 5101 .formats = RT5677_FORMATS, 5102 }, 5103 .ops = &rt5677_aif_dai_ops, 5104 }, 5105 { 5106 .name = "rt5677-aif4", 5107 .id = RT5677_AIF4, 5108 .playback = { 5109 .stream_name = "AIF4 Playback", 5110 .channels_min = 1, 5111 .channels_max = 2, 5112 .rates = RT5677_STEREO_RATES, 5113 .formats = RT5677_FORMATS, 5114 }, 5115 .capture = { 5116 .stream_name = "AIF4 Capture", 5117 .channels_min = 1, 5118 .channels_max = 2, 5119 .rates = RT5677_STEREO_RATES, 5120 .formats = RT5677_FORMATS, 5121 }, 5122 .ops = &rt5677_aif_dai_ops, 5123 }, 5124 { 5125 .name = "rt5677-slimbus", 5126 .id = RT5677_AIF5, 5127 .playback = { 5128 .stream_name = "SLIMBus Playback", 5129 .channels_min = 1, 5130 .channels_max = 2, 5131 .rates = RT5677_STEREO_RATES, 5132 .formats = RT5677_FORMATS, 5133 }, 5134 .capture = { 5135 .stream_name = "SLIMBus Capture", 5136 .channels_min = 1, 5137 .channels_max = 2, 5138 .rates = RT5677_STEREO_RATES, 5139 .formats = RT5677_FORMATS, 5140 }, 5141 .ops = &rt5677_aif_dai_ops, 5142 }, 5143 { 5144 .name = "rt5677-dspbuffer", 5145 .id = RT5677_DSPBUFF, 5146 .capture = { 5147 .stream_name = "DSP Buffer", 5148 .channels_min = 1, 5149 .channels_max = 1, 5150 .rates = SNDRV_PCM_RATE_16000, 5151 .formats = SNDRV_PCM_FMTBIT_S16_LE, 5152 }, 5153 .ops = &rt5677_dsp_dai_ops, 5154 }, 5155 }; 5156 5157 static const struct snd_soc_component_driver soc_component_dev_rt5677 = { 5158 .name = RT5677_DRV_NAME, 5159 .probe = rt5677_probe, 5160 .remove = rt5677_remove, 5161 .suspend = rt5677_suspend, 5162 .resume = rt5677_resume, 5163 .set_bias_level = rt5677_set_bias_level, 5164 .controls = rt5677_snd_controls, 5165 .num_controls = ARRAY_SIZE(rt5677_snd_controls), 5166 .dapm_widgets = rt5677_dapm_widgets, 5167 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), 5168 .dapm_routes = rt5677_dapm_routes, 5169 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 5170 .use_pmdown_time = 1, 5171 .endianness = 1, 5172 }; 5173 5174 static const struct regmap_config rt5677_regmap_physical = { 5175 .name = "physical", 5176 .reg_bits = 8, 5177 .val_bits = 16, 5178 5179 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5180 RT5677_PR_SPACING), 5181 .readable_reg = rt5677_readable_register, 5182 5183 .cache_type = REGCACHE_NONE, 5184 .ranges = rt5677_ranges, 5185 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5186 }; 5187 5188 static const struct regmap_config rt5677_regmap = { 5189 .reg_bits = 8, 5190 .val_bits = 16, 5191 5192 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5193 RT5677_PR_SPACING), 5194 5195 .volatile_reg = rt5677_volatile_register, 5196 .readable_reg = rt5677_readable_register, 5197 .reg_read = rt5677_read, 5198 .reg_write = rt5677_write, 5199 5200 .cache_type = REGCACHE_RBTREE, 5201 .reg_defaults = rt5677_reg, 5202 .num_reg_defaults = ARRAY_SIZE(rt5677_reg), 5203 .ranges = rt5677_ranges, 5204 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5205 }; 5206 5207 static const struct of_device_id rt5677_of_match[] = { 5208 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 }, 5209 { } 5210 }; 5211 MODULE_DEVICE_TABLE(of, rt5677_of_match); 5212 5213 static const struct acpi_device_id rt5677_acpi_match[] = { 5214 { "10EC5677", RT5677 }, 5215 { "RT5677CE", RT5677 }, 5216 { "10EC5677", RT5677 }, 5217 { } 5218 }; 5219 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match); 5220 5221 static const struct i2c_device_id rt5677_i2c_id[] = { 5222 { .name = "rt5677", .driver_data = RT5677 }, 5223 { } 5224 }; 5225 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); 5226 5227 static void rt5677_read_device_properties(struct rt5677_priv *rt5677, 5228 struct device *dev) 5229 { 5230 u32 val; 5231 5232 rt5677->pdata.in1_diff = 5233 device_property_read_bool(dev, "IN1") || 5234 device_property_read_bool(dev, "realtek,in1-differential"); 5235 5236 rt5677->pdata.in2_diff = 5237 device_property_read_bool(dev, "IN2") || 5238 device_property_read_bool(dev, "realtek,in2-differential"); 5239 5240 rt5677->pdata.lout1_diff = 5241 device_property_read_bool(dev, "OUT1") || 5242 device_property_read_bool(dev, "realtek,lout1-differential"); 5243 5244 rt5677->pdata.lout2_diff = 5245 device_property_read_bool(dev, "OUT2") || 5246 device_property_read_bool(dev, "realtek,lout2-differential"); 5247 5248 rt5677->pdata.lout3_diff = 5249 device_property_read_bool(dev, "OUT3") || 5250 device_property_read_bool(dev, "realtek,lout3-differential"); 5251 5252 device_property_read_u8_array(dev, "realtek,gpio-config", 5253 rt5677->pdata.gpio_config, 5254 RT5677_GPIO_NUM); 5255 5256 if (!device_property_read_u32(dev, "DCLK", &val) || 5257 !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val)) 5258 rt5677->pdata.dmic2_clk_pin = val; 5259 5260 if (!device_property_read_u32(dev, "JD1", &val) || 5261 !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) 5262 rt5677->pdata.jd1_gpio = val; 5263 5264 if (!device_property_read_u32(dev, "JD2", &val) || 5265 !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) 5266 rt5677->pdata.jd2_gpio = val; 5267 5268 if (!device_property_read_u32(dev, "JD3", &val) || 5269 !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) 5270 rt5677->pdata.jd3_gpio = val; 5271 } 5272 5273 struct rt5677_irq_desc { 5274 unsigned int enable_mask; 5275 unsigned int status_mask; 5276 unsigned int polarity_mask; 5277 }; 5278 5279 static const struct rt5677_irq_desc rt5677_irq_descs[] = { 5280 [RT5677_IRQ_JD1] = { 5281 .enable_mask = RT5677_EN_IRQ_GPIO_JD1, 5282 .status_mask = RT5677_STA_GPIO_JD1, 5283 .polarity_mask = RT5677_INV_GPIO_JD1, 5284 }, 5285 [RT5677_IRQ_JD2] = { 5286 .enable_mask = RT5677_EN_IRQ_GPIO_JD2, 5287 .status_mask = RT5677_STA_GPIO_JD2, 5288 .polarity_mask = RT5677_INV_GPIO_JD2, 5289 }, 5290 [RT5677_IRQ_JD3] = { 5291 .enable_mask = RT5677_EN_IRQ_GPIO_JD3, 5292 .status_mask = RT5677_STA_GPIO_JD3, 5293 .polarity_mask = RT5677_INV_GPIO_JD3, 5294 }, 5295 }; 5296 5297 static bool rt5677_check_hotword(struct rt5677_priv *rt5677) 5298 { 5299 int reg_gpio; 5300 5301 if (!rt5677->is_dsp_mode) 5302 return false; 5303 5304 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio)) 5305 return false; 5306 5307 /* Firmware sets GPIO1 pin to be GPIO1 after hotword is detected */ 5308 if ((reg_gpio & RT5677_GPIO1_PIN_MASK) == RT5677_GPIO1_PIN_IRQ) 5309 return false; 5310 5311 /* Set GPIO1 pin back to be IRQ output for jack detect */ 5312 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5313 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5314 5315 rt5677_spi_hotword_detected(); 5316 return true; 5317 } 5318 5319 static irqreturn_t rt5677_irq(int unused, void *data) 5320 { 5321 struct rt5677_priv *rt5677 = data; 5322 int ret, loop, i, reg_irq, virq; 5323 bool irq_fired = false; 5324 5325 mutex_lock(&rt5677->irq_lock); 5326 5327 /* 5328 * Loop to handle interrupts until the last i2c read shows no pending 5329 * irqs. The interrupt line is shared by multiple interrupt sources. 5330 * After the regmap_read() below, a new interrupt source line may 5331 * become high before the regmap_write() finishes, so there isn't a 5332 * rising edge on the shared interrupt line for the new interrupt. Thus, 5333 * the loop is needed to avoid missing irqs. 5334 * 5335 * A safeguard of 20 loops is used to avoid hanging in the irq handler 5336 * if there is something wrong with the interrupt status update. The 5337 * interrupt sources here are audio jack plug/unplug events which 5338 * shouldn't happen at a high frequency for a long period of time. 5339 * Empirically, more than 3 loops have never been seen. 5340 */ 5341 for (loop = 0; loop < 20; loop++) { 5342 /* Read interrupt status */ 5343 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq); 5344 if (ret) { 5345 dev_err(rt5677->dev, "failed reading IRQ status: %d\n", 5346 ret); 5347 goto exit; 5348 } 5349 5350 irq_fired = false; 5351 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5352 if (reg_irq & rt5677_irq_descs[i].status_mask) { 5353 irq_fired = true; 5354 virq = irq_find_mapping(rt5677->domain, i); 5355 if (virq) 5356 handle_nested_irq(virq); 5357 5358 /* Clear the interrupt by flipping the polarity 5359 * of the interrupt source line that fired 5360 */ 5361 reg_irq ^= rt5677_irq_descs[i].polarity_mask; 5362 } 5363 } 5364 5365 /* Exit the loop only when we know for sure that GPIO1 pin 5366 * was low at some point since irq_lock was acquired. Any event 5367 * after that point creates a rising edge that triggers another 5368 * call to rt5677_irq(). 5369 */ 5370 if (!irq_fired && !rt5677_check_hotword(rt5677)) 5371 goto exit; 5372 5373 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); 5374 if (ret) { 5375 dev_err(rt5677->dev, "failed updating IRQ status: %d\n", 5376 ret); 5377 goto exit; 5378 } 5379 } 5380 exit: 5381 WARN_ON_ONCE(loop == 20); 5382 mutex_unlock(&rt5677->irq_lock); 5383 if (irq_fired) 5384 return IRQ_HANDLED; 5385 else 5386 return IRQ_NONE; 5387 } 5388 5389 static void rt5677_resume_irq_check(struct work_struct *work) 5390 { 5391 int i, virq; 5392 struct rt5677_priv *rt5677 = 5393 container_of(work, struct rt5677_priv, resume_irq_check.work); 5394 5395 /* This is needed to check and clear the interrupt status register 5396 * at resume. If the headset is plugged/unplugged when the device is 5397 * fully suspended, there won't be a rising edge at resume to trigger 5398 * the interrupt. Without this, we miss the next unplug/plug event. 5399 */ 5400 rt5677_irq(0, rt5677); 5401 5402 /* Call all enabled jack detect irq handlers again. This is needed in 5403 * addition to the above check for a corner case caused by jack gpio 5404 * debounce. After codec irq is disabled at suspend, the delayed work 5405 * scheduled by soc-jack may run and read wrong jack gpio values, since 5406 * the regmap is in cache only mode. At resume, there is no irq because 5407 * rt5677_irq has already ran and cleared the irq status at suspend. 5408 * Without this explicit check, unplug the headset right after suspend 5409 * starts, then after resume the headset is still shown as plugged in. 5410 */ 5411 guard(mutex)(&rt5677->irq_lock); 5412 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5413 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) { 5414 virq = irq_find_mapping(rt5677->domain, i); 5415 if (virq) 5416 handle_nested_irq(virq); 5417 } 5418 } 5419 } 5420 5421 static void rt5677_irq_bus_lock(struct irq_data *data) 5422 { 5423 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5424 5425 mutex_lock(&rt5677->irq_lock); 5426 } 5427 5428 static void rt5677_irq_bus_sync_unlock(struct irq_data *data) 5429 { 5430 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5431 5432 // Set the enable/disable bits for the jack detect IRQs. 5433 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1, 5434 RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 | 5435 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en); 5436 mutex_unlock(&rt5677->irq_lock); 5437 } 5438 5439 static void rt5677_irq_enable(struct irq_data *data) 5440 { 5441 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5442 5443 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask; 5444 } 5445 5446 static void rt5677_irq_disable(struct irq_data *data) 5447 { 5448 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5449 5450 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask; 5451 } 5452 5453 static struct irq_chip rt5677_irq_chip = { 5454 .name = "rt5677_irq_chip", 5455 .irq_bus_lock = rt5677_irq_bus_lock, 5456 .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock, 5457 .irq_disable = rt5677_irq_disable, 5458 .irq_enable = rt5677_irq_enable, 5459 }; 5460 5461 static int rt5677_irq_map(struct irq_domain *h, unsigned int virq, 5462 irq_hw_number_t hw) 5463 { 5464 struct rt5677_priv *rt5677 = h->host_data; 5465 5466 irq_set_chip_data(virq, rt5677); 5467 irq_set_chip(virq, &rt5677_irq_chip); 5468 irq_set_nested_thread(virq, 1); 5469 irq_set_noprobe(virq); 5470 return 0; 5471 } 5472 5473 5474 static const struct irq_domain_ops rt5677_domain_ops = { 5475 .map = rt5677_irq_map, 5476 .xlate = irq_domain_xlate_twocell, 5477 }; 5478 5479 static int rt5677_init_irq(struct i2c_client *i2c) 5480 { 5481 int ret; 5482 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 5483 unsigned int jd_mask = 0, jd_val = 0; 5484 5485 if (!rt5677->pdata.jd1_gpio && 5486 !rt5677->pdata.jd2_gpio && 5487 !rt5677->pdata.jd3_gpio) 5488 return 0; 5489 5490 if (!i2c->irq) { 5491 dev_err(&i2c->dev, "No interrupt specified\n"); 5492 return -EINVAL; 5493 } 5494 5495 mutex_init(&rt5677->irq_lock); 5496 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check); 5497 5498 /* 5499 * Select RC as the debounce clock so that GPIO works even when 5500 * MCLK is gated which happens when there is no audio stream 5501 * (SND_SOC_BIAS_OFF). 5502 */ 5503 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 5504 RT5677_IRQ_DEBOUNCE_SEL_MASK, 5505 RT5677_IRQ_DEBOUNCE_SEL_RC); 5506 /* Enable auto power on RC when GPIO states are changed */ 5507 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff); 5508 5509 /* Select and enable jack detection sources per platform data */ 5510 if (rt5677->pdata.jd1_gpio) { 5511 jd_mask |= RT5677_SEL_GPIO_JD1_MASK; 5512 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT; 5513 } 5514 if (rt5677->pdata.jd2_gpio) { 5515 jd_mask |= RT5677_SEL_GPIO_JD2_MASK; 5516 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT; 5517 } 5518 if (rt5677->pdata.jd3_gpio) { 5519 jd_mask |= RT5677_SEL_GPIO_JD3_MASK; 5520 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT; 5521 } 5522 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val); 5523 5524 /* Set GPIO1 pin to be IRQ output */ 5525 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5526 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5527 5528 /* Ready to listen for interrupts */ 5529 rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev), 5530 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677); 5531 if (!rt5677->domain) { 5532 dev_err(&i2c->dev, "Failed to create IRQ domain\n"); 5533 return -ENOMEM; 5534 } 5535 5536 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq, 5537 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5538 "rt5677", rt5677); 5539 if (ret) 5540 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 5541 5542 rt5677->irq = i2c->irq; 5543 5544 return ret; 5545 } 5546 5547 static const struct acpi_gpio_params rt5677_acpi_reset_gpios = {0, 0, true}; 5548 static const struct acpi_gpio_params rt5677_acpi_ldo2_gpios = {1, 0, false}; 5549 5550 static const struct acpi_gpio_mapping rt5677_acpi_gpios[] = { 5551 { "realtek,reset-gpios", &rt5677_acpi_reset_gpios, 1 }, 5552 { "realtek,pow-ldo2-gpios", &rt5677_acpi_ldo2_gpios, 1 }, 5553 {}, 5554 }; 5555 5556 static int rt5677_i2c_probe(struct i2c_client *i2c) 5557 { 5558 struct rt5677_priv *rt5677; 5559 int ret; 5560 unsigned int val; 5561 5562 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), 5563 GFP_KERNEL); 5564 if (rt5677 == NULL) 5565 return -ENOMEM; 5566 5567 rt5677->dev = &i2c->dev; 5568 rt5677->set_dsp_vad = rt5677_set_dsp_vad; 5569 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work); 5570 i2c_set_clientdata(i2c, rt5677); 5571 5572 rt5677->type = (enum rt5677_type)(uintptr_t)i2c_get_match_data(i2c); 5573 if (rt5677->type == 0) 5574 return -EINVAL; 5575 5576 if (devm_acpi_dev_add_driver_gpios(rt5677->dev, rt5677_acpi_gpios)) 5577 dev_warn(rt5677->dev, "Unable to add GPIO mapping table\n"); 5578 5579 rt5677_read_device_properties(rt5677, &i2c->dev); 5580 5581 /* pow-ldo2 and reset are optional. The codec pins may be statically 5582 * connected on the board without gpios. If the gpio device property 5583 * isn't specified, devm_gpiod_get_optional returns NULL. 5584 */ 5585 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, 5586 "realtek,pow-ldo2", GPIOD_OUT_HIGH); 5587 if (IS_ERR(rt5677->pow_ldo2)) { 5588 ret = PTR_ERR(rt5677->pow_ldo2); 5589 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); 5590 return ret; 5591 } 5592 5593 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, 5594 "realtek,reset", GPIOD_OUT_HIGH); 5595 5596 if (IS_ERR(rt5677->reset_pin)) { 5597 ret = PTR_ERR(rt5677->reset_pin); 5598 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); 5599 return ret; 5600 } 5601 5602 if (rt5677->reset_pin) { 5603 msleep(1); 5604 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 5605 } 5606 5607 if (rt5677->pow_ldo2 || rt5677->reset_pin) { 5608 /* Wait a while until I2C bus becomes available. The datasheet 5609 * does not specify the exact we should wait but startup 5610 * sequence mentiones at least a few milliseconds. 5611 */ 5612 msleep(10); 5613 } 5614 5615 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, 5616 &rt5677_regmap_physical); 5617 if (IS_ERR(rt5677->regmap_physical)) { 5618 ret = PTR_ERR(rt5677->regmap_physical); 5619 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5620 ret); 5621 return ret; 5622 } 5623 5624 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); 5625 if (IS_ERR(rt5677->regmap)) { 5626 ret = PTR_ERR(rt5677->regmap); 5627 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5628 ret); 5629 return ret; 5630 } 5631 5632 ret = regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); 5633 if (ret) { 5634 dev_err(&i2c->dev, 5635 "Failed to read ID register: %d\n", ret); 5636 return -ENODEV; 5637 } 5638 5639 if (val != RT5677_DEVICE_ID) { 5640 dev_err(&i2c->dev, 5641 "Device with ID register %#x is not rt5677\n", val); 5642 return -ENODEV; 5643 } 5644 5645 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 5646 5647 ret = regmap_register_patch(rt5677->regmap, init_list, 5648 ARRAY_SIZE(init_list)); 5649 if (ret != 0) 5650 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 5651 5652 if (rt5677->pdata.in1_diff) 5653 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5654 RT5677_IN_DF1, RT5677_IN_DF1); 5655 5656 if (rt5677->pdata.in2_diff) 5657 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5658 RT5677_IN_DF2, RT5677_IN_DF2); 5659 5660 if (rt5677->pdata.lout1_diff) 5661 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5662 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); 5663 5664 if (rt5677->pdata.lout2_diff) 5665 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5666 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); 5667 5668 if (rt5677->pdata.lout3_diff) 5669 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5670 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); 5671 5672 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 5673 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, 5674 RT5677_GPIO5_FUNC_MASK, 5675 RT5677_GPIO5_FUNC_DMIC); 5676 rt5677_update_gpio_bits(rt5677, RT5677_GPIO5, 5677 RT5677_GPIOx_DIR_MASK, 5678 RT5677_GPIOx_DIR_OUT); 5679 } 5680 5681 if (rt5677->pdata.micbias1_vdd_3v3) 5682 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, 5683 RT5677_MICBIAS1_CTRL_VDD_MASK, 5684 RT5677_MICBIAS1_CTRL_VDD_3_3V); 5685 5686 rt5677_init_gpio(i2c); 5687 ret = rt5677_init_irq(i2c); 5688 if (ret) 5689 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret); 5690 5691 return devm_snd_soc_register_component(&i2c->dev, 5692 &soc_component_dev_rt5677, 5693 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 5694 } 5695 5696 static void rt5677_i2c_remove(struct i2c_client *i2c) 5697 { 5698 rt5677_free_gpio(i2c); 5699 } 5700 5701 static struct i2c_driver rt5677_i2c_driver = { 5702 .driver = { 5703 .name = RT5677_DRV_NAME, 5704 .of_match_table = rt5677_of_match, 5705 .acpi_match_table = rt5677_acpi_match, 5706 }, 5707 .id_table = rt5677_i2c_id, 5708 .probe = rt5677_i2c_probe, 5709 .remove = rt5677_i2c_remove, 5710 }; 5711 module_i2c_driver(rt5677_i2c_driver); 5712 5713 MODULE_DESCRIPTION("ASoC RT5677 driver"); 5714 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 5715 MODULE_LICENSE("GPL v2"); 5716 5717 MODULE_FIRMWARE("rt5677_elf_vad"); 5718