1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5677.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #include <linux/cleanup.h> 10 #include <linux/bits.h> 11 #include <linux/delay.h> 12 #include <linux/firmware.h> 13 #include <linux/fs.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqdomain.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm.h> 23 #include <linux/property.h> 24 #include <linux/regmap.h> 25 #include <linux/spi/spi.h> 26 #include <linux/workqueue.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 35 #include "rl6231.h" 36 #include "rt5677.h" 37 #include "rt5677-spi.h" 38 39 #define RT5677_DEVICE_ID 0x6327 40 41 /* Register controlling boot vector */ 42 #define RT5677_DSP_BOOT_VECTOR 0x1801f090 43 #define RT5677_MODEL_ADDR 0x5FFC9800 44 45 #define RT5677_PR_RANGE_BASE (0xff + 1) 46 #define RT5677_PR_SPACING 0x100 47 48 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 49 50 static const struct regmap_range_cfg rt5677_ranges[] = { 51 { 52 .name = "PR", 53 .range_min = RT5677_PR_BASE, 54 .range_max = RT5677_PR_BASE + 0xfd, 55 .selector_reg = RT5677_PRIV_INDEX, 56 .selector_mask = 0xff, 57 .selector_shift = 0x0, 58 .window_start = RT5677_PRIV_DATA, 59 .window_len = 0x1, 60 }, 61 }; 62 63 static const struct reg_sequence init_list[] = { 64 {RT5677_ASRC_12, 0x0018}, 65 {RT5677_PR_BASE + 0x3d, 0x364d}, 66 {RT5677_PR_BASE + 0x17, 0x4fc0}, 67 {RT5677_PR_BASE + 0x13, 0x0312}, 68 {RT5677_PR_BASE + 0x1e, 0x0000}, 69 {RT5677_PR_BASE + 0x12, 0x0eaa}, 70 {RT5677_PR_BASE + 0x14, 0x018a}, 71 {RT5677_PR_BASE + 0x15, 0x0490}, 72 {RT5677_PR_BASE + 0x38, 0x0f71}, 73 {RT5677_PR_BASE + 0x39, 0x0f71}, 74 }; 75 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 76 77 static const struct reg_default rt5677_reg[] = { 78 {RT5677_RESET , 0x0000}, 79 {RT5677_LOUT1 , 0xa800}, 80 {RT5677_IN1 , 0x0000}, 81 {RT5677_MICBIAS , 0x0000}, 82 {RT5677_SLIMBUS_PARAM , 0x0000}, 83 {RT5677_SLIMBUS_RX , 0x0000}, 84 {RT5677_SLIMBUS_CTRL , 0x0000}, 85 {RT5677_SIDETONE_CTRL , 0x000b}, 86 {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, 87 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, 88 {RT5677_DAC4_DIG_VOL , 0xafaf}, 89 {RT5677_DAC3_DIG_VOL , 0xafaf}, 90 {RT5677_DAC1_DIG_VOL , 0xafaf}, 91 {RT5677_DAC2_DIG_VOL , 0xafaf}, 92 {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, 93 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, 94 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, 95 {RT5677_STO1_2_ADC_BST , 0x0000}, 96 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, 97 {RT5677_ADC_BST_CTRL2 , 0x0000}, 98 {RT5677_STO3_4_ADC_BST , 0x0000}, 99 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, 100 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, 101 {RT5677_STO4_ADC_MIXER , 0xd4c0}, 102 {RT5677_STO3_ADC_MIXER , 0xd4c0}, 103 {RT5677_STO2_ADC_MIXER , 0xd4c0}, 104 {RT5677_STO1_ADC_MIXER , 0xd4c0}, 105 {RT5677_MONO_ADC_MIXER , 0xd4d1}, 106 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, 107 {RT5677_STO1_DAC_MIXER , 0xaaaa}, 108 {RT5677_MONO_DAC_MIXER , 0xaaaa}, 109 {RT5677_DD1_MIXER , 0xaaaa}, 110 {RT5677_DD2_MIXER , 0xaaaa}, 111 {RT5677_IF3_DATA , 0x0000}, 112 {RT5677_IF4_DATA , 0x0000}, 113 {RT5677_PDM_OUT_CTRL , 0x8888}, 114 {RT5677_PDM_DATA_CTRL1 , 0x0000}, 115 {RT5677_PDM_DATA_CTRL2 , 0x0000}, 116 {RT5677_PDM1_DATA_CTRL2 , 0x0000}, 117 {RT5677_PDM1_DATA_CTRL3 , 0x0000}, 118 {RT5677_PDM1_DATA_CTRL4 , 0x0000}, 119 {RT5677_PDM2_DATA_CTRL2 , 0x0000}, 120 {RT5677_PDM2_DATA_CTRL3 , 0x0000}, 121 {RT5677_PDM2_DATA_CTRL4 , 0x0000}, 122 {RT5677_TDM1_CTRL1 , 0x0300}, 123 {RT5677_TDM1_CTRL2 , 0x0000}, 124 {RT5677_TDM1_CTRL3 , 0x4000}, 125 {RT5677_TDM1_CTRL4 , 0x0123}, 126 {RT5677_TDM1_CTRL5 , 0x4567}, 127 {RT5677_TDM2_CTRL1 , 0x0300}, 128 {RT5677_TDM2_CTRL2 , 0x0000}, 129 {RT5677_TDM2_CTRL3 , 0x4000}, 130 {RT5677_TDM2_CTRL4 , 0x0123}, 131 {RT5677_TDM2_CTRL5 , 0x4567}, 132 {RT5677_I2C_MASTER_CTRL1 , 0x0001}, 133 {RT5677_I2C_MASTER_CTRL2 , 0x0000}, 134 {RT5677_I2C_MASTER_CTRL3 , 0x0000}, 135 {RT5677_I2C_MASTER_CTRL4 , 0x0000}, 136 {RT5677_I2C_MASTER_CTRL5 , 0x0000}, 137 {RT5677_I2C_MASTER_CTRL6 , 0x0000}, 138 {RT5677_I2C_MASTER_CTRL7 , 0x0000}, 139 {RT5677_I2C_MASTER_CTRL8 , 0x0000}, 140 {RT5677_DMIC_CTRL1 , 0x1505}, 141 {RT5677_DMIC_CTRL2 , 0x0055}, 142 {RT5677_HAP_GENE_CTRL1 , 0x0111}, 143 {RT5677_HAP_GENE_CTRL2 , 0x0064}, 144 {RT5677_HAP_GENE_CTRL3 , 0xef0e}, 145 {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, 146 {RT5677_HAP_GENE_CTRL5 , 0xef0e}, 147 {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, 148 {RT5677_HAP_GENE_CTRL7 , 0xef0e}, 149 {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, 150 {RT5677_HAP_GENE_CTRL9 , 0xf000}, 151 {RT5677_HAP_GENE_CTRL10 , 0x0000}, 152 {RT5677_PWR_DIG1 , 0x0000}, 153 {RT5677_PWR_DIG2 , 0x0000}, 154 {RT5677_PWR_ANLG1 , 0x0055}, 155 {RT5677_PWR_ANLG2 , 0x0000}, 156 {RT5677_PWR_DSP1 , 0x0001}, 157 {RT5677_PWR_DSP_ST , 0x0000}, 158 {RT5677_PWR_DSP2 , 0x0000}, 159 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, 160 {RT5677_PRIV_INDEX , 0x0000}, 161 {RT5677_PRIV_DATA , 0x0000}, 162 {RT5677_I2S4_SDP , 0x8000}, 163 {RT5677_I2S1_SDP , 0x8000}, 164 {RT5677_I2S2_SDP , 0x8000}, 165 {RT5677_I2S3_SDP , 0x8000}, 166 {RT5677_CLK_TREE_CTRL1 , 0x1111}, 167 {RT5677_CLK_TREE_CTRL2 , 0x1111}, 168 {RT5677_CLK_TREE_CTRL3 , 0x0000}, 169 {RT5677_PLL1_CTRL1 , 0x0000}, 170 {RT5677_PLL1_CTRL2 , 0x0000}, 171 {RT5677_PLL2_CTRL1 , 0x0c60}, 172 {RT5677_PLL2_CTRL2 , 0x2000}, 173 {RT5677_GLB_CLK1 , 0x0000}, 174 {RT5677_GLB_CLK2 , 0x0000}, 175 {RT5677_ASRC_1 , 0x0000}, 176 {RT5677_ASRC_2 , 0x0000}, 177 {RT5677_ASRC_3 , 0x0000}, 178 {RT5677_ASRC_4 , 0x0000}, 179 {RT5677_ASRC_5 , 0x0000}, 180 {RT5677_ASRC_6 , 0x0000}, 181 {RT5677_ASRC_7 , 0x0000}, 182 {RT5677_ASRC_8 , 0x0000}, 183 {RT5677_ASRC_9 , 0x0000}, 184 {RT5677_ASRC_10 , 0x0000}, 185 {RT5677_ASRC_11 , 0x0000}, 186 {RT5677_ASRC_12 , 0x0018}, 187 {RT5677_ASRC_13 , 0x0000}, 188 {RT5677_ASRC_14 , 0x0000}, 189 {RT5677_ASRC_15 , 0x0000}, 190 {RT5677_ASRC_16 , 0x0000}, 191 {RT5677_ASRC_17 , 0x0000}, 192 {RT5677_ASRC_18 , 0x0000}, 193 {RT5677_ASRC_19 , 0x0000}, 194 {RT5677_ASRC_20 , 0x0000}, 195 {RT5677_ASRC_21 , 0x000c}, 196 {RT5677_ASRC_22 , 0x0000}, 197 {RT5677_ASRC_23 , 0x0000}, 198 {RT5677_VAD_CTRL1 , 0x2184}, 199 {RT5677_VAD_CTRL2 , 0x010a}, 200 {RT5677_VAD_CTRL3 , 0x0aea}, 201 {RT5677_VAD_CTRL4 , 0x000c}, 202 {RT5677_VAD_CTRL5 , 0x0000}, 203 {RT5677_DSP_INB_CTRL1 , 0x0000}, 204 {RT5677_DSP_INB_CTRL2 , 0x0000}, 205 {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, 206 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, 207 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, 208 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, 209 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, 210 {RT5677_ADC_EQ_CTRL1 , 0x6000}, 211 {RT5677_ADC_EQ_CTRL2 , 0x0000}, 212 {RT5677_EQ_CTRL1 , 0xc000}, 213 {RT5677_EQ_CTRL2 , 0x0000}, 214 {RT5677_EQ_CTRL3 , 0x0000}, 215 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, 216 {RT5677_JD_CTRL1 , 0x0000}, 217 {RT5677_JD_CTRL2 , 0x0000}, 218 {RT5677_JD_CTRL3 , 0x0000}, 219 {RT5677_IRQ_CTRL1 , 0x0000}, 220 {RT5677_IRQ_CTRL2 , 0x0000}, 221 {RT5677_GPIO_ST , 0x0000}, 222 {RT5677_GPIO_CTRL1 , 0x0000}, 223 {RT5677_GPIO_CTRL2 , 0x0000}, 224 {RT5677_GPIO_CTRL3 , 0x0000}, 225 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, 226 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, 227 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, 228 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, 229 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, 230 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, 231 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, 232 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, 233 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, 234 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, 235 {RT5677_MB_DRC_CTRL1 , 0x0f20}, 236 {RT5677_DRC1_CTRL1 , 0x001f}, 237 {RT5677_DRC1_CTRL2 , 0x020c}, 238 {RT5677_DRC1_CTRL3 , 0x1f00}, 239 {RT5677_DRC1_CTRL4 , 0x0000}, 240 {RT5677_DRC1_CTRL5 , 0x0000}, 241 {RT5677_DRC1_CTRL6 , 0x0029}, 242 {RT5677_DRC2_CTRL1 , 0x001f}, 243 {RT5677_DRC2_CTRL2 , 0x020c}, 244 {RT5677_DRC2_CTRL3 , 0x1f00}, 245 {RT5677_DRC2_CTRL4 , 0x0000}, 246 {RT5677_DRC2_CTRL5 , 0x0000}, 247 {RT5677_DRC2_CTRL6 , 0x0029}, 248 {RT5677_DRC1_HL_CTRL1 , 0x8000}, 249 {RT5677_DRC1_HL_CTRL2 , 0x0200}, 250 {RT5677_DRC2_HL_CTRL1 , 0x8000}, 251 {RT5677_DRC2_HL_CTRL2 , 0x0200}, 252 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, 253 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, 254 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, 255 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, 256 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, 257 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, 258 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, 259 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, 260 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, 261 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, 262 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, 263 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, 264 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, 265 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, 266 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, 267 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, 268 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, 269 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, 270 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, 271 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, 272 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, 273 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, 274 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, 275 {RT5677_DIG_MISC , 0x0000}, 276 {RT5677_GEN_CTRL1 , 0x0000}, 277 {RT5677_GEN_CTRL2 , 0x0000}, 278 {RT5677_VENDOR_ID , 0x0000}, 279 {RT5677_VENDOR_ID1 , 0x10ec}, 280 {RT5677_VENDOR_ID2 , 0x6327}, 281 }; 282 283 static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 284 { 285 int i; 286 287 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 288 if (reg >= rt5677_ranges[i].range_min && 289 reg <= rt5677_ranges[i].range_max) { 290 return true; 291 } 292 } 293 294 switch (reg) { 295 case RT5677_RESET: 296 case RT5677_SLIMBUS_PARAM: 297 case RT5677_PDM_DATA_CTRL1: 298 case RT5677_PDM_DATA_CTRL2: 299 case RT5677_PDM1_DATA_CTRL4: 300 case RT5677_PDM2_DATA_CTRL4: 301 case RT5677_I2C_MASTER_CTRL1: 302 case RT5677_I2C_MASTER_CTRL7: 303 case RT5677_I2C_MASTER_CTRL8: 304 case RT5677_HAP_GENE_CTRL2: 305 case RT5677_PWR_ANLG2: /* Modified by DSP firmware */ 306 case RT5677_PWR_DSP_ST: 307 case RT5677_PRIV_DATA: 308 case RT5677_ASRC_22: 309 case RT5677_ASRC_23: 310 case RT5677_VAD_CTRL5: 311 case RT5677_ADC_EQ_CTRL1: 312 case RT5677_EQ_CTRL1: 313 case RT5677_IRQ_CTRL1: 314 case RT5677_IRQ_CTRL2: 315 case RT5677_GPIO_ST: 316 case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */ 317 case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */ 318 case RT5677_DSP_INB1_SRC_CTRL4: 319 case RT5677_DSP_INB2_SRC_CTRL4: 320 case RT5677_DSP_INB3_SRC_CTRL4: 321 case RT5677_DSP_OUTB1_SRC_CTRL4: 322 case RT5677_DSP_OUTB2_SRC_CTRL4: 323 case RT5677_VENDOR_ID: 324 case RT5677_VENDOR_ID1: 325 case RT5677_VENDOR_ID2: 326 return true; 327 default: 328 return false; 329 } 330 } 331 332 static bool rt5677_readable_register(struct device *dev, unsigned int reg) 333 { 334 int i; 335 336 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 337 if (reg >= rt5677_ranges[i].range_min && 338 reg <= rt5677_ranges[i].range_max) { 339 return true; 340 } 341 } 342 343 switch (reg) { 344 case RT5677_RESET: 345 case RT5677_LOUT1: 346 case RT5677_IN1: 347 case RT5677_MICBIAS: 348 case RT5677_SLIMBUS_PARAM: 349 case RT5677_SLIMBUS_RX: 350 case RT5677_SLIMBUS_CTRL: 351 case RT5677_SIDETONE_CTRL: 352 case RT5677_ANA_DAC1_2_3_SRC: 353 case RT5677_IF_DSP_DAC3_4_MIXER: 354 case RT5677_DAC4_DIG_VOL: 355 case RT5677_DAC3_DIG_VOL: 356 case RT5677_DAC1_DIG_VOL: 357 case RT5677_DAC2_DIG_VOL: 358 case RT5677_IF_DSP_DAC2_MIXER: 359 case RT5677_STO1_ADC_DIG_VOL: 360 case RT5677_MONO_ADC_DIG_VOL: 361 case RT5677_STO1_2_ADC_BST: 362 case RT5677_STO2_ADC_DIG_VOL: 363 case RT5677_ADC_BST_CTRL2: 364 case RT5677_STO3_4_ADC_BST: 365 case RT5677_STO3_ADC_DIG_VOL: 366 case RT5677_STO4_ADC_DIG_VOL: 367 case RT5677_STO4_ADC_MIXER: 368 case RT5677_STO3_ADC_MIXER: 369 case RT5677_STO2_ADC_MIXER: 370 case RT5677_STO1_ADC_MIXER: 371 case RT5677_MONO_ADC_MIXER: 372 case RT5677_ADC_IF_DSP_DAC1_MIXER: 373 case RT5677_STO1_DAC_MIXER: 374 case RT5677_MONO_DAC_MIXER: 375 case RT5677_DD1_MIXER: 376 case RT5677_DD2_MIXER: 377 case RT5677_IF3_DATA: 378 case RT5677_IF4_DATA: 379 case RT5677_PDM_OUT_CTRL: 380 case RT5677_PDM_DATA_CTRL1: 381 case RT5677_PDM_DATA_CTRL2: 382 case RT5677_PDM1_DATA_CTRL2: 383 case RT5677_PDM1_DATA_CTRL3: 384 case RT5677_PDM1_DATA_CTRL4: 385 case RT5677_PDM2_DATA_CTRL2: 386 case RT5677_PDM2_DATA_CTRL3: 387 case RT5677_PDM2_DATA_CTRL4: 388 case RT5677_TDM1_CTRL1: 389 case RT5677_TDM1_CTRL2: 390 case RT5677_TDM1_CTRL3: 391 case RT5677_TDM1_CTRL4: 392 case RT5677_TDM1_CTRL5: 393 case RT5677_TDM2_CTRL1: 394 case RT5677_TDM2_CTRL2: 395 case RT5677_TDM2_CTRL3: 396 case RT5677_TDM2_CTRL4: 397 case RT5677_TDM2_CTRL5: 398 case RT5677_I2C_MASTER_CTRL1: 399 case RT5677_I2C_MASTER_CTRL2: 400 case RT5677_I2C_MASTER_CTRL3: 401 case RT5677_I2C_MASTER_CTRL4: 402 case RT5677_I2C_MASTER_CTRL5: 403 case RT5677_I2C_MASTER_CTRL6: 404 case RT5677_I2C_MASTER_CTRL7: 405 case RT5677_I2C_MASTER_CTRL8: 406 case RT5677_DMIC_CTRL1: 407 case RT5677_DMIC_CTRL2: 408 case RT5677_HAP_GENE_CTRL1: 409 case RT5677_HAP_GENE_CTRL2: 410 case RT5677_HAP_GENE_CTRL3: 411 case RT5677_HAP_GENE_CTRL4: 412 case RT5677_HAP_GENE_CTRL5: 413 case RT5677_HAP_GENE_CTRL6: 414 case RT5677_HAP_GENE_CTRL7: 415 case RT5677_HAP_GENE_CTRL8: 416 case RT5677_HAP_GENE_CTRL9: 417 case RT5677_HAP_GENE_CTRL10: 418 case RT5677_PWR_DIG1: 419 case RT5677_PWR_DIG2: 420 case RT5677_PWR_ANLG1: 421 case RT5677_PWR_ANLG2: 422 case RT5677_PWR_DSP1: 423 case RT5677_PWR_DSP_ST: 424 case RT5677_PWR_DSP2: 425 case RT5677_ADC_DAC_HPF_CTRL1: 426 case RT5677_PRIV_INDEX: 427 case RT5677_PRIV_DATA: 428 case RT5677_I2S4_SDP: 429 case RT5677_I2S1_SDP: 430 case RT5677_I2S2_SDP: 431 case RT5677_I2S3_SDP: 432 case RT5677_CLK_TREE_CTRL1: 433 case RT5677_CLK_TREE_CTRL2: 434 case RT5677_CLK_TREE_CTRL3: 435 case RT5677_PLL1_CTRL1: 436 case RT5677_PLL1_CTRL2: 437 case RT5677_PLL2_CTRL1: 438 case RT5677_PLL2_CTRL2: 439 case RT5677_GLB_CLK1: 440 case RT5677_GLB_CLK2: 441 case RT5677_ASRC_1: 442 case RT5677_ASRC_2: 443 case RT5677_ASRC_3: 444 case RT5677_ASRC_4: 445 case RT5677_ASRC_5: 446 case RT5677_ASRC_6: 447 case RT5677_ASRC_7: 448 case RT5677_ASRC_8: 449 case RT5677_ASRC_9: 450 case RT5677_ASRC_10: 451 case RT5677_ASRC_11: 452 case RT5677_ASRC_12: 453 case RT5677_ASRC_13: 454 case RT5677_ASRC_14: 455 case RT5677_ASRC_15: 456 case RT5677_ASRC_16: 457 case RT5677_ASRC_17: 458 case RT5677_ASRC_18: 459 case RT5677_ASRC_19: 460 case RT5677_ASRC_20: 461 case RT5677_ASRC_21: 462 case RT5677_ASRC_22: 463 case RT5677_ASRC_23: 464 case RT5677_VAD_CTRL1: 465 case RT5677_VAD_CTRL2: 466 case RT5677_VAD_CTRL3: 467 case RT5677_VAD_CTRL4: 468 case RT5677_VAD_CTRL5: 469 case RT5677_DSP_INB_CTRL1: 470 case RT5677_DSP_INB_CTRL2: 471 case RT5677_DSP_IN_OUTB_CTRL: 472 case RT5677_DSP_OUTB0_1_DIG_VOL: 473 case RT5677_DSP_OUTB2_3_DIG_VOL: 474 case RT5677_DSP_OUTB4_5_DIG_VOL: 475 case RT5677_DSP_OUTB6_7_DIG_VOL: 476 case RT5677_ADC_EQ_CTRL1: 477 case RT5677_ADC_EQ_CTRL2: 478 case RT5677_EQ_CTRL1: 479 case RT5677_EQ_CTRL2: 480 case RT5677_EQ_CTRL3: 481 case RT5677_SOFT_VOL_ZERO_CROSS1: 482 case RT5677_JD_CTRL1: 483 case RT5677_JD_CTRL2: 484 case RT5677_JD_CTRL3: 485 case RT5677_IRQ_CTRL1: 486 case RT5677_IRQ_CTRL2: 487 case RT5677_GPIO_ST: 488 case RT5677_GPIO_CTRL1: 489 case RT5677_GPIO_CTRL2: 490 case RT5677_GPIO_CTRL3: 491 case RT5677_STO1_ADC_HI_FILTER1: 492 case RT5677_STO1_ADC_HI_FILTER2: 493 case RT5677_MONO_ADC_HI_FILTER1: 494 case RT5677_MONO_ADC_HI_FILTER2: 495 case RT5677_STO2_ADC_HI_FILTER1: 496 case RT5677_STO2_ADC_HI_FILTER2: 497 case RT5677_STO3_ADC_HI_FILTER1: 498 case RT5677_STO3_ADC_HI_FILTER2: 499 case RT5677_STO4_ADC_HI_FILTER1: 500 case RT5677_STO4_ADC_HI_FILTER2: 501 case RT5677_MB_DRC_CTRL1: 502 case RT5677_DRC1_CTRL1: 503 case RT5677_DRC1_CTRL2: 504 case RT5677_DRC1_CTRL3: 505 case RT5677_DRC1_CTRL4: 506 case RT5677_DRC1_CTRL5: 507 case RT5677_DRC1_CTRL6: 508 case RT5677_DRC2_CTRL1: 509 case RT5677_DRC2_CTRL2: 510 case RT5677_DRC2_CTRL3: 511 case RT5677_DRC2_CTRL4: 512 case RT5677_DRC2_CTRL5: 513 case RT5677_DRC2_CTRL6: 514 case RT5677_DRC1_HL_CTRL1: 515 case RT5677_DRC1_HL_CTRL2: 516 case RT5677_DRC2_HL_CTRL1: 517 case RT5677_DRC2_HL_CTRL2: 518 case RT5677_DSP_INB1_SRC_CTRL1: 519 case RT5677_DSP_INB1_SRC_CTRL2: 520 case RT5677_DSP_INB1_SRC_CTRL3: 521 case RT5677_DSP_INB1_SRC_CTRL4: 522 case RT5677_DSP_INB2_SRC_CTRL1: 523 case RT5677_DSP_INB2_SRC_CTRL2: 524 case RT5677_DSP_INB2_SRC_CTRL3: 525 case RT5677_DSP_INB2_SRC_CTRL4: 526 case RT5677_DSP_INB3_SRC_CTRL1: 527 case RT5677_DSP_INB3_SRC_CTRL2: 528 case RT5677_DSP_INB3_SRC_CTRL3: 529 case RT5677_DSP_INB3_SRC_CTRL4: 530 case RT5677_DSP_OUTB1_SRC_CTRL1: 531 case RT5677_DSP_OUTB1_SRC_CTRL2: 532 case RT5677_DSP_OUTB1_SRC_CTRL3: 533 case RT5677_DSP_OUTB1_SRC_CTRL4: 534 case RT5677_DSP_OUTB2_SRC_CTRL1: 535 case RT5677_DSP_OUTB2_SRC_CTRL2: 536 case RT5677_DSP_OUTB2_SRC_CTRL3: 537 case RT5677_DSP_OUTB2_SRC_CTRL4: 538 case RT5677_DSP_OUTB_0123_MIXER_CTRL: 539 case RT5677_DSP_OUTB_45_MIXER_CTRL: 540 case RT5677_DSP_OUTB_67_MIXER_CTRL: 541 case RT5677_DIG_MISC: 542 case RT5677_GEN_CTRL1: 543 case RT5677_GEN_CTRL2: 544 case RT5677_VENDOR_ID: 545 case RT5677_VENDOR_ID1: 546 case RT5677_VENDOR_ID2: 547 return true; 548 default: 549 return false; 550 } 551 } 552 553 /** 554 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. 555 * @rt5677: Private Data. 556 * @addr: Address index. 557 * @value: Address data. 558 * @opcode: opcode value 559 * 560 * Returns 0 for success or negative error code. 561 */ 562 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, 563 unsigned int addr, unsigned int value, unsigned int opcode) 564 { 565 struct snd_soc_component *component = rt5677->component; 566 int ret; 567 568 guard(mutex)(&rt5677->dsp_cmd_lock); 569 570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 571 addr >> 16); 572 if (ret < 0) { 573 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 574 return ret; 575 } 576 577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 578 addr & 0xffff); 579 if (ret < 0) { 580 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 581 return ret; 582 } 583 584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, 585 value >> 16); 586 if (ret < 0) { 587 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); 588 return ret; 589 } 590 591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, 592 value & 0xffff); 593 if (ret < 0) { 594 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); 595 return ret; 596 } 597 598 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 599 opcode); 600 if (ret < 0) { 601 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 602 return ret; 603 } 604 605 return ret; 606 } 607 608 /** 609 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. 610 * @rt5677: Private Data. 611 * @addr: Address index. 612 * @value: Address data. 613 * 614 * 615 * Returns 0 for success or negative error code. 616 */ 617 static int rt5677_dsp_mode_i2c_read_addr( 618 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) 619 { 620 struct snd_soc_component *component = rt5677->component; 621 int ret; 622 unsigned int msb, lsb; 623 624 guard(mutex)(&rt5677->dsp_cmd_lock); 625 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 627 addr >> 16); 628 if (ret < 0) { 629 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 630 return ret; 631 } 632 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 634 addr & 0xffff); 635 if (ret < 0) { 636 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 637 return ret; 638 } 639 640 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 641 0x0002); 642 if (ret < 0) { 643 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 644 return ret; 645 } 646 647 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); 648 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); 649 *value = (msb << 16) | lsb; 650 651 return ret; 652 } 653 654 /** 655 * rt5677_dsp_mode_i2c_write - Write register on DSP mode. 656 * @rt5677: Private Data. 657 * @reg: Register index. 658 * @value: Register data. 659 * 660 * 661 * Returns 0 for success or negative error code. 662 */ 663 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, 664 unsigned int reg, unsigned int value) 665 { 666 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, 667 value, 0x0001); 668 } 669 670 /** 671 * rt5677_dsp_mode_i2c_read - Read register on DSP mode. 672 * @rt5677: Private Data 673 * @reg: Register index. 674 * @value: Register data. 675 * 676 * 677 * Returns 0 for success or negative error code. 678 */ 679 static int rt5677_dsp_mode_i2c_read( 680 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) 681 { 682 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, 683 value); 684 685 *value &= 0xffff; 686 687 return ret; 688 } 689 690 static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on) 691 { 692 if (on) { 693 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 694 RT5677_PWR_DSP, RT5677_PWR_DSP); 695 rt5677->is_dsp_mode = true; 696 } else { 697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 698 RT5677_PWR_DSP, 0x0); 699 rt5677->is_dsp_mode = false; 700 } 701 } 702 703 static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677) 704 { 705 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt5677->component); 706 /* Force dapm to sync before we enable the 707 * DSP to prevent write corruption 708 */ 709 snd_soc_dapm_sync(dapm); 710 711 /* DMIC1 power = enabled 712 * DMIC CLK = 256 * fs / 12 713 */ 714 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 715 RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT); 716 717 /* I2S pre divide 2 = /6 (clk_sys2) */ 718 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 719 RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6); 720 721 /* DSP Clock = MCLK1 (bypassed PLL2) */ 722 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, 723 RT5677_DSP_CLK_SRC_BYPASS); 724 725 /* SAD Threshold1 */ 726 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f); 727 /* SAD Threshold2 */ 728 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5); 729 /* SAD Sample Rate Converter = Up 6 (8K to 48K) 730 * SAD Output Sample Rate = Same as I2S 731 * SAD Threshold3 732 */ 733 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4, 734 RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK | 735 RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT); 736 /* Minimum frame level within a pre-determined duration = 32 frames 737 * Bypass ADPCM Encoder/Decoder = Bypass ADPCM 738 * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable 739 * SAD Buffer Over-Writing = enable 740 * SAD Buffer Pop Mode Control = disable 741 * SAD Buffer Push Mode Control = enable 742 * SAD Detector Control = enable 743 * SAD Function Control = enable 744 * SAD Function Reset = normal 745 */ 746 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 747 RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE | 748 RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH | 749 RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC | 750 RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT); 751 752 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it 753 * is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save 754 * power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack 755 * Detection" for more info. 756 */ 757 758 /* Private register, no doc */ 759 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, 760 0x0f00, 0x0100); 761 762 /* LDO2 output = 1.2V 763 * LDO1 output = 1.2V (LDO_IN = 1.8V) 764 */ 765 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 766 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 767 5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT); 768 769 /* Codec core power = power on 770 * LDO1 power = power on 771 */ 772 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 773 RT5677_PWR_CORE | RT5677_PWR_LDO1, 774 RT5677_PWR_CORE | RT5677_PWR_LDO1); 775 776 /* Isolation for DCVDD4 = normal (set during probe) 777 * Isolation for DCVDD2 = normal (set during probe) 778 * Isolation for DSP = normal 779 * Isolation for Band 0~7 = disable 780 * Isolation for InBound 4~10 and OutBound 4~10 = disable 781 */ 782 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 783 RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO | 784 RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO | 785 RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO | 786 RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO | 787 RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO | 788 RT5677_PWR_MLT_ISO); 789 790 /* System Band 0~7 = power on 791 * InBound 4~10 and OutBound 4~10 = power on 792 * DSP = power on 793 * DSP CPU = stop (will be set to "run" after firmware loaded) 794 */ 795 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 796 RT5677_PWR_SR7 | RT5677_PWR_SR6 | 797 RT5677_PWR_SR5 | RT5677_PWR_SR4 | 798 RT5677_PWR_SR3 | RT5677_PWR_SR2 | 799 RT5677_PWR_SR1 | RT5677_PWR_SR0 | 800 RT5677_PWR_MLT | RT5677_PWR_DSP | 801 RT5677_PWR_DSP_CPU); 802 803 return 0; 804 } 805 806 static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf, 807 unsigned int len) 808 { 809 struct snd_soc_component *component = rt5677->component; 810 Elf32_Ehdr *elf_hdr; 811 Elf32_Phdr *pr_hdr; 812 Elf32_Half i; 813 int ret = 0; 814 815 if (!buf || (len < sizeof(Elf32_Ehdr))) 816 return -ENOMEM; 817 818 elf_hdr = (Elf32_Ehdr *)buf; 819 #ifndef EM_XTENSA 820 #define EM_XTENSA 94 821 #endif 822 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1)) 823 dev_err(component->dev, "Wrong ELF header prefix\n"); 824 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr)) 825 dev_err(component->dev, "Wrong ELF header size\n"); 826 if (elf_hdr->e_machine != EM_XTENSA) 827 dev_err(component->dev, "Wrong DSP code file\n"); 828 829 if (len < elf_hdr->e_phoff) 830 return -ENOMEM; 831 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff); 832 for (i = 0; i < elf_hdr->e_phnum; i++) { 833 /* TODO: handle p_memsz != p_filesz */ 834 if (pr_hdr->p_paddr && pr_hdr->p_filesz) { 835 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n", 836 pr_hdr->p_filesz, pr_hdr->p_paddr); 837 838 ret = rt5677_spi_write(pr_hdr->p_paddr, 839 buf + pr_hdr->p_offset, 840 pr_hdr->p_filesz); 841 if (ret) 842 dev_err(component->dev, "Load firmware failed %d\n", 843 ret); 844 } 845 pr_hdr++; 846 } 847 return ret; 848 } 849 850 static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677) 851 { 852 const struct firmware *fwp; 853 struct device *dev = rt5677->component->dev; 854 int ret = 0; 855 856 /* Load dsp firmware from rt5677_elf_vad file */ 857 ret = request_firmware(&fwp, "rt5677_elf_vad", dev); 858 if (ret) { 859 dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret); 860 return ret; 861 } 862 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size); 863 864 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size); 865 release_firmware(fwp); 866 return ret; 867 } 868 869 static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on) 870 { 871 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 872 rt5677->dsp_vad_en_request = on; 873 rt5677->dsp_vad_en = on; 874 875 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) 876 return -ENXIO; 877 878 schedule_delayed_work(&rt5677->dsp_work, 0); 879 return 0; 880 } 881 882 static void rt5677_dsp_work(struct work_struct *work) 883 { 884 struct rt5677_priv *rt5677 = 885 container_of(work, struct rt5677_priv, dsp_work.work); 886 static bool activity; 887 bool enable = rt5677->dsp_vad_en; 888 int i, val; 889 890 891 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", 892 enable, activity); 893 894 if (enable && !activity) { 895 activity = true; 896 897 /* Before a hotword is detected, GPIO1 pin is configured as IRQ 898 * output so that jack detect works. When a hotword is detected, 899 * the DSP firmware configures the GPIO1 pin as GPIO1 and 900 * drives a 1. rt5677_irq() is called after a rising edge on 901 * the GPIO1 pin, due to either jack detect event or hotword 902 * event, or both. All possible events are checked and handled 903 * in rt5677_irq() where GPIO1 pin is configured back to IRQ 904 * output if a hotword is detected. 905 */ 906 907 rt5677_set_vad_source(rt5677); 908 rt5677_set_dsp_mode(rt5677, true); 909 910 #define RT5677_BOOT_RETRY 20 911 for (i = 0; i < RT5677_BOOT_RETRY; i++) { 912 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val); 913 if (val == 0x3ff) 914 break; 915 udelay(500); 916 } 917 if (i == RT5677_BOOT_RETRY && val != 0x3ff) { 918 dev_err(rt5677->component->dev, "DSP Boot Timed Out!"); 919 return; 920 } 921 922 /* Boot the firmware from IRAM instead of SRAM0. */ 923 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 924 0x0009, 0x0003); 925 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 926 0x0019, 0x0003); 927 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 928 0x0009, 0x0003); 929 930 rt5677_load_dsp_from_file(rt5677); 931 932 /* Set DSP CPU to Run */ 933 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 934 RT5677_PWR_DSP_CPU, 0x0); 935 } else if (!enable && activity) { 936 activity = false; 937 938 /* Don't turn off the DSP while handling irqs */ 939 scoped_guard(mutex, &rt5677->irq_lock) { 940 /* Set DSP CPU to Stop */ 941 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 942 RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU); 943 944 rt5677_set_dsp_mode(rt5677, false); 945 946 /* Disable and clear VAD interrupt */ 947 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); 948 949 /* Set GPIO1 pin back to be IRQ output for jack detect */ 950 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 951 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 952 } 953 } 954 } 955 956 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 957 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 958 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 959 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 960 961 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 962 static const DECLARE_TLV_DB_RANGE(bst_tlv, 963 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 964 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 965 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 966 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 967 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 968 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 969 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 970 ); 971 972 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, 973 struct snd_ctl_elem_value *ucontrol) 974 { 975 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 976 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 977 978 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request; 979 980 return 0; 981 } 982 983 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, 984 struct snd_ctl_elem_value *ucontrol) 985 { 986 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 987 988 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]); 989 990 return 0; 991 } 992 993 static const struct snd_kcontrol_new rt5677_snd_controls[] = { 994 /* OUTPUT Control */ 995 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 996 RT5677_LOUT1_L_MUTE_SFT, 1, 1), 997 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, 998 RT5677_LOUT2_L_MUTE_SFT, 1, 1), 999 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, 1000 RT5677_LOUT3_L_MUTE_SFT, 1, 1), 1001 1002 /* DAC Digital Volume */ 1003 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 1004 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1005 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 1006 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1007 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 1008 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1009 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 1010 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1011 1012 /* IN1/IN2 Control */ 1013 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 1014 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), 1015 1016 /* ADC Digital Volume Control */ 1017 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, 1018 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1019 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, 1020 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1021 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, 1022 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1023 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, 1024 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1025 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, 1026 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1027 1028 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 1029 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1030 adc_vol_tlv), 1031 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 1032 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1033 adc_vol_tlv), 1034 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 1035 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1036 adc_vol_tlv), 1037 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 1038 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1039 adc_vol_tlv), 1040 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 1041 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, 1042 adc_vol_tlv), 1043 1044 /* Sidetone Control */ 1045 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, 1046 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), 1047 1048 /* ADC Boost Volume Control */ 1049 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1050 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 1051 adc_bst_tlv), 1052 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1053 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 1054 adc_bst_tlv), 1055 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1056 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 1057 adc_bst_tlv), 1058 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1059 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 1060 adc_bst_tlv), 1061 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 1062 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 1063 adc_bst_tlv), 1064 1065 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, 1066 rt5677_dsp_vad_get, rt5677_dsp_vad_put), 1067 }; 1068 1069 /** 1070 * set_dmic_clk - Set parameter of dmic. 1071 * 1072 * @w: DAPM widget. 1073 * @kcontrol: The kcontrol of this widget. 1074 * @event: Event id. 1075 * 1076 * Choose dmic clock between 1MHz and 3MHz. 1077 * It is better for clock to approximate 3MHz. 1078 */ 1079 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1080 struct snd_kcontrol *kcontrol, int event) 1081 { 1082 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1083 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1084 int idx, rate; 1085 1086 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, 1087 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT); 1088 idx = rl6231_calc_dmic_clk(rate); 1089 if (idx < 0) 1090 dev_err(component->dev, "Failed to set DMIC clock\n"); 1091 else 1092 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 1093 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); 1094 return idx; 1095 } 1096 1097 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 1098 struct snd_soc_dapm_widget *sink) 1099 { 1100 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1101 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1102 unsigned int val; 1103 1104 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); 1105 val &= RT5677_SCLK_SRC_MASK; 1106 if (val == RT5677_SCLK_SRC_PLL1) 1107 return 1; 1108 else 1109 return 0; 1110 } 1111 1112 static int is_using_asrc(struct snd_soc_dapm_widget *source, 1113 struct snd_soc_dapm_widget *sink) 1114 { 1115 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1116 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1117 unsigned int reg, shift, val; 1118 1119 if (source->reg == RT5677_ASRC_1) { 1120 switch (source->shift) { 1121 case 12: 1122 reg = RT5677_ASRC_4; 1123 shift = 0; 1124 break; 1125 case 13: 1126 reg = RT5677_ASRC_4; 1127 shift = 4; 1128 break; 1129 case 14: 1130 reg = RT5677_ASRC_4; 1131 shift = 8; 1132 break; 1133 case 15: 1134 reg = RT5677_ASRC_4; 1135 shift = 12; 1136 break; 1137 default: 1138 return 0; 1139 } 1140 } else { 1141 switch (source->shift) { 1142 case 0: 1143 reg = RT5677_ASRC_6; 1144 shift = 8; 1145 break; 1146 case 1: 1147 reg = RT5677_ASRC_6; 1148 shift = 12; 1149 break; 1150 case 2: 1151 reg = RT5677_ASRC_5; 1152 shift = 0; 1153 break; 1154 case 3: 1155 reg = RT5677_ASRC_5; 1156 shift = 4; 1157 break; 1158 case 4: 1159 reg = RT5677_ASRC_5; 1160 shift = 8; 1161 break; 1162 case 5: 1163 reg = RT5677_ASRC_5; 1164 shift = 12; 1165 break; 1166 case 12: 1167 reg = RT5677_ASRC_3; 1168 shift = 0; 1169 break; 1170 case 13: 1171 reg = RT5677_ASRC_3; 1172 shift = 4; 1173 break; 1174 case 14: 1175 reg = RT5677_ASRC_3; 1176 shift = 12; 1177 break; 1178 default: 1179 return 0; 1180 } 1181 } 1182 1183 regmap_read(rt5677->regmap, reg, &val); 1184 val = (val >> shift) & 0xf; 1185 1186 switch (val) { 1187 case 1 ... 6: 1188 return 1; 1189 default: 1190 return 0; 1191 } 1192 1193 } 1194 1195 static int can_use_asrc(struct snd_soc_dapm_widget *source, 1196 struct snd_soc_dapm_widget *sink) 1197 { 1198 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1199 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1200 1201 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) 1202 return 1; 1203 1204 return 0; 1205 } 1206 1207 /** 1208 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters 1209 * @component: SoC audio component device. 1210 * @filter_mask: mask of filters. 1211 * @clk_src: clock source 1212 * 1213 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can 1214 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1215 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1216 * ASRC function will track i2s clock and generate a corresponding system clock 1217 * for codec. This function provides an API to select the clock source for a 1218 * set of filters specified by the mask. And the codec driver will turn on ASRC 1219 * for these filters if ASRC is selected as their clock source. 1220 */ 1221 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component, 1222 unsigned int filter_mask, unsigned int clk_src) 1223 { 1224 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1225 unsigned int asrc3_mask = 0, asrc3_value = 0; 1226 unsigned int asrc4_mask = 0, asrc4_value = 0; 1227 unsigned int asrc5_mask = 0, asrc5_value = 0; 1228 unsigned int asrc6_mask = 0, asrc6_value = 0; 1229 unsigned int asrc7_mask = 0, asrc7_value = 0; 1230 unsigned int asrc8_mask = 0, asrc8_value = 0; 1231 1232 switch (clk_src) { 1233 case RT5677_CLK_SEL_SYS: 1234 case RT5677_CLK_SEL_I2S1_ASRC: 1235 case RT5677_CLK_SEL_I2S2_ASRC: 1236 case RT5677_CLK_SEL_I2S3_ASRC: 1237 case RT5677_CLK_SEL_I2S4_ASRC: 1238 case RT5677_CLK_SEL_I2S5_ASRC: 1239 case RT5677_CLK_SEL_I2S6_ASRC: 1240 case RT5677_CLK_SEL_SYS2: 1241 case RT5677_CLK_SEL_SYS3: 1242 case RT5677_CLK_SEL_SYS4: 1243 case RT5677_CLK_SEL_SYS5: 1244 case RT5677_CLK_SEL_SYS6: 1245 case RT5677_CLK_SEL_SYS7: 1246 break; 1247 1248 default: 1249 return -EINVAL; 1250 } 1251 1252 /* ASRC 3 */ 1253 if (filter_mask & RT5677_DA_STEREO_FILTER) { 1254 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK; 1255 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK) 1256 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT); 1257 } 1258 1259 if (filter_mask & RT5677_DA_MONO2_L_FILTER) { 1260 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK; 1261 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK) 1262 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT); 1263 } 1264 1265 if (filter_mask & RT5677_DA_MONO2_R_FILTER) { 1266 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK; 1267 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK) 1268 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT); 1269 } 1270 1271 if (asrc3_mask) 1272 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, 1273 asrc3_value); 1274 1275 /* ASRC 4 */ 1276 if (filter_mask & RT5677_DA_MONO3_L_FILTER) { 1277 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK; 1278 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK) 1279 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT); 1280 } 1281 1282 if (filter_mask & RT5677_DA_MONO3_R_FILTER) { 1283 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK; 1284 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK) 1285 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT); 1286 } 1287 1288 if (filter_mask & RT5677_DA_MONO4_L_FILTER) { 1289 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK; 1290 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK) 1291 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT); 1292 } 1293 1294 if (filter_mask & RT5677_DA_MONO4_R_FILTER) { 1295 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK; 1296 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK) 1297 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT); 1298 } 1299 1300 if (asrc4_mask) 1301 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, 1302 asrc4_value); 1303 1304 /* ASRC 5 */ 1305 if (filter_mask & RT5677_AD_STEREO1_FILTER) { 1306 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK; 1307 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK) 1308 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT); 1309 } 1310 1311 if (filter_mask & RT5677_AD_STEREO2_FILTER) { 1312 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK; 1313 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK) 1314 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT); 1315 } 1316 1317 if (filter_mask & RT5677_AD_STEREO3_FILTER) { 1318 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK; 1319 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK) 1320 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT); 1321 } 1322 1323 if (filter_mask & RT5677_AD_STEREO4_FILTER) { 1324 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK; 1325 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK) 1326 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT); 1327 } 1328 1329 if (asrc5_mask) 1330 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, 1331 asrc5_value); 1332 1333 /* ASRC 6 */ 1334 if (filter_mask & RT5677_AD_MONO_L_FILTER) { 1335 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK; 1336 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK) 1337 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT); 1338 } 1339 1340 if (filter_mask & RT5677_AD_MONO_R_FILTER) { 1341 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK; 1342 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK) 1343 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT); 1344 } 1345 1346 if (asrc6_mask) 1347 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, 1348 asrc6_value); 1349 1350 /* ASRC 7 */ 1351 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) { 1352 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK; 1353 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK) 1354 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT); 1355 } 1356 1357 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) { 1358 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK; 1359 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK) 1360 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT); 1361 } 1362 1363 if (asrc7_mask) 1364 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, 1365 asrc7_value); 1366 1367 /* ASRC 8 */ 1368 if (filter_mask & RT5677_I2S1_SOURCE) { 1369 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK; 1370 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK) 1371 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); 1372 } 1373 1374 if (filter_mask & RT5677_I2S2_SOURCE) { 1375 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK; 1376 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK) 1377 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); 1378 } 1379 1380 if (filter_mask & RT5677_I2S3_SOURCE) { 1381 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK; 1382 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK) 1383 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); 1384 } 1385 1386 if (filter_mask & RT5677_I2S4_SOURCE) { 1387 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK; 1388 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK) 1389 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); 1390 } 1391 1392 if (asrc8_mask) 1393 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, 1394 asrc8_value); 1395 1396 return 0; 1397 } 1398 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src); 1399 1400 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source, 1401 struct snd_soc_dapm_widget *sink) 1402 { 1403 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1404 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1405 unsigned int asrc_setting; 1406 1407 switch (source->shift) { 1408 case 11: 1409 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1410 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >> 1411 RT5677_AD_STO1_CLK_SEL_SFT; 1412 break; 1413 1414 case 10: 1415 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1416 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >> 1417 RT5677_AD_STO2_CLK_SEL_SFT; 1418 break; 1419 1420 case 9: 1421 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1422 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >> 1423 RT5677_AD_STO3_CLK_SEL_SFT; 1424 break; 1425 1426 case 8: 1427 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1428 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >> 1429 RT5677_AD_STO4_CLK_SEL_SFT; 1430 break; 1431 1432 case 7: 1433 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1434 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >> 1435 RT5677_AD_MONOL_CLK_SEL_SFT; 1436 break; 1437 1438 case 6: 1439 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1440 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >> 1441 RT5677_AD_MONOR_CLK_SEL_SFT; 1442 break; 1443 1444 default: 1445 return 0; 1446 } 1447 1448 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC && 1449 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC) 1450 return 1; 1451 1452 return 0; 1453 } 1454 1455 /* Digital Mixer */ 1456 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 1457 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1458 RT5677_M_STO1_ADC_L1_SFT, 1, 1), 1459 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1460 RT5677_M_STO1_ADC_L2_SFT, 1, 1), 1461 }; 1462 1463 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { 1464 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1465 RT5677_M_STO1_ADC_R1_SFT, 1, 1), 1466 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1467 RT5677_M_STO1_ADC_R2_SFT, 1, 1), 1468 }; 1469 1470 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { 1471 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1472 RT5677_M_STO2_ADC_L1_SFT, 1, 1), 1473 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1474 RT5677_M_STO2_ADC_L2_SFT, 1, 1), 1475 }; 1476 1477 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { 1478 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1479 RT5677_M_STO2_ADC_R1_SFT, 1, 1), 1480 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1481 RT5677_M_STO2_ADC_R2_SFT, 1, 1), 1482 }; 1483 1484 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { 1485 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1486 RT5677_M_STO3_ADC_L1_SFT, 1, 1), 1487 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1488 RT5677_M_STO3_ADC_L2_SFT, 1, 1), 1489 }; 1490 1491 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { 1492 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1493 RT5677_M_STO3_ADC_R1_SFT, 1, 1), 1494 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1495 RT5677_M_STO3_ADC_R2_SFT, 1, 1), 1496 }; 1497 1498 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { 1499 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1500 RT5677_M_STO4_ADC_L1_SFT, 1, 1), 1501 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1502 RT5677_M_STO4_ADC_L2_SFT, 1, 1), 1503 }; 1504 1505 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { 1506 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1507 RT5677_M_STO4_ADC_R1_SFT, 1, 1), 1508 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1509 RT5677_M_STO4_ADC_R2_SFT, 1, 1), 1510 }; 1511 1512 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { 1513 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1514 RT5677_M_MONO_ADC_L1_SFT, 1, 1), 1515 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1516 RT5677_M_MONO_ADC_L2_SFT, 1, 1), 1517 }; 1518 1519 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { 1520 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1521 RT5677_M_MONO_ADC_R1_SFT, 1, 1), 1522 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1523 RT5677_M_MONO_ADC_R2_SFT, 1, 1), 1524 }; 1525 1526 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { 1527 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1528 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), 1529 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1530 RT5677_M_DAC1_L_SFT, 1, 1), 1531 }; 1532 1533 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { 1534 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1535 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), 1536 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1537 RT5677_M_DAC1_R_SFT, 1, 1), 1538 }; 1539 1540 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { 1541 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER, 1542 RT5677_M_ST_DAC1_L_SFT, 1, 1), 1543 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1544 RT5677_M_DAC1_L_STO_L_SFT, 1, 1), 1545 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, 1546 RT5677_M_DAC2_L_STO_L_SFT, 1, 1), 1547 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1548 RT5677_M_DAC1_R_STO_L_SFT, 1, 1), 1549 }; 1550 1551 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { 1552 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER, 1553 RT5677_M_ST_DAC1_R_SFT, 1, 1), 1554 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1555 RT5677_M_DAC1_R_STO_R_SFT, 1, 1), 1556 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, 1557 RT5677_M_DAC2_R_STO_R_SFT, 1, 1), 1558 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1559 RT5677_M_DAC1_L_STO_R_SFT, 1, 1), 1560 }; 1561 1562 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { 1563 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER, 1564 RT5677_M_ST_DAC2_L_SFT, 1, 1), 1565 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, 1566 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), 1567 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1568 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), 1569 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1570 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), 1571 }; 1572 1573 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { 1574 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER, 1575 RT5677_M_ST_DAC2_R_SFT, 1, 1), 1576 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, 1577 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), 1578 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1579 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), 1580 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1581 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), 1582 }; 1583 1584 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { 1585 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, 1586 RT5677_M_STO_L_DD1_L_SFT, 1, 1), 1587 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, 1588 RT5677_M_MONO_L_DD1_L_SFT, 1, 1), 1589 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1590 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), 1591 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1592 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), 1593 }; 1594 1595 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { 1596 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, 1597 RT5677_M_STO_R_DD1_R_SFT, 1, 1), 1598 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, 1599 RT5677_M_MONO_R_DD1_R_SFT, 1, 1), 1600 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1601 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), 1602 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1603 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), 1604 }; 1605 1606 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { 1607 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, 1608 RT5677_M_STO_L_DD2_L_SFT, 1, 1), 1609 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, 1610 RT5677_M_MONO_L_DD2_L_SFT, 1, 1), 1611 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1612 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), 1613 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1614 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), 1615 }; 1616 1617 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { 1618 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, 1619 RT5677_M_STO_R_DD2_R_SFT, 1, 1), 1620 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, 1621 RT5677_M_MONO_R_DD2_R_SFT, 1, 1), 1622 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1623 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), 1624 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1625 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), 1626 }; 1627 1628 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { 1629 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1630 RT5677_DSP_IB_01_H_SFT, 1, 1), 1631 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1632 RT5677_DSP_IB_23_H_SFT, 1, 1), 1633 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1634 RT5677_DSP_IB_45_H_SFT, 1, 1), 1635 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1636 RT5677_DSP_IB_6_H_SFT, 1, 1), 1637 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1638 RT5677_DSP_IB_7_H_SFT, 1, 1), 1639 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1640 RT5677_DSP_IB_8_H_SFT, 1, 1), 1641 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1642 RT5677_DSP_IB_9_H_SFT, 1, 1), 1643 }; 1644 1645 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { 1646 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1647 RT5677_DSP_IB_01_L_SFT, 1, 1), 1648 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1649 RT5677_DSP_IB_23_L_SFT, 1, 1), 1650 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1651 RT5677_DSP_IB_45_L_SFT, 1, 1), 1652 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1653 RT5677_DSP_IB_6_L_SFT, 1, 1), 1654 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1655 RT5677_DSP_IB_7_L_SFT, 1, 1), 1656 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1657 RT5677_DSP_IB_8_L_SFT, 1, 1), 1658 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1659 RT5677_DSP_IB_9_L_SFT, 1, 1), 1660 }; 1661 1662 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { 1663 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1664 RT5677_DSP_IB_01_H_SFT, 1, 1), 1665 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1666 RT5677_DSP_IB_23_H_SFT, 1, 1), 1667 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1668 RT5677_DSP_IB_45_H_SFT, 1, 1), 1669 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1670 RT5677_DSP_IB_6_H_SFT, 1, 1), 1671 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1672 RT5677_DSP_IB_7_H_SFT, 1, 1), 1673 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1674 RT5677_DSP_IB_8_H_SFT, 1, 1), 1675 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1676 RT5677_DSP_IB_9_H_SFT, 1, 1), 1677 }; 1678 1679 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { 1680 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1681 RT5677_DSP_IB_01_L_SFT, 1, 1), 1682 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1683 RT5677_DSP_IB_23_L_SFT, 1, 1), 1684 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1685 RT5677_DSP_IB_45_L_SFT, 1, 1), 1686 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1687 RT5677_DSP_IB_6_L_SFT, 1, 1), 1688 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1689 RT5677_DSP_IB_7_L_SFT, 1, 1), 1690 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1691 RT5677_DSP_IB_8_L_SFT, 1, 1), 1692 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1693 RT5677_DSP_IB_9_L_SFT, 1, 1), 1694 }; 1695 1696 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { 1697 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1698 RT5677_DSP_IB_01_H_SFT, 1, 1), 1699 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1700 RT5677_DSP_IB_23_H_SFT, 1, 1), 1701 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1702 RT5677_DSP_IB_45_H_SFT, 1, 1), 1703 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1704 RT5677_DSP_IB_6_H_SFT, 1, 1), 1705 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1706 RT5677_DSP_IB_7_H_SFT, 1, 1), 1707 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1708 RT5677_DSP_IB_8_H_SFT, 1, 1), 1709 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1710 RT5677_DSP_IB_9_H_SFT, 1, 1), 1711 }; 1712 1713 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { 1714 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1715 RT5677_DSP_IB_01_L_SFT, 1, 1), 1716 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1717 RT5677_DSP_IB_23_L_SFT, 1, 1), 1718 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1719 RT5677_DSP_IB_45_L_SFT, 1, 1), 1720 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1721 RT5677_DSP_IB_6_L_SFT, 1, 1), 1722 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1723 RT5677_DSP_IB_7_L_SFT, 1, 1), 1724 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1725 RT5677_DSP_IB_8_L_SFT, 1, 1), 1726 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1727 RT5677_DSP_IB_9_L_SFT, 1, 1), 1728 }; 1729 1730 1731 /* Mux */ 1732 /* DAC1 L/R Source */ /* MX-29 [10:8] */ 1733 static const char * const rt5677_dac1_src[] = { 1734 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 1735 "OB 01" 1736 }; 1737 1738 static SOC_ENUM_SINGLE_DECL( 1739 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1740 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 1741 1742 static const struct snd_kcontrol_new rt5677_dac1_mux = 1743 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); 1744 1745 /* ADDA1 L/R Source */ /* MX-29 [1:0] */ 1746 static const char * const rt5677_adda1_src[] = { 1747 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 1748 }; 1749 1750 static SOC_ENUM_SINGLE_DECL( 1751 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1752 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 1753 1754 static const struct snd_kcontrol_new rt5677_adda1_mux = 1755 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); 1756 1757 1758 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ 1759 static const char * const rt5677_dac2l_src[] = { 1760 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 1761 "OB 2", 1762 }; 1763 1764 static SOC_ENUM_SINGLE_DECL( 1765 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, 1766 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 1767 1768 static const struct snd_kcontrol_new rt5677_dac2_l_mux = 1769 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); 1770 1771 static const char * const rt5677_dac2r_src[] = { 1772 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 1773 "OB 3", "Haptic Generator", "VAD ADC" 1774 }; 1775 1776 static SOC_ENUM_SINGLE_DECL( 1777 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, 1778 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 1779 1780 static const struct snd_kcontrol_new rt5677_dac2_r_mux = 1781 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); 1782 1783 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ 1784 static const char * const rt5677_dac3l_src[] = { 1785 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 1786 "SLB DAC 4", "OB 4" 1787 }; 1788 1789 static SOC_ENUM_SINGLE_DECL( 1790 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1791 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1792 1793 static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1794 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); 1795 1796 static const char * const rt5677_dac3r_src[] = { 1797 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1798 "SLB DAC 5", "OB 5" 1799 }; 1800 1801 static SOC_ENUM_SINGLE_DECL( 1802 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1803 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1804 1805 static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1806 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); 1807 1808 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ 1809 static const char * const rt5677_dac4l_src[] = { 1810 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1811 "SLB DAC 6", "OB 6" 1812 }; 1813 1814 static SOC_ENUM_SINGLE_DECL( 1815 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1816 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1817 1818 static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1819 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); 1820 1821 static const char * const rt5677_dac4r_src[] = { 1822 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1823 "SLB DAC 7", "OB 7" 1824 }; 1825 1826 static SOC_ENUM_SINGLE_DECL( 1827 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1828 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1829 1830 static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1831 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); 1832 1833 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1834 static const char * const rt5677_iob_bypass_src[] = { 1835 "Bypass", "Pass SRC" 1836 }; 1837 1838 static SOC_ENUM_SINGLE_DECL( 1839 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1840 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1841 1842 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1843 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); 1844 1845 static SOC_ENUM_SINGLE_DECL( 1846 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1847 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1848 1849 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1850 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); 1851 1852 static SOC_ENUM_SINGLE_DECL( 1853 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1854 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1855 1856 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1857 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); 1858 1859 static SOC_ENUM_SINGLE_DECL( 1860 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1861 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1862 1863 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1864 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); 1865 1866 static SOC_ENUM_SINGLE_DECL( 1867 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1868 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1869 1870 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1871 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1872 1873 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1874 static const char * const rt5677_stereo_adc2_src[] = { 1875 "DD MIX1", "DMIC", "Stereo DAC MIX" 1876 }; 1877 1878 static SOC_ENUM_SINGLE_DECL( 1879 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, 1880 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1881 1882 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1883 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); 1884 1885 static SOC_ENUM_SINGLE_DECL( 1886 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1887 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1888 1889 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1890 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); 1891 1892 static SOC_ENUM_SINGLE_DECL( 1893 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1894 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1895 1896 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1897 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); 1898 1899 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1900 static const char * const rt5677_dmic_src[] = { 1901 "DMIC1", "DMIC2", "DMIC3", "DMIC4" 1902 }; 1903 1904 static SOC_ENUM_SINGLE_DECL( 1905 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, 1906 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1907 1908 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1909 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); 1910 1911 static SOC_ENUM_SINGLE_DECL( 1912 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1913 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1914 1915 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1916 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); 1917 1918 static SOC_ENUM_SINGLE_DECL( 1919 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1920 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1921 1922 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1923 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); 1924 1925 static SOC_ENUM_SINGLE_DECL( 1926 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1927 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1928 1929 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1930 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); 1931 1932 static SOC_ENUM_SINGLE_DECL( 1933 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1934 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1935 1936 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1937 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); 1938 1939 static SOC_ENUM_SINGLE_DECL( 1940 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1941 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1942 1943 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1944 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); 1945 1946 /* Stereo2 ADC Source */ /* MX-26 [0] */ 1947 static const char * const rt5677_stereo2_adc_lr_src[] = { 1948 "L", "LR" 1949 }; 1950 1951 static SOC_ENUM_SINGLE_DECL( 1952 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, 1953 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1954 1955 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1956 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1957 1958 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1959 static const char * const rt5677_stereo_adc1_src[] = { 1960 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1961 }; 1962 1963 static SOC_ENUM_SINGLE_DECL( 1964 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, 1965 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1966 1967 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1968 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); 1969 1970 static SOC_ENUM_SINGLE_DECL( 1971 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1972 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1973 1974 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1975 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); 1976 1977 static SOC_ENUM_SINGLE_DECL( 1978 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1979 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1980 1981 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1982 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); 1983 1984 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ 1985 static const char * const rt5677_mono_adc2_l_src[] = { 1986 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1987 }; 1988 1989 static SOC_ENUM_SINGLE_DECL( 1990 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, 1991 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 1992 1993 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 1994 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); 1995 1996 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ 1997 static const char * const rt5677_mono_adc1_l_src[] = { 1998 "DD MIX1L", "ADC1", "MONO DAC MIXL" 1999 }; 2000 2001 static SOC_ENUM_SINGLE_DECL( 2002 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, 2003 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 2004 2005 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 2006 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); 2007 2008 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ 2009 static const char * const rt5677_mono_adc2_r_src[] = { 2010 "DD MIX1R", "DMIC", "MONO DAC MIXR" 2011 }; 2012 2013 static SOC_ENUM_SINGLE_DECL( 2014 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, 2015 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 2016 2017 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 2018 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); 2019 2020 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ 2021 static const char * const rt5677_mono_adc1_r_src[] = { 2022 "DD MIX1R", "ADC2", "MONO DAC MIXR" 2023 }; 2024 2025 static SOC_ENUM_SINGLE_DECL( 2026 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, 2027 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 2028 2029 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 2030 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); 2031 2032 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 2033 static const char * const rt5677_stereo4_adc2_src[] = { 2034 "DD MIX1", "DMIC", "DD MIX2" 2035 }; 2036 2037 static SOC_ENUM_SINGLE_DECL( 2038 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, 2039 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 2040 2041 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 2042 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); 2043 2044 2045 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 2046 static const char * const rt5677_stereo4_adc1_src[] = { 2047 "DD MIX1", "ADC1/2", "DD MIX2" 2048 }; 2049 2050 static SOC_ENUM_SINGLE_DECL( 2051 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, 2052 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 2053 2054 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 2055 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); 2056 2057 /* InBound0/1 Source */ /* MX-A3 [14:12] */ 2058 static const char * const rt5677_inbound01_src[] = { 2059 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", 2060 "VAD ADC/DAC1 FS" 2061 }; 2062 2063 static SOC_ENUM_SINGLE_DECL( 2064 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, 2065 RT5677_IB01_SRC_SFT, rt5677_inbound01_src); 2066 2067 static const struct snd_kcontrol_new rt5677_ib01_src_mux = 2068 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); 2069 2070 /* InBound2/3 Source */ /* MX-A3 [10:8] */ 2071 static const char * const rt5677_inbound23_src[] = { 2072 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", 2073 "DAC1 FS", "IF4 DAC" 2074 }; 2075 2076 static SOC_ENUM_SINGLE_DECL( 2077 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, 2078 RT5677_IB23_SRC_SFT, rt5677_inbound23_src); 2079 2080 static const struct snd_kcontrol_new rt5677_ib23_src_mux = 2081 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); 2082 2083 /* InBound4/5 Source */ /* MX-A3 [6:4] */ 2084 static const char * const rt5677_inbound45_src[] = { 2085 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", 2086 "IF3 DAC" 2087 }; 2088 2089 static SOC_ENUM_SINGLE_DECL( 2090 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, 2091 RT5677_IB45_SRC_SFT, rt5677_inbound45_src); 2092 2093 static const struct snd_kcontrol_new rt5677_ib45_src_mux = 2094 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); 2095 2096 /* InBound6 Source */ /* MX-A3 [2:0] */ 2097 static const char * const rt5677_inbound6_src[] = { 2098 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", 2099 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" 2100 }; 2101 2102 static SOC_ENUM_SINGLE_DECL( 2103 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, 2104 RT5677_IB6_SRC_SFT, rt5677_inbound6_src); 2105 2106 static const struct snd_kcontrol_new rt5677_ib6_src_mux = 2107 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); 2108 2109 /* InBound7 Source */ /* MX-A4 [14:12] */ 2110 static const char * const rt5677_inbound7_src[] = { 2111 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", 2112 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" 2113 }; 2114 2115 static SOC_ENUM_SINGLE_DECL( 2116 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, 2117 RT5677_IB7_SRC_SFT, rt5677_inbound7_src); 2118 2119 static const struct snd_kcontrol_new rt5677_ib7_src_mux = 2120 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); 2121 2122 /* InBound8 Source */ /* MX-A4 [10:8] */ 2123 static const char * const rt5677_inbound8_src[] = { 2124 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", 2125 "MONO ADC MIX L", "DACL1 FS" 2126 }; 2127 2128 static SOC_ENUM_SINGLE_DECL( 2129 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, 2130 RT5677_IB8_SRC_SFT, rt5677_inbound8_src); 2131 2132 static const struct snd_kcontrol_new rt5677_ib8_src_mux = 2133 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); 2134 2135 /* InBound9 Source */ /* MX-A4 [6:4] */ 2136 static const char * const rt5677_inbound9_src[] = { 2137 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", 2138 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" 2139 }; 2140 2141 static SOC_ENUM_SINGLE_DECL( 2142 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, 2143 RT5677_IB9_SRC_SFT, rt5677_inbound9_src); 2144 2145 static const struct snd_kcontrol_new rt5677_ib9_src_mux = 2146 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); 2147 2148 /* VAD Source */ /* MX-9F [6:4] */ 2149 static const char * const rt5677_vad_src[] = { 2150 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", 2151 "STO3 ADC MIX L" 2152 }; 2153 2154 static SOC_ENUM_SINGLE_DECL( 2155 rt5677_vad_enum, RT5677_VAD_CTRL4, 2156 RT5677_VAD_SRC_SFT, rt5677_vad_src); 2157 2158 static const struct snd_kcontrol_new rt5677_vad_src_mux = 2159 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); 2160 2161 /* Sidetone Source */ /* MX-13 [11:9] */ 2162 static const char * const rt5677_sidetone_src[] = { 2163 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" 2164 }; 2165 2166 static SOC_ENUM_SINGLE_DECL( 2167 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, 2168 RT5677_ST_SEL_SFT, rt5677_sidetone_src); 2169 2170 static const struct snd_kcontrol_new rt5677_sidetone_mux = 2171 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); 2172 2173 /* DAC1/2 Source */ /* MX-15 [1:0] */ 2174 static const char * const rt5677_dac12_src[] = { 2175 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2176 }; 2177 2178 static SOC_ENUM_SINGLE_DECL( 2179 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, 2180 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); 2181 2182 static const struct snd_kcontrol_new rt5677_dac12_mux = 2183 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); 2184 2185 /* DAC3 Source */ /* MX-15 [5:4] */ 2186 static const char * const rt5677_dac3_src[] = { 2187 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" 2188 }; 2189 2190 static SOC_ENUM_SINGLE_DECL( 2191 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, 2192 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); 2193 2194 static const struct snd_kcontrol_new rt5677_dac3_mux = 2195 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 2196 2197 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 2198 static const char * const rt5677_pdm_src[] = { 2199 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2200 }; 2201 2202 static SOC_ENUM_SINGLE_DECL( 2203 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, 2204 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 2205 2206 static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 2207 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); 2208 2209 static SOC_ENUM_SINGLE_DECL( 2210 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 2211 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 2212 2213 static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 2214 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); 2215 2216 static SOC_ENUM_SINGLE_DECL( 2217 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 2218 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 2219 2220 static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 2221 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); 2222 2223 static SOC_ENUM_SINGLE_DECL( 2224 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 2225 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 2226 2227 static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 2228 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 2229 2230 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ 2231 static const char * const rt5677_if12_adc1_src[] = { 2232 "STO1 ADC MIX", "OB01", "VAD ADC" 2233 }; 2234 2235 static SOC_ENUM_SINGLE_DECL( 2236 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, 2237 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 2238 2239 static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 2240 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); 2241 2242 static SOC_ENUM_SINGLE_DECL( 2243 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 2244 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 2245 2246 static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 2247 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); 2248 2249 static SOC_ENUM_SINGLE_DECL( 2250 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 2251 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 2252 2253 static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 2254 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); 2255 2256 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 2257 static const char * const rt5677_if12_adc2_src[] = { 2258 "STO2 ADC MIX", "OB23" 2259 }; 2260 2261 static SOC_ENUM_SINGLE_DECL( 2262 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, 2263 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 2264 2265 static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 2266 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); 2267 2268 static SOC_ENUM_SINGLE_DECL( 2269 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 2270 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 2271 2272 static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 2273 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); 2274 2275 static SOC_ENUM_SINGLE_DECL( 2276 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 2277 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 2278 2279 static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 2280 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); 2281 2282 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 2283 static const char * const rt5677_if12_adc3_src[] = { 2284 "STO3 ADC MIX", "MONO ADC MIX", "OB45" 2285 }; 2286 2287 static SOC_ENUM_SINGLE_DECL( 2288 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, 2289 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 2290 2291 static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 2292 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); 2293 2294 static SOC_ENUM_SINGLE_DECL( 2295 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 2296 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 2297 2298 static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 2299 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); 2300 2301 static SOC_ENUM_SINGLE_DECL( 2302 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 2303 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 2304 2305 static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 2306 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 2307 2308 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 2309 static const char * const rt5677_if12_adc4_src[] = { 2310 "STO4 ADC MIX", "OB67", "OB01" 2311 }; 2312 2313 static SOC_ENUM_SINGLE_DECL( 2314 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, 2315 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 2316 2317 static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 2318 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); 2319 2320 static SOC_ENUM_SINGLE_DECL( 2321 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 2322 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 2323 2324 static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 2325 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); 2326 2327 static SOC_ENUM_SINGLE_DECL( 2328 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 2329 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 2330 2331 static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 2332 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 2333 2334 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ 2335 static const char * const rt5677_if34_adc_src[] = { 2336 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 2337 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 2338 }; 2339 2340 static SOC_ENUM_SINGLE_DECL( 2341 rt5677_if3_adc_enum, RT5677_IF3_DATA, 2342 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 2343 2344 static const struct snd_kcontrol_new rt5677_if3_adc_mux = 2345 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); 2346 2347 static SOC_ENUM_SINGLE_DECL( 2348 rt5677_if4_adc_enum, RT5677_IF4_DATA, 2349 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 2350 2351 static const struct snd_kcontrol_new rt5677_if4_adc_mux = 2352 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 2353 2354 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ 2355 static const char * const rt5677_if12_adc_swap_src[] = { 2356 "L/R", "R/L", "L/L", "R/R" 2357 }; 2358 2359 static SOC_ENUM_SINGLE_DECL( 2360 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, 2361 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); 2362 2363 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = 2364 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); 2365 2366 static SOC_ENUM_SINGLE_DECL( 2367 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, 2368 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2369 2370 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = 2371 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); 2372 2373 static SOC_ENUM_SINGLE_DECL( 2374 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, 2375 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2376 2377 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = 2378 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); 2379 2380 static SOC_ENUM_SINGLE_DECL( 2381 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, 2382 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2383 2384 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = 2385 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); 2386 2387 static SOC_ENUM_SINGLE_DECL( 2388 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, 2389 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2390 2391 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = 2392 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); 2393 2394 static SOC_ENUM_SINGLE_DECL( 2395 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, 2396 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2397 2398 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = 2399 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); 2400 2401 static SOC_ENUM_SINGLE_DECL( 2402 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, 2403 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2404 2405 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = 2406 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); 2407 2408 static SOC_ENUM_SINGLE_DECL( 2409 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, 2410 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2411 2412 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = 2413 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); 2414 2415 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ 2416 static const char * const rt5677_if1_adc_tdm_swap_src[] = { 2417 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2418 "3/1/2/4", "3/4/1/2" 2419 }; 2420 2421 static SOC_ENUM_SINGLE_DECL( 2422 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, 2423 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); 2424 2425 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = 2426 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); 2427 2428 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ 2429 static const char * const rt5677_if2_adc_tdm_swap_src[] = { 2430 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2431 "2/3/1/4", "3/4/1/2" 2432 }; 2433 2434 static SOC_ENUM_SINGLE_DECL( 2435 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, 2436 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); 2437 2438 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = 2439 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); 2440 2441 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] 2442 MX-3F[14:12][10:8][6:4][2:0] 2443 MX-43[14:12][10:8][6:4][2:0] 2444 MX-44[14:12][10:8][6:4][2:0] */ 2445 static const char * const rt5677_if12_dac_tdm_sel_src[] = { 2446 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 2447 }; 2448 2449 static SOC_ENUM_SINGLE_DECL( 2450 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, 2451 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2452 2453 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = 2454 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); 2455 2456 static SOC_ENUM_SINGLE_DECL( 2457 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, 2458 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2459 2460 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = 2461 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); 2462 2463 static SOC_ENUM_SINGLE_DECL( 2464 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, 2465 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2466 2467 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = 2468 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); 2469 2470 static SOC_ENUM_SINGLE_DECL( 2471 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, 2472 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2473 2474 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = 2475 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); 2476 2477 static SOC_ENUM_SINGLE_DECL( 2478 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, 2479 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2480 2481 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = 2482 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); 2483 2484 static SOC_ENUM_SINGLE_DECL( 2485 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, 2486 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2487 2488 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = 2489 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); 2490 2491 static SOC_ENUM_SINGLE_DECL( 2492 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, 2493 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2494 2495 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = 2496 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); 2497 2498 static SOC_ENUM_SINGLE_DECL( 2499 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, 2500 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2501 2502 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = 2503 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); 2504 2505 static SOC_ENUM_SINGLE_DECL( 2506 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, 2507 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2508 2509 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = 2510 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); 2511 2512 static SOC_ENUM_SINGLE_DECL( 2513 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, 2514 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2515 2516 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = 2517 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); 2518 2519 static SOC_ENUM_SINGLE_DECL( 2520 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, 2521 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2522 2523 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = 2524 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); 2525 2526 static SOC_ENUM_SINGLE_DECL( 2527 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, 2528 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2529 2530 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = 2531 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); 2532 2533 static SOC_ENUM_SINGLE_DECL( 2534 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, 2535 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2536 2537 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = 2538 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); 2539 2540 static SOC_ENUM_SINGLE_DECL( 2541 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, 2542 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2543 2544 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = 2545 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); 2546 2547 static SOC_ENUM_SINGLE_DECL( 2548 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, 2549 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2550 2551 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = 2552 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); 2553 2554 static SOC_ENUM_SINGLE_DECL( 2555 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, 2556 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2557 2558 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = 2559 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); 2560 2561 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2562 struct snd_kcontrol *kcontrol, int event) 2563 { 2564 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2565 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2566 2567 switch (event) { 2568 case SND_SOC_DAPM_POST_PMU: 2569 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2570 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); 2571 break; 2572 2573 case SND_SOC_DAPM_PRE_PMD: 2574 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2575 RT5677_PWR_BST1_P, 0); 2576 break; 2577 2578 default: 2579 return 0; 2580 } 2581 2582 return 0; 2583 } 2584 2585 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, 2586 struct snd_kcontrol *kcontrol, int event) 2587 { 2588 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2589 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2590 2591 switch (event) { 2592 case SND_SOC_DAPM_POST_PMU: 2593 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2594 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); 2595 break; 2596 2597 case SND_SOC_DAPM_PRE_PMD: 2598 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2599 RT5677_PWR_BST2_P, 0); 2600 break; 2601 2602 default: 2603 return 0; 2604 } 2605 2606 return 0; 2607 } 2608 2609 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, 2610 struct snd_kcontrol *kcontrol, int event) 2611 { 2612 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2613 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2614 2615 switch (event) { 2616 case SND_SOC_DAPM_PRE_PMU: 2617 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); 2618 break; 2619 2620 case SND_SOC_DAPM_POST_PMU: 2621 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); 2622 break; 2623 2624 default: 2625 return 0; 2626 } 2627 2628 return 0; 2629 } 2630 2631 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, 2632 struct snd_kcontrol *kcontrol, int event) 2633 { 2634 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2635 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2636 2637 switch (event) { 2638 case SND_SOC_DAPM_PRE_PMU: 2639 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); 2640 break; 2641 2642 case SND_SOC_DAPM_POST_PMU: 2643 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); 2644 break; 2645 2646 default: 2647 return 0; 2648 } 2649 2650 return 0; 2651 } 2652 2653 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, 2654 struct snd_kcontrol *kcontrol, int event) 2655 { 2656 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2657 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2658 2659 switch (event) { 2660 case SND_SOC_DAPM_POST_PMU: 2661 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2662 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2663 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 2664 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 2665 break; 2666 2667 case SND_SOC_DAPM_PRE_PMD: 2668 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2669 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2670 RT5677_PWR_CLK_MB, 0); 2671 break; 2672 2673 default: 2674 return 0; 2675 } 2676 2677 return 0; 2678 } 2679 2680 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, 2681 struct snd_kcontrol *kcontrol, int event) 2682 { 2683 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2684 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2685 unsigned int value; 2686 2687 switch (event) { 2688 case SND_SOC_DAPM_PRE_PMU: 2689 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); 2690 if (value & RT5677_IF1_ADC_CTRL_MASK) 2691 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 2692 RT5677_IF1_ADC_MODE_MASK, 2693 RT5677_IF1_ADC_MODE_TDM); 2694 break; 2695 2696 default: 2697 return 0; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, 2704 struct snd_kcontrol *kcontrol, int event) 2705 { 2706 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2707 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2708 unsigned int value; 2709 2710 switch (event) { 2711 case SND_SOC_DAPM_PRE_PMU: 2712 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); 2713 if (value & RT5677_IF2_ADC_CTRL_MASK) 2714 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 2715 RT5677_IF2_ADC_MODE_MASK, 2716 RT5677_IF2_ADC_MODE_TDM); 2717 break; 2718 2719 default: 2720 return 0; 2721 } 2722 2723 return 0; 2724 } 2725 2726 static int rt5677_vref_event(struct snd_soc_dapm_widget *w, 2727 struct snd_kcontrol *kcontrol, int event) 2728 { 2729 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2730 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2731 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2732 2733 switch (event) { 2734 case SND_SOC_DAPM_POST_PMU: 2735 if (snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_ON && 2736 !rt5677->is_vref_slow) { 2737 mdelay(20); 2738 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 2739 RT5677_PWR_FV1 | RT5677_PWR_FV2, 2740 RT5677_PWR_FV1 | RT5677_PWR_FV2); 2741 rt5677->is_vref_slow = true; 2742 } 2743 break; 2744 2745 default: 2746 return 0; 2747 } 2748 2749 return 0; 2750 } 2751 2752 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w, 2753 struct snd_kcontrol *kcontrol, int event) 2754 { 2755 switch (event) { 2756 case SND_SOC_DAPM_POST_PMU: 2757 msleep(50); 2758 break; 2759 2760 default: 2761 return 0; 2762 } 2763 2764 return 0; 2765 } 2766 2767 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2768 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2769 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | 2770 SND_SOC_DAPM_POST_PMU), 2771 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, 2772 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | 2773 SND_SOC_DAPM_POST_PMU), 2774 2775 /* ASRC */ 2776 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0), 2777 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0), 2778 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0), 2779 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0), 2780 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, 2781 rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU), 2782 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL, 2783 0), 2784 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL, 2785 0), 2786 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL, 2787 0), 2788 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL, 2789 0), 2790 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL, 2791 0), 2792 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL, 2793 0), 2794 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL, 2795 0), 2796 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL, 2797 0), 2798 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL, 2799 0), 2800 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL, 2801 0), 2802 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL, 2803 0), 2804 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL, 2805 0), 2806 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0), 2807 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0), 2808 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0), 2809 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0), 2810 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL, 2811 0), 2812 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL, 2813 0), 2814 2815 /* Input Side */ 2816 /* micbias */ 2817 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 2818 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | 2819 SND_SOC_DAPM_POST_PMU), 2820 2821 /* Input Lines */ 2822 SND_SOC_DAPM_INPUT("DMIC L1"), 2823 SND_SOC_DAPM_INPUT("DMIC R1"), 2824 SND_SOC_DAPM_INPUT("DMIC L2"), 2825 SND_SOC_DAPM_INPUT("DMIC R2"), 2826 SND_SOC_DAPM_INPUT("DMIC L3"), 2827 SND_SOC_DAPM_INPUT("DMIC R3"), 2828 SND_SOC_DAPM_INPUT("DMIC L4"), 2829 SND_SOC_DAPM_INPUT("DMIC R4"), 2830 2831 SND_SOC_DAPM_INPUT("IN1P"), 2832 SND_SOC_DAPM_INPUT("IN1N"), 2833 SND_SOC_DAPM_INPUT("IN2P"), 2834 SND_SOC_DAPM_INPUT("IN2N"), 2835 2836 SND_SOC_DAPM_INPUT("Haptic Generator"), 2837 2838 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2839 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2840 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2841 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2842 2843 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, 2844 RT5677_DMIC_1_EN_SFT, 0, NULL, 0), 2845 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, 2846 RT5677_DMIC_2_EN_SFT, 0, NULL, 0), 2847 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, 2848 RT5677_DMIC_3_EN_SFT, 0, NULL, 0), 2849 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, 2850 RT5677_DMIC_4_EN_SFT, 0, NULL, 0), 2851 2852 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2853 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2854 2855 /* Boost */ 2856 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, 2857 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, 2858 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2859 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, 2860 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, 2861 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2862 2863 /* ADCs */ 2864 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 2865 0, 0), 2866 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 2867 0, 0), 2868 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), 2869 2870 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, 2871 RT5677_PWR_ADC_L_BIT, 0, NULL, 0), 2872 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, 2873 RT5677_PWR_ADC_R_BIT, 0, NULL, 0), 2874 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, 2875 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), 2876 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, 2877 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), 2878 2879 /* ADC Mux */ 2880 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2881 &rt5677_sto1_dmic_mux), 2882 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2883 &rt5677_sto1_adc1_mux), 2884 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2885 &rt5677_sto1_adc2_mux), 2886 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 2887 &rt5677_sto2_dmic_mux), 2888 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2889 &rt5677_sto2_adc1_mux), 2890 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2891 &rt5677_sto2_adc2_mux), 2892 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, 2893 &rt5677_sto2_adc_lr_mux), 2894 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, 2895 &rt5677_sto3_dmic_mux), 2896 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2897 &rt5677_sto3_adc1_mux), 2898 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2899 &rt5677_sto3_adc2_mux), 2900 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, 2901 &rt5677_sto4_dmic_mux), 2902 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2903 &rt5677_sto4_adc1_mux), 2904 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2905 &rt5677_sto4_adc2_mux), 2906 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2907 &rt5677_mono_dmic_l_mux), 2908 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2909 &rt5677_mono_dmic_r_mux), 2910 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, 2911 &rt5677_mono_adc2_l_mux), 2912 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, 2913 &rt5677_mono_adc1_l_mux), 2914 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, 2915 &rt5677_mono_adc1_r_mux), 2916 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, 2917 &rt5677_mono_adc2_r_mux), 2918 2919 /* ADC Mixer */ 2920 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, 2921 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), 2922 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, 2923 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), 2924 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, 2925 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), 2926 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, 2927 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), 2928 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2929 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), 2930 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2931 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), 2932 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 2933 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), 2934 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 2935 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), 2936 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, 2937 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), 2938 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, 2939 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), 2940 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, 2941 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), 2942 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, 2943 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), 2944 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, 2945 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2946 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2947 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), 2948 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, 2949 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2950 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2951 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), 2952 2953 /* ADC PGA */ 2954 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2955 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2956 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2957 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2958 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2959 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2960 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2961 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2962 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2963 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2964 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2965 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2966 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2967 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2968 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2969 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2970 2971 /* DSP */ 2972 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2973 &rt5677_ib9_src_mux), 2974 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, 2975 &rt5677_ib8_src_mux), 2976 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, 2977 &rt5677_ib7_src_mux), 2978 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, 2979 &rt5677_ib6_src_mux), 2980 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, 2981 &rt5677_ib45_src_mux), 2982 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, 2983 &rt5677_ib23_src_mux), 2984 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, 2985 &rt5677_ib01_src_mux), 2986 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, 2987 &rt5677_ib45_bypass_src_mux), 2988 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2989 &rt5677_ib23_bypass_src_mux), 2990 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2991 &rt5677_ib01_bypass_src_mux), 2992 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2993 &rt5677_ob23_bypass_src_mux), 2994 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2995 &rt5677_ob01_bypass_src_mux), 2996 2997 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), 2998 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), 2999 3000 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), 3001 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), 3002 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), 3003 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), 3004 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), 3005 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), 3006 3007 /* Digital Interface */ 3008 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, 3009 RT5677_PWR_I2S1_BIT, 0, NULL, 0), 3010 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3011 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3012 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3013 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3014 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3015 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3016 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3017 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3018 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3019 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3020 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3021 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3022 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3023 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3024 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3025 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3026 3027 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, 3028 RT5677_PWR_I2S2_BIT, 0, NULL, 0), 3029 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3030 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3031 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3032 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3033 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3034 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3035 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3036 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3037 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3038 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3039 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3040 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3041 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3042 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3043 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3044 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3045 3046 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, 3047 RT5677_PWR_I2S3_BIT, 0, NULL, 0), 3048 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3049 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3050 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3051 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3052 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3053 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3054 3055 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, 3056 RT5677_PWR_I2S4_BIT, 0, NULL, 0), 3057 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3058 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3059 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3060 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3061 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3062 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3063 3064 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, 3065 RT5677_PWR_SLB_BIT, 0, NULL, 0), 3066 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3067 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3068 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3069 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3070 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3071 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3072 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3073 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3074 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3075 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3076 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3077 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3078 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3079 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3080 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3081 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3082 3083 /* Digital Interface Select */ 3084 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3085 &rt5677_if1_adc1_mux), 3086 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3087 &rt5677_if1_adc2_mux), 3088 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3089 &rt5677_if1_adc3_mux), 3090 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3091 &rt5677_if1_adc4_mux), 3092 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3093 &rt5677_if1_adc1_swap_mux), 3094 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3095 &rt5677_if1_adc2_swap_mux), 3096 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3097 &rt5677_if1_adc3_swap_mux), 3098 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3099 &rt5677_if1_adc4_swap_mux), 3100 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3101 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, 3102 SND_SOC_DAPM_PRE_PMU), 3103 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3104 &rt5677_if2_adc1_mux), 3105 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3106 &rt5677_if2_adc2_mux), 3107 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3108 &rt5677_if2_adc3_mux), 3109 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3110 &rt5677_if2_adc4_mux), 3111 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3112 &rt5677_if2_adc1_swap_mux), 3113 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3114 &rt5677_if2_adc2_swap_mux), 3115 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3116 &rt5677_if2_adc3_swap_mux), 3117 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3118 &rt5677_if2_adc4_swap_mux), 3119 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3120 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, 3121 SND_SOC_DAPM_PRE_PMU), 3122 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 3123 &rt5677_if3_adc_mux), 3124 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 3125 &rt5677_if4_adc_mux), 3126 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, 3127 &rt5677_slb_adc1_mux), 3128 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, 3129 &rt5677_slb_adc2_mux), 3130 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, 3131 &rt5677_slb_adc3_mux), 3132 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 3133 &rt5677_slb_adc4_mux), 3134 3135 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3136 &rt5677_if1_dac0_tdm_sel_mux), 3137 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3138 &rt5677_if1_dac1_tdm_sel_mux), 3139 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3140 &rt5677_if1_dac2_tdm_sel_mux), 3141 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3142 &rt5677_if1_dac3_tdm_sel_mux), 3143 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3144 &rt5677_if1_dac4_tdm_sel_mux), 3145 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3146 &rt5677_if1_dac5_tdm_sel_mux), 3147 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3148 &rt5677_if1_dac6_tdm_sel_mux), 3149 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3150 &rt5677_if1_dac7_tdm_sel_mux), 3151 3152 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3153 &rt5677_if2_dac0_tdm_sel_mux), 3154 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3155 &rt5677_if2_dac1_tdm_sel_mux), 3156 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3157 &rt5677_if2_dac2_tdm_sel_mux), 3158 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3159 &rt5677_if2_dac3_tdm_sel_mux), 3160 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3161 &rt5677_if2_dac4_tdm_sel_mux), 3162 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3163 &rt5677_if2_dac5_tdm_sel_mux), 3164 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3165 &rt5677_if2_dac6_tdm_sel_mux), 3166 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3167 &rt5677_if2_dac7_tdm_sel_mux), 3168 3169 /* Audio Interface */ 3170 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 3171 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 3172 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 3173 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 3174 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 3175 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 3176 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), 3177 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), 3178 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), 3179 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), 3180 SND_SOC_DAPM_AIF_OUT("DSPTX", "DSP Buffer", 0, SND_SOC_NOPM, 0, 0), 3181 3182 /* Sidetone Mux */ 3183 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, 3184 &rt5677_sidetone_mux), 3185 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, 3186 RT5677_ST_EN_SFT, 0, NULL, 0), 3187 3188 /* VAD Mux*/ 3189 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, 3190 &rt5677_vad_src_mux), 3191 3192 /* Tensilica DSP */ 3193 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 3194 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, 3195 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), 3196 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, 3197 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), 3198 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, 3199 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), 3200 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, 3201 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), 3202 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, 3203 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), 3204 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, 3205 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 3206 3207 /* Output Side */ 3208 /* DAC mixer before sound effect */ 3209 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 3210 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 3211 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 3212 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), 3213 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), 3214 3215 /* DAC Mux */ 3216 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, 3217 &rt5677_dac1_mux), 3218 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, 3219 &rt5677_adda1_mux), 3220 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, 3221 &rt5677_dac12_mux), 3222 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, 3223 &rt5677_dac3_mux), 3224 3225 /* DAC2 channel Mux */ 3226 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, 3227 &rt5677_dac2_l_mux), 3228 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, 3229 &rt5677_dac2_r_mux), 3230 3231 /* DAC3 channel Mux */ 3232 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, 3233 &rt5677_dac3_l_mux), 3234 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, 3235 &rt5677_dac3_r_mux), 3236 3237 /* DAC4 channel Mux */ 3238 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, 3239 &rt5677_dac4_l_mux), 3240 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, 3241 &rt5677_dac4_r_mux), 3242 3243 /* DAC Mixer */ 3244 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, 3245 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event, 3246 SND_SOC_DAPM_POST_PMU), 3247 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2, 3248 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event, 3249 SND_SOC_DAPM_POST_PMU), 3250 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2, 3251 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event, 3252 SND_SOC_DAPM_POST_PMU), 3253 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2, 3254 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event, 3255 SND_SOC_DAPM_POST_PMU), 3256 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2, 3257 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event, 3258 SND_SOC_DAPM_POST_PMU), 3259 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2, 3260 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event, 3261 SND_SOC_DAPM_POST_PMU), 3262 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2, 3263 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event, 3264 SND_SOC_DAPM_POST_PMU), 3265 3266 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 3267 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), 3268 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 3269 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), 3270 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 3271 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), 3272 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 3273 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), 3274 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, 3275 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), 3276 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, 3277 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), 3278 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, 3279 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), 3280 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, 3281 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), 3282 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3283 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3284 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3285 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3286 3287 /* DACs */ 3288 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, 3289 RT5677_PWR_DAC1_BIT, 0), 3290 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, 3291 RT5677_PWR_DAC2_BIT, 0), 3292 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, 3293 RT5677_PWR_DAC3_BIT, 0), 3294 3295 /* PDM */ 3296 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, 3297 RT5677_PWR_PDM1_BIT, 0, NULL, 0), 3298 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, 3299 RT5677_PWR_PDM2_BIT, 0, NULL, 0), 3300 3301 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, 3302 1, &rt5677_pdm1_l_mux), 3303 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, 3304 1, &rt5677_pdm1_r_mux), 3305 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, 3306 1, &rt5677_pdm2_l_mux), 3307 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 3308 1, &rt5677_pdm2_r_mux), 3309 3310 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 3311 0, NULL, 0), 3312 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 3313 0, NULL, 0), 3314 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 3315 0, NULL, 0), 3316 3317 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, 3318 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3319 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, 3320 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3321 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, 3322 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3323 3324 /* Output Lines */ 3325 SND_SOC_DAPM_OUTPUT("LOUT1"), 3326 SND_SOC_DAPM_OUTPUT("LOUT2"), 3327 SND_SOC_DAPM_OUTPUT("LOUT3"), 3328 SND_SOC_DAPM_OUTPUT("PDM1L"), 3329 SND_SOC_DAPM_OUTPUT("PDM1R"), 3330 SND_SOC_DAPM_OUTPUT("PDM2L"), 3331 SND_SOC_DAPM_OUTPUT("PDM2R"), 3332 3333 SND_SOC_DAPM_POST("vref", rt5677_vref_event), 3334 }; 3335 3336 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 3337 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc }, 3338 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc }, 3339 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc }, 3340 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc }, 3341 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc }, 3342 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc }, 3343 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc}, 3344 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc}, 3345 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc}, 3346 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc}, 3347 3348 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 3349 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc }, 3350 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc }, 3351 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc }, 3352 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc }, 3353 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc }, 3354 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc }, 3355 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 3356 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc }, 3357 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc }, 3358 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc }, 3359 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 3360 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 3361 3362 { "DMIC1", NULL, "DMIC L1" }, 3363 { "DMIC1", NULL, "DMIC R1" }, 3364 { "DMIC2", NULL, "DMIC L2" }, 3365 { "DMIC2", NULL, "DMIC R2" }, 3366 { "DMIC3", NULL, "DMIC L3" }, 3367 { "DMIC3", NULL, "DMIC R3" }, 3368 { "DMIC4", NULL, "DMIC L4" }, 3369 { "DMIC4", NULL, "DMIC R4" }, 3370 3371 { "DMIC L1", NULL, "DMIC CLK" }, 3372 { "DMIC R1", NULL, "DMIC CLK" }, 3373 { "DMIC L2", NULL, "DMIC CLK" }, 3374 { "DMIC R2", NULL, "DMIC CLK" }, 3375 { "DMIC L3", NULL, "DMIC CLK" }, 3376 { "DMIC R3", NULL, "DMIC CLK" }, 3377 { "DMIC L4", NULL, "DMIC CLK" }, 3378 { "DMIC R4", NULL, "DMIC CLK" }, 3379 3380 { "DMIC L1", NULL, "DMIC1 power" }, 3381 { "DMIC R1", NULL, "DMIC1 power" }, 3382 { "DMIC L3", NULL, "DMIC3 power" }, 3383 { "DMIC R3", NULL, "DMIC3 power" }, 3384 { "DMIC L4", NULL, "DMIC4 power" }, 3385 { "DMIC R4", NULL, "DMIC4 power" }, 3386 3387 { "BST1", NULL, "IN1P" }, 3388 { "BST1", NULL, "IN1N" }, 3389 { "BST2", NULL, "IN2P" }, 3390 { "BST2", NULL, "IN2N" }, 3391 3392 { "IN1P", NULL, "MICBIAS1" }, 3393 { "IN1N", NULL, "MICBIAS1" }, 3394 { "IN2P", NULL, "MICBIAS1" }, 3395 { "IN2N", NULL, "MICBIAS1" }, 3396 3397 { "ADC 1", NULL, "BST1" }, 3398 { "ADC 1", NULL, "ADC 1 power" }, 3399 { "ADC 1", NULL, "ADC1 clock" }, 3400 { "ADC 2", NULL, "BST2" }, 3401 { "ADC 2", NULL, "ADC 2 power" }, 3402 { "ADC 2", NULL, "ADC2 clock" }, 3403 3404 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 3405 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 3406 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, 3407 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, 3408 3409 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 3410 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 3411 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, 3412 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, 3413 3414 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, 3415 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, 3416 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, 3417 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, 3418 3419 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, 3420 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, 3421 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, 3422 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, 3423 3424 { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, 3425 { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, 3426 { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, 3427 { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, 3428 3429 { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, 3430 { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, 3431 { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, 3432 { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, 3433 3434 { "ADC 1_2", NULL, "ADC 1" }, 3435 { "ADC 1_2", NULL, "ADC 2" }, 3436 3437 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3438 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3439 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3440 3441 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3442 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 3443 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3444 3445 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3446 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3447 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3448 3449 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3450 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, 3451 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3452 3453 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3454 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3455 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3456 3457 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3458 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3459 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3460 3461 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3462 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3463 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, 3464 3465 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3466 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3467 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, 3468 3469 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, 3470 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, 3471 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3472 3473 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, 3474 { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, 3475 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3476 3477 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, 3478 { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, 3479 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3480 3481 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, 3482 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, 3483 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3484 3485 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3486 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3487 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3488 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3489 3490 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 3491 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 3492 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 3493 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 3494 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3495 3496 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 3497 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 3498 3499 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3500 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3501 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3502 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3503 3504 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, 3505 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, 3506 3507 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, 3508 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, 3509 3510 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, 3511 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, 3512 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 3513 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, 3514 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3515 3516 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 3517 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 3518 3519 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3520 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3521 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3522 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3523 3524 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, 3525 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, 3526 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, 3527 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, 3528 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3529 3530 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, 3531 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, 3532 3533 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3534 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3535 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3536 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3537 3538 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, 3539 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, 3540 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, 3541 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, 3542 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3543 3544 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, 3545 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, 3546 3547 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, 3548 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, 3549 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 3550 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3551 3552 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, 3553 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, 3554 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 3555 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3556 3557 { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, 3558 { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, 3559 3560 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3561 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3562 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3563 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3564 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3565 3566 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3567 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3568 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3569 3570 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3571 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3572 3573 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3574 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3575 { "IF1 ADC3 Mux", "OB45", "OB45" }, 3576 3577 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3578 { "IF1 ADC4 Mux", "OB67", "OB67" }, 3579 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3580 3581 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, 3582 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, 3583 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, 3584 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, 3585 3586 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, 3587 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, 3588 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, 3589 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, 3590 3591 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, 3592 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, 3593 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, 3594 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, 3595 3596 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, 3597 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, 3598 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, 3599 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, 3600 3601 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, 3602 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, 3603 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, 3604 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, 3605 3606 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, 3607 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, 3608 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, 3609 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, 3610 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, 3611 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, 3612 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, 3613 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, 3614 3615 { "AIF1TX", NULL, "I2S1" }, 3616 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, 3617 3618 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3619 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3620 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3621 3622 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3623 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3624 3625 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3626 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3627 { "IF2 ADC3 Mux", "OB45", "OB45" }, 3628 3629 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3630 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3631 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3632 3633 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, 3634 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, 3635 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, 3636 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, 3637 3638 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, 3639 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, 3640 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, 3641 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, 3642 3643 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, 3644 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, 3645 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, 3646 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, 3647 3648 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, 3649 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, 3650 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, 3651 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, 3652 3653 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, 3654 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, 3655 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, 3656 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, 3657 3658 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, 3659 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, 3660 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, 3661 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, 3662 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, 3663 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, 3664 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, 3665 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, 3666 3667 { "AIF2TX", NULL, "I2S2" }, 3668 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, 3669 3670 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3671 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3672 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3673 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3674 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3675 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3676 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3677 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3678 3679 { "AIF3TX", NULL, "I2S3" }, 3680 { "AIF3TX", NULL, "IF3 ADC Mux" }, 3681 3682 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3683 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3684 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3685 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3686 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3687 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3688 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3689 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3690 3691 { "AIF4TX", NULL, "I2S4" }, 3692 { "AIF4TX", NULL, "IF4 ADC Mux" }, 3693 3694 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3695 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3696 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3697 3698 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3699 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3700 3701 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3702 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3703 { "SLB ADC3 Mux", "OB45", "OB45" }, 3704 3705 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3706 { "SLB ADC4 Mux", "OB67", "OB67" }, 3707 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3708 3709 { "SLBTX", NULL, "SLB" }, 3710 { "SLBTX", NULL, "SLB ADC1 Mux" }, 3711 { "SLBTX", NULL, "SLB ADC2 Mux" }, 3712 { "SLBTX", NULL, "SLB ADC3 Mux" }, 3713 { "SLBTX", NULL, "SLB ADC4 Mux" }, 3714 3715 { "DSPTX", NULL, "IB01 Bypass Mux" }, 3716 3717 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3718 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3719 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, 3720 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3721 /* The IB01 Mux controls the source for InBound0 and InBound1. 3722 * When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to 3723 * InBound0 and "DAC1 FS" goes to InBound1. "VAD ADC" is used for 3724 * hotwording. "DAC1 FS" is not used currently. 3725 * 3726 * Creating a common widget node for "VAD ADC" + "DAC1 FS" and 3727 * connecting the common widget to IB01 Mux causes the issue where 3728 * there is an active path going from system playback -> "DAC1 FS" -> 3729 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses 3730 * DAPM. Therefore "DAC1 FS" is ignored for now. 3731 */ 3732 { "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" }, 3733 3734 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, 3735 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, 3736 3737 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, 3738 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, 3739 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, 3740 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3741 { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, 3742 { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, 3743 3744 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, 3745 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, 3746 3747 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, 3748 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, 3749 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, 3750 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3751 { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, 3752 3753 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, 3754 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, 3755 3756 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 3757 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 3758 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, 3759 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3760 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, 3761 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3762 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3763 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3764 3765 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 3766 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 3767 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, 3768 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3769 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, 3770 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3771 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3772 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3773 3774 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3775 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3776 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3777 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3778 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3779 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, 3780 3781 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3782 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3783 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3784 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3785 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3786 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, 3787 { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, 3788 3789 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3790 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3791 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3792 { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, 3793 { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, 3794 { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, 3795 { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, 3796 3797 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3798 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3799 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3800 { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, 3801 { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, 3802 { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, 3803 { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, 3804 3805 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3806 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3807 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3808 { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, 3809 { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, 3810 { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, 3811 { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, 3812 3813 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3814 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3815 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3816 { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, 3817 { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, 3818 { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, 3819 { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, 3820 3821 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3822 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3823 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3824 { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, 3825 { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, 3826 { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, 3827 { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, 3828 3829 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3830 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3831 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3832 { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, 3833 { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, 3834 { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, 3835 { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, 3836 3837 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, 3838 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, 3839 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, 3840 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, 3841 3842 { "OutBound2", NULL, "OB23 Bypass Mux" }, 3843 { "OutBound3", NULL, "OB23 Bypass Mux" }, 3844 { "OutBound4", NULL, "OB4 MIX" }, 3845 { "OutBound5", NULL, "OB5 MIX" }, 3846 { "OutBound6", NULL, "OB6 MIX" }, 3847 { "OutBound7", NULL, "OB7 MIX" }, 3848 3849 { "OB45", NULL, "OutBound4" }, 3850 { "OB45", NULL, "OutBound5" }, 3851 { "OB67", NULL, "OutBound6" }, 3852 { "OB67", NULL, "OutBound7" }, 3853 3854 { "IF1 DAC0", NULL, "AIF1RX" }, 3855 { "IF1 DAC1", NULL, "AIF1RX" }, 3856 { "IF1 DAC2", NULL, "AIF1RX" }, 3857 { "IF1 DAC3", NULL, "AIF1RX" }, 3858 { "IF1 DAC4", NULL, "AIF1RX" }, 3859 { "IF1 DAC5", NULL, "AIF1RX" }, 3860 { "IF1 DAC6", NULL, "AIF1RX" }, 3861 { "IF1 DAC7", NULL, "AIF1RX" }, 3862 { "IF1 DAC0", NULL, "I2S1" }, 3863 { "IF1 DAC1", NULL, "I2S1" }, 3864 { "IF1 DAC2", NULL, "I2S1" }, 3865 { "IF1 DAC3", NULL, "I2S1" }, 3866 { "IF1 DAC4", NULL, "I2S1" }, 3867 { "IF1 DAC5", NULL, "I2S1" }, 3868 { "IF1 DAC6", NULL, "I2S1" }, 3869 { "IF1 DAC7", NULL, "I2S1" }, 3870 3871 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, 3872 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, 3873 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, 3874 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, 3875 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, 3876 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, 3877 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, 3878 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, 3879 3880 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, 3881 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, 3882 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, 3883 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, 3884 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, 3885 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, 3886 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, 3887 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, 3888 3889 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, 3890 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, 3891 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, 3892 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, 3893 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, 3894 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, 3895 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, 3896 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, 3897 3898 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, 3899 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, 3900 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, 3901 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, 3902 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, 3903 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, 3904 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, 3905 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, 3906 3907 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, 3908 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, 3909 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, 3910 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, 3911 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, 3912 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, 3913 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, 3914 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, 3915 3916 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, 3917 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, 3918 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, 3919 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, 3920 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, 3921 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, 3922 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, 3923 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, 3924 3925 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, 3926 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, 3927 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, 3928 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, 3929 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, 3930 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, 3931 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, 3932 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, 3933 3934 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, 3935 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, 3936 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, 3937 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, 3938 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, 3939 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, 3940 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, 3941 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, 3942 3943 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, 3944 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, 3945 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, 3946 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, 3947 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, 3948 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, 3949 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, 3950 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, 3951 3952 { "IF2 DAC0", NULL, "AIF2RX" }, 3953 { "IF2 DAC1", NULL, "AIF2RX" }, 3954 { "IF2 DAC2", NULL, "AIF2RX" }, 3955 { "IF2 DAC3", NULL, "AIF2RX" }, 3956 { "IF2 DAC4", NULL, "AIF2RX" }, 3957 { "IF2 DAC5", NULL, "AIF2RX" }, 3958 { "IF2 DAC6", NULL, "AIF2RX" }, 3959 { "IF2 DAC7", NULL, "AIF2RX" }, 3960 { "IF2 DAC0", NULL, "I2S2" }, 3961 { "IF2 DAC1", NULL, "I2S2" }, 3962 { "IF2 DAC2", NULL, "I2S2" }, 3963 { "IF2 DAC3", NULL, "I2S2" }, 3964 { "IF2 DAC4", NULL, "I2S2" }, 3965 { "IF2 DAC5", NULL, "I2S2" }, 3966 { "IF2 DAC6", NULL, "I2S2" }, 3967 { "IF2 DAC7", NULL, "I2S2" }, 3968 3969 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, 3970 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, 3971 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, 3972 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, 3973 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, 3974 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, 3975 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, 3976 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, 3977 3978 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, 3979 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, 3980 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, 3981 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, 3982 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, 3983 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, 3984 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, 3985 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, 3986 3987 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, 3988 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, 3989 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, 3990 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, 3991 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, 3992 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, 3993 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, 3994 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, 3995 3996 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, 3997 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, 3998 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, 3999 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, 4000 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, 4001 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, 4002 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, 4003 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, 4004 4005 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, 4006 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, 4007 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, 4008 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, 4009 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, 4010 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, 4011 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, 4012 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, 4013 4014 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, 4015 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, 4016 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, 4017 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, 4018 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, 4019 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, 4020 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, 4021 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, 4022 4023 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, 4024 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, 4025 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, 4026 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, 4027 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, 4028 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, 4029 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, 4030 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, 4031 4032 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, 4033 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, 4034 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, 4035 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, 4036 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, 4037 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, 4038 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, 4039 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, 4040 4041 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, 4042 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, 4043 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, 4044 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, 4045 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, 4046 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, 4047 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, 4048 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, 4049 4050 { "IF3 DAC", NULL, "AIF3RX" }, 4051 { "IF3 DAC", NULL, "I2S3" }, 4052 4053 { "IF4 DAC", NULL, "AIF4RX" }, 4054 { "IF4 DAC", NULL, "I2S4" }, 4055 4056 { "IF3 DAC L", NULL, "IF3 DAC" }, 4057 { "IF3 DAC R", NULL, "IF3 DAC" }, 4058 4059 { "IF4 DAC L", NULL, "IF4 DAC" }, 4060 { "IF4 DAC R", NULL, "IF4 DAC" }, 4061 4062 { "SLB DAC0", NULL, "SLBRX" }, 4063 { "SLB DAC1", NULL, "SLBRX" }, 4064 { "SLB DAC2", NULL, "SLBRX" }, 4065 { "SLB DAC3", NULL, "SLBRX" }, 4066 { "SLB DAC4", NULL, "SLBRX" }, 4067 { "SLB DAC5", NULL, "SLBRX" }, 4068 { "SLB DAC6", NULL, "SLBRX" }, 4069 { "SLB DAC7", NULL, "SLBRX" }, 4070 { "SLB DAC0", NULL, "SLB" }, 4071 { "SLB DAC1", NULL, "SLB" }, 4072 { "SLB DAC2", NULL, "SLB" }, 4073 { "SLB DAC3", NULL, "SLB" }, 4074 { "SLB DAC4", NULL, "SLB" }, 4075 { "SLB DAC5", NULL, "SLB" }, 4076 { "SLB DAC6", NULL, "SLB" }, 4077 { "SLB DAC7", NULL, "SLB" }, 4078 4079 { "SLB DAC01", NULL, "SLB DAC0" }, 4080 { "SLB DAC01", NULL, "SLB DAC1" }, 4081 { "SLB DAC23", NULL, "SLB DAC2" }, 4082 { "SLB DAC23", NULL, "SLB DAC3" }, 4083 { "SLB DAC45", NULL, "SLB DAC4" }, 4084 { "SLB DAC45", NULL, "SLB DAC5" }, 4085 { "SLB DAC67", NULL, "SLB DAC6" }, 4086 { "SLB DAC67", NULL, "SLB DAC7" }, 4087 4088 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 4089 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 4090 { "ADDA1 Mux", "OB 67", "OB67" }, 4091 4092 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, 4093 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, 4094 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, 4095 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, 4096 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, 4097 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, 4098 4099 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, 4100 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, 4101 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, 4102 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, 4103 4104 { "DAC1 FS", NULL, "DAC1 MIXL" }, 4105 { "DAC1 FS", NULL, "DAC1 MIXR" }, 4106 4107 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" }, 4108 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" }, 4109 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4110 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4111 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, 4112 { "DAC2 L Mux", "OB 2", "OutBound2" }, 4113 4114 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" }, 4115 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" }, 4116 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4117 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4118 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, 4119 { "DAC2 R Mux", "OB 3", "OutBound3" }, 4120 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, 4121 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, 4122 4123 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" }, 4124 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" }, 4125 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4126 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4127 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, 4128 { "DAC3 L Mux", "OB 4", "OutBound4" }, 4129 4130 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" }, 4131 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" }, 4132 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4133 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4134 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, 4135 { "DAC3 R Mux", "OB 5", "OutBound5" }, 4136 4137 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 4138 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 4139 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4140 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4141 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, 4142 { "DAC4 L Mux", "OB 6", "OutBound6" }, 4143 4144 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 4145 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 4146 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4147 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4148 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, 4149 { "DAC4 R Mux", "OB 7", "OutBound7" }, 4150 4151 { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, 4152 { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, 4153 { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, 4154 { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, 4155 { "Sidetone Mux", "ADC1", "ADC 1" }, 4156 { "Sidetone Mux", "ADC2", "ADC 2" }, 4157 { "Sidetone Mux", NULL, "Sidetone Power" }, 4158 4159 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4160 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4161 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4162 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, 4163 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 4164 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4165 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4166 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4167 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, 4168 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 4169 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 4170 4171 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4172 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4173 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4174 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, 4175 { "Mono DAC MIXL", NULL, "dac mono2 left filter" }, 4176 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4177 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4178 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4179 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4180 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, 4181 { "Mono DAC MIXR", NULL, "dac mono2 right filter" }, 4182 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4183 4184 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4185 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4186 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, 4187 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, 4188 { "DD1 MIXL", NULL, "dac mono3 left filter" }, 4189 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4190 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4191 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4192 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, 4193 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, 4194 { "DD1 MIXR", NULL, "dac mono3 right filter" }, 4195 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4196 4197 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4198 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4199 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, 4200 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, 4201 { "DD2 MIXL", NULL, "dac mono4 left filter" }, 4202 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4203 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4204 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4205 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, 4206 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, 4207 { "DD2 MIXR", NULL, "dac mono4 right filter" }, 4208 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4209 4210 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, 4211 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, 4212 { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, 4213 { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, 4214 { "DD1 MIX", NULL, "DD1 MIXL" }, 4215 { "DD1 MIX", NULL, "DD1 MIXR" }, 4216 { "DD2 MIX", NULL, "DD2 MIXL" }, 4217 { "DD2 MIX", NULL, "DD2 MIXR" }, 4218 4219 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, 4220 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, 4221 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, 4222 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, 4223 4224 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 4225 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 4226 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, 4227 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, 4228 4229 { "DAC 1", NULL, "DAC12 SRC Mux" }, 4230 { "DAC 2", NULL, "DAC12 SRC Mux" }, 4231 { "DAC 3", NULL, "DAC3 SRC Mux" }, 4232 4233 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4234 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4235 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, 4236 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, 4237 { "PDM1 L Mux", NULL, "PDM1 Power" }, 4238 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4239 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4240 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, 4241 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, 4242 { "PDM1 R Mux", NULL, "PDM1 Power" }, 4243 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4244 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4245 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, 4246 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, 4247 { "PDM2 L Mux", NULL, "PDM2 Power" }, 4248 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4249 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4250 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, 4251 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, 4252 { "PDM2 R Mux", NULL, "PDM2 Power" }, 4253 4254 { "LOUT1 amp", NULL, "DAC 1" }, 4255 { "LOUT2 amp", NULL, "DAC 2" }, 4256 { "LOUT3 amp", NULL, "DAC 3" }, 4257 4258 { "LOUT1 vref", NULL, "LOUT1 amp" }, 4259 { "LOUT2 vref", NULL, "LOUT2 amp" }, 4260 { "LOUT3 vref", NULL, "LOUT3 amp" }, 4261 4262 { "LOUT1", NULL, "LOUT1 vref" }, 4263 { "LOUT2", NULL, "LOUT2 vref" }, 4264 { "LOUT3", NULL, "LOUT3 vref" }, 4265 4266 { "PDM1L", NULL, "PDM1 L Mux" }, 4267 { "PDM1R", NULL, "PDM1 R Mux" }, 4268 { "PDM2L", NULL, "PDM2 L Mux" }, 4269 { "PDM2R", NULL, "PDM2 R Mux" }, 4270 }; 4271 4272 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { 4273 { "DMIC L2", NULL, "DMIC1 power" }, 4274 { "DMIC R2", NULL, "DMIC1 power" }, 4275 }; 4276 4277 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { 4278 { "DMIC L2", NULL, "DMIC2 power" }, 4279 { "DMIC R2", NULL, "DMIC2 power" }, 4280 }; 4281 4282 static int rt5677_hw_params(struct snd_pcm_substream *substream, 4283 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 4284 { 4285 struct snd_soc_component *component = dai->component; 4286 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4287 unsigned int val_len = 0, val_clk, mask_clk; 4288 int pre_div, bclk_ms, frame_size; 4289 4290 rt5677->lrck[dai->id] = params_rate(params); 4291 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 4292 if (pre_div < 0) { 4293 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", 4294 rt5677->sysclk, rt5677->lrck[dai->id]); 4295 return -EINVAL; 4296 } 4297 frame_size = snd_soc_params_to_frame_size(params); 4298 if (frame_size < 0) { 4299 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 4300 return -EINVAL; 4301 } 4302 bclk_ms = frame_size > 32; 4303 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); 4304 4305 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 4306 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); 4307 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 4308 bclk_ms, pre_div, dai->id); 4309 4310 switch (params_width(params)) { 4311 case 16: 4312 break; 4313 case 20: 4314 val_len |= RT5677_I2S_DL_20; 4315 break; 4316 case 24: 4317 val_len |= RT5677_I2S_DL_24; 4318 break; 4319 case 8: 4320 val_len |= RT5677_I2S_DL_8; 4321 break; 4322 default: 4323 return -EINVAL; 4324 } 4325 4326 switch (dai->id) { 4327 case RT5677_AIF1: 4328 mask_clk = RT5677_I2S_PD1_MASK; 4329 val_clk = pre_div << RT5677_I2S_PD1_SFT; 4330 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4331 RT5677_I2S_DL_MASK, val_len); 4332 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4333 mask_clk, val_clk); 4334 break; 4335 case RT5677_AIF2: 4336 mask_clk = RT5677_I2S_PD2_MASK; 4337 val_clk = pre_div << RT5677_I2S_PD2_SFT; 4338 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4339 RT5677_I2S_DL_MASK, val_len); 4340 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4341 mask_clk, val_clk); 4342 break; 4343 case RT5677_AIF3: 4344 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; 4345 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | 4346 pre_div << RT5677_I2S_PD3_SFT; 4347 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4348 RT5677_I2S_DL_MASK, val_len); 4349 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4350 mask_clk, val_clk); 4351 break; 4352 case RT5677_AIF4: 4353 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; 4354 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | 4355 pre_div << RT5677_I2S_PD4_SFT; 4356 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4357 RT5677_I2S_DL_MASK, val_len); 4358 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4359 mask_clk, val_clk); 4360 break; 4361 default: 4362 break; 4363 } 4364 4365 return 0; 4366 } 4367 4368 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 4369 { 4370 struct snd_soc_component *component = dai->component; 4371 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4372 unsigned int reg_val = 0; 4373 4374 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 4375 case SND_SOC_DAIFMT_CBP_CFP: 4376 rt5677->master[dai->id] = 1; 4377 break; 4378 case SND_SOC_DAIFMT_CBC_CFC: 4379 reg_val |= RT5677_I2S_MS_S; 4380 rt5677->master[dai->id] = 0; 4381 break; 4382 default: 4383 return -EINVAL; 4384 } 4385 4386 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 4387 case SND_SOC_DAIFMT_NB_NF: 4388 break; 4389 case SND_SOC_DAIFMT_IB_NF: 4390 reg_val |= RT5677_I2S_BP_INV; 4391 break; 4392 default: 4393 return -EINVAL; 4394 } 4395 4396 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 4397 case SND_SOC_DAIFMT_I2S: 4398 break; 4399 case SND_SOC_DAIFMT_LEFT_J: 4400 reg_val |= RT5677_I2S_DF_LEFT; 4401 break; 4402 case SND_SOC_DAIFMT_DSP_A: 4403 reg_val |= RT5677_I2S_DF_PCM_A; 4404 break; 4405 case SND_SOC_DAIFMT_DSP_B: 4406 reg_val |= RT5677_I2S_DF_PCM_B; 4407 break; 4408 default: 4409 return -EINVAL; 4410 } 4411 4412 switch (dai->id) { 4413 case RT5677_AIF1: 4414 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4415 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4416 RT5677_I2S_DF_MASK, reg_val); 4417 break; 4418 case RT5677_AIF2: 4419 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4420 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4421 RT5677_I2S_DF_MASK, reg_val); 4422 break; 4423 case RT5677_AIF3: 4424 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4425 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4426 RT5677_I2S_DF_MASK, reg_val); 4427 break; 4428 case RT5677_AIF4: 4429 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4430 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4431 RT5677_I2S_DF_MASK, reg_val); 4432 break; 4433 default: 4434 break; 4435 } 4436 4437 4438 return 0; 4439 } 4440 4441 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, 4442 int clk_id, unsigned int freq, int dir) 4443 { 4444 struct snd_soc_component *component = dai->component; 4445 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4446 unsigned int reg_val = 0; 4447 4448 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) 4449 return 0; 4450 4451 switch (clk_id) { 4452 case RT5677_SCLK_S_MCLK: 4453 reg_val |= RT5677_SCLK_SRC_MCLK; 4454 break; 4455 case RT5677_SCLK_S_PLL1: 4456 reg_val |= RT5677_SCLK_SRC_PLL1; 4457 break; 4458 case RT5677_SCLK_S_RCCLK: 4459 reg_val |= RT5677_SCLK_SRC_RCCLK; 4460 break; 4461 default: 4462 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 4463 return -EINVAL; 4464 } 4465 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4466 RT5677_SCLK_SRC_MASK, reg_val); 4467 rt5677->sysclk = freq; 4468 rt5677->sysclk_src = clk_id; 4469 4470 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 4471 4472 return 0; 4473 } 4474 4475 /** 4476 * rt5677_pll_calc - Calcualte PLL M/N/K code. 4477 * @freq_in: external clock provided to codec. 4478 * @freq_out: target clock which codec works on. 4479 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. 4480 * 4481 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. 4482 * 4483 * Returns 0 for success or negative error code. 4484 */ 4485 static int rt5677_pll_calc(const unsigned int freq_in, 4486 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 4487 { 4488 if (RT5677_PLL_INP_MIN > freq_in) 4489 return -EINVAL; 4490 4491 return rl6231_pll_calc(freq_in, freq_out, pll_code); 4492 } 4493 4494 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 4495 unsigned int freq_in, unsigned int freq_out) 4496 { 4497 struct snd_soc_component *component = dai->component; 4498 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4499 struct rl6231_pll_code pll_code; 4500 int ret; 4501 4502 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 4503 freq_out == rt5677->pll_out) 4504 return 0; 4505 4506 if (!freq_in || !freq_out) { 4507 dev_dbg(component->dev, "PLL disabled\n"); 4508 4509 rt5677->pll_in = 0; 4510 rt5677->pll_out = 0; 4511 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4512 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); 4513 return 0; 4514 } 4515 4516 switch (source) { 4517 case RT5677_PLL1_S_MCLK: 4518 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4519 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); 4520 break; 4521 case RT5677_PLL1_S_BCLK1: 4522 case RT5677_PLL1_S_BCLK2: 4523 case RT5677_PLL1_S_BCLK3: 4524 case RT5677_PLL1_S_BCLK4: 4525 switch (dai->id) { 4526 case RT5677_AIF1: 4527 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4528 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); 4529 break; 4530 case RT5677_AIF2: 4531 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4532 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); 4533 break; 4534 case RT5677_AIF3: 4535 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4536 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); 4537 break; 4538 case RT5677_AIF4: 4539 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4540 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); 4541 break; 4542 default: 4543 break; 4544 } 4545 break; 4546 default: 4547 dev_err(component->dev, "Unknown PLL source %d\n", source); 4548 return -EINVAL; 4549 } 4550 4551 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); 4552 if (ret < 0) { 4553 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 4554 return ret; 4555 } 4556 4557 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", 4558 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 4559 pll_code.n_code, pll_code.k_code); 4560 4561 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 4562 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); 4563 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 4564 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT) | 4565 (pll_code.m_bp << RT5677_PLL_M_BP_SFT)); 4566 4567 rt5677->pll_in = freq_in; 4568 rt5677->pll_out = freq_out; 4569 rt5677->pll_src = source; 4570 4571 return 0; 4572 } 4573 4574 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 4575 unsigned int rx_mask, int slots, int slot_width) 4576 { 4577 struct snd_soc_component *component = dai->component; 4578 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4579 unsigned int val = 0, slot_width_25 = 0; 4580 4581 if (rx_mask || tx_mask) 4582 val |= (1 << 12); 4583 4584 switch (slots) { 4585 case 4: 4586 val |= (1 << 10); 4587 break; 4588 case 6: 4589 val |= (2 << 10); 4590 break; 4591 case 8: 4592 val |= (3 << 10); 4593 break; 4594 case 2: 4595 default: 4596 break; 4597 } 4598 4599 switch (slot_width) { 4600 case 20: 4601 val |= (1 << 8); 4602 break; 4603 case 25: 4604 slot_width_25 = 0x8080; 4605 fallthrough; 4606 case 24: 4607 val |= (2 << 8); 4608 break; 4609 case 32: 4610 val |= (3 << 8); 4611 break; 4612 case 16: 4613 default: 4614 break; 4615 } 4616 4617 switch (dai->id) { 4618 case RT5677_AIF1: 4619 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, 4620 val); 4621 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, 4622 slot_width_25); 4623 break; 4624 case RT5677_AIF2: 4625 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, 4626 val); 4627 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, 4628 slot_width_25); 4629 break; 4630 default: 4631 break; 4632 } 4633 4634 return 0; 4635 } 4636 4637 static int rt5677_set_bias_level(struct snd_soc_component *component, 4638 enum snd_soc_bias_level level) 4639 { 4640 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4641 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 4642 enum snd_soc_bias_level prev_bias = snd_soc_dapm_get_bias_level(dapm); 4643 4644 switch (level) { 4645 case SND_SOC_BIAS_ON: 4646 break; 4647 4648 case SND_SOC_BIAS_PREPARE: 4649 if (prev_bias == SND_SOC_BIAS_STANDBY) { 4650 4651 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4652 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 4653 5 << RT5677_LDO1_SEL_SFT | 4654 5 << RT5677_LDO2_SEL_SFT); 4655 regmap_update_bits(rt5677->regmap, 4656 RT5677_PR_BASE + RT5677_BIAS_CUR4, 4657 0x0f00, 0x0f00); 4658 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4659 RT5677_PWR_FV1 | RT5677_PWR_FV2 | 4660 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4661 RT5677_PWR_BG | RT5677_PWR_VREF2, 4662 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4663 RT5677_PWR_BG | RT5677_PWR_VREF2); 4664 rt5677->is_vref_slow = false; 4665 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4666 RT5677_PWR_CORE, RT5677_PWR_CORE); 4667 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4668 0x1, 0x1); 4669 } 4670 break; 4671 4672 case SND_SOC_BIAS_STANDBY: 4673 if (prev_bias == SND_SOC_BIAS_OFF && 4674 rt5677->dsp_vad_en_request) { 4675 /* Re-enable the DSP if it was turned off at suspend */ 4676 rt5677->dsp_vad_en = true; 4677 /* The delay is to wait for MCLK */ 4678 schedule_delayed_work(&rt5677->dsp_work, 4679 msecs_to_jiffies(1000)); 4680 } 4681 break; 4682 4683 case SND_SOC_BIAS_OFF: 4684 flush_delayed_work(&rt5677->dsp_work); 4685 if (rt5677->is_dsp_mode) { 4686 /* Turn off the DSP before suspend */ 4687 rt5677->dsp_vad_en = false; 4688 schedule_delayed_work(&rt5677->dsp_work, 0); 4689 flush_delayed_work(&rt5677->dsp_work); 4690 } 4691 4692 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 4693 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 4694 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 4695 2 << RT5677_LDO1_SEL_SFT | 4696 2 << RT5677_LDO2_SEL_SFT); 4697 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4698 RT5677_PWR_CORE, 0); 4699 regmap_update_bits(rt5677->regmap, 4700 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4701 4702 if (rt5677->dsp_vad_en) 4703 rt5677_set_dsp_vad(component, true); 4704 break; 4705 4706 default: 4707 break; 4708 } 4709 4710 return 0; 4711 } 4712 4713 static int rt5677_update_gpio_bits(struct rt5677_priv *rt5677, unsigned offset, int m, int v) 4714 { 4715 unsigned int bank = offset / 5; 4716 unsigned int shift = (offset % 5) * 3; 4717 unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2; 4718 4719 return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift); 4720 } 4721 4722 #ifdef CONFIG_GPIOLIB 4723 static int rt5677_gpio_set(struct gpio_chip *chip, unsigned int offset, 4724 int value) 4725 { 4726 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4727 int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO; 4728 int m = RT5677_GPIOx_OUT_MASK; 4729 4730 return rt5677_update_gpio_bits(rt5677, offset, m, level); 4731 } 4732 4733 static int rt5677_gpio_direction_out(struct gpio_chip *chip, 4734 unsigned offset, int value) 4735 { 4736 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4737 int level = value ? RT5677_GPIOx_OUT_HI : RT5677_GPIOx_OUT_LO; 4738 int m = RT5677_GPIOx_DIR_MASK | RT5677_GPIOx_OUT_MASK; 4739 int v = RT5677_GPIOx_DIR_OUT | level; 4740 4741 return rt5677_update_gpio_bits(rt5677, offset, m, v); 4742 } 4743 4744 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) 4745 { 4746 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4747 int value, ret; 4748 4749 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); 4750 if (ret < 0) 4751 return ret; 4752 4753 return (value & (0x1 << offset)) >> offset; 4754 } 4755 4756 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 4757 { 4758 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4759 int m = RT5677_GPIOx_DIR_MASK; 4760 int v = RT5677_GPIOx_DIR_IN; 4761 4762 return rt5677_update_gpio_bits(rt5677, offset, m, v); 4763 } 4764 4765 static int rt5677_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 4766 { 4767 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4768 unsigned int shift = RT5677_GPIOx_DIR_SFT + (offset % 5) * 3; 4769 unsigned int bank = offset / 5; 4770 unsigned int reg = bank ? RT5677_GPIO_CTRL3 : RT5677_GPIO_CTRL2; 4771 int ret; 4772 4773 ret = regmap_test_bits(rt5677->regmap, reg, BIT(shift)); 4774 if (ret < 0) 4775 return ret; 4776 4777 return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 4778 } 4779 4780 /* 4781 * Configures the GPIO as 4782 * 0 - floating 4783 * 1 - pull down 4784 * 2 - pull up 4785 */ 4786 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4787 int value) 4788 { 4789 int shift; 4790 4791 switch (offset) { 4792 case RT5677_GPIO1 ... RT5677_GPIO2: 4793 shift = 2 * (1 - offset); 4794 regmap_update_bits(rt5677->regmap, 4795 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, 4796 0x3 << shift, 4797 (value & 0x3) << shift); 4798 break; 4799 4800 case RT5677_GPIO3 ... RT5677_GPIO6: 4801 shift = 2 * (9 - offset); 4802 regmap_update_bits(rt5677->regmap, 4803 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, 4804 0x3 << shift, 4805 (value & 0x3) << shift); 4806 break; 4807 4808 default: 4809 break; 4810 } 4811 } 4812 4813 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) 4814 { 4815 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4816 int irq; 4817 4818 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || 4819 (rt5677->pdata.jd1_gpio == 2 && 4820 offset == RT5677_GPIO2) || 4821 (rt5677->pdata.jd1_gpio == 3 && 4822 offset == RT5677_GPIO3)) { 4823 irq = RT5677_IRQ_JD1; 4824 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || 4825 (rt5677->pdata.jd2_gpio == 2 && 4826 offset == RT5677_GPIO5) || 4827 (rt5677->pdata.jd2_gpio == 3 && 4828 offset == RT5677_GPIO6)) { 4829 irq = RT5677_IRQ_JD2; 4830 } else if ((rt5677->pdata.jd3_gpio == 1 && 4831 offset == RT5677_GPIO4) || 4832 (rt5677->pdata.jd3_gpio == 2 && 4833 offset == RT5677_GPIO5) || 4834 (rt5677->pdata.jd3_gpio == 3 && 4835 offset == RT5677_GPIO6)) { 4836 irq = RT5677_IRQ_JD3; 4837 } else { 4838 return -ENXIO; 4839 } 4840 4841 return irq_create_mapping(rt5677->domain, irq); 4842 } 4843 4844 static const struct gpio_chip rt5677_template_chip = { 4845 .label = RT5677_DRV_NAME, 4846 .owner = THIS_MODULE, 4847 .get_direction = rt5677_gpio_get_direction, 4848 .direction_output = rt5677_gpio_direction_out, 4849 .set = rt5677_gpio_set, 4850 .direction_input = rt5677_gpio_direction_in, 4851 .get = rt5677_gpio_get, 4852 .to_irq = rt5677_to_irq, 4853 .can_sleep = 1, 4854 }; 4855 4856 static void rt5677_init_gpio(struct i2c_client *i2c) 4857 { 4858 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4859 int ret; 4860 4861 rt5677->gpio_chip = rt5677_template_chip; 4862 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; 4863 rt5677->gpio_chip.parent = &i2c->dev; 4864 rt5677->gpio_chip.base = -1; 4865 4866 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); 4867 if (ret != 0) 4868 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); 4869 } 4870 4871 static void rt5677_free_gpio(struct i2c_client *i2c) 4872 { 4873 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4874 4875 gpiochip_remove(&rt5677->gpio_chip); 4876 } 4877 #else 4878 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4879 int value) 4880 { 4881 } 4882 4883 static void rt5677_init_gpio(struct i2c_client *i2c) 4884 { 4885 } 4886 4887 static void rt5677_free_gpio(struct i2c_client *i2c) 4888 { 4889 } 4890 #endif 4891 4892 static int rt5677_probe(struct snd_soc_component *component) 4893 { 4894 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 4895 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4896 int i; 4897 4898 rt5677->component = component; 4899 4900 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4901 snd_soc_dapm_add_routes(dapm, 4902 rt5677_dmic2_clk_2, 4903 ARRAY_SIZE(rt5677_dmic2_clk_2)); 4904 } else { /*use dmic1 clock by default*/ 4905 snd_soc_dapm_add_routes(dapm, 4906 rt5677_dmic2_clk_1, 4907 ARRAY_SIZE(rt5677_dmic2_clk_1)); 4908 } 4909 4910 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF); 4911 4912 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4913 ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020); 4914 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 4915 RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO); 4916 4917 for (i = 0; i < RT5677_GPIO_NUM; i++) 4918 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); 4919 4920 mutex_init(&rt5677->dsp_cmd_lock); 4921 mutex_init(&rt5677->dsp_pri_lock); 4922 4923 return 0; 4924 } 4925 4926 static void rt5677_remove(struct snd_soc_component *component) 4927 { 4928 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4929 4930 cancel_delayed_work_sync(&rt5677->dsp_work); 4931 4932 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4933 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4934 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4935 } 4936 4937 #ifdef CONFIG_PM 4938 static int rt5677_suspend(struct snd_soc_component *component) 4939 { 4940 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4941 4942 if (rt5677->irq) { 4943 cancel_delayed_work_sync(&rt5677->resume_irq_check); 4944 disable_irq(rt5677->irq); 4945 } 4946 4947 if (!rt5677->dsp_vad_en) { 4948 regcache_cache_only(rt5677->regmap, true); 4949 regcache_mark_dirty(rt5677->regmap); 4950 4951 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4952 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4953 } 4954 4955 return 0; 4956 } 4957 4958 static int rt5677_resume(struct snd_soc_component *component) 4959 { 4960 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4961 4962 if (!rt5677->dsp_vad_en) { 4963 rt5677->pll_src = 0; 4964 rt5677->pll_in = 0; 4965 rt5677->pll_out = 0; 4966 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); 4967 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 4968 if (rt5677->pow_ldo2 || rt5677->reset_pin) 4969 msleep(10); 4970 4971 regcache_cache_only(rt5677->regmap, false); 4972 regcache_sync(rt5677->regmap); 4973 } 4974 4975 if (rt5677->irq) { 4976 enable_irq(rt5677->irq); 4977 schedule_delayed_work(&rt5677->resume_irq_check, 0); 4978 } 4979 4980 return 0; 4981 } 4982 #else 4983 #define rt5677_suspend NULL 4984 #define rt5677_resume NULL 4985 #endif 4986 4987 static int rt5677_read(void *context, unsigned int reg, unsigned int *val) 4988 { 4989 struct i2c_client *client = context; 4990 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4991 4992 if (rt5677->is_dsp_mode) { 4993 if (reg > 0xff) { 4994 scoped_guard(mutex, &rt5677->dsp_pri_lock) { 4995 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4996 reg & 0xff); 4997 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); 4998 } 4999 } else { 5000 rt5677_dsp_mode_i2c_read(rt5677, reg, val); 5001 } 5002 } else { 5003 regmap_read(rt5677->regmap_physical, reg, val); 5004 } 5005 5006 return 0; 5007 } 5008 5009 static int rt5677_write(void *context, unsigned int reg, unsigned int val) 5010 { 5011 struct i2c_client *client = context; 5012 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 5013 5014 if (rt5677->is_dsp_mode) { 5015 if (reg > 0xff) { 5016 scoped_guard(mutex, &rt5677->dsp_pri_lock) { 5017 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 5018 reg & 0xff); 5019 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, 5020 val); 5021 } 5022 } else { 5023 rt5677_dsp_mode_i2c_write(rt5677, reg, val); 5024 } 5025 } else { 5026 regmap_write(rt5677->regmap_physical, reg, val); 5027 } 5028 5029 return 0; 5030 } 5031 5032 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 5033 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 5034 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 5035 5036 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = { 5037 .hw_params = rt5677_hw_params, 5038 .set_fmt = rt5677_set_dai_fmt, 5039 .set_sysclk = rt5677_set_dai_sysclk, 5040 .set_pll = rt5677_set_dai_pll, 5041 .set_tdm_slot = rt5677_set_tdm_slot, 5042 }; 5043 5044 static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = { 5045 .set_sysclk = rt5677_set_dai_sysclk, 5046 .set_pll = rt5677_set_dai_pll, 5047 }; 5048 5049 static struct snd_soc_dai_driver rt5677_dai[] = { 5050 { 5051 .name = "rt5677-aif1", 5052 .id = RT5677_AIF1, 5053 .playback = { 5054 .stream_name = "AIF1 Playback", 5055 .channels_min = 1, 5056 .channels_max = 2, 5057 .rates = RT5677_STEREO_RATES, 5058 .formats = RT5677_FORMATS, 5059 }, 5060 .capture = { 5061 .stream_name = "AIF1 Capture", 5062 .channels_min = 1, 5063 .channels_max = 2, 5064 .rates = RT5677_STEREO_RATES, 5065 .formats = RT5677_FORMATS, 5066 }, 5067 .ops = &rt5677_aif_dai_ops, 5068 }, 5069 { 5070 .name = "rt5677-aif2", 5071 .id = RT5677_AIF2, 5072 .playback = { 5073 .stream_name = "AIF2 Playback", 5074 .channels_min = 1, 5075 .channels_max = 2, 5076 .rates = RT5677_STEREO_RATES, 5077 .formats = RT5677_FORMATS, 5078 }, 5079 .capture = { 5080 .stream_name = "AIF2 Capture", 5081 .channels_min = 1, 5082 .channels_max = 2, 5083 .rates = RT5677_STEREO_RATES, 5084 .formats = RT5677_FORMATS, 5085 }, 5086 .ops = &rt5677_aif_dai_ops, 5087 }, 5088 { 5089 .name = "rt5677-aif3", 5090 .id = RT5677_AIF3, 5091 .playback = { 5092 .stream_name = "AIF3 Playback", 5093 .channels_min = 1, 5094 .channels_max = 2, 5095 .rates = RT5677_STEREO_RATES, 5096 .formats = RT5677_FORMATS, 5097 }, 5098 .capture = { 5099 .stream_name = "AIF3 Capture", 5100 .channels_min = 1, 5101 .channels_max = 2, 5102 .rates = RT5677_STEREO_RATES, 5103 .formats = RT5677_FORMATS, 5104 }, 5105 .ops = &rt5677_aif_dai_ops, 5106 }, 5107 { 5108 .name = "rt5677-aif4", 5109 .id = RT5677_AIF4, 5110 .playback = { 5111 .stream_name = "AIF4 Playback", 5112 .channels_min = 1, 5113 .channels_max = 2, 5114 .rates = RT5677_STEREO_RATES, 5115 .formats = RT5677_FORMATS, 5116 }, 5117 .capture = { 5118 .stream_name = "AIF4 Capture", 5119 .channels_min = 1, 5120 .channels_max = 2, 5121 .rates = RT5677_STEREO_RATES, 5122 .formats = RT5677_FORMATS, 5123 }, 5124 .ops = &rt5677_aif_dai_ops, 5125 }, 5126 { 5127 .name = "rt5677-slimbus", 5128 .id = RT5677_AIF5, 5129 .playback = { 5130 .stream_name = "SLIMBus Playback", 5131 .channels_min = 1, 5132 .channels_max = 2, 5133 .rates = RT5677_STEREO_RATES, 5134 .formats = RT5677_FORMATS, 5135 }, 5136 .capture = { 5137 .stream_name = "SLIMBus Capture", 5138 .channels_min = 1, 5139 .channels_max = 2, 5140 .rates = RT5677_STEREO_RATES, 5141 .formats = RT5677_FORMATS, 5142 }, 5143 .ops = &rt5677_aif_dai_ops, 5144 }, 5145 { 5146 .name = "rt5677-dspbuffer", 5147 .id = RT5677_DSPBUFF, 5148 .capture = { 5149 .stream_name = "DSP Buffer", 5150 .channels_min = 1, 5151 .channels_max = 1, 5152 .rates = SNDRV_PCM_RATE_16000, 5153 .formats = SNDRV_PCM_FMTBIT_S16_LE, 5154 }, 5155 .ops = &rt5677_dsp_dai_ops, 5156 }, 5157 }; 5158 5159 static const struct snd_soc_component_driver soc_component_dev_rt5677 = { 5160 .name = RT5677_DRV_NAME, 5161 .probe = rt5677_probe, 5162 .remove = rt5677_remove, 5163 .suspend = rt5677_suspend, 5164 .resume = rt5677_resume, 5165 .set_bias_level = rt5677_set_bias_level, 5166 .controls = rt5677_snd_controls, 5167 .num_controls = ARRAY_SIZE(rt5677_snd_controls), 5168 .dapm_widgets = rt5677_dapm_widgets, 5169 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), 5170 .dapm_routes = rt5677_dapm_routes, 5171 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 5172 .use_pmdown_time = 1, 5173 .endianness = 1, 5174 }; 5175 5176 static const struct regmap_config rt5677_regmap_physical = { 5177 .name = "physical", 5178 .reg_bits = 8, 5179 .val_bits = 16, 5180 5181 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5182 RT5677_PR_SPACING), 5183 .readable_reg = rt5677_readable_register, 5184 5185 .cache_type = REGCACHE_NONE, 5186 .ranges = rt5677_ranges, 5187 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5188 }; 5189 5190 static const struct regmap_config rt5677_regmap = { 5191 .reg_bits = 8, 5192 .val_bits = 16, 5193 5194 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5195 RT5677_PR_SPACING), 5196 5197 .volatile_reg = rt5677_volatile_register, 5198 .readable_reg = rt5677_readable_register, 5199 .reg_read = rt5677_read, 5200 .reg_write = rt5677_write, 5201 5202 .cache_type = REGCACHE_RBTREE, 5203 .reg_defaults = rt5677_reg, 5204 .num_reg_defaults = ARRAY_SIZE(rt5677_reg), 5205 .ranges = rt5677_ranges, 5206 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5207 }; 5208 5209 static const struct of_device_id rt5677_of_match[] = { 5210 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 }, 5211 { } 5212 }; 5213 MODULE_DEVICE_TABLE(of, rt5677_of_match); 5214 5215 static const struct acpi_device_id rt5677_acpi_match[] = { 5216 { "10EC5677", RT5677 }, 5217 { "RT5677CE", RT5677 }, 5218 { "10EC5677", RT5677 }, 5219 { } 5220 }; 5221 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match); 5222 5223 static const struct i2c_device_id rt5677_i2c_id[] = { 5224 { .name = "rt5677", .driver_data = RT5677 }, 5225 { } 5226 }; 5227 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); 5228 5229 static void rt5677_read_device_properties(struct rt5677_priv *rt5677, 5230 struct device *dev) 5231 { 5232 u32 val; 5233 5234 rt5677->pdata.in1_diff = 5235 device_property_read_bool(dev, "IN1") || 5236 device_property_read_bool(dev, "realtek,in1-differential"); 5237 5238 rt5677->pdata.in2_diff = 5239 device_property_read_bool(dev, "IN2") || 5240 device_property_read_bool(dev, "realtek,in2-differential"); 5241 5242 rt5677->pdata.lout1_diff = 5243 device_property_read_bool(dev, "OUT1") || 5244 device_property_read_bool(dev, "realtek,lout1-differential"); 5245 5246 rt5677->pdata.lout2_diff = 5247 device_property_read_bool(dev, "OUT2") || 5248 device_property_read_bool(dev, "realtek,lout2-differential"); 5249 5250 rt5677->pdata.lout3_diff = 5251 device_property_read_bool(dev, "OUT3") || 5252 device_property_read_bool(dev, "realtek,lout3-differential"); 5253 5254 device_property_read_u8_array(dev, "realtek,gpio-config", 5255 rt5677->pdata.gpio_config, 5256 RT5677_GPIO_NUM); 5257 5258 if (!device_property_read_u32(dev, "DCLK", &val) || 5259 !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val)) 5260 rt5677->pdata.dmic2_clk_pin = val; 5261 5262 if (!device_property_read_u32(dev, "JD1", &val) || 5263 !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) 5264 rt5677->pdata.jd1_gpio = val; 5265 5266 if (!device_property_read_u32(dev, "JD2", &val) || 5267 !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) 5268 rt5677->pdata.jd2_gpio = val; 5269 5270 if (!device_property_read_u32(dev, "JD3", &val) || 5271 !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) 5272 rt5677->pdata.jd3_gpio = val; 5273 } 5274 5275 struct rt5677_irq_desc { 5276 unsigned int enable_mask; 5277 unsigned int status_mask; 5278 unsigned int polarity_mask; 5279 }; 5280 5281 static const struct rt5677_irq_desc rt5677_irq_descs[] = { 5282 [RT5677_IRQ_JD1] = { 5283 .enable_mask = RT5677_EN_IRQ_GPIO_JD1, 5284 .status_mask = RT5677_STA_GPIO_JD1, 5285 .polarity_mask = RT5677_INV_GPIO_JD1, 5286 }, 5287 [RT5677_IRQ_JD2] = { 5288 .enable_mask = RT5677_EN_IRQ_GPIO_JD2, 5289 .status_mask = RT5677_STA_GPIO_JD2, 5290 .polarity_mask = RT5677_INV_GPIO_JD2, 5291 }, 5292 [RT5677_IRQ_JD3] = { 5293 .enable_mask = RT5677_EN_IRQ_GPIO_JD3, 5294 .status_mask = RT5677_STA_GPIO_JD3, 5295 .polarity_mask = RT5677_INV_GPIO_JD3, 5296 }, 5297 }; 5298 5299 static bool rt5677_check_hotword(struct rt5677_priv *rt5677) 5300 { 5301 int reg_gpio; 5302 5303 if (!rt5677->is_dsp_mode) 5304 return false; 5305 5306 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio)) 5307 return false; 5308 5309 /* Firmware sets GPIO1 pin to be GPIO1 after hotword is detected */ 5310 if ((reg_gpio & RT5677_GPIO1_PIN_MASK) == RT5677_GPIO1_PIN_IRQ) 5311 return false; 5312 5313 /* Set GPIO1 pin back to be IRQ output for jack detect */ 5314 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5315 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5316 5317 rt5677_spi_hotword_detected(); 5318 return true; 5319 } 5320 5321 static irqreturn_t rt5677_irq(int unused, void *data) 5322 { 5323 struct rt5677_priv *rt5677 = data; 5324 int ret, loop, i, reg_irq, virq; 5325 bool irq_fired = false; 5326 5327 mutex_lock(&rt5677->irq_lock); 5328 5329 /* 5330 * Loop to handle interrupts until the last i2c read shows no pending 5331 * irqs. The interrupt line is shared by multiple interrupt sources. 5332 * After the regmap_read() below, a new interrupt source line may 5333 * become high before the regmap_write() finishes, so there isn't a 5334 * rising edge on the shared interrupt line for the new interrupt. Thus, 5335 * the loop is needed to avoid missing irqs. 5336 * 5337 * A safeguard of 20 loops is used to avoid hanging in the irq handler 5338 * if there is something wrong with the interrupt status update. The 5339 * interrupt sources here are audio jack plug/unplug events which 5340 * shouldn't happen at a high frequency for a long period of time. 5341 * Empirically, more than 3 loops have never been seen. 5342 */ 5343 for (loop = 0; loop < 20; loop++) { 5344 /* Read interrupt status */ 5345 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq); 5346 if (ret) { 5347 dev_err(rt5677->dev, "failed reading IRQ status: %d\n", 5348 ret); 5349 goto exit; 5350 } 5351 5352 irq_fired = false; 5353 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5354 if (reg_irq & rt5677_irq_descs[i].status_mask) { 5355 irq_fired = true; 5356 virq = irq_find_mapping(rt5677->domain, i); 5357 if (virq) 5358 handle_nested_irq(virq); 5359 5360 /* Clear the interrupt by flipping the polarity 5361 * of the interrupt source line that fired 5362 */ 5363 reg_irq ^= rt5677_irq_descs[i].polarity_mask; 5364 } 5365 } 5366 5367 /* Exit the loop only when we know for sure that GPIO1 pin 5368 * was low at some point since irq_lock was acquired. Any event 5369 * after that point creates a rising edge that triggers another 5370 * call to rt5677_irq(). 5371 */ 5372 if (!irq_fired && !rt5677_check_hotword(rt5677)) 5373 goto exit; 5374 5375 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); 5376 if (ret) { 5377 dev_err(rt5677->dev, "failed updating IRQ status: %d\n", 5378 ret); 5379 goto exit; 5380 } 5381 } 5382 exit: 5383 WARN_ON_ONCE(loop == 20); 5384 mutex_unlock(&rt5677->irq_lock); 5385 if (irq_fired) 5386 return IRQ_HANDLED; 5387 else 5388 return IRQ_NONE; 5389 } 5390 5391 static void rt5677_resume_irq_check(struct work_struct *work) 5392 { 5393 int i, virq; 5394 struct rt5677_priv *rt5677 = 5395 container_of(work, struct rt5677_priv, resume_irq_check.work); 5396 5397 /* This is needed to check and clear the interrupt status register 5398 * at resume. If the headset is plugged/unplugged when the device is 5399 * fully suspended, there won't be a rising edge at resume to trigger 5400 * the interrupt. Without this, we miss the next unplug/plug event. 5401 */ 5402 rt5677_irq(0, rt5677); 5403 5404 /* Call all enabled jack detect irq handlers again. This is needed in 5405 * addition to the above check for a corner case caused by jack gpio 5406 * debounce. After codec irq is disabled at suspend, the delayed work 5407 * scheduled by soc-jack may run and read wrong jack gpio values, since 5408 * the regmap is in cache only mode. At resume, there is no irq because 5409 * rt5677_irq has already ran and cleared the irq status at suspend. 5410 * Without this explicit check, unplug the headset right after suspend 5411 * starts, then after resume the headset is still shown as plugged in. 5412 */ 5413 guard(mutex)(&rt5677->irq_lock); 5414 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5415 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) { 5416 virq = irq_find_mapping(rt5677->domain, i); 5417 if (virq) 5418 handle_nested_irq(virq); 5419 } 5420 } 5421 } 5422 5423 static void rt5677_irq_bus_lock(struct irq_data *data) 5424 { 5425 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5426 5427 mutex_lock(&rt5677->irq_lock); 5428 } 5429 5430 static void rt5677_irq_bus_sync_unlock(struct irq_data *data) 5431 { 5432 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5433 5434 // Set the enable/disable bits for the jack detect IRQs. 5435 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1, 5436 RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 | 5437 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en); 5438 mutex_unlock(&rt5677->irq_lock); 5439 } 5440 5441 static void rt5677_irq_enable(struct irq_data *data) 5442 { 5443 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5444 5445 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask; 5446 } 5447 5448 static void rt5677_irq_disable(struct irq_data *data) 5449 { 5450 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5451 5452 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask; 5453 } 5454 5455 static struct irq_chip rt5677_irq_chip = { 5456 .name = "rt5677_irq_chip", 5457 .irq_bus_lock = rt5677_irq_bus_lock, 5458 .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock, 5459 .irq_disable = rt5677_irq_disable, 5460 .irq_enable = rt5677_irq_enable, 5461 }; 5462 5463 static int rt5677_irq_map(struct irq_domain *h, unsigned int virq, 5464 irq_hw_number_t hw) 5465 { 5466 struct rt5677_priv *rt5677 = h->host_data; 5467 5468 irq_set_chip_data(virq, rt5677); 5469 irq_set_chip(virq, &rt5677_irq_chip); 5470 irq_set_nested_thread(virq, 1); 5471 irq_set_noprobe(virq); 5472 return 0; 5473 } 5474 5475 5476 static const struct irq_domain_ops rt5677_domain_ops = { 5477 .map = rt5677_irq_map, 5478 .xlate = irq_domain_xlate_twocell, 5479 }; 5480 5481 static int rt5677_init_irq(struct i2c_client *i2c) 5482 { 5483 int ret; 5484 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 5485 unsigned int jd_mask = 0, jd_val = 0; 5486 5487 if (!rt5677->pdata.jd1_gpio && 5488 !rt5677->pdata.jd2_gpio && 5489 !rt5677->pdata.jd3_gpio) 5490 return 0; 5491 5492 if (!i2c->irq) { 5493 dev_err(&i2c->dev, "No interrupt specified\n"); 5494 return -EINVAL; 5495 } 5496 5497 mutex_init(&rt5677->irq_lock); 5498 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check); 5499 5500 /* 5501 * Select RC as the debounce clock so that GPIO works even when 5502 * MCLK is gated which happens when there is no audio stream 5503 * (SND_SOC_BIAS_OFF). 5504 */ 5505 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 5506 RT5677_IRQ_DEBOUNCE_SEL_MASK, 5507 RT5677_IRQ_DEBOUNCE_SEL_RC); 5508 /* Enable auto power on RC when GPIO states are changed */ 5509 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff); 5510 5511 /* Select and enable jack detection sources per platform data */ 5512 if (rt5677->pdata.jd1_gpio) { 5513 jd_mask |= RT5677_SEL_GPIO_JD1_MASK; 5514 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT; 5515 } 5516 if (rt5677->pdata.jd2_gpio) { 5517 jd_mask |= RT5677_SEL_GPIO_JD2_MASK; 5518 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT; 5519 } 5520 if (rt5677->pdata.jd3_gpio) { 5521 jd_mask |= RT5677_SEL_GPIO_JD3_MASK; 5522 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT; 5523 } 5524 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val); 5525 5526 /* Set GPIO1 pin to be IRQ output */ 5527 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5528 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5529 5530 /* Ready to listen for interrupts */ 5531 rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev), 5532 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677); 5533 if (!rt5677->domain) { 5534 dev_err(&i2c->dev, "Failed to create IRQ domain\n"); 5535 return -ENOMEM; 5536 } 5537 5538 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq, 5539 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5540 "rt5677", rt5677); 5541 if (ret) 5542 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 5543 5544 rt5677->irq = i2c->irq; 5545 5546 return ret; 5547 } 5548 5549 static const struct acpi_gpio_params rt5677_acpi_reset_gpios = {0, 0, true}; 5550 static const struct acpi_gpio_params rt5677_acpi_ldo2_gpios = {1, 0, false}; 5551 5552 static const struct acpi_gpio_mapping rt5677_acpi_gpios[] = { 5553 { "realtek,reset-gpios", &rt5677_acpi_reset_gpios, 1 }, 5554 { "realtek,pow-ldo2-gpios", &rt5677_acpi_ldo2_gpios, 1 }, 5555 {}, 5556 }; 5557 5558 static int rt5677_i2c_probe(struct i2c_client *i2c) 5559 { 5560 struct rt5677_priv *rt5677; 5561 int ret; 5562 unsigned int val; 5563 5564 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), 5565 GFP_KERNEL); 5566 if (rt5677 == NULL) 5567 return -ENOMEM; 5568 5569 rt5677->dev = &i2c->dev; 5570 rt5677->set_dsp_vad = rt5677_set_dsp_vad; 5571 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work); 5572 i2c_set_clientdata(i2c, rt5677); 5573 5574 rt5677->type = (enum rt5677_type)(uintptr_t)i2c_get_match_data(i2c); 5575 if (rt5677->type == 0) 5576 return -EINVAL; 5577 5578 if (devm_acpi_dev_add_driver_gpios(rt5677->dev, rt5677_acpi_gpios)) 5579 dev_warn(rt5677->dev, "Unable to add GPIO mapping table\n"); 5580 5581 rt5677_read_device_properties(rt5677, &i2c->dev); 5582 5583 /* pow-ldo2 and reset are optional. The codec pins may be statically 5584 * connected on the board without gpios. If the gpio device property 5585 * isn't specified, devm_gpiod_get_optional returns NULL. 5586 */ 5587 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, 5588 "realtek,pow-ldo2", GPIOD_OUT_HIGH); 5589 if (IS_ERR(rt5677->pow_ldo2)) { 5590 ret = PTR_ERR(rt5677->pow_ldo2); 5591 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); 5592 return ret; 5593 } 5594 5595 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, 5596 "realtek,reset", GPIOD_OUT_HIGH); 5597 5598 if (IS_ERR(rt5677->reset_pin)) { 5599 ret = PTR_ERR(rt5677->reset_pin); 5600 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); 5601 return ret; 5602 } 5603 5604 if (rt5677->reset_pin) { 5605 msleep(1); 5606 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 5607 } 5608 5609 if (rt5677->pow_ldo2 || rt5677->reset_pin) { 5610 /* Wait a while until I2C bus becomes available. The datasheet 5611 * does not specify the exact we should wait but startup 5612 * sequence mentiones at least a few milliseconds. 5613 */ 5614 msleep(10); 5615 } 5616 5617 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, 5618 &rt5677_regmap_physical); 5619 if (IS_ERR(rt5677->regmap_physical)) { 5620 ret = PTR_ERR(rt5677->regmap_physical); 5621 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5622 ret); 5623 return ret; 5624 } 5625 5626 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); 5627 if (IS_ERR(rt5677->regmap)) { 5628 ret = PTR_ERR(rt5677->regmap); 5629 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5630 ret); 5631 return ret; 5632 } 5633 5634 ret = regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); 5635 if (ret) { 5636 dev_err(&i2c->dev, 5637 "Failed to read ID register: %d\n", ret); 5638 return -ENODEV; 5639 } 5640 5641 if (val != RT5677_DEVICE_ID) { 5642 dev_err(&i2c->dev, 5643 "Device with ID register %#x is not rt5677\n", val); 5644 return -ENODEV; 5645 } 5646 5647 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 5648 5649 ret = regmap_register_patch(rt5677->regmap, init_list, 5650 ARRAY_SIZE(init_list)); 5651 if (ret != 0) 5652 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 5653 5654 if (rt5677->pdata.in1_diff) 5655 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5656 RT5677_IN_DF1, RT5677_IN_DF1); 5657 5658 if (rt5677->pdata.in2_diff) 5659 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5660 RT5677_IN_DF2, RT5677_IN_DF2); 5661 5662 if (rt5677->pdata.lout1_diff) 5663 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5664 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); 5665 5666 if (rt5677->pdata.lout2_diff) 5667 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5668 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); 5669 5670 if (rt5677->pdata.lout3_diff) 5671 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5672 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); 5673 5674 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 5675 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, 5676 RT5677_GPIO5_FUNC_MASK, 5677 RT5677_GPIO5_FUNC_DMIC); 5678 rt5677_update_gpio_bits(rt5677, RT5677_GPIO5, 5679 RT5677_GPIOx_DIR_MASK, 5680 RT5677_GPIOx_DIR_OUT); 5681 } 5682 5683 if (rt5677->pdata.micbias1_vdd_3v3) 5684 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, 5685 RT5677_MICBIAS1_CTRL_VDD_MASK, 5686 RT5677_MICBIAS1_CTRL_VDD_3_3V); 5687 5688 rt5677_init_gpio(i2c); 5689 ret = rt5677_init_irq(i2c); 5690 if (ret) 5691 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret); 5692 5693 return devm_snd_soc_register_component(&i2c->dev, 5694 &soc_component_dev_rt5677, 5695 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 5696 } 5697 5698 static void rt5677_i2c_remove(struct i2c_client *i2c) 5699 { 5700 rt5677_free_gpio(i2c); 5701 } 5702 5703 static struct i2c_driver rt5677_i2c_driver = { 5704 .driver = { 5705 .name = RT5677_DRV_NAME, 5706 .of_match_table = rt5677_of_match, 5707 .acpi_match_table = rt5677_acpi_match, 5708 }, 5709 .id_table = rt5677_i2c_id, 5710 .probe = rt5677_i2c_probe, 5711 .remove = rt5677_i2c_remove, 5712 }; 5713 module_i2c_driver(rt5677_i2c_driver); 5714 5715 MODULE_DESCRIPTION("ASoC RT5677 driver"); 5716 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 5717 MODULE_LICENSE("GPL v2"); 5718 5719 MODULE_FIRMWARE("rt5677_elf_vad"); 5720