1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/input.h> 11 #include <linux/spi/spi.h> 12 #include <linux/device.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/slab.h> 18 #include <linux/sched.h> 19 #include <linux/uaccess.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/pm_qos.h> 22 #include <linux/sysfs.h> 23 #include <linux/clk.h> 24 #include <linux/firmware.h> 25 #include <linux/acpi.h> 26 27 #include "rt5677-spi.h" 28 29 #define RT5677_SPI_BURST_LEN 240 30 #define RT5677_SPI_HEADER 5 31 #define RT5677_SPI_FREQ 6000000 32 33 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. 34 * DataPhase word size of 16-bit commands is 2 bytes. 35 * DataPhase word size of 32-bit commands is 4 bytes. 36 * DataPhase word size of burst commands is 8 bytes. 37 * The DSP CPU is little-endian. 38 */ 39 #define RT5677_SPI_WRITE_BURST 0x5 40 #define RT5677_SPI_READ_BURST 0x4 41 #define RT5677_SPI_WRITE_32 0x3 42 #define RT5677_SPI_READ_32 0x2 43 #define RT5677_SPI_WRITE_16 0x1 44 #define RT5677_SPI_READ_16 0x0 45 46 static struct spi_device *g_spi; 47 static DEFINE_MUTEX(spi_mutex); 48 49 /* Select a suitable transfer command for the next transfer to ensure 50 * the transfer address is always naturally aligned while minimizing 51 * the total number of transfers required. 52 * 53 * 3 transfer commands are available: 54 * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes 55 * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes 56 * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes 57 * 58 * Note: 59 * 16 Bit writes and reads are restricted to the address range 60 * 0x18020000 ~ 0x18021000 61 * 62 * For example, reading 256 bytes at 0x60030004 uses the following commands: 63 * 0x60030004 RT5677_SPI_READ_32 4 bytes 64 * 0x60030008 RT5677_SPI_READ_BURST 240 bytes 65 * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes 66 * 0x60030100 RT5677_SPI_READ_32 4 bytes 67 * 68 * Input: 69 * @read: true for read commands; false for write commands 70 * @align: alignment of the next transfer address 71 * @remain: number of bytes remaining to transfer 72 * 73 * Output: 74 * @len: number of bytes to transfer with the selected command 75 * Returns the selected command 76 */ 77 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) 78 { 79 u8 cmd; 80 81 if (align == 4 || remain <= 4) { 82 cmd = RT5677_SPI_READ_32; 83 *len = 4; 84 } else { 85 cmd = RT5677_SPI_READ_BURST; 86 *len = (((remain - 1) >> 3) + 1) << 3; 87 *len = min_t(u32, *len, RT5677_SPI_BURST_LEN); 88 } 89 return read ? cmd : cmd + 1; 90 } 91 92 /* Copy dstlen bytes from src to dst, while reversing byte order for each word. 93 * If srclen < dstlen, zeros are padded. 94 */ 95 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) 96 { 97 u32 w, i, si; 98 u32 word_size = min_t(u32, dstlen, 8); 99 100 for (w = 0; w < dstlen; w += word_size) { 101 for (i = 0; i < word_size && i + w < dstlen; i++) { 102 si = w + word_size - i - 1; 103 dst[w + i] = si < srclen ? src[si] : 0; 104 } 105 } 106 } 107 108 /* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */ 109 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) 110 { 111 u32 offset; 112 int status = 0; 113 struct spi_transfer t[2]; 114 struct spi_message m; 115 /* +4 bytes is for the DummyPhase following the AddressPhase */ 116 u8 header[RT5677_SPI_HEADER + 4]; 117 u8 body[RT5677_SPI_BURST_LEN]; 118 u8 spi_cmd; 119 u8 *cb = rxbuf; 120 121 if (!g_spi) 122 return -ENODEV; 123 124 if ((addr & 3) || (len & 3)) { 125 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); 126 return -EACCES; 127 } 128 129 memset(t, 0, sizeof(t)); 130 t[0].tx_buf = header; 131 t[0].len = sizeof(header); 132 t[0].speed_hz = RT5677_SPI_FREQ; 133 t[1].rx_buf = body; 134 t[1].speed_hz = RT5677_SPI_FREQ; 135 spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); 136 137 for (offset = 0; offset < len; offset += t[1].len) { 138 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, 139 len - offset, &t[1].len); 140 141 /* Construct SPI message header */ 142 header[0] = spi_cmd; 143 header[1] = ((addr + offset) & 0xff000000) >> 24; 144 header[2] = ((addr + offset) & 0x00ff0000) >> 16; 145 header[3] = ((addr + offset) & 0x0000ff00) >> 8; 146 header[4] = ((addr + offset) & 0x000000ff) >> 0; 147 148 mutex_lock(&spi_mutex); 149 status |= spi_sync(g_spi, &m); 150 mutex_unlock(&spi_mutex); 151 152 153 /* Copy data back to caller buffer */ 154 rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len); 155 } 156 return status; 157 } 158 EXPORT_SYMBOL_GPL(rt5677_spi_read); 159 160 /* Write DSP address space using SPI. addr has to be 4-byte aligned. 161 * If len is not 4-byte aligned, then extra zeros are written at the end 162 * as padding. 163 */ 164 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) 165 { 166 u32 offset; 167 int status = 0; 168 struct spi_transfer t; 169 struct spi_message m; 170 /* +1 byte is for the DummyPhase following the DataPhase */ 171 u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; 172 u8 *body = buf + RT5677_SPI_HEADER; 173 u8 spi_cmd; 174 const u8 *cb = txbuf; 175 176 if (!g_spi) 177 return -ENODEV; 178 179 if (addr & 3) { 180 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); 181 return -EACCES; 182 } 183 184 memset(&t, 0, sizeof(t)); 185 t.tx_buf = buf; 186 t.speed_hz = RT5677_SPI_FREQ; 187 spi_message_init_with_transfers(&m, &t, 1); 188 189 for (offset = 0; offset < len;) { 190 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, 191 len - offset, &t.len); 192 193 /* Construct SPI message header */ 194 buf[0] = spi_cmd; 195 buf[1] = ((addr + offset) & 0xff000000) >> 24; 196 buf[2] = ((addr + offset) & 0x00ff0000) >> 16; 197 buf[3] = ((addr + offset) & 0x0000ff00) >> 8; 198 buf[4] = ((addr + offset) & 0x000000ff) >> 0; 199 200 /* Fetch data from caller buffer */ 201 rt5677_spi_reverse(body, t.len, cb + offset, len - offset); 202 offset += t.len; 203 t.len += RT5677_SPI_HEADER + 1; 204 205 mutex_lock(&spi_mutex); 206 status |= spi_sync(g_spi, &m); 207 mutex_unlock(&spi_mutex); 208 } 209 return status; 210 } 211 EXPORT_SYMBOL_GPL(rt5677_spi_write); 212 213 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) 214 { 215 return rt5677_spi_write(addr, fw->data, fw->size); 216 } 217 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); 218 219 static int rt5677_spi_probe(struct spi_device *spi) 220 { 221 g_spi = spi; 222 return 0; 223 } 224 225 static const struct acpi_device_id rt5677_spi_acpi_id[] = { 226 { "RT5677AA", 0 }, 227 { } 228 }; 229 MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id); 230 231 static struct spi_driver rt5677_spi_driver = { 232 .driver = { 233 .name = "rt5677", 234 .acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id), 235 }, 236 .probe = rt5677_spi_probe, 237 }; 238 module_spi_driver(rt5677_spi_driver); 239 240 MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); 241 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 242 MODULE_LICENSE("GPL v2"); 243