1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5668.c -- RT5668B ALSA SoC audio component driver 4 * 5 * Copyright 2018 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/cleanup.h> 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/pm.h> 15 #include <linux/i2c.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/acpi.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/mutex.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/rt5668.h> 31 32 #include "rl6231.h" 33 #include "rt5668.h" 34 35 #define RT5668_NUM_SUPPLIES 3 36 37 static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = { 38 "AVDD", 39 "MICVDD", 40 "VBAT", 41 }; 42 43 struct rt5668_priv { 44 struct snd_soc_component *component; 45 struct rt5668_platform_data pdata; 46 struct gpio_desc *ldo1_en; 47 struct regmap *regmap; 48 struct snd_soc_jack *hs_jack; 49 struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES]; 50 struct delayed_work jack_detect_work; 51 struct delayed_work jd_check_work; 52 struct mutex calibrate_mutex; 53 54 int sysclk; 55 int sysclk_src; 56 int lrck[RT5668_AIFS]; 57 int bclk[RT5668_AIFS]; 58 int master[RT5668_AIFS]; 59 60 int pll_src; 61 int pll_in; 62 int pll_out; 63 64 int jack_type; 65 }; 66 67 static const struct reg_default rt5668_reg[] = { 68 {0x0002, 0x8080}, 69 {0x0003, 0x8000}, 70 {0x0005, 0x0000}, 71 {0x0006, 0x0000}, 72 {0x0008, 0x800f}, 73 {0x000b, 0x0000}, 74 {0x0010, 0x4040}, 75 {0x0011, 0x0000}, 76 {0x0012, 0x1404}, 77 {0x0013, 0x1000}, 78 {0x0014, 0xa00a}, 79 {0x0015, 0x0404}, 80 {0x0016, 0x0404}, 81 {0x0019, 0xafaf}, 82 {0x001c, 0x2f2f}, 83 {0x001f, 0x0000}, 84 {0x0022, 0x5757}, 85 {0x0023, 0x0039}, 86 {0x0024, 0x000b}, 87 {0x0026, 0xc0c4}, 88 {0x0029, 0x8080}, 89 {0x002a, 0xa0a0}, 90 {0x002b, 0x0300}, 91 {0x0030, 0x0000}, 92 {0x003c, 0x0080}, 93 {0x0044, 0x0c0c}, 94 {0x0049, 0x0000}, 95 {0x0061, 0x0000}, 96 {0x0062, 0x0000}, 97 {0x0063, 0x003f}, 98 {0x0064, 0x0000}, 99 {0x0065, 0x0000}, 100 {0x0066, 0x0030}, 101 {0x0067, 0x0000}, 102 {0x006b, 0x0000}, 103 {0x006c, 0x0000}, 104 {0x006d, 0x2200}, 105 {0x006e, 0x0a10}, 106 {0x0070, 0x8000}, 107 {0x0071, 0x8000}, 108 {0x0073, 0x0000}, 109 {0x0074, 0x0000}, 110 {0x0075, 0x0002}, 111 {0x0076, 0x0001}, 112 {0x0079, 0x0000}, 113 {0x007a, 0x0000}, 114 {0x007b, 0x0000}, 115 {0x007c, 0x0100}, 116 {0x007e, 0x0000}, 117 {0x0080, 0x0000}, 118 {0x0081, 0x0000}, 119 {0x0082, 0x0000}, 120 {0x0083, 0x0000}, 121 {0x0084, 0x0000}, 122 {0x0085, 0x0000}, 123 {0x0086, 0x0005}, 124 {0x0087, 0x0000}, 125 {0x0088, 0x0000}, 126 {0x008c, 0x0003}, 127 {0x008d, 0x0000}, 128 {0x008e, 0x0060}, 129 {0x008f, 0x1000}, 130 {0x0091, 0x0c26}, 131 {0x0092, 0x0073}, 132 {0x0093, 0x0000}, 133 {0x0094, 0x0080}, 134 {0x0098, 0x0000}, 135 {0x009a, 0x0000}, 136 {0x009b, 0x0000}, 137 {0x009c, 0x0000}, 138 {0x009d, 0x0000}, 139 {0x009e, 0x100c}, 140 {0x009f, 0x0000}, 141 {0x00a0, 0x0000}, 142 {0x00a3, 0x0002}, 143 {0x00a4, 0x0001}, 144 {0x00ae, 0x2040}, 145 {0x00af, 0x0000}, 146 {0x00b6, 0x0000}, 147 {0x00b7, 0x0000}, 148 {0x00b8, 0x0000}, 149 {0x00b9, 0x0002}, 150 {0x00be, 0x0000}, 151 {0x00c0, 0x0160}, 152 {0x00c1, 0x82a0}, 153 {0x00c2, 0x0000}, 154 {0x00d0, 0x0000}, 155 {0x00d1, 0x2244}, 156 {0x00d2, 0x3300}, 157 {0x00d3, 0x2200}, 158 {0x00d4, 0x0000}, 159 {0x00d9, 0x0009}, 160 {0x00da, 0x0000}, 161 {0x00db, 0x0000}, 162 {0x00dc, 0x00c0}, 163 {0x00dd, 0x2220}, 164 {0x00de, 0x3131}, 165 {0x00df, 0x3131}, 166 {0x00e0, 0x3131}, 167 {0x00e2, 0x0000}, 168 {0x00e3, 0x4000}, 169 {0x00e4, 0x0aa0}, 170 {0x00e5, 0x3131}, 171 {0x00e6, 0x3131}, 172 {0x00e7, 0x3131}, 173 {0x00e8, 0x3131}, 174 {0x00ea, 0xb320}, 175 {0x00eb, 0x0000}, 176 {0x00f0, 0x0000}, 177 {0x00f1, 0x00d0}, 178 {0x00f2, 0x00d0}, 179 {0x00f6, 0x0000}, 180 {0x00fa, 0x0000}, 181 {0x00fb, 0x0000}, 182 {0x00fc, 0x0000}, 183 {0x00fd, 0x0000}, 184 {0x00fe, 0x10ec}, 185 {0x00ff, 0x6530}, 186 {0x0100, 0xa0a0}, 187 {0x010b, 0x0000}, 188 {0x010c, 0xae00}, 189 {0x010d, 0xaaa0}, 190 {0x010e, 0x8aa2}, 191 {0x010f, 0x02a2}, 192 {0x0110, 0xc000}, 193 {0x0111, 0x04a2}, 194 {0x0112, 0x2800}, 195 {0x0113, 0x0000}, 196 {0x0117, 0x0100}, 197 {0x0125, 0x0410}, 198 {0x0132, 0x6026}, 199 {0x0136, 0x5555}, 200 {0x0138, 0x3700}, 201 {0x013a, 0x2000}, 202 {0x013b, 0x2000}, 203 {0x013c, 0x2005}, 204 {0x013f, 0x0000}, 205 {0x0142, 0x0000}, 206 {0x0145, 0x0002}, 207 {0x0146, 0x0000}, 208 {0x0147, 0x0000}, 209 {0x0148, 0x0000}, 210 {0x0149, 0x0000}, 211 {0x0150, 0x79a1}, 212 {0x0151, 0x0000}, 213 {0x0160, 0x4ec0}, 214 {0x0161, 0x0080}, 215 {0x0162, 0x0200}, 216 {0x0163, 0x0800}, 217 {0x0164, 0x0000}, 218 {0x0165, 0x0000}, 219 {0x0166, 0x0000}, 220 {0x0167, 0x000f}, 221 {0x0168, 0x000f}, 222 {0x0169, 0x0021}, 223 {0x0190, 0x413d}, 224 {0x0194, 0x0000}, 225 {0x0195, 0x0000}, 226 {0x0197, 0x0022}, 227 {0x0198, 0x0000}, 228 {0x0199, 0x0000}, 229 {0x01af, 0x0000}, 230 {0x01b0, 0x0400}, 231 {0x01b1, 0x0000}, 232 {0x01b2, 0x0000}, 233 {0x01b3, 0x0000}, 234 {0x01b4, 0x0000}, 235 {0x01b5, 0x0000}, 236 {0x01b6, 0x01c3}, 237 {0x01b7, 0x02a0}, 238 {0x01b8, 0x03e9}, 239 {0x01b9, 0x1389}, 240 {0x01ba, 0xc351}, 241 {0x01bb, 0x0009}, 242 {0x01bc, 0x0018}, 243 {0x01bd, 0x002a}, 244 {0x01be, 0x004c}, 245 {0x01bf, 0x0097}, 246 {0x01c0, 0x433d}, 247 {0x01c1, 0x2800}, 248 {0x01c2, 0x0000}, 249 {0x01c3, 0x0000}, 250 {0x01c4, 0x0000}, 251 {0x01c5, 0x0000}, 252 {0x01c6, 0x0000}, 253 {0x01c7, 0x0000}, 254 {0x01c8, 0x40af}, 255 {0x01c9, 0x0702}, 256 {0x01ca, 0x0000}, 257 {0x01cb, 0x0000}, 258 {0x01cc, 0x5757}, 259 {0x01cd, 0x5757}, 260 {0x01ce, 0x5757}, 261 {0x01cf, 0x5757}, 262 {0x01d0, 0x5757}, 263 {0x01d1, 0x5757}, 264 {0x01d2, 0x5757}, 265 {0x01d3, 0x5757}, 266 {0x01d4, 0x5757}, 267 {0x01d5, 0x5757}, 268 {0x01d6, 0x0000}, 269 {0x01d7, 0x0008}, 270 {0x01d8, 0x0029}, 271 {0x01d9, 0x3333}, 272 {0x01da, 0x0000}, 273 {0x01db, 0x0004}, 274 {0x01dc, 0x0000}, 275 {0x01de, 0x7c00}, 276 {0x01df, 0x0320}, 277 {0x01e0, 0x06a1}, 278 {0x01e1, 0x0000}, 279 {0x01e2, 0x0000}, 280 {0x01e3, 0x0000}, 281 {0x01e4, 0x0000}, 282 {0x01e6, 0x0001}, 283 {0x01e7, 0x0000}, 284 {0x01e8, 0x0000}, 285 {0x01ea, 0x0000}, 286 {0x01eb, 0x0000}, 287 {0x01ec, 0x0000}, 288 {0x01ed, 0x0000}, 289 {0x01ee, 0x0000}, 290 {0x01ef, 0x0000}, 291 {0x01f0, 0x0000}, 292 {0x01f1, 0x0000}, 293 {0x01f2, 0x0000}, 294 {0x01f3, 0x0000}, 295 {0x01f4, 0x0000}, 296 {0x0210, 0x6297}, 297 {0x0211, 0xa005}, 298 {0x0212, 0x824c}, 299 {0x0213, 0xf7ff}, 300 {0x0214, 0xf24c}, 301 {0x0215, 0x0102}, 302 {0x0216, 0x00a3}, 303 {0x0217, 0x0048}, 304 {0x0218, 0xa2c0}, 305 {0x0219, 0x0400}, 306 {0x021a, 0x00c8}, 307 {0x021b, 0x00c0}, 308 {0x021c, 0x0000}, 309 {0x0250, 0x4500}, 310 {0x0251, 0x40b3}, 311 {0x0252, 0x0000}, 312 {0x0253, 0x0000}, 313 {0x0254, 0x0000}, 314 {0x0255, 0x0000}, 315 {0x0256, 0x0000}, 316 {0x0257, 0x0000}, 317 {0x0258, 0x0000}, 318 {0x0259, 0x0000}, 319 {0x025a, 0x0005}, 320 {0x0270, 0x0000}, 321 {0x02ff, 0x0110}, 322 {0x0300, 0x001f}, 323 {0x0301, 0x032c}, 324 {0x0302, 0x5f21}, 325 {0x0303, 0x4000}, 326 {0x0304, 0x4000}, 327 {0x0305, 0x06d5}, 328 {0x0306, 0x8000}, 329 {0x0307, 0x0700}, 330 {0x0310, 0x4560}, 331 {0x0311, 0xa4a8}, 332 {0x0312, 0x7418}, 333 {0x0313, 0x0000}, 334 {0x0314, 0x0006}, 335 {0x0315, 0xffff}, 336 {0x0316, 0xc400}, 337 {0x0317, 0x0000}, 338 {0x03c0, 0x7e00}, 339 {0x03c1, 0x8000}, 340 {0x03c2, 0x8000}, 341 {0x03c3, 0x8000}, 342 {0x03c4, 0x8000}, 343 {0x03c5, 0x8000}, 344 {0x03c6, 0x8000}, 345 {0x03c7, 0x8000}, 346 {0x03c8, 0x8000}, 347 {0x03c9, 0x8000}, 348 {0x03ca, 0x8000}, 349 {0x03cb, 0x8000}, 350 {0x03cc, 0x8000}, 351 {0x03d0, 0x0000}, 352 {0x03d1, 0x0000}, 353 {0x03d2, 0x0000}, 354 {0x03d3, 0x0000}, 355 {0x03d4, 0x2000}, 356 {0x03d5, 0x2000}, 357 {0x03d6, 0x0000}, 358 {0x03d7, 0x0000}, 359 {0x03d8, 0x2000}, 360 {0x03d9, 0x2000}, 361 {0x03da, 0x2000}, 362 {0x03db, 0x2000}, 363 {0x03dc, 0x0000}, 364 {0x03dd, 0x0000}, 365 {0x03de, 0x0000}, 366 {0x03df, 0x2000}, 367 {0x03e0, 0x0000}, 368 {0x03e1, 0x0000}, 369 {0x03e2, 0x0000}, 370 {0x03e3, 0x0000}, 371 {0x03e4, 0x0000}, 372 {0x03e5, 0x0000}, 373 {0x03e6, 0x0000}, 374 {0x03e7, 0x0000}, 375 {0x03e8, 0x0000}, 376 {0x03e9, 0x0000}, 377 {0x03ea, 0x0000}, 378 {0x03eb, 0x0000}, 379 {0x03ec, 0x0000}, 380 {0x03ed, 0x0000}, 381 {0x03ee, 0x0000}, 382 {0x03ef, 0x0000}, 383 {0x03f0, 0x0800}, 384 {0x03f1, 0x0800}, 385 {0x03f2, 0x0800}, 386 {0x03f3, 0x0800}, 387 }; 388 389 static bool rt5668_volatile_register(struct device *dev, unsigned int reg) 390 { 391 switch (reg) { 392 case RT5668_RESET: 393 case RT5668_CBJ_CTRL_2: 394 case RT5668_INT_ST_1: 395 case RT5668_4BTN_IL_CMD_1: 396 case RT5668_AJD1_CTRL: 397 case RT5668_HP_CALIB_CTRL_1: 398 case RT5668_DEVICE_ID: 399 case RT5668_I2C_MODE: 400 case RT5668_HP_CALIB_CTRL_10: 401 case RT5668_EFUSE_CTRL_2: 402 case RT5668_JD_TOP_VC_VTRL: 403 case RT5668_HP_IMP_SENS_CTRL_19: 404 case RT5668_IL_CMD_1: 405 case RT5668_SAR_IL_CMD_2: 406 case RT5668_SAR_IL_CMD_4: 407 case RT5668_SAR_IL_CMD_10: 408 case RT5668_SAR_IL_CMD_11: 409 case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11: 410 case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11: 411 return true; 412 default: 413 return false; 414 } 415 } 416 417 static bool rt5668_readable_register(struct device *dev, unsigned int reg) 418 { 419 switch (reg) { 420 case RT5668_RESET: 421 case RT5668_VERSION_ID: 422 case RT5668_VENDOR_ID: 423 case RT5668_DEVICE_ID: 424 case RT5668_HP_CTRL_1: 425 case RT5668_HP_CTRL_2: 426 case RT5668_HPL_GAIN: 427 case RT5668_HPR_GAIN: 428 case RT5668_I2C_CTRL: 429 case RT5668_CBJ_BST_CTRL: 430 case RT5668_CBJ_CTRL_1: 431 case RT5668_CBJ_CTRL_2: 432 case RT5668_CBJ_CTRL_3: 433 case RT5668_CBJ_CTRL_4: 434 case RT5668_CBJ_CTRL_5: 435 case RT5668_CBJ_CTRL_6: 436 case RT5668_CBJ_CTRL_7: 437 case RT5668_DAC1_DIG_VOL: 438 case RT5668_STO1_ADC_DIG_VOL: 439 case RT5668_STO1_ADC_BOOST: 440 case RT5668_HP_IMP_GAIN_1: 441 case RT5668_HP_IMP_GAIN_2: 442 case RT5668_SIDETONE_CTRL: 443 case RT5668_STO1_ADC_MIXER: 444 case RT5668_AD_DA_MIXER: 445 case RT5668_STO1_DAC_MIXER: 446 case RT5668_A_DAC1_MUX: 447 case RT5668_DIG_INF2_DATA: 448 case RT5668_REC_MIXER: 449 case RT5668_CAL_REC: 450 case RT5668_ALC_BACK_GAIN: 451 case RT5668_PWR_DIG_1: 452 case RT5668_PWR_DIG_2: 453 case RT5668_PWR_ANLG_1: 454 case RT5668_PWR_ANLG_2: 455 case RT5668_PWR_ANLG_3: 456 case RT5668_PWR_MIXER: 457 case RT5668_PWR_VOL: 458 case RT5668_CLK_DET: 459 case RT5668_RESET_LPF_CTRL: 460 case RT5668_RESET_HPF_CTRL: 461 case RT5668_DMIC_CTRL_1: 462 case RT5668_I2S1_SDP: 463 case RT5668_I2S2_SDP: 464 case RT5668_ADDA_CLK_1: 465 case RT5668_ADDA_CLK_2: 466 case RT5668_I2S1_F_DIV_CTRL_1: 467 case RT5668_I2S1_F_DIV_CTRL_2: 468 case RT5668_TDM_CTRL: 469 case RT5668_TDM_ADDA_CTRL_1: 470 case RT5668_TDM_ADDA_CTRL_2: 471 case RT5668_DATA_SEL_CTRL_1: 472 case RT5668_TDM_TCON_CTRL: 473 case RT5668_GLB_CLK: 474 case RT5668_PLL_CTRL_1: 475 case RT5668_PLL_CTRL_2: 476 case RT5668_PLL_TRACK_1: 477 case RT5668_PLL_TRACK_2: 478 case RT5668_PLL_TRACK_3: 479 case RT5668_PLL_TRACK_4: 480 case RT5668_PLL_TRACK_5: 481 case RT5668_PLL_TRACK_6: 482 case RT5668_PLL_TRACK_11: 483 case RT5668_SDW_REF_CLK: 484 case RT5668_DEPOP_1: 485 case RT5668_DEPOP_2: 486 case RT5668_HP_CHARGE_PUMP_1: 487 case RT5668_HP_CHARGE_PUMP_2: 488 case RT5668_MICBIAS_1: 489 case RT5668_MICBIAS_2: 490 case RT5668_PLL_TRACK_12: 491 case RT5668_PLL_TRACK_14: 492 case RT5668_PLL2_CTRL_1: 493 case RT5668_PLL2_CTRL_2: 494 case RT5668_PLL2_CTRL_3: 495 case RT5668_PLL2_CTRL_4: 496 case RT5668_RC_CLK_CTRL: 497 case RT5668_I2S_M_CLK_CTRL_1: 498 case RT5668_I2S2_F_DIV_CTRL_1: 499 case RT5668_I2S2_F_DIV_CTRL_2: 500 case RT5668_EQ_CTRL_1: 501 case RT5668_EQ_CTRL_2: 502 case RT5668_IRQ_CTRL_1: 503 case RT5668_IRQ_CTRL_2: 504 case RT5668_IRQ_CTRL_3: 505 case RT5668_IRQ_CTRL_4: 506 case RT5668_INT_ST_1: 507 case RT5668_GPIO_CTRL_1: 508 case RT5668_GPIO_CTRL_2: 509 case RT5668_GPIO_CTRL_3: 510 case RT5668_HP_AMP_DET_CTRL_1: 511 case RT5668_HP_AMP_DET_CTRL_2: 512 case RT5668_MID_HP_AMP_DET: 513 case RT5668_LOW_HP_AMP_DET: 514 case RT5668_DELAY_BUF_CTRL: 515 case RT5668_SV_ZCD_1: 516 case RT5668_SV_ZCD_2: 517 case RT5668_IL_CMD_1: 518 case RT5668_IL_CMD_2: 519 case RT5668_IL_CMD_3: 520 case RT5668_IL_CMD_4: 521 case RT5668_IL_CMD_5: 522 case RT5668_IL_CMD_6: 523 case RT5668_4BTN_IL_CMD_1: 524 case RT5668_4BTN_IL_CMD_2: 525 case RT5668_4BTN_IL_CMD_3: 526 case RT5668_4BTN_IL_CMD_4: 527 case RT5668_4BTN_IL_CMD_5: 528 case RT5668_4BTN_IL_CMD_6: 529 case RT5668_4BTN_IL_CMD_7: 530 case RT5668_ADC_STO1_HP_CTRL_1: 531 case RT5668_ADC_STO1_HP_CTRL_2: 532 case RT5668_AJD1_CTRL: 533 case RT5668_JD1_THD: 534 case RT5668_JD2_THD: 535 case RT5668_JD_CTRL_1: 536 case RT5668_DUMMY_1: 537 case RT5668_DUMMY_2: 538 case RT5668_DUMMY_3: 539 case RT5668_DAC_ADC_DIG_VOL1: 540 case RT5668_BIAS_CUR_CTRL_2: 541 case RT5668_BIAS_CUR_CTRL_3: 542 case RT5668_BIAS_CUR_CTRL_4: 543 case RT5668_BIAS_CUR_CTRL_5: 544 case RT5668_BIAS_CUR_CTRL_6: 545 case RT5668_BIAS_CUR_CTRL_7: 546 case RT5668_BIAS_CUR_CTRL_8: 547 case RT5668_BIAS_CUR_CTRL_9: 548 case RT5668_BIAS_CUR_CTRL_10: 549 case RT5668_VREF_REC_OP_FB_CAP_CTRL: 550 case RT5668_CHARGE_PUMP_1: 551 case RT5668_DIG_IN_CTRL_1: 552 case RT5668_PAD_DRIVING_CTRL: 553 case RT5668_SOFT_RAMP_DEPOP: 554 case RT5668_CHOP_DAC: 555 case RT5668_CHOP_ADC: 556 case RT5668_CALIB_ADC_CTRL: 557 case RT5668_VOL_TEST: 558 case RT5668_SPKVDD_DET_STA: 559 case RT5668_TEST_MODE_CTRL_1: 560 case RT5668_TEST_MODE_CTRL_2: 561 case RT5668_TEST_MODE_CTRL_3: 562 case RT5668_TEST_MODE_CTRL_4: 563 case RT5668_TEST_MODE_CTRL_5: 564 case RT5668_PLL1_INTERNAL: 565 case RT5668_PLL2_INTERNAL: 566 case RT5668_STO_NG2_CTRL_1: 567 case RT5668_STO_NG2_CTRL_2: 568 case RT5668_STO_NG2_CTRL_3: 569 case RT5668_STO_NG2_CTRL_4: 570 case RT5668_STO_NG2_CTRL_5: 571 case RT5668_STO_NG2_CTRL_6: 572 case RT5668_STO_NG2_CTRL_7: 573 case RT5668_STO_NG2_CTRL_8: 574 case RT5668_STO_NG2_CTRL_9: 575 case RT5668_STO_NG2_CTRL_10: 576 case RT5668_STO1_DAC_SIL_DET: 577 case RT5668_SIL_PSV_CTRL1: 578 case RT5668_SIL_PSV_CTRL2: 579 case RT5668_SIL_PSV_CTRL3: 580 case RT5668_SIL_PSV_CTRL4: 581 case RT5668_SIL_PSV_CTRL5: 582 case RT5668_HP_IMP_SENS_CTRL_01: 583 case RT5668_HP_IMP_SENS_CTRL_02: 584 case RT5668_HP_IMP_SENS_CTRL_03: 585 case RT5668_HP_IMP_SENS_CTRL_04: 586 case RT5668_HP_IMP_SENS_CTRL_05: 587 case RT5668_HP_IMP_SENS_CTRL_06: 588 case RT5668_HP_IMP_SENS_CTRL_07: 589 case RT5668_HP_IMP_SENS_CTRL_08: 590 case RT5668_HP_IMP_SENS_CTRL_09: 591 case RT5668_HP_IMP_SENS_CTRL_10: 592 case RT5668_HP_IMP_SENS_CTRL_11: 593 case RT5668_HP_IMP_SENS_CTRL_12: 594 case RT5668_HP_IMP_SENS_CTRL_13: 595 case RT5668_HP_IMP_SENS_CTRL_14: 596 case RT5668_HP_IMP_SENS_CTRL_15: 597 case RT5668_HP_IMP_SENS_CTRL_16: 598 case RT5668_HP_IMP_SENS_CTRL_17: 599 case RT5668_HP_IMP_SENS_CTRL_18: 600 case RT5668_HP_IMP_SENS_CTRL_19: 601 case RT5668_HP_IMP_SENS_CTRL_20: 602 case RT5668_HP_IMP_SENS_CTRL_21: 603 case RT5668_HP_IMP_SENS_CTRL_22: 604 case RT5668_HP_IMP_SENS_CTRL_23: 605 case RT5668_HP_IMP_SENS_CTRL_24: 606 case RT5668_HP_IMP_SENS_CTRL_25: 607 case RT5668_HP_IMP_SENS_CTRL_26: 608 case RT5668_HP_IMP_SENS_CTRL_27: 609 case RT5668_HP_IMP_SENS_CTRL_28: 610 case RT5668_HP_IMP_SENS_CTRL_29: 611 case RT5668_HP_IMP_SENS_CTRL_30: 612 case RT5668_HP_IMP_SENS_CTRL_31: 613 case RT5668_HP_IMP_SENS_CTRL_32: 614 case RT5668_HP_IMP_SENS_CTRL_33: 615 case RT5668_HP_IMP_SENS_CTRL_34: 616 case RT5668_HP_IMP_SENS_CTRL_35: 617 case RT5668_HP_IMP_SENS_CTRL_36: 618 case RT5668_HP_IMP_SENS_CTRL_37: 619 case RT5668_HP_IMP_SENS_CTRL_38: 620 case RT5668_HP_IMP_SENS_CTRL_39: 621 case RT5668_HP_IMP_SENS_CTRL_40: 622 case RT5668_HP_IMP_SENS_CTRL_41: 623 case RT5668_HP_IMP_SENS_CTRL_42: 624 case RT5668_HP_IMP_SENS_CTRL_43: 625 case RT5668_HP_LOGIC_CTRL_1: 626 case RT5668_HP_LOGIC_CTRL_2: 627 case RT5668_HP_LOGIC_CTRL_3: 628 case RT5668_HP_CALIB_CTRL_1: 629 case RT5668_HP_CALIB_CTRL_2: 630 case RT5668_HP_CALIB_CTRL_3: 631 case RT5668_HP_CALIB_CTRL_4: 632 case RT5668_HP_CALIB_CTRL_5: 633 case RT5668_HP_CALIB_CTRL_6: 634 case RT5668_HP_CALIB_CTRL_7: 635 case RT5668_HP_CALIB_CTRL_9: 636 case RT5668_HP_CALIB_CTRL_10: 637 case RT5668_HP_CALIB_CTRL_11: 638 case RT5668_HP_CALIB_STA_1: 639 case RT5668_HP_CALIB_STA_2: 640 case RT5668_HP_CALIB_STA_3: 641 case RT5668_HP_CALIB_STA_4: 642 case RT5668_HP_CALIB_STA_5: 643 case RT5668_HP_CALIB_STA_6: 644 case RT5668_HP_CALIB_STA_7: 645 case RT5668_HP_CALIB_STA_8: 646 case RT5668_HP_CALIB_STA_9: 647 case RT5668_HP_CALIB_STA_10: 648 case RT5668_HP_CALIB_STA_11: 649 case RT5668_SAR_IL_CMD_1: 650 case RT5668_SAR_IL_CMD_2: 651 case RT5668_SAR_IL_CMD_3: 652 case RT5668_SAR_IL_CMD_4: 653 case RT5668_SAR_IL_CMD_5: 654 case RT5668_SAR_IL_CMD_6: 655 case RT5668_SAR_IL_CMD_7: 656 case RT5668_SAR_IL_CMD_8: 657 case RT5668_SAR_IL_CMD_9: 658 case RT5668_SAR_IL_CMD_10: 659 case RT5668_SAR_IL_CMD_11: 660 case RT5668_SAR_IL_CMD_12: 661 case RT5668_SAR_IL_CMD_13: 662 case RT5668_EFUSE_CTRL_1: 663 case RT5668_EFUSE_CTRL_2: 664 case RT5668_EFUSE_CTRL_3: 665 case RT5668_EFUSE_CTRL_4: 666 case RT5668_EFUSE_CTRL_5: 667 case RT5668_EFUSE_CTRL_6: 668 case RT5668_EFUSE_CTRL_7: 669 case RT5668_EFUSE_CTRL_8: 670 case RT5668_EFUSE_CTRL_9: 671 case RT5668_EFUSE_CTRL_10: 672 case RT5668_EFUSE_CTRL_11: 673 case RT5668_JD_TOP_VC_VTRL: 674 case RT5668_DRC1_CTRL_0: 675 case RT5668_DRC1_CTRL_1: 676 case RT5668_DRC1_CTRL_2: 677 case RT5668_DRC1_CTRL_3: 678 case RT5668_DRC1_CTRL_4: 679 case RT5668_DRC1_CTRL_5: 680 case RT5668_DRC1_CTRL_6: 681 case RT5668_DRC1_HARD_LMT_CTRL_1: 682 case RT5668_DRC1_HARD_LMT_CTRL_2: 683 case RT5668_DRC1_PRIV_1: 684 case RT5668_DRC1_PRIV_2: 685 case RT5668_DRC1_PRIV_3: 686 case RT5668_DRC1_PRIV_4: 687 case RT5668_DRC1_PRIV_5: 688 case RT5668_DRC1_PRIV_6: 689 case RT5668_DRC1_PRIV_7: 690 case RT5668_DRC1_PRIV_8: 691 case RT5668_EQ_AUTO_RCV_CTRL1: 692 case RT5668_EQ_AUTO_RCV_CTRL2: 693 case RT5668_EQ_AUTO_RCV_CTRL3: 694 case RT5668_EQ_AUTO_RCV_CTRL4: 695 case RT5668_EQ_AUTO_RCV_CTRL5: 696 case RT5668_EQ_AUTO_RCV_CTRL6: 697 case RT5668_EQ_AUTO_RCV_CTRL7: 698 case RT5668_EQ_AUTO_RCV_CTRL8: 699 case RT5668_EQ_AUTO_RCV_CTRL9: 700 case RT5668_EQ_AUTO_RCV_CTRL10: 701 case RT5668_EQ_AUTO_RCV_CTRL11: 702 case RT5668_EQ_AUTO_RCV_CTRL12: 703 case RT5668_EQ_AUTO_RCV_CTRL13: 704 case RT5668_ADC_L_EQ_LPF1_A1: 705 case RT5668_R_EQ_LPF1_A1: 706 case RT5668_L_EQ_LPF1_H0: 707 case RT5668_R_EQ_LPF1_H0: 708 case RT5668_L_EQ_BPF1_A1: 709 case RT5668_R_EQ_BPF1_A1: 710 case RT5668_L_EQ_BPF1_A2: 711 case RT5668_R_EQ_BPF1_A2: 712 case RT5668_L_EQ_BPF1_H0: 713 case RT5668_R_EQ_BPF1_H0: 714 case RT5668_L_EQ_BPF2_A1: 715 case RT5668_R_EQ_BPF2_A1: 716 case RT5668_L_EQ_BPF2_A2: 717 case RT5668_R_EQ_BPF2_A2: 718 case RT5668_L_EQ_BPF2_H0: 719 case RT5668_R_EQ_BPF2_H0: 720 case RT5668_L_EQ_BPF3_A1: 721 case RT5668_R_EQ_BPF3_A1: 722 case RT5668_L_EQ_BPF3_A2: 723 case RT5668_R_EQ_BPF3_A2: 724 case RT5668_L_EQ_BPF3_H0: 725 case RT5668_R_EQ_BPF3_H0: 726 case RT5668_L_EQ_BPF4_A1: 727 case RT5668_R_EQ_BPF4_A1: 728 case RT5668_L_EQ_BPF4_A2: 729 case RT5668_R_EQ_BPF4_A2: 730 case RT5668_L_EQ_BPF4_H0: 731 case RT5668_R_EQ_BPF4_H0: 732 case RT5668_L_EQ_HPF1_A1: 733 case RT5668_R_EQ_HPF1_A1: 734 case RT5668_L_EQ_HPF1_H0: 735 case RT5668_R_EQ_HPF1_H0: 736 case RT5668_L_EQ_PRE_VOL: 737 case RT5668_R_EQ_PRE_VOL: 738 case RT5668_L_EQ_POST_VOL: 739 case RT5668_R_EQ_POST_VOL: 740 case RT5668_I2C_MODE: 741 return true; 742 default: 743 return false; 744 } 745 } 746 747 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0); 748 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 749 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 750 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 751 752 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 753 static const DECLARE_TLV_DB_RANGE(bst_tlv, 754 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 755 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 756 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 757 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 758 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 759 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 760 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 761 ); 762 763 /* Interface data select */ 764 static const char * const rt5668_data_select[] = { 765 "L/R", "R/L", "L/L", "R/R" 766 }; 767 768 static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum, 769 RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select); 770 771 static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum, 772 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select); 773 774 static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum, 775 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select); 776 777 static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum, 778 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select); 779 780 static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum, 781 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select); 782 783 static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux = 784 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum); 785 786 static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux = 787 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum); 788 789 static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux = 790 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum); 791 792 static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux = 793 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum); 794 795 static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux = 796 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum); 797 798 static void rt5668_reset(struct regmap *regmap) 799 { 800 regmap_write(regmap, RT5668_RESET, 0); 801 regmap_write(regmap, RT5668_I2C_MODE, 1); 802 } 803 804 static int rt5668_button_detect(struct snd_soc_component *component) 805 { 806 int btn_type, val; 807 808 val = snd_soc_component_read(component, RT5668_4BTN_IL_CMD_1); 809 btn_type = val & 0xfff0; 810 snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val); 811 pr_debug("%s btn_type=%x\n", __func__, btn_type); 812 813 return btn_type; 814 } 815 816 static void rt5668_enable_push_button_irq(struct snd_soc_component *component, 817 bool enable) 818 { 819 if (enable) { 820 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 821 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN); 822 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, 823 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN); 824 snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040); 825 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 826 RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK, 827 RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR); 828 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, 829 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN); 830 } else { 831 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, 832 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS); 833 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 834 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS); 835 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 836 RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS); 837 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 838 RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST); 839 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, 840 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE); 841 } 842 } 843 844 /** 845 * rt5668_headset_detect - Detect headset. 846 * @component: SoC audio component device. 847 * @jack_insert: Jack insert or not. 848 * 849 * Detect whether is headset or not when jack inserted. 850 * 851 * Returns detect status. 852 */ 853 static int rt5668_headset_detect(struct snd_soc_component *component, 854 int jack_insert) 855 { 856 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 857 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 858 unsigned int val, count; 859 860 if (jack_insert) { 861 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 862 snd_soc_dapm_sync(dapm); 863 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, 864 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH); 865 866 count = 0; 867 val = snd_soc_component_read(component, RT5668_CBJ_CTRL_2) 868 & RT5668_JACK_TYPE_MASK; 869 while (val == 0 && count < 50) { 870 usleep_range(10000, 15000); 871 val = snd_soc_component_read(component, 872 RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK; 873 count++; 874 } 875 876 switch (val) { 877 case 0x1: 878 case 0x2: 879 rt5668->jack_type = SND_JACK_HEADSET; 880 rt5668_enable_push_button_irq(component, true); 881 break; 882 default: 883 rt5668->jack_type = SND_JACK_HEADPHONE; 884 } 885 886 } else { 887 rt5668_enable_push_button_irq(component, false); 888 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, 889 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW); 890 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 891 snd_soc_dapm_sync(dapm); 892 893 rt5668->jack_type = 0; 894 } 895 896 dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type); 897 return rt5668->jack_type; 898 } 899 900 static irqreturn_t rt5668_irq(int irq, void *data) 901 { 902 struct rt5668_priv *rt5668 = data; 903 904 mod_delayed_work(system_power_efficient_wq, 905 &rt5668->jack_detect_work, msecs_to_jiffies(250)); 906 907 return IRQ_HANDLED; 908 } 909 910 static void rt5668_jd_check_handler(struct work_struct *work) 911 { 912 struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv, 913 jd_check_work.work); 914 915 if (snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL) 916 & RT5668_JDH_RS_MASK) { 917 /* jack out */ 918 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); 919 920 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, 921 SND_JACK_HEADSET | 922 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 923 SND_JACK_BTN_2 | SND_JACK_BTN_3); 924 } else { 925 schedule_delayed_work(&rt5668->jd_check_work, 500); 926 } 927 } 928 929 static int rt5668_set_jack_detect(struct snd_soc_component *component, 930 struct snd_soc_jack *hs_jack, void *data) 931 { 932 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 933 934 switch (rt5668->pdata.jd_src) { 935 case RT5668_JD1: 936 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2, 937 RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL); 938 snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002); 939 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3, 940 RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN); 941 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 942 RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN); 943 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 944 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ); 945 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, 946 RT5668_POW_IRQ | RT5668_POW_JDH | 947 RT5668_POW_ANA, RT5668_POW_IRQ | 948 RT5668_POW_JDH | RT5668_POW_ANA); 949 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2, 950 RT5668_PWR_JDH | RT5668_PWR_JDL, 951 RT5668_PWR_JDH | RT5668_PWR_JDL); 952 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, 953 RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK, 954 RT5668_JD1_EN | RT5668_JD1_POL_NOR); 955 mod_delayed_work(system_power_efficient_wq, 956 &rt5668->jack_detect_work, msecs_to_jiffies(250)); 957 break; 958 959 case RT5668_JD_NULL: 960 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, 961 RT5668_JD1_EN_MASK, RT5668_JD1_DIS); 962 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, 963 RT5668_POW_JDH | RT5668_POW_JDL, 0); 964 break; 965 966 default: 967 dev_warn(component->dev, "Wrong JD source\n"); 968 break; 969 } 970 971 rt5668->hs_jack = hs_jack; 972 973 return 0; 974 } 975 976 static void rt5668_jack_detect_handler(struct work_struct *work) 977 { 978 struct rt5668_priv *rt5668 = 979 container_of(work, struct rt5668_priv, jack_detect_work.work); 980 int val, btn_type; 981 982 if (!rt5668->component || 983 !snd_soc_card_is_instantiated(rt5668->component->card)) { 984 /* card not yet ready, try later */ 985 mod_delayed_work(system_power_efficient_wq, 986 &rt5668->jack_detect_work, msecs_to_jiffies(15)); 987 return; 988 } 989 990 guard(mutex)(&rt5668->calibrate_mutex); 991 992 val = snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL) 993 & RT5668_JDH_RS_MASK; 994 if (!val) { 995 /* jack in */ 996 if (rt5668->jack_type == 0) { 997 /* jack was out, report jack type */ 998 rt5668->jack_type = 999 rt5668_headset_detect(rt5668->component, 1); 1000 } else { 1001 /* jack is already in, report button event */ 1002 rt5668->jack_type = SND_JACK_HEADSET; 1003 btn_type = rt5668_button_detect(rt5668->component); 1004 /** 1005 * rt5668 can report three kinds of button behavior, 1006 * one click, double click and hold. However, 1007 * currently we will report button pressed/released 1008 * event. So all the three button behaviors are 1009 * treated as button pressed. 1010 */ 1011 switch (btn_type) { 1012 case 0x8000: 1013 case 0x4000: 1014 case 0x2000: 1015 rt5668->jack_type |= SND_JACK_BTN_0; 1016 break; 1017 case 0x1000: 1018 case 0x0800: 1019 case 0x0400: 1020 rt5668->jack_type |= SND_JACK_BTN_1; 1021 break; 1022 case 0x0200: 1023 case 0x0100: 1024 case 0x0080: 1025 rt5668->jack_type |= SND_JACK_BTN_2; 1026 break; 1027 case 0x0040: 1028 case 0x0020: 1029 case 0x0010: 1030 rt5668->jack_type |= SND_JACK_BTN_3; 1031 break; 1032 case 0x0000: /* unpressed */ 1033 break; 1034 default: 1035 btn_type = 0; 1036 dev_err(rt5668->component->dev, 1037 "Unexpected button code 0x%04x\n", 1038 btn_type); 1039 break; 1040 } 1041 } 1042 } else { 1043 /* jack out */ 1044 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); 1045 } 1046 1047 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, 1048 SND_JACK_HEADSET | 1049 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1050 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1051 1052 if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1053 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1054 schedule_delayed_work(&rt5668->jd_check_work, 0); 1055 else 1056 cancel_delayed_work_sync(&rt5668->jd_check_work); 1057 } 1058 1059 static const struct snd_kcontrol_new rt5668_snd_controls[] = { 1060 /* Headphone Output Volume */ 1061 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN, 1062 RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv), 1063 1064 /* DAC Digital Volume */ 1065 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL, 1066 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv), 1067 1068 /* IN Boost Volume */ 1069 SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL, 1070 RT5668_BST_CBJ_SFT, 8, 0, bst_tlv), 1071 1072 /* ADC Digital Volume Control */ 1073 SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL, 1074 RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1), 1075 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL, 1076 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv), 1077 1078 /* ADC Boost Volume Control */ 1079 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST, 1080 RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT, 1081 3, 0, adc_bst_tlv), 1082 }; 1083 1084 1085 static int rt5668_div_sel(struct rt5668_priv *rt5668, 1086 int target, const int div[], int size) 1087 { 1088 int i; 1089 1090 if (rt5668->sysclk < target) { 1091 pr_err("sysclk rate %d is too low\n", 1092 rt5668->sysclk); 1093 return 0; 1094 } 1095 1096 for (i = 0; i < size - 1; i++) { 1097 pr_info("div[%d]=%d\n", i, div[i]); 1098 if (target * div[i] == rt5668->sysclk) 1099 return i; 1100 if (target * div[i + 1] > rt5668->sysclk) { 1101 pr_err("can't find div for sysclk %d\n", 1102 rt5668->sysclk); 1103 return i; 1104 } 1105 } 1106 1107 if (target * div[i] < rt5668->sysclk) 1108 pr_err("sysclk rate %d is too high\n", 1109 rt5668->sysclk); 1110 1111 return size - 1; 1112 1113 } 1114 1115 /** 1116 * set_dmic_clk - Set parameter of dmic. 1117 * 1118 * @w: DAPM widget. 1119 * @kcontrol: The kcontrol of this widget. 1120 * @event: Event id. 1121 * 1122 * Choose dmic clock between 1MHz and 3MHz. 1123 * It is better for clock to approximate 3MHz. 1124 */ 1125 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1126 struct snd_kcontrol *kcontrol, int event) 1127 { 1128 struct snd_soc_component *component = 1129 snd_soc_dapm_to_component(w->dapm); 1130 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1131 int idx; 1132 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1133 1134 idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div)); 1135 1136 snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1, 1137 RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT); 1138 1139 return 0; 1140 } 1141 1142 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1143 struct snd_kcontrol *kcontrol, int event) 1144 { 1145 struct snd_soc_component *component = 1146 snd_soc_dapm_to_component(w->dapm); 1147 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1148 int ref, val, reg, idx; 1149 static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1150 1151 val = snd_soc_component_read(component, RT5668_GPIO_CTRL_1) & 1152 RT5668_GP4_PIN_MASK; 1153 if (w->shift == RT5668_PWR_ADC_S1F_BIT && 1154 val == RT5668_GP4_PIN_ADCDAT2) 1155 ref = 256 * rt5668->lrck[RT5668_AIF2]; 1156 else 1157 ref = 256 * rt5668->lrck[RT5668_AIF1]; 1158 1159 idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div)); 1160 1161 if (w->shift == RT5668_PWR_ADC_S1F_BIT) 1162 reg = RT5668_PLL_TRACK_3; 1163 else 1164 reg = RT5668_PLL_TRACK_2; 1165 1166 snd_soc_component_update_bits(component, reg, 1167 RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT); 1168 1169 return 0; 1170 } 1171 1172 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1173 struct snd_soc_dapm_widget *sink) 1174 { 1175 unsigned int val; 1176 struct snd_soc_component *component = 1177 snd_soc_dapm_to_component(w->dapm); 1178 1179 val = snd_soc_component_read(component, RT5668_GLB_CLK); 1180 val &= RT5668_SCLK_SRC_MASK; 1181 if (val == RT5668_SCLK_SRC_PLL1) 1182 return 1; 1183 else 1184 return 0; 1185 } 1186 1187 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1188 struct snd_soc_dapm_widget *sink) 1189 { 1190 unsigned int reg, shift, val; 1191 struct snd_soc_component *component = 1192 snd_soc_dapm_to_component(w->dapm); 1193 1194 switch (w->shift) { 1195 case RT5668_ADC_STO1_ASRC_SFT: 1196 reg = RT5668_PLL_TRACK_3; 1197 shift = RT5668_FILTER_CLK_SEL_SFT; 1198 break; 1199 case RT5668_DAC_STO1_ASRC_SFT: 1200 reg = RT5668_PLL_TRACK_2; 1201 shift = RT5668_FILTER_CLK_SEL_SFT; 1202 break; 1203 default: 1204 return 0; 1205 } 1206 1207 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1208 switch (val) { 1209 case RT5668_CLK_SEL_I2S1_ASRC: 1210 case RT5668_CLK_SEL_I2S2_ASRC: 1211 return 1; 1212 default: 1213 return 0; 1214 } 1215 1216 } 1217 1218 /* Digital Mixer */ 1219 static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = { 1220 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, 1221 RT5668_M_STO1_ADC_L1_SFT, 1, 1), 1222 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, 1223 RT5668_M_STO1_ADC_L2_SFT, 1, 1), 1224 }; 1225 1226 static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = { 1227 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, 1228 RT5668_M_STO1_ADC_R1_SFT, 1, 1), 1229 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, 1230 RT5668_M_STO1_ADC_R2_SFT, 1, 1), 1231 }; 1232 1233 static const struct snd_kcontrol_new rt5668_dac_l_mix[] = { 1234 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, 1235 RT5668_M_ADCMIX_L_SFT, 1, 1), 1236 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, 1237 RT5668_M_DAC1_L_SFT, 1, 1), 1238 }; 1239 1240 static const struct snd_kcontrol_new rt5668_dac_r_mix[] = { 1241 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, 1242 RT5668_M_ADCMIX_R_SFT, 1, 1), 1243 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, 1244 RT5668_M_DAC1_R_SFT, 1, 1), 1245 }; 1246 1247 static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = { 1248 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, 1249 RT5668_M_DAC_L1_STO_L_SFT, 1, 1), 1250 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, 1251 RT5668_M_DAC_R1_STO_L_SFT, 1, 1), 1252 }; 1253 1254 static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = { 1255 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, 1256 RT5668_M_DAC_L1_STO_R_SFT, 1, 1), 1257 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, 1258 RT5668_M_DAC_R1_STO_R_SFT, 1, 1), 1259 }; 1260 1261 /* Analog Input Mixer */ 1262 static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = { 1263 SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER, 1264 RT5668_M_CBJ_RM1_L_SFT, 1, 1), 1265 }; 1266 1267 /* STO1 ADC1 Source */ 1268 /* MX-26 [13] [5] */ 1269 static const char * const rt5668_sto1_adc1_src[] = { 1270 "DAC MIX", "ADC" 1271 }; 1272 1273 static SOC_ENUM_SINGLE_DECL( 1274 rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER, 1275 RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src); 1276 1277 static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux = 1278 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum); 1279 1280 static SOC_ENUM_SINGLE_DECL( 1281 rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER, 1282 RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src); 1283 1284 static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux = 1285 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum); 1286 1287 /* STO1 ADC Source */ 1288 /* MX-26 [11:10] [3:2] */ 1289 static const char * const rt5668_sto1_adc_src[] = { 1290 "ADC1 L", "ADC1 R" 1291 }; 1292 1293 static SOC_ENUM_SINGLE_DECL( 1294 rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER, 1295 RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src); 1296 1297 static const struct snd_kcontrol_new rt5668_sto1_adcl_mux = 1298 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum); 1299 1300 static SOC_ENUM_SINGLE_DECL( 1301 rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER, 1302 RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src); 1303 1304 static const struct snd_kcontrol_new rt5668_sto1_adcr_mux = 1305 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum); 1306 1307 /* STO1 ADC2 Source */ 1308 /* MX-26 [12] [4] */ 1309 static const char * const rt5668_sto1_adc2_src[] = { 1310 "DAC MIX", "DMIC" 1311 }; 1312 1313 static SOC_ENUM_SINGLE_DECL( 1314 rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER, 1315 RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src); 1316 1317 static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux = 1318 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum); 1319 1320 static SOC_ENUM_SINGLE_DECL( 1321 rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER, 1322 RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src); 1323 1324 static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux = 1325 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum); 1326 1327 /* MX-79 [6:4] I2S1 ADC data location */ 1328 static const unsigned int rt5668_if1_adc_slot_values[] = { 1329 0, 1330 2, 1331 4, 1332 6, 1333 }; 1334 1335 static const char * const rt5668_if1_adc_slot_src[] = { 1336 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1337 }; 1338 1339 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum, 1340 RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK, 1341 rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values); 1342 1343 static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux = 1344 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum); 1345 1346 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1347 /* MX-2B [4], MX-2B [0]*/ 1348 static const char * const rt5668_alg_dac1_src[] = { 1349 "Stereo1 DAC Mixer", "DAC1" 1350 }; 1351 1352 static SOC_ENUM_SINGLE_DECL( 1353 rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX, 1354 RT5668_A_DACL1_SFT, rt5668_alg_dac1_src); 1355 1356 static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux = 1357 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum); 1358 1359 static SOC_ENUM_SINGLE_DECL( 1360 rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX, 1361 RT5668_A_DACR1_SFT, rt5668_alg_dac1_src); 1362 1363 static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux = 1364 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum); 1365 1366 /* Out Switch */ 1367 static const struct snd_kcontrol_new hpol_switch = 1368 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, 1369 RT5668_L_MUTE_SFT, 1, 1); 1370 static const struct snd_kcontrol_new hpor_switch = 1371 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, 1372 RT5668_R_MUTE_SFT, 1, 1); 1373 1374 static int rt5668_hp_event(struct snd_soc_dapm_widget *w, 1375 struct snd_kcontrol *kcontrol, int event) 1376 { 1377 struct snd_soc_component *component = 1378 snd_soc_dapm_to_component(w->dapm); 1379 1380 switch (event) { 1381 case SND_SOC_DAPM_PRE_PMU: 1382 snd_soc_component_write(component, 1383 RT5668_HP_LOGIC_CTRL_2, 0x0012); 1384 snd_soc_component_write(component, 1385 RT5668_HP_CTRL_2, 0x6000); 1386 snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1, 1387 RT5668_NG2_EN_MASK, RT5668_NG2_EN); 1388 snd_soc_component_update_bits(component, 1389 RT5668_DEPOP_1, 0x60, 0x60); 1390 break; 1391 1392 case SND_SOC_DAPM_POST_PMD: 1393 snd_soc_component_update_bits(component, 1394 RT5668_DEPOP_1, 0x60, 0x0); 1395 snd_soc_component_write(component, 1396 RT5668_HP_CTRL_2, 0x0000); 1397 break; 1398 1399 default: 1400 return 0; 1401 } 1402 1403 return 0; 1404 1405 } 1406 1407 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1408 struct snd_kcontrol *kcontrol, int event) 1409 { 1410 switch (event) { 1411 case SND_SOC_DAPM_POST_PMU: 1412 /*Add delay to avoid pop noise*/ 1413 msleep(150); 1414 break; 1415 1416 default: 1417 return 0; 1418 } 1419 1420 return 0; 1421 } 1422 1423 static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1424 struct snd_kcontrol *kcontrol, int event) 1425 { 1426 struct snd_soc_component *component = 1427 snd_soc_dapm_to_component(w->dapm); 1428 1429 switch (event) { 1430 case SND_SOC_DAPM_PRE_PMU: 1431 switch (w->shift) { 1432 case RT5668_PWR_VREF1_BIT: 1433 snd_soc_component_update_bits(component, 1434 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0); 1435 break; 1436 1437 case RT5668_PWR_VREF2_BIT: 1438 snd_soc_component_update_bits(component, 1439 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0); 1440 break; 1441 1442 default: 1443 break; 1444 } 1445 break; 1446 1447 case SND_SOC_DAPM_POST_PMU: 1448 usleep_range(15000, 20000); 1449 switch (w->shift) { 1450 case RT5668_PWR_VREF1_BIT: 1451 snd_soc_component_update_bits(component, 1452 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 1453 RT5668_PWR_FV1); 1454 break; 1455 1456 case RT5668_PWR_VREF2_BIT: 1457 snd_soc_component_update_bits(component, 1458 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 1459 RT5668_PWR_FV2); 1460 break; 1461 1462 default: 1463 break; 1464 } 1465 break; 1466 1467 default: 1468 return 0; 1469 } 1470 1471 return 0; 1472 } 1473 1474 static const unsigned int rt5668_adcdat_pin_values[] = { 1475 1, 1476 3, 1477 }; 1478 1479 static const char * const rt5668_adcdat_pin_select[] = { 1480 "ADCDAT1", 1481 "ADCDAT2", 1482 }; 1483 1484 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum, 1485 RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK, 1486 rt5668_adcdat_pin_select, rt5668_adcdat_pin_values); 1487 1488 static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl = 1489 SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum); 1490 1491 static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = { 1492 SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT, 1493 0, NULL, 0), 1494 SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT, 1495 0, NULL, 0), 1496 SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT, 1497 0, NULL, 0), 1498 SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT, 1499 0, NULL, 0), 1500 SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0, 1501 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1502 SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0, 1503 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1504 1505 /* ASRC */ 1506 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1, 1507 RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1508 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1, 1509 RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1510 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1, 1511 RT5668_AD_ASRC_SFT, 0, NULL, 0), 1512 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1, 1513 RT5668_DA_ASRC_SFT, 0, NULL, 0), 1514 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1, 1515 RT5668_DMIC_ASRC_SFT, 0, NULL, 0), 1516 1517 /* Input Side */ 1518 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT, 1519 0, NULL, 0), 1520 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT, 1521 0, NULL, 0), 1522 1523 /* Input Lines */ 1524 SND_SOC_DAPM_INPUT("DMIC L1"), 1525 SND_SOC_DAPM_INPUT("DMIC R1"), 1526 1527 SND_SOC_DAPM_INPUT("IN1P"), 1528 1529 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1530 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1531 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1, 1532 RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1533 1534 /* Boost */ 1535 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1536 0, 0, NULL, 0), 1537 1538 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3, 1539 RT5668_PWR_CBJ_BIT, 0, NULL, 0), 1540 1541 /* REC Mixer */ 1542 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix, 1543 ARRAY_SIZE(rt5668_rec1_l_mix)), 1544 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2, 1545 RT5668_PWR_RM1_L_BIT, 0, NULL, 0), 1546 1547 /* ADCs */ 1548 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1549 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1550 1551 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1, 1552 RT5668_PWR_ADC_L1_BIT, 0, NULL, 0), 1553 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1, 1554 RT5668_PWR_ADC_R1_BIT, 0, NULL, 0), 1555 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC, 1556 RT5668_CKGEN_ADC1_SFT, 0, NULL, 0), 1557 1558 /* ADC Mux */ 1559 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1560 &rt5668_sto1_adc1l_mux), 1561 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1562 &rt5668_sto1_adc1r_mux), 1563 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1564 &rt5668_sto1_adc2l_mux), 1565 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1566 &rt5668_sto1_adc2r_mux), 1567 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1568 &rt5668_sto1_adcl_mux), 1569 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1570 &rt5668_sto1_adcr_mux), 1571 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1572 &rt5668_if1_adc_slot_mux), 1573 1574 /* ADC Mixer */ 1575 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2, 1576 RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1577 SND_SOC_DAPM_PRE_PMU), 1578 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL, 1579 RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix, 1580 ARRAY_SIZE(rt5668_sto1_adc_l_mix)), 1581 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL, 1582 RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix, 1583 ARRAY_SIZE(rt5668_sto1_adc_r_mix)), 1584 1585 /* ADC PGA */ 1586 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1587 1588 /* Digital Interface */ 1589 SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT, 1590 0, NULL, 0), 1591 SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT, 1592 0, NULL, 0), 1593 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1594 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1595 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1596 1597 /* Digital Interface Select */ 1598 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1599 &rt5668_if1_01_adc_swap_mux), 1600 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1601 &rt5668_if1_23_adc_swap_mux), 1602 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1603 &rt5668_if1_45_adc_swap_mux), 1604 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1605 &rt5668_if1_67_adc_swap_mux), 1606 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1607 &rt5668_if2_adc_swap_mux), 1608 1609 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1610 &rt5668_adcdat_pin_ctrl), 1611 1612 /* Audio Interface */ 1613 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1614 RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1), 1615 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1616 RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1), 1617 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1618 1619 /* Output Side */ 1620 /* DAC mixer before sound effect */ 1621 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1622 rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)), 1623 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1624 rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)), 1625 1626 /* DAC channel Mux */ 1627 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1628 &rt5668_alg_dac_l1_mux), 1629 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1630 &rt5668_alg_dac_r1_mux), 1631 1632 /* DAC Mixer */ 1633 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2, 1634 RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1635 SND_SOC_DAPM_PRE_PMU), 1636 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1637 rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)), 1638 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1639 rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)), 1640 1641 /* DACs */ 1642 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1, 1643 RT5668_PWR_DAC_L1_BIT, 0), 1644 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1, 1645 RT5668_PWR_DAC_R1_BIT, 0), 1646 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC, 1647 RT5668_CKGEN_DAC1_SFT, 0, NULL, 0), 1648 1649 /* HPO */ 1650 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event, 1651 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1652 1653 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1, 1654 RT5668_PWR_HA_L_BIT, 0, NULL, 0), 1655 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1, 1656 RT5668_PWR_HA_R_BIT, 0, NULL, 0), 1657 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1, 1658 RT5668_PUMP_EN_SFT, 0, NULL, 0), 1659 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1, 1660 RT5668_CAPLESS_EN_SFT, 0, NULL, 0), 1661 1662 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1663 &hpol_switch), 1664 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1665 &hpor_switch), 1666 1667 /* CLK DET */ 1668 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET, 1669 RT5668_SYS_CLK_DET_SFT, 0, NULL, 0), 1670 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET, 1671 RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0), 1672 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET, 1673 RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0), 1674 SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET, 1675 RT5668_POW_CLK_DET_SFT, 0, NULL, 0), 1676 1677 /* Output Lines */ 1678 SND_SOC_DAPM_OUTPUT("HPOL"), 1679 SND_SOC_DAPM_OUTPUT("HPOR"), 1680 1681 }; 1682 1683 static const struct snd_soc_dapm_route rt5668_dapm_routes[] = { 1684 /*PLL*/ 1685 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1686 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1687 1688 /*ASRC*/ 1689 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1690 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1691 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1692 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1693 1694 /*Vref*/ 1695 {"MICBIAS1", NULL, "Vref1"}, 1696 {"MICBIAS1", NULL, "Vref2"}, 1697 {"MICBIAS2", NULL, "Vref1"}, 1698 {"MICBIAS2", NULL, "Vref2"}, 1699 1700 {"CLKDET SYS", NULL, "CLKDET"}, 1701 1702 {"IN1P", NULL, "LDO2"}, 1703 1704 {"BST1 CBJ", NULL, "IN1P"}, 1705 {"BST1 CBJ", NULL, "CBJ Power"}, 1706 {"CBJ Power", NULL, "Vref2"}, 1707 1708 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1709 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1710 1711 {"ADC1 L", NULL, "RECMIX1L"}, 1712 {"ADC1 L", NULL, "ADC1 L Power"}, 1713 {"ADC1 L", NULL, "ADC1 clock"}, 1714 1715 {"DMIC L1", NULL, "DMIC CLK"}, 1716 {"DMIC L1", NULL, "DMIC1 Power"}, 1717 {"DMIC R1", NULL, "DMIC CLK"}, 1718 {"DMIC R1", NULL, "DMIC1 Power"}, 1719 {"DMIC CLK", NULL, "DMIC ASRC"}, 1720 1721 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1722 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1723 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1724 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1725 1726 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1727 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1728 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1729 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1730 1731 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1732 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1733 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1734 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1735 1736 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1737 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1738 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1739 1740 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1741 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1742 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1743 1744 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1745 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1746 1747 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1748 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1749 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1750 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1751 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1752 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1753 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1754 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1755 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1756 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1757 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1758 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1759 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1760 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1761 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1762 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1763 1764 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1765 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1766 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1767 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1768 {"IF1_ADC Mux", NULL, "I2S1"}, 1769 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1770 {"AIF1TX", NULL, "ADCDAT Mux"}, 1771 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1772 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1773 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1774 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1775 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1776 {"AIF2TX", NULL, "ADCDAT Mux"}, 1777 1778 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1779 {"IF1 DAC1 L", NULL, "I2S1"}, 1780 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1781 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1782 {"IF1 DAC1 R", NULL, "I2S1"}, 1783 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1784 1785 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1786 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1787 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1788 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1789 1790 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1791 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1792 1793 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1794 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1795 1796 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1797 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1798 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1799 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1800 1801 {"DAC L1", NULL, "DAC L1 Source"}, 1802 {"DAC R1", NULL, "DAC R1 Source"}, 1803 1804 {"DAC L1", NULL, "DAC 1 Clock"}, 1805 {"DAC R1", NULL, "DAC 1 Clock"}, 1806 1807 {"HP Amp", NULL, "DAC L1"}, 1808 {"HP Amp", NULL, "DAC R1"}, 1809 {"HP Amp", NULL, "HP Amp L"}, 1810 {"HP Amp", NULL, "HP Amp R"}, 1811 {"HP Amp", NULL, "Capless"}, 1812 {"HP Amp", NULL, "Charge Pump"}, 1813 {"HP Amp", NULL, "CLKDET SYS"}, 1814 {"HP Amp", NULL, "CBJ Power"}, 1815 {"HP Amp", NULL, "Vref2"}, 1816 {"HPOL Playback", "Switch", "HP Amp"}, 1817 {"HPOR Playback", "Switch", "HP Amp"}, 1818 {"HPOL", NULL, "HPOL Playback"}, 1819 {"HPOR", NULL, "HPOR Playback"}, 1820 }; 1821 1822 static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1823 unsigned int rx_mask, int slots, int slot_width) 1824 { 1825 struct snd_soc_component *component = dai->component; 1826 unsigned int val = 0; 1827 1828 switch (slots) { 1829 case 4: 1830 val |= RT5668_TDM_TX_CH_4; 1831 val |= RT5668_TDM_RX_CH_4; 1832 break; 1833 case 6: 1834 val |= RT5668_TDM_TX_CH_6; 1835 val |= RT5668_TDM_RX_CH_6; 1836 break; 1837 case 8: 1838 val |= RT5668_TDM_TX_CH_8; 1839 val |= RT5668_TDM_RX_CH_8; 1840 break; 1841 case 2: 1842 break; 1843 default: 1844 return -EINVAL; 1845 } 1846 1847 snd_soc_component_update_bits(component, RT5668_TDM_CTRL, 1848 RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val); 1849 1850 switch (slot_width) { 1851 case 16: 1852 val = RT5668_TDM_CL_16; 1853 break; 1854 case 20: 1855 val = RT5668_TDM_CL_20; 1856 break; 1857 case 24: 1858 val = RT5668_TDM_CL_24; 1859 break; 1860 case 32: 1861 val = RT5668_TDM_CL_32; 1862 break; 1863 default: 1864 return -EINVAL; 1865 } 1866 1867 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, 1868 RT5668_TDM_CL_MASK, val); 1869 1870 return 0; 1871 } 1872 1873 1874 static int rt5668_hw_params(struct snd_pcm_substream *substream, 1875 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1876 { 1877 struct snd_soc_component *component = dai->component; 1878 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1879 unsigned int len_1 = 0, len_2 = 0; 1880 int pre_div, frame_size; 1881 1882 rt5668->lrck[dai->id] = params_rate(params); 1883 pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]); 1884 1885 frame_size = snd_soc_params_to_frame_size(params); 1886 if (frame_size < 0) { 1887 dev_err(component->dev, "Unsupported frame size: %d\n", 1888 frame_size); 1889 return -EINVAL; 1890 } 1891 1892 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 1893 rt5668->lrck[dai->id], pre_div, dai->id); 1894 1895 switch (params_width(params)) { 1896 case 16: 1897 break; 1898 case 20: 1899 len_1 |= RT5668_I2S1_DL_20; 1900 len_2 |= RT5668_I2S2_DL_20; 1901 break; 1902 case 24: 1903 len_1 |= RT5668_I2S1_DL_24; 1904 len_2 |= RT5668_I2S2_DL_24; 1905 break; 1906 case 32: 1907 len_1 |= RT5668_I2S1_DL_32; 1908 len_2 |= RT5668_I2S2_DL_24; 1909 break; 1910 case 8: 1911 len_1 |= RT5668_I2S2_DL_8; 1912 len_2 |= RT5668_I2S2_DL_8; 1913 break; 1914 default: 1915 return -EINVAL; 1916 } 1917 1918 switch (dai->id) { 1919 case RT5668_AIF1: 1920 snd_soc_component_update_bits(component, RT5668_I2S1_SDP, 1921 RT5668_I2S1_DL_MASK, len_1); 1922 if (rt5668->master[RT5668_AIF1]) { 1923 snd_soc_component_update_bits(component, 1924 RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK, 1925 pre_div << RT5668_I2S_M_DIV_SFT); 1926 } 1927 if (params_channels(params) == 1) /* mono mode */ 1928 snd_soc_component_update_bits(component, 1929 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, 1930 RT5668_I2S1_MONO_EN); 1931 else 1932 snd_soc_component_update_bits(component, 1933 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, 1934 RT5668_I2S1_MONO_DIS); 1935 break; 1936 case RT5668_AIF2: 1937 snd_soc_component_update_bits(component, RT5668_I2S2_SDP, 1938 RT5668_I2S2_DL_MASK, len_2); 1939 if (rt5668->master[RT5668_AIF2]) { 1940 snd_soc_component_update_bits(component, 1941 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK, 1942 pre_div << RT5668_I2S2_M_PD_SFT); 1943 } 1944 if (params_channels(params) == 1) /* mono mode */ 1945 snd_soc_component_update_bits(component, 1946 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, 1947 RT5668_I2S2_MONO_EN); 1948 else 1949 snd_soc_component_update_bits(component, 1950 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, 1951 RT5668_I2S2_MONO_DIS); 1952 break; 1953 default: 1954 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 1955 return -EINVAL; 1956 } 1957 1958 return 0; 1959 } 1960 1961 static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1962 { 1963 struct snd_soc_component *component = dai->component; 1964 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1965 unsigned int reg_val = 0, tdm_ctrl = 0; 1966 1967 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1968 case SND_SOC_DAIFMT_CBP_CFP: 1969 rt5668->master[dai->id] = 1; 1970 break; 1971 case SND_SOC_DAIFMT_CBC_CFC: 1972 rt5668->master[dai->id] = 0; 1973 break; 1974 default: 1975 return -EINVAL; 1976 } 1977 1978 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1979 case SND_SOC_DAIFMT_NB_NF: 1980 break; 1981 case SND_SOC_DAIFMT_IB_NF: 1982 reg_val |= RT5668_I2S_BP_INV; 1983 tdm_ctrl |= RT5668_TDM_S_BP_INV; 1984 break; 1985 case SND_SOC_DAIFMT_NB_IF: 1986 if (dai->id == RT5668_AIF1) 1987 tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV; 1988 else 1989 return -EINVAL; 1990 break; 1991 case SND_SOC_DAIFMT_IB_IF: 1992 if (dai->id == RT5668_AIF1) 1993 tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV | 1994 RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV; 1995 else 1996 return -EINVAL; 1997 break; 1998 default: 1999 return -EINVAL; 2000 } 2001 2002 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2003 case SND_SOC_DAIFMT_I2S: 2004 break; 2005 case SND_SOC_DAIFMT_LEFT_J: 2006 reg_val |= RT5668_I2S_DF_LEFT; 2007 tdm_ctrl |= RT5668_TDM_DF_LEFT; 2008 break; 2009 case SND_SOC_DAIFMT_DSP_A: 2010 reg_val |= RT5668_I2S_DF_PCM_A; 2011 tdm_ctrl |= RT5668_TDM_DF_PCM_A; 2012 break; 2013 case SND_SOC_DAIFMT_DSP_B: 2014 reg_val |= RT5668_I2S_DF_PCM_B; 2015 tdm_ctrl |= RT5668_TDM_DF_PCM_B; 2016 break; 2017 default: 2018 return -EINVAL; 2019 } 2020 2021 switch (dai->id) { 2022 case RT5668_AIF1: 2023 snd_soc_component_update_bits(component, RT5668_I2S1_SDP, 2024 RT5668_I2S_DF_MASK, reg_val); 2025 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, 2026 RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK | 2027 RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK | 2028 RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK, 2029 tdm_ctrl | rt5668->master[dai->id]); 2030 break; 2031 case RT5668_AIF2: 2032 if (rt5668->master[dai->id] == 0) 2033 reg_val |= RT5668_I2S2_MS_S; 2034 snd_soc_component_update_bits(component, RT5668_I2S2_SDP, 2035 RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK | 2036 RT5668_I2S_DF_MASK, reg_val); 2037 break; 2038 default: 2039 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2040 return -EINVAL; 2041 } 2042 return 0; 2043 } 2044 2045 static int rt5668_set_component_sysclk(struct snd_soc_component *component, 2046 int clk_id, int source, unsigned int freq, int dir) 2047 { 2048 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2049 unsigned int reg_val = 0, src = 0; 2050 2051 if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src) 2052 return 0; 2053 2054 switch (clk_id) { 2055 case RT5668_SCLK_S_MCLK: 2056 reg_val |= RT5668_SCLK_SRC_MCLK; 2057 src = RT5668_CLK_SRC_MCLK; 2058 break; 2059 case RT5668_SCLK_S_PLL1: 2060 reg_val |= RT5668_SCLK_SRC_PLL1; 2061 src = RT5668_CLK_SRC_PLL1; 2062 break; 2063 case RT5668_SCLK_S_PLL2: 2064 reg_val |= RT5668_SCLK_SRC_PLL2; 2065 src = RT5668_CLK_SRC_PLL2; 2066 break; 2067 case RT5668_SCLK_S_RCCLK: 2068 reg_val |= RT5668_SCLK_SRC_RCCLK; 2069 src = RT5668_CLK_SRC_RCCLK; 2070 break; 2071 default: 2072 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2073 return -EINVAL; 2074 } 2075 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2076 RT5668_SCLK_SRC_MASK, reg_val); 2077 2078 if (rt5668->master[RT5668_AIF2]) { 2079 snd_soc_component_update_bits(component, 2080 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK, 2081 src << RT5668_I2S2_SRC_SFT); 2082 } 2083 2084 rt5668->sysclk = freq; 2085 rt5668->sysclk_src = clk_id; 2086 2087 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2088 freq, clk_id); 2089 2090 return 0; 2091 } 2092 2093 static int rt5668_set_component_pll(struct snd_soc_component *component, 2094 int pll_id, int source, unsigned int freq_in, 2095 unsigned int freq_out) 2096 { 2097 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2098 struct rl6231_pll_code pll_code; 2099 int ret; 2100 2101 if (source == rt5668->pll_src && freq_in == rt5668->pll_in && 2102 freq_out == rt5668->pll_out) 2103 return 0; 2104 2105 if (!freq_in || !freq_out) { 2106 dev_dbg(component->dev, "PLL disabled\n"); 2107 2108 rt5668->pll_in = 0; 2109 rt5668->pll_out = 0; 2110 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2111 RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK); 2112 return 0; 2113 } 2114 2115 switch (source) { 2116 case RT5668_PLL1_S_MCLK: 2117 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2118 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK); 2119 break; 2120 case RT5668_PLL1_S_BCLK1: 2121 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2122 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1); 2123 break; 2124 default: 2125 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2126 return -EINVAL; 2127 } 2128 2129 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2130 if (ret < 0) { 2131 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2132 return ret; 2133 } 2134 2135 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2136 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2137 pll_code.n_code, pll_code.k_code); 2138 2139 snd_soc_component_write(component, RT5668_PLL_CTRL_1, 2140 pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code); 2141 snd_soc_component_write(component, RT5668_PLL_CTRL_2, 2142 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT) | 2143 (pll_code.m_bp << RT5668_PLL_M_BP_SFT)); 2144 2145 rt5668->pll_in = freq_in; 2146 rt5668->pll_out = freq_out; 2147 rt5668->pll_src = source; 2148 2149 return 0; 2150 } 2151 2152 static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2153 { 2154 struct snd_soc_component *component = dai->component; 2155 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2156 2157 rt5668->bclk[dai->id] = ratio; 2158 2159 switch (ratio) { 2160 case 64: 2161 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, 2162 RT5668_I2S2_BCLK_MS2_MASK, 2163 RT5668_I2S2_BCLK_MS2_64); 2164 break; 2165 case 32: 2166 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, 2167 RT5668_I2S2_BCLK_MS2_MASK, 2168 RT5668_I2S2_BCLK_MS2_32); 2169 break; 2170 default: 2171 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2172 return -EINVAL; 2173 } 2174 2175 return 0; 2176 } 2177 2178 static int rt5668_set_bias_level(struct snd_soc_component *component, 2179 enum snd_soc_bias_level level) 2180 { 2181 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2182 2183 switch (level) { 2184 case SND_SOC_BIAS_PREPARE: 2185 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2186 RT5668_PWR_MB | RT5668_PWR_BG, 2187 RT5668_PWR_MB | RT5668_PWR_BG); 2188 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2189 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 2190 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO); 2191 break; 2192 2193 case SND_SOC_BIAS_STANDBY: 2194 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2195 RT5668_PWR_MB, RT5668_PWR_MB); 2196 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2197 RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL); 2198 break; 2199 case SND_SOC_BIAS_OFF: 2200 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2201 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0); 2202 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2203 RT5668_PWR_MB | RT5668_PWR_BG, 0); 2204 break; 2205 2206 default: 2207 break; 2208 } 2209 2210 return 0; 2211 } 2212 2213 static int rt5668_probe(struct snd_soc_component *component) 2214 { 2215 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2216 2217 rt5668->component = component; 2218 2219 return 0; 2220 } 2221 2222 static void rt5668_remove(struct snd_soc_component *component) 2223 { 2224 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2225 2226 rt5668_reset(rt5668->regmap); 2227 } 2228 2229 #ifdef CONFIG_PM 2230 static int rt5668_suspend(struct snd_soc_component *component) 2231 { 2232 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2233 2234 regcache_cache_only(rt5668->regmap, true); 2235 regcache_mark_dirty(rt5668->regmap); 2236 return 0; 2237 } 2238 2239 static int rt5668_resume(struct snd_soc_component *component) 2240 { 2241 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2242 2243 regcache_cache_only(rt5668->regmap, false); 2244 regcache_sync(rt5668->regmap); 2245 2246 return 0; 2247 } 2248 #else 2249 #define rt5668_suspend NULL 2250 #define rt5668_resume NULL 2251 #endif 2252 2253 #define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2254 #define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2255 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2256 2257 static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = { 2258 .hw_params = rt5668_hw_params, 2259 .set_fmt = rt5668_set_dai_fmt, 2260 .set_tdm_slot = rt5668_set_tdm_slot, 2261 }; 2262 2263 static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = { 2264 .hw_params = rt5668_hw_params, 2265 .set_fmt = rt5668_set_dai_fmt, 2266 .set_bclk_ratio = rt5668_set_bclk_ratio, 2267 }; 2268 2269 static struct snd_soc_dai_driver rt5668_dai[] = { 2270 { 2271 .name = "rt5668-aif1", 2272 .id = RT5668_AIF1, 2273 .playback = { 2274 .stream_name = "AIF1 Playback", 2275 .channels_min = 1, 2276 .channels_max = 2, 2277 .rates = RT5668_STEREO_RATES, 2278 .formats = RT5668_FORMATS, 2279 }, 2280 .capture = { 2281 .stream_name = "AIF1 Capture", 2282 .channels_min = 1, 2283 .channels_max = 2, 2284 .rates = RT5668_STEREO_RATES, 2285 .formats = RT5668_FORMATS, 2286 }, 2287 .ops = &rt5668_aif1_dai_ops, 2288 }, 2289 { 2290 .name = "rt5668-aif2", 2291 .id = RT5668_AIF2, 2292 .capture = { 2293 .stream_name = "AIF2 Capture", 2294 .channels_min = 1, 2295 .channels_max = 2, 2296 .rates = RT5668_STEREO_RATES, 2297 .formats = RT5668_FORMATS, 2298 }, 2299 .ops = &rt5668_aif2_dai_ops, 2300 }, 2301 }; 2302 2303 static const struct snd_soc_component_driver soc_component_dev_rt5668 = { 2304 .probe = rt5668_probe, 2305 .remove = rt5668_remove, 2306 .suspend = rt5668_suspend, 2307 .resume = rt5668_resume, 2308 .set_bias_level = rt5668_set_bias_level, 2309 .controls = rt5668_snd_controls, 2310 .num_controls = ARRAY_SIZE(rt5668_snd_controls), 2311 .dapm_widgets = rt5668_dapm_widgets, 2312 .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets), 2313 .dapm_routes = rt5668_dapm_routes, 2314 .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes), 2315 .set_sysclk = rt5668_set_component_sysclk, 2316 .set_pll = rt5668_set_component_pll, 2317 .set_jack = rt5668_set_jack_detect, 2318 .use_pmdown_time = 1, 2319 .endianness = 1, 2320 }; 2321 2322 static const struct regmap_config rt5668_regmap = { 2323 .reg_bits = 16, 2324 .val_bits = 16, 2325 .max_register = RT5668_I2C_MODE, 2326 .volatile_reg = rt5668_volatile_register, 2327 .readable_reg = rt5668_readable_register, 2328 .cache_type = REGCACHE_MAPLE, 2329 .reg_defaults = rt5668_reg, 2330 .num_reg_defaults = ARRAY_SIZE(rt5668_reg), 2331 .use_single_read = true, 2332 .use_single_write = true, 2333 }; 2334 2335 static const struct i2c_device_id rt5668_i2c_id[] = { 2336 { .name = "rt5668b" }, 2337 { } 2338 }; 2339 MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id); 2340 2341 static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev) 2342 { 2343 2344 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", 2345 &rt5668->pdata.dmic1_data_pin); 2346 of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin", 2347 &rt5668->pdata.dmic1_clk_pin); 2348 of_property_read_u32(dev->of_node, "realtek,jd-src", 2349 &rt5668->pdata.jd_src); 2350 2351 return 0; 2352 } 2353 2354 static void rt5668_calibrate(struct rt5668_priv *rt5668) 2355 { 2356 int value, count; 2357 2358 guard(mutex)(&rt5668->calibrate_mutex); 2359 2360 rt5668_reset(rt5668->regmap); 2361 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf); 2362 usleep_range(15000, 20000); 2363 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf); 2364 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); 2365 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001); 2366 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); 2367 regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080); 2368 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040); 2369 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069); 2370 regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000); 2371 regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000); 2372 regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26); 2373 regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05); 2374 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c); 2375 regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d); 2376 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f); 2377 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01); 2378 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321); 2379 regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004); 2380 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00); 2381 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1); 2382 regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311); 2383 regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000); 2384 regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320); 2385 2386 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00); 2387 2388 for (count = 0; count < 60; count++) { 2389 regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value); 2390 if (!(value & 0x8000)) 2391 break; 2392 2393 usleep_range(10000, 10005); 2394 } 2395 2396 if (count >= 60) 2397 pr_err("HP Calibration Failure\n"); 2398 2399 /* restore settings */ 2400 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4); 2401 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000); 2402 } 2403 2404 static int rt5668_i2c_probe(struct i2c_client *i2c) 2405 { 2406 struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev); 2407 struct rt5668_priv *rt5668; 2408 int i, ret; 2409 unsigned int val; 2410 2411 rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv), 2412 GFP_KERNEL); 2413 2414 if (rt5668 == NULL) 2415 return -ENOMEM; 2416 2417 i2c_set_clientdata(i2c, rt5668); 2418 2419 if (pdata) 2420 rt5668->pdata = *pdata; 2421 else 2422 rt5668_parse_dt(rt5668, &i2c->dev); 2423 2424 rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap); 2425 if (IS_ERR(rt5668->regmap)) { 2426 ret = PTR_ERR(rt5668->regmap); 2427 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2428 ret); 2429 return ret; 2430 } 2431 2432 for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++) 2433 rt5668->supplies[i].supply = rt5668_supply_names[i]; 2434 2435 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies), 2436 rt5668->supplies); 2437 if (ret != 0) { 2438 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2439 return ret; 2440 } 2441 2442 ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies), 2443 rt5668->supplies); 2444 if (ret != 0) { 2445 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2446 return ret; 2447 } 2448 2449 rt5668->ldo1_en = devm_gpiod_get_optional(&i2c->dev, 2450 "realtek,ldo1-en", 2451 GPIOD_OUT_HIGH); 2452 if (IS_ERR(rt5668->ldo1_en)) { 2453 dev_err(&i2c->dev, "Fail gpio request ldo1_en\n"); 2454 return PTR_ERR(rt5668->ldo1_en); 2455 } 2456 2457 /* Sleep for 300 ms minimum */ 2458 usleep_range(300000, 350000); 2459 2460 regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1); 2461 usleep_range(10000, 15000); 2462 2463 regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val); 2464 if (val != DEVICE_ID) { 2465 pr_err("Device with ID register %x is not rt5668\n", val); 2466 return -ENODEV; 2467 } 2468 2469 rt5668_reset(rt5668->regmap); 2470 2471 rt5668_calibrate(rt5668); 2472 2473 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000); 2474 2475 /* DMIC pin*/ 2476 if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) { 2477 switch (rt5668->pdata.dmic1_data_pin) { 2478 case RT5668_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2479 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, 2480 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2); 2481 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2482 RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA); 2483 break; 2484 2485 case RT5668_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2486 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, 2487 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5); 2488 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2489 RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA); 2490 break; 2491 2492 default: 2493 dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n"); 2494 break; 2495 } 2496 2497 switch (rt5668->pdata.dmic1_clk_pin) { 2498 case RT5668_DMIC1_CLK_GPIO1: /* share with IRQ */ 2499 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2500 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK); 2501 break; 2502 2503 case RT5668_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2504 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2505 RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK); 2506 break; 2507 2508 default: 2509 dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n"); 2510 break; 2511 } 2512 } 2513 2514 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2515 RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK, 2516 RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X); 2517 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); 2518 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2519 RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK, 2520 RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1); 2521 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); 2522 2523 INIT_DELAYED_WORK(&rt5668->jack_detect_work, 2524 rt5668_jack_detect_handler); 2525 INIT_DELAYED_WORK(&rt5668->jd_check_work, 2526 rt5668_jd_check_handler); 2527 2528 mutex_init(&rt5668->calibrate_mutex); 2529 2530 if (i2c->irq) { 2531 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2532 rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2533 | IRQF_ONESHOT, "rt5668", rt5668); 2534 if (ret) 2535 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 2536 2537 } 2538 2539 return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668, 2540 rt5668_dai, ARRAY_SIZE(rt5668_dai)); 2541 } 2542 2543 static void rt5668_i2c_shutdown(struct i2c_client *client) 2544 { 2545 struct rt5668_priv *rt5668 = i2c_get_clientdata(client); 2546 2547 rt5668_reset(rt5668->regmap); 2548 } 2549 2550 #ifdef CONFIG_OF 2551 static const struct of_device_id rt5668_of_match[] = { 2552 {.compatible = "realtek,rt5668b"}, 2553 { } 2554 }; 2555 MODULE_DEVICE_TABLE(of, rt5668_of_match); 2556 #endif 2557 2558 #ifdef CONFIG_ACPI 2559 static const struct acpi_device_id rt5668_acpi_match[] = { 2560 { "10EC5668" }, 2561 { } 2562 }; 2563 MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match); 2564 #endif 2565 2566 static struct i2c_driver rt5668_i2c_driver = { 2567 .driver = { 2568 .name = "rt5668b", 2569 .of_match_table = of_match_ptr(rt5668_of_match), 2570 .acpi_match_table = ACPI_PTR(rt5668_acpi_match), 2571 }, 2572 .probe = rt5668_i2c_probe, 2573 .shutdown = rt5668_i2c_shutdown, 2574 .id_table = rt5668_i2c_id, 2575 }; 2576 module_i2c_driver(rt5668_i2c_driver); 2577 2578 MODULE_DESCRIPTION("ASoC RT5668B driver"); 2579 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2580 MODULE_LICENSE("GPL v2"); 2581