1 /* 2 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver 3 * 4 * Copyright 2016 Realtek Microelectronics 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __RT5665_H__ 13 #define __RT5665_H__ 14 15 #include <sound/rt5665.h> 16 17 #define DEVICE_ID 0x6451 18 19 /* Info */ 20 #define RT5665_RESET 0x0000 21 #define RT5665_VENDOR_ID 0x00fd 22 #define RT5665_VENDOR_ID_1 0x00fe 23 #define RT5665_DEVICE_ID 0x00ff 24 /* I/O - Output */ 25 #define RT5665_LOUT 0x0001 26 #define RT5665_HP_CTRL_1 0x0002 27 #define RT5665_HP_CTRL_2 0x0003 28 #define RT5665_MONO_OUT 0x0004 29 #define RT5665_HPL_GAIN 0x0005 30 #define RT5665_HPR_GAIN 0x0006 31 #define RT5665_MONO_GAIN 0x0007 32 33 /* I/O - Input */ 34 #define RT5665_CAL_BST_CTRL 0x000a 35 #define RT5665_CBJ_BST_CTRL 0x000b 36 #define RT5665_IN1_IN2 0x000c 37 #define RT5665_IN3_IN4 0x000d 38 #define RT5665_INL1_INR1_VOL 0x000f 39 /* I/O - Speaker */ 40 #define RT5665_EJD_CTRL_1 0x0010 41 #define RT5665_EJD_CTRL_2 0x0011 42 #define RT5665_EJD_CTRL_3 0x0012 43 #define RT5665_EJD_CTRL_4 0x0013 44 #define RT5665_EJD_CTRL_5 0x0014 45 #define RT5665_EJD_CTRL_6 0x0015 46 #define RT5665_EJD_CTRL_7 0x0016 47 /* I/O - ADC/DAC/DMIC */ 48 #define RT5665_DAC2_CTRL 0x0017 49 #define RT5665_DAC2_DIG_VOL 0x0018 50 #define RT5665_DAC1_DIG_VOL 0x0019 51 #define RT5665_DAC3_DIG_VOL 0x001a 52 #define RT5665_DAC3_CTRL 0x001b 53 #define RT5665_STO1_ADC_DIG_VOL 0x001c 54 #define RT5665_MONO_ADC_DIG_VOL 0x001d 55 #define RT5665_STO2_ADC_DIG_VOL 0x001e 56 #define RT5665_STO1_ADC_BOOST 0x001f 57 #define RT5665_MONO_ADC_BOOST 0x0020 58 #define RT5665_STO2_ADC_BOOST 0x0021 59 #define RT5665_HP_IMP_GAIN_1 0x0022 60 #define RT5665_HP_IMP_GAIN_2 0x0023 61 /* Mixer - D-D */ 62 #define RT5665_STO1_ADC_MIXER 0x0026 63 #define RT5665_MONO_ADC_MIXER 0x0027 64 #define RT5665_STO2_ADC_MIXER 0x0028 65 #define RT5665_AD_DA_MIXER 0x0029 66 #define RT5665_STO1_DAC_MIXER 0x002a 67 #define RT5665_MONO_DAC_MIXER 0x002b 68 #define RT5665_STO2_DAC_MIXER 0x002c 69 #define RT5665_A_DAC1_MUX 0x002d 70 #define RT5665_A_DAC2_MUX 0x002e 71 #define RT5665_DIG_INF2_DATA 0x002f 72 #define RT5665_DIG_INF3_DATA 0x0030 73 /* Mixer - PDM */ 74 #define RT5665_PDM_OUT_CTRL 0x0031 75 #define RT5665_PDM_DATA_CTRL_1 0x0032 76 #define RT5665_PDM_DATA_CTRL_2 0x0033 77 #define RT5665_PDM_DATA_CTRL_3 0x0034 78 #define RT5665_PDM_DATA_CTRL_4 0x0035 79 /* Mixer - ADC */ 80 #define RT5665_REC1_GAIN 0x003a 81 #define RT5665_REC1_L1_MIXER 0x003b 82 #define RT5665_REC1_L2_MIXER 0x003c 83 #define RT5665_REC1_R1_MIXER 0x003d 84 #define RT5665_REC1_R2_MIXER 0x003e 85 #define RT5665_REC2_GAIN 0x003f 86 #define RT5665_REC2_L1_MIXER 0x0040 87 #define RT5665_REC2_L2_MIXER 0x0041 88 #define RT5665_REC2_R1_MIXER 0x0042 89 #define RT5665_REC2_R2_MIXER 0x0043 90 #define RT5665_CAL_REC 0x0044 91 /* Mixer - DAC */ 92 #define RT5665_ALC_BACK_GAIN 0x0049 93 #define RT5665_MONOMIX_GAIN 0x004a 94 #define RT5665_MONOMIX_IN_GAIN 0x004b 95 #define RT5665_OUT_L_GAIN 0x004d 96 #define RT5665_OUT_L_MIXER 0x004e 97 #define RT5665_OUT_R_GAIN 0x004f 98 #define RT5665_OUT_R_MIXER 0x0050 99 #define RT5665_LOUT_MIXER 0x0052 100 /* Power */ 101 #define RT5665_PWR_DIG_1 0x0061 102 #define RT5665_PWR_DIG_2 0x0062 103 #define RT5665_PWR_ANLG_1 0x0063 104 #define RT5665_PWR_ANLG_2 0x0064 105 #define RT5665_PWR_ANLG_3 0x0065 106 #define RT5665_PWR_MIXER 0x0066 107 #define RT5665_PWR_VOL 0x0067 108 /* Clock Detect */ 109 #define RT5665_CLK_DET 0x006b 110 /* Filter */ 111 #define RT5665_HPF_CTRL1 0x006d 112 /* DMIC */ 113 #define RT5665_DMIC_CTRL_1 0x006e 114 #define RT5665_DMIC_CTRL_2 0x006f 115 /* Format - ADC/DAC */ 116 #define RT5665_I2S1_SDP 0x0070 117 #define RT5665_I2S2_SDP 0x0071 118 #define RT5665_I2S3_SDP 0x0072 119 #define RT5665_ADDA_CLK_1 0x0073 120 #define RT5665_ADDA_CLK_2 0x0074 121 #define RT5665_I2S1_F_DIV_CTRL_1 0x0075 122 #define RT5665_I2S1_F_DIV_CTRL_2 0x0076 123 /* Format - TDM Control */ 124 #define RT5665_TDM_CTRL_1 0x0078 125 #define RT5665_TDM_CTRL_2 0x0079 126 #define RT5665_TDM_CTRL_3 0x007a 127 #define RT5665_TDM_CTRL_4 0x007b 128 #define RT5665_TDM_CTRL_5 0x007c 129 #define RT5665_TDM_CTRL_6 0x007d 130 #define RT5665_TDM_CTRL_7 0x007e 131 #define RT5665_TDM_CTRL_8 0x007f 132 /* Function - Analog */ 133 #define RT5665_GLB_CLK 0x0080 134 #define RT5665_PLL_CTRL_1 0x0081 135 #define RT5665_PLL_CTRL_2 0x0082 136 #define RT5665_ASRC_1 0x0083 137 #define RT5665_ASRC_2 0x0084 138 #define RT5665_ASRC_3 0x0085 139 #define RT5665_ASRC_4 0x0086 140 #define RT5665_ASRC_5 0x0087 141 #define RT5665_ASRC_6 0x0088 142 #define RT5665_ASRC_7 0x0089 143 #define RT5665_ASRC_8 0x008a 144 #define RT5665_ASRC_9 0x008b 145 #define RT5665_ASRC_10 0x008c 146 #define RT5665_DEPOP_1 0x008e 147 #define RT5665_DEPOP_2 0x008f 148 #define RT5665_HP_CHARGE_PUMP_1 0x0091 149 #define RT5665_HP_CHARGE_PUMP_2 0x0092 150 #define RT5665_MICBIAS_1 0x0093 151 #define RT5665_MICBIAS_2 0x0094 152 #define RT5665_ASRC_12 0x0098 153 #define RT5665_ASRC_13 0x0099 154 #define RT5665_ASRC_14 0x009a 155 #define RT5665_RC_CLK_CTRL 0x009f 156 #define RT5665_I2S_M_CLK_CTRL_1 0x00a0 157 #define RT5665_I2S2_F_DIV_CTRL_1 0x00a1 158 #define RT5665_I2S2_F_DIV_CTRL_2 0x00a2 159 #define RT5665_I2S3_F_DIV_CTRL_1 0x00a3 160 #define RT5665_I2S3_F_DIV_CTRL_2 0x00a4 161 /* Function - Digital */ 162 #define RT5665_EQ_CTRL_1 0x00ae 163 #define RT5665_EQ_CTRL_2 0x00af 164 #define RT5665_IRQ_CTRL_1 0x00b6 165 #define RT5665_IRQ_CTRL_2 0x00b7 166 #define RT5665_IRQ_CTRL_3 0x00b8 167 #define RT5665_IRQ_CTRL_4 0x00b9 168 #define RT5665_IRQ_CTRL_5 0x00ba 169 #define RT5665_IRQ_CTRL_6 0x00bb 170 #define RT5665_INT_ST_1 0x00be 171 #define RT5665_GPIO_CTRL_1 0x00c0 172 #define RT5665_GPIO_CTRL_2 0x00c1 173 #define RT5665_GPIO_CTRL_3 0x00c2 174 #define RT5665_GPIO_CTRL_4 0x00c3 175 #define RT5665_GPIO_STA 0x00c4 176 #define RT5665_HP_AMP_DET_CTRL_1 0x00d0 177 #define RT5665_HP_AMP_DET_CTRL_2 0x00d1 178 #define RT5665_MID_HP_AMP_DET 0x00d3 179 #define RT5665_LOW_HP_AMP_DET 0x00d4 180 #define RT5665_SV_ZCD_1 0x00d9 181 #define RT5665_SV_ZCD_2 0x00da 182 #define RT5665_IL_CMD_1 0x00db 183 #define RT5665_IL_CMD_2 0x00dc 184 #define RT5665_IL_CMD_3 0x00dd 185 #define RT5665_IL_CMD_4 0x00de 186 #define RT5665_4BTN_IL_CMD_1 0x00df 187 #define RT5665_4BTN_IL_CMD_2 0x00e0 188 #define RT5665_4BTN_IL_CMD_3 0x00e1 189 #define RT5665_PSV_IL_CMD_1 0x00e2 190 191 #define RT5665_ADC_STO1_HP_CTRL_1 0x00ea 192 #define RT5665_ADC_STO1_HP_CTRL_2 0x00eb 193 #define RT5665_ADC_MONO_HP_CTRL_1 0x00ec 194 #define RT5665_ADC_MONO_HP_CTRL_2 0x00ed 195 #define RT5665_ADC_STO2_HP_CTRL_1 0x00ee 196 #define RT5665_ADC_STO2_HP_CTRL_2 0x00ef 197 #define RT5665_AJD1_CTRL 0x00f0 198 #define RT5665_JD1_THD 0x00f1 199 #define RT5665_JD2_THD 0x00f2 200 #define RT5665_JD_CTRL_1 0x00f6 201 #define RT5665_JD_CTRL_2 0x00f7 202 #define RT5665_JD_CTRL_3 0x00f8 203 /* General Control */ 204 #define RT5665_DIG_MISC 0x00fa 205 #define RT5665_DUMMY_2 0x00fb 206 #define RT5665_DUMMY_3 0x00fc 207 208 #define RT5665_DAC_ADC_DIG_VOL1 0x0100 209 #define RT5665_DAC_ADC_DIG_VOL2 0x0101 210 #define RT5665_BIAS_CUR_CTRL_1 0x010a 211 #define RT5665_BIAS_CUR_CTRL_2 0x010b 212 #define RT5665_BIAS_CUR_CTRL_3 0x010c 213 #define RT5665_BIAS_CUR_CTRL_4 0x010d 214 #define RT5665_BIAS_CUR_CTRL_5 0x010e 215 #define RT5665_BIAS_CUR_CTRL_6 0x010f 216 #define RT5665_BIAS_CUR_CTRL_7 0x0110 217 #define RT5665_BIAS_CUR_CTRL_8 0x0111 218 #define RT5665_BIAS_CUR_CTRL_9 0x0112 219 #define RT5665_BIAS_CUR_CTRL_10 0x0113 220 #define RT5665_VREF_REC_OP_FB_CAP_CTRL 0x0117 221 #define RT5665_CHARGE_PUMP_1 0x0125 222 #define RT5665_DIG_IN_CTRL_1 0x0132 223 #define RT5665_DIG_IN_CTRL_2 0x0133 224 #define RT5665_PAD_DRIVING_CTRL 0x0137 225 #define RT5665_SOFT_RAMP_DEPOP 0x0138 226 #define RT5665_PLL 0x0139 227 #define RT5665_CHOP_DAC 0x013a 228 #define RT5665_CHOP_ADC 0x013b 229 #define RT5665_CALIB_ADC_CTRL 0x013c 230 #define RT5665_VOL_TEST 0x013f 231 #define RT5665_TEST_MODE_CTRL_1 0x0145 232 #define RT5665_TEST_MODE_CTRL_2 0x0146 233 #define RT5665_TEST_MODE_CTRL_3 0x0147 234 #define RT5665_TEST_MODE_CTRL_4 0x0148 235 #define RT5665_BASSBACK_CTRL 0x0150 236 #define RT5665_STO_NG2_CTRL_1 0x0160 237 #define RT5665_STO_NG2_CTRL_2 0x0161 238 #define RT5665_STO_NG2_CTRL_3 0x0162 239 #define RT5665_STO_NG2_CTRL_4 0x0163 240 #define RT5665_STO_NG2_CTRL_5 0x0164 241 #define RT5665_STO_NG2_CTRL_6 0x0165 242 #define RT5665_STO_NG2_CTRL_7 0x0166 243 #define RT5665_STO_NG2_CTRL_8 0x0167 244 #define RT5665_MONO_NG2_CTRL_1 0x0170 245 #define RT5665_MONO_NG2_CTRL_2 0x0171 246 #define RT5665_MONO_NG2_CTRL_3 0x0172 247 #define RT5665_MONO_NG2_CTRL_4 0x0173 248 #define RT5665_MONO_NG2_CTRL_5 0x0174 249 #define RT5665_MONO_NG2_CTRL_6 0x0175 250 #define RT5665_STO1_DAC_SIL_DET 0x0190 251 #define RT5665_MONOL_DAC_SIL_DET 0x0191 252 #define RT5665_MONOR_DAC_SIL_DET 0x0192 253 #define RT5665_STO2_DAC_SIL_DET 0x0193 254 #define RT5665_SIL_PSV_CTRL1 0x0194 255 #define RT5665_SIL_PSV_CTRL2 0x0195 256 #define RT5665_SIL_PSV_CTRL3 0x0196 257 #define RT5665_SIL_PSV_CTRL4 0x0197 258 #define RT5665_SIL_PSV_CTRL5 0x0198 259 #define RT5665_SIL_PSV_CTRL6 0x0199 260 #define RT5665_MONO_AMP_CALIB_CTRL_1 0x01a0 261 #define RT5665_MONO_AMP_CALIB_CTRL_2 0x01a1 262 #define RT5665_MONO_AMP_CALIB_CTRL_3 0x01a2 263 #define RT5665_MONO_AMP_CALIB_CTRL_4 0x01a3 264 #define RT5665_MONO_AMP_CALIB_CTRL_5 0x01a4 265 #define RT5665_MONO_AMP_CALIB_CTRL_6 0x01a5 266 #define RT5665_MONO_AMP_CALIB_CTRL_7 0x01a6 267 #define RT5665_MONO_AMP_CALIB_STA1 0x01a7 268 #define RT5665_MONO_AMP_CALIB_STA2 0x01a8 269 #define RT5665_MONO_AMP_CALIB_STA3 0x01a9 270 #define RT5665_MONO_AMP_CALIB_STA4 0x01aa 271 #define RT5665_MONO_AMP_CALIB_STA6 0x01ab 272 #define RT5665_HP_IMP_SENS_CTRL_01 0x01b5 273 #define RT5665_HP_IMP_SENS_CTRL_02 0x01b6 274 #define RT5665_HP_IMP_SENS_CTRL_03 0x01b7 275 #define RT5665_HP_IMP_SENS_CTRL_04 0x01b8 276 #define RT5665_HP_IMP_SENS_CTRL_05 0x01b9 277 #define RT5665_HP_IMP_SENS_CTRL_06 0x01ba 278 #define RT5665_HP_IMP_SENS_CTRL_07 0x01bb 279 #define RT5665_HP_IMP_SENS_CTRL_08 0x01bc 280 #define RT5665_HP_IMP_SENS_CTRL_09 0x01bd 281 #define RT5665_HP_IMP_SENS_CTRL_10 0x01be 282 #define RT5665_HP_IMP_SENS_CTRL_11 0x01bf 283 #define RT5665_HP_IMP_SENS_CTRL_12 0x01c0 284 #define RT5665_HP_IMP_SENS_CTRL_13 0x01c1 285 #define RT5665_HP_IMP_SENS_CTRL_14 0x01c2 286 #define RT5665_HP_IMP_SENS_CTRL_15 0x01c3 287 #define RT5665_HP_IMP_SENS_CTRL_16 0x01c4 288 #define RT5665_HP_IMP_SENS_CTRL_17 0x01c5 289 #define RT5665_HP_IMP_SENS_CTRL_18 0x01c6 290 #define RT5665_HP_IMP_SENS_CTRL_19 0x01c7 291 #define RT5665_HP_IMP_SENS_CTRL_20 0x01c8 292 #define RT5665_HP_IMP_SENS_CTRL_21 0x01c9 293 #define RT5665_HP_IMP_SENS_CTRL_22 0x01ca 294 #define RT5665_HP_IMP_SENS_CTRL_23 0x01cb 295 #define RT5665_HP_IMP_SENS_CTRL_24 0x01cc 296 #define RT5665_HP_IMP_SENS_CTRL_25 0x01cd 297 #define RT5665_HP_IMP_SENS_CTRL_26 0x01ce 298 #define RT5665_HP_IMP_SENS_CTRL_27 0x01cf 299 #define RT5665_HP_IMP_SENS_CTRL_28 0x01d0 300 #define RT5665_HP_IMP_SENS_CTRL_29 0x01d1 301 #define RT5665_HP_IMP_SENS_CTRL_30 0x01d2 302 #define RT5665_HP_IMP_SENS_CTRL_31 0x01d3 303 #define RT5665_HP_IMP_SENS_CTRL_32 0x01d4 304 #define RT5665_HP_IMP_SENS_CTRL_33 0x01d5 305 #define RT5665_HP_IMP_SENS_CTRL_34 0x01d6 306 #define RT5665_HP_LOGIC_CTRL_1 0x01da 307 #define RT5665_HP_LOGIC_CTRL_2 0x01db 308 #define RT5665_HP_LOGIC_CTRL_3 0x01dc 309 #define RT5665_HP_CALIB_CTRL_1 0x01de 310 #define RT5665_HP_CALIB_CTRL_2 0x01df 311 #define RT5665_HP_CALIB_CTRL_3 0x01e0 312 #define RT5665_HP_CALIB_CTRL_4 0x01e1 313 #define RT5665_HP_CALIB_CTRL_5 0x01e2 314 #define RT5665_HP_CALIB_CTRL_6 0x01e3 315 #define RT5665_HP_CALIB_CTRL_7 0x01e4 316 #define RT5665_HP_CALIB_CTRL_9 0x01e6 317 #define RT5665_HP_CALIB_CTRL_10 0x01e7 318 #define RT5665_HP_CALIB_CTRL_11 0x01e8 319 #define RT5665_HP_CALIB_STA_1 0x01ea 320 #define RT5665_HP_CALIB_STA_2 0x01eb 321 #define RT5665_HP_CALIB_STA_3 0x01ec 322 #define RT5665_HP_CALIB_STA_4 0x01ed 323 #define RT5665_HP_CALIB_STA_5 0x01ee 324 #define RT5665_HP_CALIB_STA_6 0x01ef 325 #define RT5665_HP_CALIB_STA_7 0x01f0 326 #define RT5665_HP_CALIB_STA_8 0x01f1 327 #define RT5665_HP_CALIB_STA_9 0x01f2 328 #define RT5665_HP_CALIB_STA_10 0x01f3 329 #define RT5665_HP_CALIB_STA_11 0x01f4 330 #define RT5665_PGM_TAB_CTRL1 0x0200 331 #define RT5665_PGM_TAB_CTRL2 0x0201 332 #define RT5665_PGM_TAB_CTRL3 0x0202 333 #define RT5665_PGM_TAB_CTRL4 0x0203 334 #define RT5665_PGM_TAB_CTRL5 0x0204 335 #define RT5665_PGM_TAB_CTRL6 0x0205 336 #define RT5665_PGM_TAB_CTRL7 0x0206 337 #define RT5665_PGM_TAB_CTRL8 0x0207 338 #define RT5665_PGM_TAB_CTRL9 0x0208 339 #define RT5665_SAR_IL_CMD_1 0x0210 340 #define RT5665_SAR_IL_CMD_2 0x0211 341 #define RT5665_SAR_IL_CMD_3 0x0212 342 #define RT5665_SAR_IL_CMD_4 0x0213 343 #define RT5665_SAR_IL_CMD_5 0x0214 344 #define RT5665_SAR_IL_CMD_6 0x0215 345 #define RT5665_SAR_IL_CMD_7 0x0216 346 #define RT5665_SAR_IL_CMD_8 0x0217 347 #define RT5665_SAR_IL_CMD_9 0x0218 348 #define RT5665_SAR_IL_CMD_10 0x0219 349 #define RT5665_SAR_IL_CMD_11 0x021a 350 #define RT5665_SAR_IL_CMD_12 0x021b 351 #define RT5665_DRC1_CTRL_0 0x02ff 352 #define RT5665_DRC1_CTRL_1 0x0300 353 #define RT5665_DRC1_CTRL_2 0x0301 354 #define RT5665_DRC1_CTRL_3 0x0302 355 #define RT5665_DRC1_CTRL_4 0x0303 356 #define RT5665_DRC1_CTRL_5 0x0304 357 #define RT5665_DRC1_CTRL_6 0x0305 358 #define RT5665_DRC1_HARD_LMT_CTRL_1 0x0306 359 #define RT5665_DRC1_HARD_LMT_CTRL_2 0x0307 360 #define RT5665_DRC1_PRIV_1 0x0310 361 #define RT5665_DRC1_PRIV_2 0x0311 362 #define RT5665_DRC1_PRIV_3 0x0312 363 #define RT5665_DRC1_PRIV_4 0x0313 364 #define RT5665_DRC1_PRIV_5 0x0314 365 #define RT5665_DRC1_PRIV_6 0x0315 366 #define RT5665_DRC1_PRIV_7 0x0316 367 #define RT5665_DRC1_PRIV_8 0x0317 368 #define RT5665_ALC_PGA_CTRL_1 0x0330 369 #define RT5665_ALC_PGA_CTRL_2 0x0331 370 #define RT5665_ALC_PGA_CTRL_3 0x0332 371 #define RT5665_ALC_PGA_CTRL_4 0x0333 372 #define RT5665_ALC_PGA_CTRL_5 0x0334 373 #define RT5665_ALC_PGA_CTRL_6 0x0335 374 #define RT5665_ALC_PGA_CTRL_7 0x0336 375 #define RT5665_ALC_PGA_CTRL_8 0x0337 376 #define RT5665_ALC_PGA_STA_1 0x0338 377 #define RT5665_ALC_PGA_STA_2 0x0339 378 #define RT5665_ALC_PGA_STA_3 0x033a 379 #define RT5665_EQ_AUTO_RCV_CTRL1 0x03c0 380 #define RT5665_EQ_AUTO_RCV_CTRL2 0x03c1 381 #define RT5665_EQ_AUTO_RCV_CTRL3 0x03c2 382 #define RT5665_EQ_AUTO_RCV_CTRL4 0x03c3 383 #define RT5665_EQ_AUTO_RCV_CTRL5 0x03c4 384 #define RT5665_EQ_AUTO_RCV_CTRL6 0x03c5 385 #define RT5665_EQ_AUTO_RCV_CTRL7 0x03c6 386 #define RT5665_EQ_AUTO_RCV_CTRL8 0x03c7 387 #define RT5665_EQ_AUTO_RCV_CTRL9 0x03c8 388 #define RT5665_EQ_AUTO_RCV_CTRL10 0x03c9 389 #define RT5665_EQ_AUTO_RCV_CTRL11 0x03ca 390 #define RT5665_EQ_AUTO_RCV_CTRL12 0x03cb 391 #define RT5665_EQ_AUTO_RCV_CTRL13 0x03cc 392 #define RT5665_ADC_L_EQ_LPF1_A1 0x03d0 393 #define RT5665_R_EQ_LPF1_A1 0x03d1 394 #define RT5665_L_EQ_LPF1_H0 0x03d2 395 #define RT5665_R_EQ_LPF1_H0 0x03d3 396 #define RT5665_L_EQ_BPF1_A1 0x03d4 397 #define RT5665_R_EQ_BPF1_A1 0x03d5 398 #define RT5665_L_EQ_BPF1_A2 0x03d6 399 #define RT5665_R_EQ_BPF1_A2 0x03d7 400 #define RT5665_L_EQ_BPF1_H0 0x03d8 401 #define RT5665_R_EQ_BPF1_H0 0x03d9 402 #define RT5665_L_EQ_BPF2_A1 0x03da 403 #define RT5665_R_EQ_BPF2_A1 0x03db 404 #define RT5665_L_EQ_BPF2_A2 0x03dc 405 #define RT5665_R_EQ_BPF2_A2 0x03dd 406 #define RT5665_L_EQ_BPF2_H0 0x03de 407 #define RT5665_R_EQ_BPF2_H0 0x03df 408 #define RT5665_L_EQ_BPF3_A1 0x03e0 409 #define RT5665_R_EQ_BPF3_A1 0x03e1 410 #define RT5665_L_EQ_BPF3_A2 0x03e2 411 #define RT5665_R_EQ_BPF3_A2 0x03e3 412 #define RT5665_L_EQ_BPF3_H0 0x03e4 413 #define RT5665_R_EQ_BPF3_H0 0x03e5 414 #define RT5665_L_EQ_BPF4_A1 0x03e6 415 #define RT5665_R_EQ_BPF4_A1 0x03e7 416 #define RT5665_L_EQ_BPF4_A2 0x03e8 417 #define RT5665_R_EQ_BPF4_A2 0x03e9 418 #define RT5665_L_EQ_BPF4_H0 0x03ea 419 #define RT5665_R_EQ_BPF4_H0 0x03eb 420 #define RT5665_L_EQ_HPF1_A1 0x03ec 421 #define RT5665_R_EQ_HPF1_A1 0x03ed 422 #define RT5665_L_EQ_HPF1_H0 0x03ee 423 #define RT5665_R_EQ_HPF1_H0 0x03ef 424 #define RT5665_L_EQ_PRE_VOL 0x03f0 425 #define RT5665_R_EQ_PRE_VOL 0x03f1 426 #define RT5665_L_EQ_POST_VOL 0x03f2 427 #define RT5665_R_EQ_POST_VOL 0x03f3 428 #define RT5665_SCAN_MODE_CTRL 0x07f0 429 #define RT5665_I2C_MODE 0x07fa 430 431 432 433 /* global definition */ 434 #define RT5665_L_MUTE (0x1 << 15) 435 #define RT5665_L_MUTE_SFT 15 436 #define RT5665_VOL_L_MUTE (0x1 << 14) 437 #define RT5665_VOL_L_SFT 14 438 #define RT5665_R_MUTE (0x1 << 7) 439 #define RT5665_R_MUTE_SFT 7 440 #define RT5665_VOL_R_MUTE (0x1 << 6) 441 #define RT5665_VOL_R_SFT 6 442 #define RT5665_L_VOL_MASK (0x3f << 8) 443 #define RT5665_L_VOL_SFT 8 444 #define RT5665_R_VOL_MASK (0x3f) 445 #define RT5665_R_VOL_SFT 0 446 447 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ 448 #define RT5665_G_HP (0xf << 8) 449 #define RT5665_G_HP_SFT 8 450 #define RT5665_G_STO_DA_DMIX (0xf) 451 #define RT5665_G_STO_DA_SFT 0 452 453 /* CBJ Control (0x000b) */ 454 #define RT5665_BST_CBJ_MASK (0xf << 8) 455 #define RT5665_BST_CBJ_SFT 8 456 457 /* IN1/IN2 Control (0x000c) */ 458 #define RT5665_IN1_DF_MASK (0x1 << 15) 459 #define RT5665_IN1_DF 15 460 #define RT5665_BST1_MASK (0x7f << 8) 461 #define RT5665_BST1_SFT 8 462 #define RT5665_IN2_DF_MASK (0x1 << 7) 463 #define RT5665_IN2_DF 7 464 #define RT5665_BST2_MASK (0x7f) 465 #define RT5665_BST2_SFT 0 466 467 /* IN3/IN4 Control (0x000d) */ 468 #define RT5665_IN3_DF_MASK (0x1 << 15) 469 #define RT5665_IN3_DF 15 470 #define RT5665_BST3_MASK (0x7f << 8) 471 #define RT5665_BST3_SFT 8 472 #define RT5665_IN4_DF_MASK (0x1 << 7) 473 #define RT5665_IN4_DF 7 474 #define RT5665_BST4_MASK (0x7f) 475 #define RT5665_BST4_SFT 0 476 477 /* INL and INR Volume Control (0x000f) */ 478 #define RT5665_INL_VOL_MASK (0x1f << 8) 479 #define RT5665_INL_VOL_SFT 8 480 #define RT5665_INR_VOL_MASK (0x1f) 481 #define RT5665_INR_VOL_SFT 0 482 483 /* Embeeded Jack and Type Detection Control 1 (0x0010) */ 484 #define RT5665_EMB_JD_EN (0x1 << 15) 485 #define RT5665_EMB_JD_EN_SFT 15 486 #define RT5665_JD_MODE (0x1 << 13) 487 #define RT5665_JD_MODE_SFT 13 488 #define RT5665_POLA_EXT_JD_MASK (0x1 << 11) 489 #define RT5665_POLA_EXT_JD_LOW (0x1 << 11) 490 #define RT5665_POLA_EXT_JD_HIGH (0x0 << 11) 491 #define RT5665_EXT_JD_DIG (0x1 << 9) 492 #define RT5665_POL_FAST_OFF_MASK (0x1 << 8) 493 #define RT5665_POL_FAST_OFF_HIGH (0x1 << 8) 494 #define RT5665_POL_FAST_OFF_LOW (0x0 << 8) 495 #define RT5665_VREF_POW_MASK (0x1 << 6) 496 #define RT5665_VREF_POW_FSM (0x0 << 6) 497 #define RT5665_VREF_POW_REG (0x1 << 6) 498 #define RT5665_MB1_PATH_MASK (0x1 << 5) 499 #define RT5665_CTRL_MB1_REG (0x1 << 5) 500 #define RT5665_CTRL_MB1_FSM (0x0 << 5) 501 #define RT5665_MB2_PATH_MASK (0x1 << 4) 502 #define RT5665_CTRL_MB2_REG (0x1 << 4) 503 #define RT5665_CTRL_MB2_FSM (0x0 << 4) 504 #define RT5665_TRIG_JD_MASK (0x1 << 3) 505 #define RT5665_TRIG_JD_HIGH (0x1 << 3) 506 #define RT5665_TRIG_JD_LOW (0x0 << 3) 507 508 /* Embeeded Jack and Type Detection Control 2 (0x0011) */ 509 #define RT5665_EXT_JD_SRC (0x7 << 4) 510 #define RT5665_EXT_JD_SRC_SFT 4 511 #define RT5665_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) 512 #define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) 513 #define RT5665_EXT_JD_SRC_JD1_1 (0x2 << 4) 514 #define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4) 515 #define RT5665_EXT_JD_SRC_JD2 (0x4 << 4) 516 #define RT5665_EXT_JD_SRC_JD3 (0x5 << 4) 517 #define RT5665_EXT_JD_SRC_MANUAL (0x6 << 4) 518 519 /* Combo Jack and Type Detection Control 4 (0x0013) */ 520 #define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12) 521 #define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12) 522 #define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12) 523 #define RT5665_CBJ_JD_TEST_MASK (0x1 << 6) 524 #define RT5665_CBJ_JD_TEST_NORM (0x0 << 6) 525 #define RT5665_CBJ_JD_TEST_MODE (0x1 << 6) 526 527 /* Slience Detection Control (0x0015) */ 528 #define RT5665_SIL_DET_MASK (0x1 << 15) 529 #define RT5665_SIL_DET_DIS (0x0 << 15) 530 #define RT5665_SIL_DET_EN (0x1 << 15) 531 532 /* DAC2 Control (0x0017) */ 533 #define RT5665_M_DAC2_L_VOL (0x1 << 13) 534 #define RT5665_M_DAC2_L_VOL_SFT 13 535 #define RT5665_M_DAC2_R_VOL (0x1 << 12) 536 #define RT5665_M_DAC2_R_VOL_SFT 12 537 #define RT5665_DAC_L2_SEL_MASK (0x7 << 4) 538 #define RT5665_DAC_L2_SEL_SFT 4 539 #define RT5665_DAC_R2_SEL_MASK (0x7 << 0) 540 #define RT5665_DAC_R2_SEL_SFT 0 541 542 /* Sidetone Control (0x0018) */ 543 #define RT5665_ST_SEL_MASK (0x7 << 9) 544 #define RT5665_ST_SEL_SFT 9 545 #define RT5665_ST_EN (0x1 << 6) 546 #define RT5665_ST_EN_SFT 6 547 548 /* DAC1 Digital Volume (0x0019) */ 549 #define RT5665_DAC_L1_VOL_MASK (0xff << 8) 550 #define RT5665_DAC_L1_VOL_SFT 8 551 #define RT5665_DAC_R1_VOL_MASK (0xff) 552 #define RT5665_DAC_R1_VOL_SFT 0 553 554 /* DAC2 Digital Volume (0x001a) */ 555 #define RT5665_DAC_L2_VOL_MASK (0xff << 8) 556 #define RT5665_DAC_L2_VOL_SFT 8 557 #define RT5665_DAC_R2_VOL_MASK (0xff) 558 #define RT5665_DAC_R2_VOL_SFT 0 559 560 /* DAC3 Control (0x001b) */ 561 #define RT5665_M_DAC3_L_VOL (0x1 << 13) 562 #define RT5665_M_DAC3_L_VOL_SFT 13 563 #define RT5665_M_DAC3_R_VOL (0x1 << 12) 564 #define RT5665_M_DAC3_R_VOL_SFT 12 565 #define RT5665_DAC_L3_SEL_MASK (0x7 << 4) 566 #define RT5665_DAC_L3_SEL_SFT 4 567 #define RT5665_DAC_R3_SEL_MASK (0x7 << 0) 568 #define RT5665_DAC_R3_SEL_SFT 0 569 570 /* ADC Digital Volume Control (0x001c) */ 571 #define RT5665_ADC_L_VOL_MASK (0x7f << 8) 572 #define RT5665_ADC_L_VOL_SFT 8 573 #define RT5665_ADC_R_VOL_MASK (0x7f) 574 #define RT5665_ADC_R_VOL_SFT 0 575 576 /* Mono ADC Digital Volume Control (0x001d) */ 577 #define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8) 578 #define RT5665_MONO_ADC_L_VOL_SFT 8 579 #define RT5665_MONO_ADC_R_VOL_MASK (0x7f) 580 #define RT5665_MONO_ADC_R_VOL_SFT 0 581 582 /* Stereo1 ADC Boost Gain Control (0x001f) */ 583 #define RT5665_STO1_ADC_L_BST_MASK (0x3 << 14) 584 #define RT5665_STO1_ADC_L_BST_SFT 14 585 #define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12) 586 #define RT5665_STO1_ADC_R_BST_SFT 12 587 588 /* Mono ADC Boost Gain Control (0x0020) */ 589 #define RT5665_MONO_ADC_L_BST_MASK (0x3 << 14) 590 #define RT5665_MONO_ADC_L_BST_SFT 14 591 #define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12) 592 #define RT5665_MONO_ADC_R_BST_SFT 12 593 594 /* Stereo1 ADC Boost Gain Control (0x001f) */ 595 #define RT5665_STO2_ADC_L_BST_MASK (0x3 << 14) 596 #define RT5665_STO2_ADC_L_BST_SFT 14 597 #define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12) 598 #define RT5665_STO2_ADC_R_BST_SFT 12 599 600 /* Stereo1 ADC Mixer Control (0x0026) */ 601 #define RT5665_M_STO1_ADC_L1 (0x1 << 15) 602 #define RT5665_M_STO1_ADC_L1_SFT 15 603 #define RT5665_M_STO1_ADC_L2 (0x1 << 14) 604 #define RT5665_M_STO1_ADC_L2_SFT 14 605 #define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13) 606 #define RT5665_STO1_ADC1L_SRC_SFT 13 607 #define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13) 608 #define RT5665_STO1_ADC1_SRC_DACMIX (0x0 << 13) 609 #define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12) 610 #define RT5665_STO1_ADC2L_SRC_SFT 12 611 #define RT5665_STO1_ADCL_SRC_MASK (0x3 << 10) 612 #define RT5665_STO1_ADCL_SRC_SFT 10 613 #define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9) 614 #define RT5665_STO1_DD_L_SRC_SFT 9 615 #define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8) 616 #define RT5665_STO1_DMIC_SRC_SFT 8 617 #define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8) 618 #define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8) 619 #define RT5665_M_STO1_ADC_R1 (0x1 << 7) 620 #define RT5665_M_STO1_ADC_R1_SFT 7 621 #define RT5665_M_STO1_ADC_R2 (0x1 << 6) 622 #define RT5665_M_STO1_ADC_R2_SFT 6 623 #define RT5665_STO1_ADC1R_SRC_MASK (0x1 << 5) 624 #define RT5665_STO1_ADC1R_SRC_SFT 5 625 #define RT5665_STO1_ADC2R_SRC_MASK (0x1 << 4) 626 #define RT5665_STO1_ADC2R_SRC_SFT 4 627 #define RT5665_STO1_ADCR_SRC_MASK (0x3 << 2) 628 #define RT5665_STO1_ADCR_SRC_SFT 2 629 #define RT5665_STO1_DD_R_SRC_MASK (0x3) 630 #define RT5665_STO1_DD_R_SRC_SFT 0 631 632 633 /* Mono1 ADC Mixer control (0x0027) */ 634 #define RT5665_M_MONO_ADC_L1 (0x1 << 15) 635 #define RT5665_M_MONO_ADC_L1_SFT 15 636 #define RT5665_M_MONO_ADC_L2 (0x1 << 14) 637 #define RT5665_M_MONO_ADC_L2_SFT 14 638 #define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13) 639 #define RT5665_MONO_ADC_L1_SRC_SFT 13 640 #define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12) 641 #define RT5665_MONO_ADC_L2_SRC_SFT 12 642 #define RT5665_MONO_ADC_L_SRC_MASK (0x3 << 10) 643 #define RT5665_MONO_ADC_L_SRC_SFT 10 644 #define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9) 645 #define RT5665_MONO_DD_L_SRC_SFT 9 646 #define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8) 647 #define RT5665_MONO_DMIC_L_SRC_SFT 8 648 #define RT5665_M_MONO_ADC_R1 (0x1 << 7) 649 #define RT5665_M_MONO_ADC_R1_SFT 7 650 #define RT5665_M_MONO_ADC_R2 (0x1 << 6) 651 #define RT5665_M_MONO_ADC_R2_SFT 6 652 #define RT5665_MONO_ADC_R1_SRC_MASK (0x1 << 5) 653 #define RT5665_MONO_ADC_R1_SRC_SFT 5 654 #define RT5665_MONO_ADC_R2_SRC_MASK (0x1 << 4) 655 #define RT5665_MONO_ADC_R2_SRC_SFT 4 656 #define RT5665_MONO_ADC_R_SRC_MASK (0x3 << 2) 657 #define RT5665_MONO_ADC_R_SRC_SFT 2 658 #define RT5665_MONO_DD_R_SRC_MASK (0x1 << 1) 659 #define RT5665_MONO_DD_R_SRC_SFT 1 660 #define RT5665_MONO_DMIC_R_SRC_MASK 0x1 661 #define RT5665_MONO_DMIC_R_SRC_SFT 0 662 663 /* Stereo2 ADC Mixer Control (0x0028) */ 664 #define RT5665_M_STO2_ADC_L1 (0x1 << 15) 665 #define RT5665_M_STO2_ADC_L1_UN (0x0 << 15) 666 #define RT5665_M_STO2_ADC_L1_SFT 15 667 #define RT5665_M_STO2_ADC_L2 (0x1 << 14) 668 #define RT5665_M_STO2_ADC_L2_SFT 14 669 #define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13) 670 #define RT5665_STO2_ADC1L_SRC_SFT 13 671 #define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13) 672 #define RT5665_STO2_ADC1_SRC_DACMIX (0x0 << 13) 673 #define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12) 674 #define RT5665_STO2_ADC2L_SRC_SFT 12 675 #define RT5665_STO2_ADCL_SRC_MASK (0x3 << 10) 676 #define RT5665_STO2_ADCL_SRC_SFT 10 677 #define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9) 678 #define RT5665_STO2_DD_L_SRC_SFT 9 679 #define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8) 680 #define RT5665_STO2_DMIC_SRC_SFT 8 681 #define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8) 682 #define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8) 683 #define RT5665_M_STO2_ADC_R1 (0x1 << 7) 684 #define RT5665_M_STO2_ADC_R1_UN (0x0 << 7) 685 #define RT5665_M_STO2_ADC_R1_SFT 7 686 #define RT5665_M_STO2_ADC_R2 (0x1 << 6) 687 #define RT5665_M_STO2_ADC_R2_SFT 6 688 #define RT5665_STO2_ADC1R_SRC_MASK (0x1 << 5) 689 #define RT5665_STO2_ADC1R_SRC_SFT 5 690 #define RT5665_STO2_ADC2R_SRC_MASK (0x1 << 4) 691 #define RT5665_STO2_ADC2R_SRC_SFT 4 692 #define RT5665_STO2_ADCR_SRC_MASK (0x3 << 2) 693 #define RT5665_STO2_ADCR_SRC_SFT 2 694 #define RT5665_STO2_DD_R_SRC_MASK (0x1 << 1) 695 #define RT5665_STO2_DD_R_SRC_SFT 1 696 697 /* ADC Mixer to DAC Mixer Control (0x0029) */ 698 #define RT5665_M_ADCMIX_L (0x1 << 15) 699 #define RT5665_M_ADCMIX_L_SFT 15 700 #define RT5665_M_DAC1_L (0x1 << 14) 701 #define RT5665_M_DAC1_L_SFT 14 702 #define RT5665_DAC1_R_SEL_MASK (0x3 << 10) 703 #define RT5665_DAC1_R_SEL_SFT 10 704 #define RT5665_DAC1_L_SEL_MASK (0x3 << 8) 705 #define RT5665_DAC1_L_SEL_SFT 8 706 #define RT5665_M_ADCMIX_R (0x1 << 7) 707 #define RT5665_M_ADCMIX_R_SFT 7 708 #define RT5665_M_DAC1_R (0x1 << 6) 709 #define RT5665_M_DAC1_R_SFT 6 710 711 /* Stereo1 DAC Mixer Control (0x002a) */ 712 #define RT5665_M_DAC_L1_STO_L (0x1 << 15) 713 #define RT5665_M_DAC_L1_STO_L_SFT 15 714 #define RT5665_G_DAC_L1_STO_L_MASK (0x1 << 14) 715 #define RT5665_G_DAC_L1_STO_L_SFT 14 716 #define RT5665_M_DAC_R1_STO_L (0x1 << 13) 717 #define RT5665_M_DAC_R1_STO_L_SFT 13 718 #define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12) 719 #define RT5665_G_DAC_R1_STO_L_SFT 12 720 #define RT5665_M_DAC_L2_STO_L (0x1 << 11) 721 #define RT5665_M_DAC_L2_STO_L_SFT 11 722 #define RT5665_G_DAC_L2_STO_L_MASK (0x1 << 10) 723 #define RT5665_G_DAC_L2_STO_L_SFT 10 724 #define RT5665_M_DAC_R2_STO_L (0x1 << 9) 725 #define RT5665_M_DAC_R2_STO_L_SFT 9 726 #define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8) 727 #define RT5665_G_DAC_R2_STO_L_SFT 8 728 #define RT5665_M_DAC_L1_STO_R (0x1 << 7) 729 #define RT5665_M_DAC_L1_STO_R_SFT 7 730 #define RT5665_G_DAC_L1_STO_R_MASK (0x1 << 6) 731 #define RT5665_G_DAC_L1_STO_R_SFT 6 732 #define RT5665_M_DAC_R1_STO_R (0x1 << 5) 733 #define RT5665_M_DAC_R1_STO_R_SFT 5 734 #define RT5665_G_DAC_R1_STO_R_MASK (0x1 << 4) 735 #define RT5665_G_DAC_R1_STO_R_SFT 4 736 #define RT5665_M_DAC_L2_STO_R (0x1 << 3) 737 #define RT5665_M_DAC_L2_STO_R_SFT 3 738 #define RT5665_G_DAC_L2_STO_R_MASK (0x1 << 2) 739 #define RT5665_G_DAC_L2_STO_R_SFT 2 740 #define RT5665_M_DAC_R2_STO_R (0x1 << 1) 741 #define RT5665_M_DAC_R2_STO_R_SFT 1 742 #define RT5665_G_DAC_R2_STO_R_MASK (0x1) 743 #define RT5665_G_DAC_R2_STO_R_SFT 0 744 745 /* Mono DAC Mixer Control (0x002b) */ 746 #define RT5665_M_DAC_L1_MONO_L (0x1 << 15) 747 #define RT5665_M_DAC_L1_MONO_L_SFT 15 748 #define RT5665_G_DAC_L1_MONO_L_MASK (0x1 << 14) 749 #define RT5665_G_DAC_L1_MONO_L_SFT 14 750 #define RT5665_M_DAC_R1_MONO_L (0x1 << 13) 751 #define RT5665_M_DAC_R1_MONO_L_SFT 13 752 #define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12) 753 #define RT5665_G_DAC_R1_MONO_L_SFT 12 754 #define RT5665_M_DAC_L2_MONO_L (0x1 << 11) 755 #define RT5665_M_DAC_L2_MONO_L_SFT 11 756 #define RT5665_G_DAC_L2_MONO_L_MASK (0x1 << 10) 757 #define RT5665_G_DAC_L2_MONO_L_SFT 10 758 #define RT5665_M_DAC_R2_MONO_L (0x1 << 9) 759 #define RT5665_M_DAC_R2_MONO_L_SFT 9 760 #define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8) 761 #define RT5665_G_DAC_R2_MONO_L_SFT 8 762 #define RT5665_M_DAC_L1_MONO_R (0x1 << 7) 763 #define RT5665_M_DAC_L1_MONO_R_SFT 7 764 #define RT5665_G_DAC_L1_MONO_R_MASK (0x1 << 6) 765 #define RT5665_G_DAC_L1_MONO_R_SFT 6 766 #define RT5665_M_DAC_R1_MONO_R (0x1 << 5) 767 #define RT5665_M_DAC_R1_MONO_R_SFT 5 768 #define RT5665_G_DAC_R1_MONO_R_MASK (0x1 << 4) 769 #define RT5665_G_DAC_R1_MONO_R_SFT 4 770 #define RT5665_M_DAC_L2_MONO_R (0x1 << 3) 771 #define RT5665_M_DAC_L2_MONO_R_SFT 3 772 #define RT5665_G_DAC_L2_MONO_R_MASK (0x1 << 2) 773 #define RT5665_G_DAC_L2_MONO_R_SFT 2 774 #define RT5665_M_DAC_R2_MONO_R (0x1 << 1) 775 #define RT5665_M_DAC_R2_MONO_R_SFT 1 776 #define RT5665_G_DAC_R2_MONO_R_MASK (0x1) 777 #define RT5665_G_DAC_R2_MONO_R_SFT 0 778 779 /* Stereo2 DAC Mixer Control (0x002c) */ 780 #define RT5665_M_DAC_L1_STO2_L (0x1 << 15) 781 #define RT5665_M_DAC_L1_STO2_L_SFT 15 782 #define RT5665_G_DAC_L1_STO2_L_MASK (0x1 << 14) 783 #define RT5665_G_DAC_L1_STO2_L_SFT 14 784 #define RT5665_M_DAC_L2_STO2_L (0x1 << 13) 785 #define RT5665_M_DAC_L2_STO2_L_SFT 13 786 #define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12) 787 #define RT5665_G_DAC_L2_STO2_L_SFT 12 788 #define RT5665_M_DAC_L3_STO2_L (0x1 << 11) 789 #define RT5665_M_DAC_L3_STO2_L_SFT 11 790 #define RT5665_G_DAC_L3_STO2_L_MASK (0x1 << 10) 791 #define RT5665_G_DAC_L3_STO2_L_SFT 10 792 #define RT5665_M_ST_DAC_L1 (0x1 << 9) 793 #define RT5665_M_ST_DAC_L1_SFT 9 794 #define RT5665_M_ST_DAC_R1 (0x1 << 8) 795 #define RT5665_M_ST_DAC_R1_SFT 8 796 #define RT5665_M_DAC_R1_STO2_R (0x1 << 7) 797 #define RT5665_M_DAC_R1_STO2_R_SFT 7 798 #define RT5665_G_DAC_R1_STO2_R_MASK (0x1 << 6) 799 #define RT5665_G_DAC_R1_STO2_R_SFT 6 800 #define RT5665_M_DAC_R2_STO2_R (0x1 << 5) 801 #define RT5665_M_DAC_R2_STO2_R_SFT 5 802 #define RT5665_G_DAC_R2_STO2_R_MASK (0x1 << 4) 803 #define RT5665_G_DAC_R2_STO2_R_SFT 4 804 #define RT5665_M_DAC_R3_STO2_R (0x1 << 3) 805 #define RT5665_M_DAC_R3_STO2_R_SFT 3 806 #define RT5665_G_DAC_R3_STO2_R_MASK (0x1 << 2) 807 #define RT5665_G_DAC_R3_STO2_R_SFT 2 808 809 /* Analog DAC1 Input Source Control (0x002d) */ 810 #define RT5665_DAC_MIX_L_MASK (0x3 << 12) 811 #define RT5665_DAC_MIX_L_SFT 12 812 #define RT5665_DAC_MIX_R_MASK (0x3 << 8) 813 #define RT5665_DAC_MIX_R_SFT 8 814 #define RT5665_DAC_L1_SRC_MASK (0x3 << 4) 815 #define RT5665_A_DACL1_SFT 4 816 #define RT5665_DAC_R1_SRC_MASK (0x3) 817 #define RT5665_A_DACR1_SFT 0 818 819 /* Analog DAC Input Source Control (0x002e) */ 820 #define RT5665_A_DACL2_SEL (0x1 << 4) 821 #define RT5665_A_DACL2_SFT 4 822 #define RT5665_A_DACR2_SEL (0x1 << 0) 823 #define RT5665_A_DACR2_SFT 0 824 825 /* Digital Interface Data Control (0x002f) */ 826 #define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12) 827 #define RT5665_IF2_1_ADC_IN_SFT 12 828 #define RT5665_IF2_1_DAC_SEL_MASK (0x3 << 10) 829 #define RT5665_IF2_1_DAC_SEL_SFT 10 830 #define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8) 831 #define RT5665_IF2_1_ADC_SEL_SFT 8 832 #define RT5665_IF2_2_ADC_IN_MASK (0x7 << 4) 833 #define RT5665_IF2_2_ADC_IN_SFT 4 834 #define RT5665_IF2_2_DAC_SEL_MASK (0x3 << 2) 835 #define RT5665_IF2_2_DAC_SEL_SFT 2 836 #define RT5665_IF2_2_ADC_SEL_MASK (0x3 << 0) 837 #define RT5665_IF2_2_ADC_SEL_SFT 0 838 839 /* Digital Interface Data Control (0x0030) */ 840 #define RT5665_IF3_ADC_IN_MASK (0x7 << 4) 841 #define RT5665_IF3_ADC_IN_SFT 4 842 #define RT5665_IF3_DAC_SEL_MASK (0x3 << 2) 843 #define RT5665_IF3_DAC_SEL_SFT 2 844 #define RT5665_IF3_ADC_SEL_MASK (0x3 << 0) 845 #define RT5665_IF3_ADC_SEL_SFT 0 846 847 /* PDM Output Control (0x0031) */ 848 #define RT5665_M_PDM1_L (0x1 << 14) 849 #define RT5665_M_PDM1_L_SFT 14 850 #define RT5665_M_PDM1_R (0x1 << 12) 851 #define RT5665_M_PDM1_R_SFT 12 852 #define RT5665_PDM1_L_MASK (0x3 << 10) 853 #define RT5665_PDM1_L_SFT 10 854 #define RT5665_PDM1_R_MASK (0x3 << 8) 855 #define RT5665_PDM1_R_SFT 8 856 #define RT5665_PDM1_BUSY (0x1 << 6) 857 #define RT5665_PDM_PATTERN (0x1 << 5) 858 #define RT5665_PDM_GAIN (0x1 << 4) 859 #define RT5665_LRCK_PDM_PI2C (0x1 << 3) 860 #define RT5665_PDM_DIV_MASK (0x3) 861 862 /*S/PDIF Output Control (0x0036) */ 863 #define RT5665_SPDIF_SEL_MASK (0x3 << 0) 864 #define RT5665_SPDIF_SEL_SFT 0 865 866 /* REC Left Mixer Control 2 (0x003c) */ 867 #define RT5665_M_CBJ_RM1_L (0x1 << 7) 868 #define RT5665_M_CBJ_RM1_L_SFT 7 869 #define RT5665_M_BST1_RM1_L (0x1 << 5) 870 #define RT5665_M_BST1_RM1_L_SFT 5 871 #define RT5665_M_BST2_RM1_L (0x1 << 4) 872 #define RT5665_M_BST2_RM1_L_SFT 4 873 #define RT5665_M_BST3_RM1_L (0x1 << 3) 874 #define RT5665_M_BST3_RM1_L_SFT 3 875 #define RT5665_M_BST4_RM1_L (0x1 << 2) 876 #define RT5665_M_BST4_RM1_L_SFT 2 877 #define RT5665_M_INL_RM1_L (0x1 << 1) 878 #define RT5665_M_INL_RM1_L_SFT 1 879 #define RT5665_M_INR_RM1_L (0x1) 880 #define RT5665_M_INR_RM1_L_SFT 0 881 882 /* REC Right Mixer Control 2 (0x003e) */ 883 #define RT5665_M_AEC_REF_RM1_R (0x1 << 7) 884 #define RT5665_M_AEC_REF_RM1_R_SFT 7 885 #define RT5665_M_BST1_RM1_R (0x1 << 5) 886 #define RT5665_M_BST1_RM1_R_SFT 5 887 #define RT5665_M_BST2_RM1_R (0x1 << 4) 888 #define RT5665_M_BST2_RM1_R_SFT 4 889 #define RT5665_M_BST3_RM1_R (0x1 << 3) 890 #define RT5665_M_BST3_RM1_R_SFT 3 891 #define RT5665_M_BST4_RM1_R (0x1 << 2) 892 #define RT5665_M_BST4_RM1_R_SFT 2 893 #define RT5665_M_INR_RM1_R (0x1 << 1) 894 #define RT5665_M_INR_RM1_R_SFT 1 895 #define RT5665_M_MONOVOL_RM1_R (0x1) 896 #define RT5665_M_MONOVOL_RM1_R_SFT 0 897 898 /* REC Mixer 2 Left Control 2 (0x0041) */ 899 #define RT5665_M_CBJ_RM2_L (0x1 << 7) 900 #define RT5665_M_CBJ_RM2_L_SFT 7 901 #define RT5665_M_BST1_RM2_L (0x1 << 5) 902 #define RT5665_M_BST1_RM2_L_SFT 5 903 #define RT5665_M_BST2_RM2_L (0x1 << 4) 904 #define RT5665_M_BST2_RM2_L_SFT 4 905 #define RT5665_M_BST3_RM2_L (0x1 << 3) 906 #define RT5665_M_BST3_RM2_L_SFT 3 907 #define RT5665_M_BST4_RM2_L (0x1 << 2) 908 #define RT5665_M_BST4_RM2_L_SFT 2 909 #define RT5665_M_INL_RM2_L (0x1 << 1) 910 #define RT5665_M_INL_RM2_L_SFT 1 911 #define RT5665_M_INR_RM2_L (0x1) 912 #define RT5665_M_INR_RM2_L_SFT 0 913 914 /* REC Mixer 2 Right Control 2 (0x0043) */ 915 #define RT5665_M_MONOVOL_RM2_R (0x1 << 7) 916 #define RT5665_M_MONOVOL_RM2_R_SFT 7 917 #define RT5665_M_BST1_RM2_R (0x1 << 5) 918 #define RT5665_M_BST1_RM2_R_SFT 5 919 #define RT5665_M_BST2_RM2_R (0x1 << 4) 920 #define RT5665_M_BST2_RM2_R_SFT 4 921 #define RT5665_M_BST3_RM2_R (0x1 << 3) 922 #define RT5665_M_BST3_RM2_R_SFT 3 923 #define RT5665_M_BST4_RM2_R (0x1 << 2) 924 #define RT5665_M_BST4_RM2_R_SFT 2 925 #define RT5665_M_INL_RM2_R (0x1 << 1) 926 #define RT5665_M_INL_RM2_R_SFT 1 927 #define RT5665_M_INR_RM2_R (0x1) 928 #define RT5665_M_INR_RM2_R_SFT 0 929 930 /* SPK Left Mixer Control (0x0046) */ 931 #define RT5665_M_BST3_SM_L (0x1 << 4) 932 #define RT5665_M_BST3_SM_L_SFT 4 933 #define RT5665_M_IN_R_SM_L (0x1 << 3) 934 #define RT5665_M_IN_R_SM_L_SFT 3 935 #define RT5665_M_IN_L_SM_L (0x1 << 2) 936 #define RT5665_M_IN_L_SM_L_SFT 2 937 #define RT5665_M_BST1_SM_L (0x1 << 1) 938 #define RT5665_M_BST1_SM_L_SFT 1 939 #define RT5665_M_DAC_L2_SM_L (0x1) 940 #define RT5665_M_DAC_L2_SM_L_SFT 0 941 942 /* SPK Right Mixer Control (0x0047) */ 943 #define RT5665_M_BST3_SM_R (0x1 << 4) 944 #define RT5665_M_BST3_SM_R_SFT 4 945 #define RT5665_M_IN_R_SM_R (0x1 << 3) 946 #define RT5665_M_IN_R_SM_R_SFT 3 947 #define RT5665_M_IN_L_SM_R (0x1 << 2) 948 #define RT5665_M_IN_L_SM_R_SFT 2 949 #define RT5665_M_BST4_SM_R (0x1 << 1) 950 #define RT5665_M_BST4_SM_R_SFT 1 951 #define RT5665_M_DAC_R2_SM_R (0x1) 952 #define RT5665_M_DAC_R2_SM_R_SFT 0 953 954 /* SPO Amp Input and Gain Control (0x0048) */ 955 #define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13) 956 #define RT5665_M_DAC_L2_SPKOMIX_SFT 13 957 #define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12) 958 #define RT5665_M_SPKVOLL_SPKOMIX_SFT 12 959 #define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9) 960 #define RT5665_M_DAC_R2_SPKOMIX_SFT 9 961 #define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8) 962 #define RT5665_M_SPKVOLR_SPKOMIX_SFT 8 963 964 /* MONOMIX Input and Gain Control (0x004b) */ 965 #define RT5665_G_MONOVOL_MA (0x1 << 10) 966 #define RT5665_G_MONOVOL_MA_SFT 10 967 #define RT5665_M_MONOVOL_MA (0x1 << 9) 968 #define RT5665_M_MONOVOL_MA_SFT 9 969 #define RT5665_M_DAC_L2_MA (0x1 << 8) 970 #define RT5665_M_DAC_L2_MA_SFT 8 971 #define RT5665_M_BST3_MM (0x1 << 4) 972 #define RT5665_M_BST3_MM_SFT 4 973 #define RT5665_M_BST2_MM (0x1 << 3) 974 #define RT5665_M_BST2_MM_SFT 3 975 #define RT5665_M_BST1_MM (0x1 << 2) 976 #define RT5665_M_BST1_MM_SFT 2 977 #define RT5665_M_RECMIC2L_MM (0x1 << 1) 978 #define RT5665_M_RECMIC2L_MM_SFT 1 979 #define RT5665_M_DAC_L2_MM (0x1) 980 #define RT5665_M_DAC_L2_MM_SFT 0 981 982 /* Output Left Mixer Control 1 (0x004d) */ 983 #define RT5665_G_BST3_OM_L_MASK (0x7 << 12) 984 #define RT5665_G_BST3_OM_L_SFT 12 985 #define RT5665_G_BST2_OM_L_MASK (0x7 << 9) 986 #define RT5665_G_BST2_OM_L_SFT 9 987 #define RT5665_G_BST1_OM_L_MASK (0x7 << 6) 988 #define RT5665_G_BST1_OM_L_SFT 6 989 #define RT5665_G_IN_L_OM_L_MASK (0x7 << 3) 990 #define RT5665_G_IN_L_OM_L_SFT 3 991 #define RT5665_G_DAC_L2_OM_L_MASK (0x7 << 0) 992 #define RT5665_G_DAC_L2_OM_L_SFT 0 993 994 /* Output Left Mixer Input Control (0x004e) */ 995 #define RT5665_M_BST3_OM_L (0x1 << 4) 996 #define RT5665_M_BST3_OM_L_SFT 4 997 #define RT5665_M_BST2_OM_L (0x1 << 3) 998 #define RT5665_M_BST2_OM_L_SFT 3 999 #define RT5665_M_BST1_OM_L (0x1 << 2) 1000 #define RT5665_M_BST1_OM_L_SFT 2 1001 #define RT5665_M_IN_L_OM_L (0x1 << 1) 1002 #define RT5665_M_IN_L_OM_L_SFT 1 1003 #define RT5665_M_DAC_L2_OM_L (0x1) 1004 #define RT5665_M_DAC_L2_OM_L_SFT 0 1005 1006 /* Output Right Mixer Input Control (0x0050) */ 1007 #define RT5665_M_BST4_OM_R (0x1 << 4) 1008 #define RT5665_M_BST4_OM_R_SFT 4 1009 #define RT5665_M_BST3_OM_R (0x1 << 3) 1010 #define RT5665_M_BST3_OM_R_SFT 3 1011 #define RT5665_M_BST2_OM_R (0x1 << 2) 1012 #define RT5665_M_BST2_OM_R_SFT 2 1013 #define RT5665_M_IN_R_OM_R (0x1 << 1) 1014 #define RT5665_M_IN_R_OM_R_SFT 1 1015 #define RT5665_M_DAC_R2_OM_R (0x1) 1016 #define RT5665_M_DAC_R2_OM_R_SFT 0 1017 1018 /* LOUT Mixer Control (0x0052) */ 1019 #define RT5665_M_DAC_L2_LM (0x1 << 15) 1020 #define RT5665_M_DAC_L2_LM_SFT 15 1021 #define RT5665_M_DAC_R2_LM (0x1 << 14) 1022 #define RT5665_M_DAC_R2_LM_SFT 14 1023 #define RT5665_M_OV_L_LM (0x1 << 13) 1024 #define RT5665_M_OV_L_LM_SFT 13 1025 #define RT5665_M_OV_R_LM (0x1 << 12) 1026 #define RT5665_M_OV_R_LM_SFT 12 1027 #define RT5665_LOUT_BST_SFT 11 1028 #define RT5665_LOUT_DF (0x1 << 11) 1029 #define RT5665_LOUT_DF_SFT 11 1030 1031 /* Power Management for Digital 1 (0x0061) */ 1032 #define RT5665_PWR_I2S1_1 (0x1 << 15) 1033 #define RT5665_PWR_I2S1_1_BIT 15 1034 #define RT5665_PWR_I2S1_2 (0x1 << 14) 1035 #define RT5665_PWR_I2S1_2_BIT 14 1036 #define RT5665_PWR_I2S2_1 (0x1 << 13) 1037 #define RT5665_PWR_I2S2_1_BIT 13 1038 #define RT5665_PWR_I2S2_2 (0x1 << 12) 1039 #define RT5665_PWR_I2S2_2_BIT 12 1040 #define RT5665_PWR_DAC_L1 (0x1 << 11) 1041 #define RT5665_PWR_DAC_L1_BIT 11 1042 #define RT5665_PWR_DAC_R1 (0x1 << 10) 1043 #define RT5665_PWR_DAC_R1_BIT 10 1044 #define RT5665_PWR_I2S3 (0x1 << 9) 1045 #define RT5665_PWR_I2S3_BIT 9 1046 #define RT5665_PWR_LDO (0x1 << 8) 1047 #define RT5665_PWR_LDO_BIT 8 1048 #define RT5665_PWR_DAC_L2 (0x1 << 7) 1049 #define RT5665_PWR_DAC_L2_BIT 7 1050 #define RT5665_PWR_DAC_R2 (0x1 << 6) 1051 #define RT5665_PWR_DAC_R2_BIT 6 1052 #define RT5665_PWR_ADC_L1 (0x1 << 4) 1053 #define RT5665_PWR_ADC_L1_BIT 4 1054 #define RT5665_PWR_ADC_R1 (0x1 << 3) 1055 #define RT5665_PWR_ADC_R1_BIT 3 1056 #define RT5665_PWR_ADC_L2 (0x1 << 2) 1057 #define RT5665_PWR_ADC_L2_BIT 2 1058 #define RT5665_PWR_ADC_R2 (0x1 << 1) 1059 #define RT5665_PWR_ADC_R2_BIT 1 1060 1061 /* Power Management for Digital 2 (0x0062) */ 1062 #define RT5665_PWR_ADC_S1F (0x1 << 15) 1063 #define RT5665_PWR_ADC_S1F_BIT 15 1064 #define RT5665_PWR_ADC_S2F (0x1 << 14) 1065 #define RT5665_PWR_ADC_S2F_BIT 14 1066 #define RT5665_PWR_ADC_MF_L (0x1 << 13) 1067 #define RT5665_PWR_ADC_MF_L_BIT 13 1068 #define RT5665_PWR_ADC_MF_R (0x1 << 12) 1069 #define RT5665_PWR_ADC_MF_R_BIT 12 1070 #define RT5665_PWR_DAC_S2F (0x1 << 11) 1071 #define RT5665_PWR_DAC_S2F_BIT 11 1072 #define RT5665_PWR_DAC_S1F (0x1 << 10) 1073 #define RT5665_PWR_DAC_S1F_BIT 10 1074 #define RT5665_PWR_DAC_MF_L (0x1 << 9) 1075 #define RT5665_PWR_DAC_MF_L_BIT 9 1076 #define RT5665_PWR_DAC_MF_R (0x1 << 8) 1077 #define RT5665_PWR_DAC_MF_R_BIT 8 1078 #define RT5665_PWR_PDM1 (0x1 << 7) 1079 #define RT5665_PWR_PDM1_BIT 7 1080 1081 /* Power Management for Analog 1 (0x0063) */ 1082 #define RT5665_PWR_VREF1 (0x1 << 15) 1083 #define RT5665_PWR_VREF1_BIT 15 1084 #define RT5665_PWR_FV1 (0x1 << 14) 1085 #define RT5665_PWR_FV1_BIT 14 1086 #define RT5665_PWR_VREF2 (0x1 << 13) 1087 #define RT5665_PWR_VREF2_BIT 13 1088 #define RT5665_PWR_FV2 (0x1 << 12) 1089 #define RT5665_PWR_FV2_BIT 12 1090 #define RT5665_PWR_VREF3 (0x1 << 11) 1091 #define RT5665_PWR_VREF3_BIT 11 1092 #define RT5665_PWR_FV3 (0x1 << 10) 1093 #define RT5665_PWR_FV3_BIT 10 1094 #define RT5665_PWR_MB (0x1 << 9) 1095 #define RT5665_PWR_MB_BIT 9 1096 #define RT5665_PWR_LM (0x1 << 8) 1097 #define RT5665_PWR_LM_BIT 8 1098 #define RT5665_PWR_BG (0x1 << 7) 1099 #define RT5665_PWR_BG_BIT 7 1100 #define RT5665_PWR_MA (0x1 << 6) 1101 #define RT5665_PWR_MA_BIT 6 1102 #define RT5665_PWR_HA_L (0x1 << 5) 1103 #define RT5665_PWR_HA_L_BIT 5 1104 #define RT5665_PWR_HA_R (0x1 << 4) 1105 #define RT5665_PWR_HA_R_BIT 4 1106 #define RT5665_HP_DRIVER_MASK (0x3 << 2) 1107 #define RT5665_HP_DRIVER_1X (0x0 << 2) 1108 #define RT5665_HP_DRIVER_3X (0x1 << 2) 1109 #define RT5665_HP_DRIVER_5X (0x3 << 2) 1110 #define RT5665_LDO1_DVO_MASK (0x3) 1111 #define RT5665_LDO1_DVO_09 (0x0) 1112 #define RT5665_LDO1_DVO_10 (0x1) 1113 #define RT5665_LDO1_DVO_12 (0x2) 1114 #define RT5665_LDO1_DVO_14 (0x3) 1115 1116 /* Power Management for Analog 2 (0x0064) */ 1117 #define RT5665_PWR_BST1 (0x1 << 15) 1118 #define RT5665_PWR_BST1_BIT 15 1119 #define RT5665_PWR_BST2 (0x1 << 14) 1120 #define RT5665_PWR_BST2_BIT 14 1121 #define RT5665_PWR_BST3 (0x1 << 13) 1122 #define RT5665_PWR_BST3_BIT 13 1123 #define RT5665_PWR_BST4 (0x1 << 12) 1124 #define RT5665_PWR_BST4_BIT 12 1125 #define RT5665_PWR_MB1 (0x1 << 11) 1126 #define RT5665_PWR_MB1_PWR_DOWN (0x0 << 11) 1127 #define RT5665_PWR_MB1_BIT 11 1128 #define RT5665_PWR_MB2 (0x1 << 10) 1129 #define RT5665_PWR_MB2_PWR_DOWN (0x0 << 10) 1130 #define RT5665_PWR_MB2_BIT 10 1131 #define RT5665_PWR_MB3 (0x1 << 9) 1132 #define RT5665_PWR_MB3_BIT 9 1133 #define RT5665_PWR_BST1_P (0x1 << 7) 1134 #define RT5665_PWR_BST1_P_BIT 7 1135 #define RT5665_PWR_BST2_P (0x1 << 6) 1136 #define RT5665_PWR_BST2_P_BIT 6 1137 #define RT5665_PWR_BST3_P (0x1 << 5) 1138 #define RT5665_PWR_BST3_P_BIT 5 1139 #define RT5665_PWR_BST4_P (0x1 << 4) 1140 #define RT5665_PWR_BST4_P_BIT 4 1141 #define RT5665_PWR_JD1 (0x1 << 3) 1142 #define RT5665_PWR_JD1_BIT 3 1143 #define RT5665_PWR_JD2 (0x1 << 2) 1144 #define RT5665_PWR_JD2_BIT 2 1145 #define RT5665_PWR_RM1_L (0x1 << 1) 1146 #define RT5665_PWR_RM1_L_BIT 1 1147 #define RT5665_PWR_RM1_R (0x1) 1148 #define RT5665_PWR_RM1_R_BIT 0 1149 1150 /* Power Management for Analog 3 (0x0065) */ 1151 #define RT5665_PWR_CBJ (0x1 << 9) 1152 #define RT5665_PWR_CBJ_BIT 9 1153 #define RT5665_PWR_BST_L (0x1 << 8) 1154 #define RT5665_PWR_BST_L_BIT 8 1155 #define RT5665_PWR_BST_R (0x1 << 7) 1156 #define RT5665_PWR_BST_R_BIT 7 1157 #define RT5665_PWR_PLL (0x1 << 6) 1158 #define RT5665_PWR_PLL_BIT 6 1159 #define RT5665_PWR_LDO2 (0x1 << 2) 1160 #define RT5665_PWR_LDO2_BIT 2 1161 #define RT5665_PWR_SVD (0x1 << 1) 1162 #define RT5665_PWR_SVD_BIT 1 1163 1164 /* Power Management for Mixer (0x0066) */ 1165 #define RT5665_PWR_RM2_L (0x1 << 15) 1166 #define RT5665_PWR_RM2_L_BIT 15 1167 #define RT5665_PWR_RM2_R (0x1 << 14) 1168 #define RT5665_PWR_RM2_R_BIT 14 1169 #define RT5665_PWR_OM_L (0x1 << 13) 1170 #define RT5665_PWR_OM_L_BIT 13 1171 #define RT5665_PWR_OM_R (0x1 << 12) 1172 #define RT5665_PWR_OM_R_BIT 12 1173 #define RT5665_PWR_MM (0x1 << 11) 1174 #define RT5665_PWR_MM_BIT 11 1175 #define RT5665_PWR_AEC_REF (0x1 << 6) 1176 #define RT5665_PWR_AEC_REF_BIT 6 1177 #define RT5665_PWR_STO1_DAC_L (0x1 << 5) 1178 #define RT5665_PWR_STO1_DAC_L_BIT 5 1179 #define RT5665_PWR_STO1_DAC_R (0x1 << 4) 1180 #define RT5665_PWR_STO1_DAC_R_BIT 4 1181 #define RT5665_PWR_MONO_DAC_L (0x1 << 3) 1182 #define RT5665_PWR_MONO_DAC_L_BIT 3 1183 #define RT5665_PWR_MONO_DAC_R (0x1 << 2) 1184 #define RT5665_PWR_MONO_DAC_R_BIT 2 1185 #define RT5665_PWR_STO2_DAC_L (0x1 << 1) 1186 #define RT5665_PWR_STO2_DAC_L_BIT 1 1187 #define RT5665_PWR_STO2_DAC_R (0x1) 1188 #define RT5665_PWR_STO2_DAC_R_BIT 0 1189 1190 /* Power Management for Volume (0x0067) */ 1191 #define RT5665_PWR_OV_L (0x1 << 13) 1192 #define RT5665_PWR_OV_L_BIT 13 1193 #define RT5665_PWR_OV_R (0x1 << 12) 1194 #define RT5665_PWR_OV_R_BIT 12 1195 #define RT5665_PWR_IN_L (0x1 << 9) 1196 #define RT5665_PWR_IN_L_BIT 9 1197 #define RT5665_PWR_IN_R (0x1 << 8) 1198 #define RT5665_PWR_IN_R_BIT 8 1199 #define RT5665_PWR_MV (0x1 << 7) 1200 #define RT5665_PWR_MV_BIT 7 1201 #define RT5665_PWR_MIC_DET (0x1 << 5) 1202 #define RT5665_PWR_MIC_DET_BIT 5 1203 1204 /* (0x006b) */ 1205 #define RT5665_SYS_CLK_DET 15 1206 #define RT5665_HP_CLK_DET 14 1207 #define RT5665_MONO_CLK_DET 13 1208 #define RT5665_LOUT_CLK_DET 12 1209 #define RT5665_POW_CLK_DET 0 1210 1211 /* Digital Microphone Control 1 (0x006e) */ 1212 #define RT5665_DMIC_1_EN_MASK (0x1 << 15) 1213 #define RT5665_DMIC_1_EN_SFT 15 1214 #define RT5665_DMIC_1_DIS (0x0 << 15) 1215 #define RT5665_DMIC_1_EN (0x1 << 15) 1216 #define RT5665_DMIC_2_EN_MASK (0x1 << 14) 1217 #define RT5665_DMIC_2_EN_SFT 14 1218 #define RT5665_DMIC_2_DIS (0x0 << 14) 1219 #define RT5665_DMIC_2_EN (0x1 << 14) 1220 #define RT5665_DMIC_2_DP_MASK (0x1 << 9) 1221 #define RT5665_DMIC_2_DP_SFT 9 1222 #define RT5665_DMIC_2_DP_GPIO5 (0x0 << 9) 1223 #define RT5665_DMIC_2_DP_IN2P (0x1 << 9) 1224 #define RT5665_DMIC_CLK_MASK (0x7 << 5) 1225 #define RT5665_DMIC_CLK_SFT 5 1226 #define RT5665_DMIC_1_DP_MASK (0x1 << 1) 1227 #define RT5665_DMIC_1_DP_SFT 1 1228 #define RT5665_DMIC_1_DP_GPIO4 (0x0 << 1) 1229 #define RT5665_DMIC_1_DP_IN2N (0x1 << 1) 1230 1231 1232 /* Digital Microphone Control 1 (0x006f) */ 1233 #define RT5665_DMIC_2L_LH_MASK (0x1 << 3) 1234 #define RT5665_DMIC_2L_LH_SFT 3 1235 #define RT5665_DMIC_2L_LH_RISING (0x0 << 3) 1236 #define RT5665_DMIC_2L_LH_FALLING (0x1 << 3) 1237 #define RT5665_DMIC_2R_LH_MASK (0x1 << 2) 1238 #define RT5665_DMIC_2R_LH_SFT 2 1239 #define RT5665_DMIC_2R_LH_RISING (0x0 << 2) 1240 #define RT5665_DMIC_2R_LH_FALLING (0x1 << 2) 1241 #define RT5665_DMIC_1L_LH_MASK (0x1 << 1) 1242 #define RT5665_DMIC_1L_LH_SFT 1 1243 #define RT5665_DMIC_1L_LH_RISING (0x0 << 1) 1244 #define RT5665_DMIC_1L_LH_FALLING (0x1 << 1) 1245 #define RT5665_DMIC_1R_LH_MASK (0x1 << 0) 1246 #define RT5665_DMIC_1R_LH_SFT 0 1247 #define RT5665_DMIC_1R_LH_RISING (0x0) 1248 #define RT5665_DMIC_1R_LH_FALLING (0x1) 1249 1250 /* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */ 1251 #define RT5665_I2S_MS_MASK (0x1 << 15) 1252 #define RT5665_I2S_MS_SFT 15 1253 #define RT5665_I2S_MS_M (0x0 << 15) 1254 #define RT5665_I2S_MS_S (0x1 << 15) 1255 #define RT5665_I2S_PIN_CFG_MASK (0x1 << 14) 1256 #define RT5665_I2S_PIN_CFG_SFT 14 1257 #define RT5665_I2S_CLK_SEL_MASK (0x1 << 11) 1258 #define RT5665_I2S_CLK_SEL_SFT 11 1259 #define RT5665_I2S_BP_MASK (0x1 << 8) 1260 #define RT5665_I2S_BP_SFT 8 1261 #define RT5665_I2S_BP_NOR (0x0 << 8) 1262 #define RT5665_I2S_BP_INV (0x1 << 8) 1263 #define RT5665_I2S_DL_MASK (0x3 << 4) 1264 #define RT5665_I2S_DL_SFT 4 1265 #define RT5665_I2S_DL_16 (0x0 << 4) 1266 #define RT5665_I2S_DL_20 (0x1 << 4) 1267 #define RT5665_I2S_DL_24 (0x2 << 4) 1268 #define RT5665_I2S_DL_8 (0x3 << 4) 1269 #define RT5665_I2S_DF_MASK (0x7) 1270 #define RT5665_I2S_DF_SFT 0 1271 #define RT5665_I2S_DF_I2S (0x0) 1272 #define RT5665_I2S_DF_LEFT (0x1) 1273 #define RT5665_I2S_DF_PCM_A (0x2) 1274 #define RT5665_I2S_DF_PCM_B (0x3) 1275 #define RT5665_I2S_DF_PCM_A_N (0x6) 1276 #define RT5665_I2S_DF_PCM_B_N (0x7) 1277 1278 /* ADC/DAC Clock Control 1 (0x0073) */ 1279 #define RT5665_I2S_PD1_MASK (0x7 << 12) 1280 #define RT5665_I2S_PD1_SFT 12 1281 #define RT5665_I2S_PD1_1 (0x0 << 12) 1282 #define RT5665_I2S_PD1_2 (0x1 << 12) 1283 #define RT5665_I2S_PD1_3 (0x2 << 12) 1284 #define RT5665_I2S_PD1_4 (0x3 << 12) 1285 #define RT5665_I2S_PD1_6 (0x4 << 12) 1286 #define RT5665_I2S_PD1_8 (0x5 << 12) 1287 #define RT5665_I2S_PD1_12 (0x6 << 12) 1288 #define RT5665_I2S_PD1_16 (0x7 << 12) 1289 #define RT5665_I2S_M_PD2_MASK (0x7 << 8) 1290 #define RT5665_I2S_M_PD2_SFT 8 1291 #define RT5665_I2S_M_PD2_1 (0x0 << 8) 1292 #define RT5665_I2S_M_PD2_2 (0x1 << 8) 1293 #define RT5665_I2S_M_PD2_3 (0x2 << 8) 1294 #define RT5665_I2S_M_PD2_4 (0x3 << 8) 1295 #define RT5665_I2S_M_PD2_6 (0x4 << 8) 1296 #define RT5665_I2S_M_PD2_8 (0x5 << 8) 1297 #define RT5665_I2S_M_PD2_12 (0x6 << 8) 1298 #define RT5665_I2S_M_PD2_16 (0x7 << 8) 1299 #define RT5665_I2S_CLK_SRC_MASK (0x3 << 4) 1300 #define RT5665_I2S_CLK_SRC_SFT 4 1301 #define RT5665_I2S_CLK_SRC_MCLK (0x0 << 4) 1302 #define RT5665_I2S_CLK_SRC_PLL1 (0x1 << 4) 1303 #define RT5665_I2S_CLK_SRC_RCCLK (0x2 << 4) 1304 #define RT5665_DAC_OSR_MASK (0x3 << 2) 1305 #define RT5665_DAC_OSR_SFT 2 1306 #define RT5665_DAC_OSR_128 (0x0 << 2) 1307 #define RT5665_DAC_OSR_64 (0x1 << 2) 1308 #define RT5665_DAC_OSR_32 (0x2 << 2) 1309 #define RT5665_ADC_OSR_MASK (0x3) 1310 #define RT5665_ADC_OSR_SFT 0 1311 #define RT5665_ADC_OSR_128 (0x0) 1312 #define RT5665_ADC_OSR_64 (0x1) 1313 #define RT5665_ADC_OSR_32 (0x2) 1314 1315 /* ADC/DAC Clock Control 2 (0x0074) */ 1316 #define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15) 1317 #define RT5665_I2S_BCLK_MS2_SFT 15 1318 #define RT5665_I2S_BCLK_MS2_32 (0x0 << 15) 1319 #define RT5665_I2S_BCLK_MS2_64 (0x1 << 15) 1320 #define RT5665_I2S_PD2_MASK (0x7 << 12) 1321 #define RT5665_I2S_PD2_SFT 12 1322 #define RT5665_I2S_PD2_1 (0x0 << 12) 1323 #define RT5665_I2S_PD2_2 (0x1 << 12) 1324 #define RT5665_I2S_PD2_3 (0x2 << 12) 1325 #define RT5665_I2S_PD2_4 (0x3 << 12) 1326 #define RT5665_I2S_PD2_6 (0x4 << 12) 1327 #define RT5665_I2S_PD2_8 (0x5 << 12) 1328 #define RT5665_I2S_PD2_12 (0x6 << 12) 1329 #define RT5665_I2S_PD2_16 (0x7 << 12) 1330 #define RT5665_I2S_BCLK_MS3_MASK (0x1 << 11) 1331 #define RT5665_I2S_BCLK_MS3_SFT 11 1332 #define RT5665_I2S_BCLK_MS3_32 (0x0 << 11) 1333 #define RT5665_I2S_BCLK_MS3_64 (0x1 << 11) 1334 #define RT5665_I2S_PD3_MASK (0x7 << 8) 1335 #define RT5665_I2S_PD3_SFT 8 1336 #define RT5665_I2S_PD3_1 (0x0 << 8) 1337 #define RT5665_I2S_PD3_2 (0x1 << 8) 1338 #define RT5665_I2S_PD3_3 (0x2 << 8) 1339 #define RT5665_I2S_PD3_4 (0x3 << 8) 1340 #define RT5665_I2S_PD3_6 (0x4 << 8) 1341 #define RT5665_I2S_PD3_8 (0x5 << 8) 1342 #define RT5665_I2S_PD3_12 (0x6 << 8) 1343 #define RT5665_I2S_PD3_16 (0x7 << 8) 1344 #define RT5665_I2S_PD4_MASK (0x7 << 4) 1345 #define RT5665_I2S_PD4_SFT 4 1346 #define RT5665_I2S_PD4_1 (0x0 << 4) 1347 #define RT5665_I2S_PD4_2 (0x1 << 4) 1348 #define RT5665_I2S_PD4_3 (0x2 << 4) 1349 #define RT5665_I2S_PD4_4 (0x3 << 4) 1350 #define RT5665_I2S_PD4_6 (0x4 << 4) 1351 #define RT5665_I2S_PD4_8 (0x5 << 4) 1352 #define RT5665_I2S_PD4_12 (0x6 << 4) 1353 #define RT5665_I2S_PD4_16 (0x7 << 4) 1354 1355 /* TDM control 1 (0x0078) */ 1356 #define RT5665_I2S1_MODE_MASK (0x1 << 15) 1357 #define RT5665_I2S1_MODE_I2S (0x0 << 15) 1358 #define RT5665_I2S1_MODE_TDM (0x1 << 15) 1359 #define RT5665_TDM_IN_CH_MASK (0x3 << 10) 1360 #define RT5665_TDM_IN_CH_2 (0x0 << 10) 1361 #define RT5665_TDM_IN_CH_4 (0x1 << 10) 1362 #define RT5665_TDM_IN_CH_6 (0x2 << 10) 1363 #define RT5665_TDM_IN_CH_8 (0x3 << 10) 1364 #define RT5665_TDM_OUT_CH_MASK (0x3 << 8) 1365 #define RT5665_TDM_OUT_CH_2 (0x0 << 8) 1366 #define RT5665_TDM_OUT_CH_4 (0x1 << 8) 1367 #define RT5665_TDM_OUT_CH_6 (0x2 << 8) 1368 #define RT5665_TDM_OUT_CH_8 (0x3 << 8) 1369 #define RT5665_TDM_IN_LEN_MASK (0x3 << 6) 1370 #define RT5665_TDM_IN_LEN_16 (0x0 << 6) 1371 #define RT5665_TDM_IN_LEN_20 (0x1 << 6) 1372 #define RT5665_TDM_IN_LEN_24 (0x2 << 6) 1373 #define RT5665_TDM_IN_LEN_32 (0x3 << 6) 1374 #define RT5665_TDM_OUT_LEN_MASK (0x3 << 4) 1375 #define RT5665_TDM_OUT_LEN_16 (0x0 << 4) 1376 #define RT5665_TDM_OUT_LEN_20 (0x1 << 4) 1377 #define RT5665_TDM_OUT_LEN_24 (0x2 << 4) 1378 #define RT5665_TDM_OUT_LEN_32 (0x3 << 4) 1379 1380 1381 /* TDM control 2 (0x0079) */ 1382 #define RT5665_I2S1_1_DS_ADC_SLOT01_SFT 14 1383 #define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12 1384 #define RT5665_I2S1_1_DS_ADC_SLOT45_SFT 10 1385 #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8 1386 #define RT5665_I2S1_2_DS_ADC_SLOT01_SFT 6 1387 #define RT5665_I2S1_2_DS_ADC_SLOT23_SFT 4 1388 #define RT5665_I2S1_2_DS_ADC_SLOT45_SFT 2 1389 #define RT5665_I2S1_2_DS_ADC_SLOT67_SFT 0 1390 1391 /* TDM control 3/4 (0x007a) (0x007b) */ 1392 #define RT5665_IF1_ADC1_SEL_SFT 10 1393 #define RT5665_IF1_ADC2_SEL_SFT 9 1394 #define RT5665_IF1_ADC3_SEL_SFT 8 1395 #define RT5665_IF1_ADC4_SEL_SFT 7 1396 #define RT5665_TDM_ADC_SEL_SFT 0 1397 #define RT5665_TDM_ADC_CTRL_MASK (0x1f << 0) 1398 #define RT5665_TDM_ADC_DATA_06 (0x6 << 0) 1399 1400 /* Global Clock Control (0x0080) */ 1401 #define RT5665_SCLK_SRC_MASK (0x3 << 14) 1402 #define RT5665_SCLK_SRC_SFT 14 1403 #define RT5665_SCLK_SRC_MCLK (0x0 << 14) 1404 #define RT5665_SCLK_SRC_PLL1 (0x1 << 14) 1405 #define RT5665_SCLK_SRC_RCCLK (0x2 << 14) 1406 #define RT5665_PLL1_SRC_MASK (0x7 << 8) 1407 #define RT5665_PLL1_SRC_SFT 8 1408 #define RT5665_PLL1_SRC_MCLK (0x0 << 8) 1409 #define RT5665_PLL1_SRC_BCLK1 (0x1 << 8) 1410 #define RT5665_PLL1_SRC_BCLK2 (0x2 << 8) 1411 #define RT5665_PLL1_SRC_BCLK3 (0x3 << 8) 1412 #define RT5665_PLL1_PD_MASK (0x7 << 4) 1413 #define RT5665_PLL1_PD_SFT 4 1414 1415 1416 #define RT5665_PLL_INP_MAX 40000000 1417 #define RT5665_PLL_INP_MIN 256000 1418 /* PLL M/N/K Code Control 1 (0x0081) */ 1419 #define RT5665_PLL_N_MAX 0x001ff 1420 #define RT5665_PLL_N_MASK (RT5665_PLL_N_MAX << 7) 1421 #define RT5665_PLL_N_SFT 7 1422 #define RT5665_PLL_K_MAX 0x001f 1423 #define RT5665_PLL_K_MASK (RT5665_PLL_K_MAX) 1424 #define RT5665_PLL_K_SFT 0 1425 1426 /* PLL M/N/K Code Control 2 (0x0082) */ 1427 #define RT5665_PLL_M_MAX 0x00f 1428 #define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12) 1429 #define RT5665_PLL_M_SFT 12 1430 #define RT5665_PLL_M_BP (0x1 << 11) 1431 #define RT5665_PLL_M_BP_SFT 11 1432 #define RT5665_PLL_K_BP (0x1 << 10) 1433 #define RT5665_PLL_K_BP_SFT 10 1434 1435 /* PLL tracking mode 1 (0x0083) */ 1436 #define RT5665_I2S3_ASRC_MASK (0x1 << 15) 1437 #define RT5665_I2S3_ASRC_SFT 15 1438 #define RT5665_I2S2_ASRC_MASK (0x1 << 14) 1439 #define RT5665_I2S2_ASRC_SFT 14 1440 #define RT5665_I2S1_ASRC_MASK (0x1 << 13) 1441 #define RT5665_I2S1_ASRC_SFT 13 1442 #define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12) 1443 #define RT5665_DAC_STO1_ASRC_SFT 12 1444 #define RT5665_DAC_STO2_ASRC_MASK (0x1 << 11) 1445 #define RT5665_DAC_STO2_ASRC_SFT 11 1446 #define RT5665_DAC_MONO_L_ASRC_MASK (0x1 << 10) 1447 #define RT5665_DAC_MONO_L_ASRC_SFT 10 1448 #define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9) 1449 #define RT5665_DAC_MONO_R_ASRC_SFT 9 1450 #define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8) 1451 #define RT5665_DMIC_STO1_ASRC_SFT 8 1452 #define RT5665_DMIC_STO2_ASRC_MASK (0x1 << 7) 1453 #define RT5665_DMIC_STO2_ASRC_SFT 7 1454 #define RT5665_DMIC_MONO_L_ASRC_MASK (0x1 << 6) 1455 #define RT5665_DMIC_MONO_L_ASRC_SFT 6 1456 #define RT5665_DMIC_MONO_R_ASRC_MASK (0x1 << 5) 1457 #define RT5665_DMIC_MONO_R_ASRC_SFT 5 1458 #define RT5665_ADC_STO1_ASRC_MASK (0x1 << 4) 1459 #define RT5665_ADC_STO1_ASRC_SFT 4 1460 #define RT5665_ADC_STO2_ASRC_MASK (0x1 << 3) 1461 #define RT5665_ADC_STO2_ASRC_SFT 3 1462 #define RT5665_ADC_MONO_L_ASRC_MASK (0x1 << 2) 1463 #define RT5665_ADC_MONO_L_ASRC_SFT 2 1464 #define RT5665_ADC_MONO_R_ASRC_MASK (0x1 << 1) 1465 #define RT5665_ADC_MONO_R_ASRC_SFT 1 1466 1467 /* PLL tracking mode 2 (0x0084)*/ 1468 #define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12) 1469 #define RT5665_DA_STO1_CLK_SEL_SFT 12 1470 #define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8) 1471 #define RT5665_DA_STO2_CLK_SEL_SFT 8 1472 #define RT5665_DA_MONOL_CLK_SEL_MASK (0x7 << 4) 1473 #define RT5665_DA_MONOL_CLK_SEL_SFT 4 1474 #define RT5665_DA_MONOR_CLK_SEL_MASK (0x7) 1475 #define RT5665_DA_MONOR_CLK_SEL_SFT 0 1476 1477 /* PLL tracking mode 3 (0x0085)*/ 1478 #define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12) 1479 #define RT5665_AD_STO1_CLK_SEL_SFT 12 1480 #define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8) 1481 #define RT5665_AD_STO2_CLK_SEL_SFT 8 1482 #define RT5665_AD_MONOL_CLK_SEL_MASK (0x7 << 4) 1483 #define RT5665_AD_MONOL_CLK_SEL_SFT 4 1484 #define RT5665_AD_MONOR_CLK_SEL_MASK (0x7) 1485 #define RT5665_AD_MONOR_CLK_SEL_SFT 0 1486 1487 /* ASRC Control 4 (0x0086) */ 1488 #define RT5665_I2S1_RATE_MASK (0xf << 12) 1489 #define RT5665_I2S1_RATE_SFT 12 1490 #define RT5665_I2S2_RATE_MASK (0xf << 8) 1491 #define RT5665_I2S2_RATE_SFT 8 1492 #define RT5665_I2S3_RATE_MASK (0xf << 4) 1493 #define RT5665_I2S3_RATE_SFT 4 1494 1495 /* Depop Mode Control 1 (0x008e) */ 1496 #define RT5665_PUMP_EN (0x1 << 3) 1497 1498 /* Depop Mode Control 2 (0x8f) */ 1499 #define RT5665_DEPOP_MASK (0x1 << 13) 1500 #define RT5665_DEPOP_SFT 13 1501 #define RT5665_DEPOP_AUTO (0x0 << 13) 1502 #define RT5665_DEPOP_MAN (0x1 << 13) 1503 #define RT5665_RAMP_MASK (0x1 << 12) 1504 #define RT5665_RAMP_SFT 12 1505 #define RT5665_RAMP_DIS (0x0 << 12) 1506 #define RT5665_RAMP_EN (0x1 << 12) 1507 #define RT5665_BPS_MASK (0x1 << 11) 1508 #define RT5665_BPS_SFT 11 1509 #define RT5665_BPS_DIS (0x0 << 11) 1510 #define RT5665_BPS_EN (0x1 << 11) 1511 #define RT5665_FAST_UPDN_MASK (0x1 << 10) 1512 #define RT5665_FAST_UPDN_SFT 10 1513 #define RT5665_FAST_UPDN_DIS (0x0 << 10) 1514 #define RT5665_FAST_UPDN_EN (0x1 << 10) 1515 #define RT5665_MRES_MASK (0x3 << 8) 1516 #define RT5665_MRES_SFT 8 1517 #define RT5665_MRES_15MO (0x0 << 8) 1518 #define RT5665_MRES_25MO (0x1 << 8) 1519 #define RT5665_MRES_35MO (0x2 << 8) 1520 #define RT5665_MRES_45MO (0x3 << 8) 1521 #define RT5665_VLO_MASK (0x1 << 7) 1522 #define RT5665_VLO_SFT 7 1523 #define RT5665_VLO_3V (0x0 << 7) 1524 #define RT5665_VLO_32V (0x1 << 7) 1525 #define RT5665_DIG_DP_MASK (0x1 << 6) 1526 #define RT5665_DIG_DP_SFT 6 1527 #define RT5665_DIG_DP_DIS (0x0 << 6) 1528 #define RT5665_DIG_DP_EN (0x1 << 6) 1529 #define RT5665_DP_TH_MASK (0x3 << 4) 1530 #define RT5665_DP_TH_SFT 4 1531 1532 /* Depop Mode Control 3 (0x90) */ 1533 #define RT5665_CP_SYS_MASK (0x7 << 12) 1534 #define RT5665_CP_SYS_SFT 12 1535 #define RT5665_CP_FQ1_MASK (0x7 << 8) 1536 #define RT5665_CP_FQ1_SFT 8 1537 #define RT5665_CP_FQ2_MASK (0x7 << 4) 1538 #define RT5665_CP_FQ2_SFT 4 1539 #define RT5665_CP_FQ3_MASK (0x7) 1540 #define RT5665_CP_FQ3_SFT 0 1541 #define RT5665_CP_FQ_1_5_KHZ 0 1542 #define RT5665_CP_FQ_3_KHZ 1 1543 #define RT5665_CP_FQ_6_KHZ 2 1544 #define RT5665_CP_FQ_12_KHZ 3 1545 #define RT5665_CP_FQ_24_KHZ 4 1546 #define RT5665_CP_FQ_48_KHZ 5 1547 #define RT5665_CP_FQ_96_KHZ 6 1548 #define RT5665_CP_FQ_192_KHZ 7 1549 1550 /* HPOUT charge pump 1 (0x0091) */ 1551 #define RT5665_OSW_L_MASK (0x1 << 11) 1552 #define RT5665_OSW_L_SFT 11 1553 #define RT5665_OSW_L_DIS (0x0 << 11) 1554 #define RT5665_OSW_L_EN (0x1 << 11) 1555 #define RT5665_OSW_R_MASK (0x1 << 10) 1556 #define RT5665_OSW_R_SFT 10 1557 #define RT5665_OSW_R_DIS (0x0 << 10) 1558 #define RT5665_OSW_R_EN (0x1 << 10) 1559 #define RT5665_PM_HP_MASK (0x3 << 8) 1560 #define RT5665_PM_HP_SFT 8 1561 #define RT5665_PM_HP_LV (0x0 << 8) 1562 #define RT5665_PM_HP_MV (0x1 << 8) 1563 #define RT5665_PM_HP_HV (0x2 << 8) 1564 #define RT5665_IB_HP_MASK (0x3 << 6) 1565 #define RT5665_IB_HP_SFT 6 1566 #define RT5665_IB_HP_125IL (0x0 << 6) 1567 #define RT5665_IB_HP_25IL (0x1 << 6) 1568 #define RT5665_IB_HP_5IL (0x2 << 6) 1569 #define RT5665_IB_HP_1IL (0x3 << 6) 1570 1571 /* PV detection and SPK gain control (0x92) */ 1572 #define RT5665_PVDD_DET_MASK (0x1 << 15) 1573 #define RT5665_PVDD_DET_SFT 15 1574 #define RT5665_PVDD_DET_DIS (0x0 << 15) 1575 #define RT5665_PVDD_DET_EN (0x1 << 15) 1576 #define RT5665_SPK_AG_MASK (0x1 << 14) 1577 #define RT5665_SPK_AG_SFT 14 1578 #define RT5665_SPK_AG_DIS (0x0 << 14) 1579 #define RT5665_SPK_AG_EN (0x1 << 14) 1580 1581 /* Micbias Control1 (0x93) */ 1582 #define RT5665_MIC1_BS_MASK (0x1 << 15) 1583 #define RT5665_MIC1_BS_SFT 15 1584 #define RT5665_MIC1_BS_9AV (0x0 << 15) 1585 #define RT5665_MIC1_BS_75AV (0x1 << 15) 1586 #define RT5665_MIC2_BS_MASK (0x1 << 14) 1587 #define RT5665_MIC2_BS_SFT 14 1588 #define RT5665_MIC2_BS_9AV (0x0 << 14) 1589 #define RT5665_MIC2_BS_75AV (0x1 << 14) 1590 #define RT5665_MIC1_CLK_MASK (0x1 << 13) 1591 #define RT5665_MIC1_CLK_SFT 13 1592 #define RT5665_MIC1_CLK_DIS (0x0 << 13) 1593 #define RT5665_MIC1_CLK_EN (0x1 << 13) 1594 #define RT5665_MIC2_CLK_MASK (0x1 << 12) 1595 #define RT5665_MIC2_CLK_SFT 12 1596 #define RT5665_MIC2_CLK_DIS (0x0 << 12) 1597 #define RT5665_MIC2_CLK_EN (0x1 << 12) 1598 #define RT5665_MIC1_OVCD_MASK (0x1 << 11) 1599 #define RT5665_MIC1_OVCD_SFT 11 1600 #define RT5665_MIC1_OVCD_DIS (0x0 << 11) 1601 #define RT5665_MIC1_OVCD_EN (0x1 << 11) 1602 #define RT5665_MIC1_OVTH_MASK (0x3 << 9) 1603 #define RT5665_MIC1_OVTH_SFT 9 1604 #define RT5665_MIC1_OVTH_600UA (0x0 << 9) 1605 #define RT5665_MIC1_OVTH_1500UA (0x1 << 9) 1606 #define RT5665_MIC1_OVTH_2000UA (0x2 << 9) 1607 #define RT5665_MIC2_OVCD_MASK (0x1 << 8) 1608 #define RT5665_MIC2_OVCD_SFT 8 1609 #define RT5665_MIC2_OVCD_DIS (0x0 << 8) 1610 #define RT5665_MIC2_OVCD_EN (0x1 << 8) 1611 #define RT5665_MIC2_OVTH_MASK (0x3 << 6) 1612 #define RT5665_MIC2_OVTH_SFT 6 1613 #define RT5665_MIC2_OVTH_600UA (0x0 << 6) 1614 #define RT5665_MIC2_OVTH_1500UA (0x1 << 6) 1615 #define RT5665_MIC2_OVTH_2000UA (0x2 << 6) 1616 #define RT5665_PWR_MB_MASK (0x1 << 5) 1617 #define RT5665_PWR_MB_SFT 5 1618 #define RT5665_PWR_MB_PD (0x0 << 5) 1619 #define RT5665_PWR_MB_PU (0x1 << 5) 1620 1621 /* Micbias Control2 (0x94) */ 1622 #define RT5665_PWR_CLK25M_MASK (0x1 << 9) 1623 #define RT5665_PWR_CLK25M_SFT 9 1624 #define RT5665_PWR_CLK25M_PD (0x0 << 9) 1625 #define RT5665_PWR_CLK25M_PU (0x1 << 9) 1626 #define RT5665_PWR_CLK1M_MASK (0x1 << 8) 1627 #define RT5665_PWR_CLK1M_SFT 8 1628 #define RT5665_PWR_CLK1M_PD (0x0 << 8) 1629 #define RT5665_PWR_CLK1M_PU (0x1 << 8) 1630 1631 /* I2S Master Mode Clock Control 1 (0x00a0) */ 1632 #define RT5665_CLK_SRC_MCLK (0x0) 1633 #define RT5665_CLK_SRC_PLL1 (0x1) 1634 #define RT5665_CLK_SRC_RCCLK (0x2) 1635 #define RT5665_I2S_PD_1 (0x0) 1636 #define RT5665_I2S_PD_2 (0x1) 1637 #define RT5665_I2S_PD_3 (0x2) 1638 #define RT5665_I2S_PD_4 (0x3) 1639 #define RT5665_I2S_PD_6 (0x4) 1640 #define RT5665_I2S_PD_8 (0x5) 1641 #define RT5665_I2S_PD_12 (0x6) 1642 #define RT5665_I2S_PD_16 (0x7) 1643 #define RT5665_I2S2_SRC_MASK (0x3 << 12) 1644 #define RT5665_I2S2_SRC_SFT 12 1645 #define RT5665_I2S2_M_PD_MASK (0x7 << 8) 1646 #define RT5665_I2S2_M_PD_SFT 8 1647 #define RT5665_I2S3_SRC_MASK (0x3 << 4) 1648 #define RT5665_I2S3_SRC_SFT 4 1649 #define RT5665_I2S3_M_PD_MASK (0x7 << 0) 1650 #define RT5665_I2S3_M_PD_SFT 0 1651 1652 1653 /* EQ Control 1 (0x00b0) */ 1654 #define RT5665_EQ_SRC_DAC (0x0 << 15) 1655 #define RT5665_EQ_SRC_ADC (0x1 << 15) 1656 #define RT5665_EQ_UPD (0x1 << 14) 1657 #define RT5665_EQ_UPD_BIT 14 1658 #define RT5665_EQ_CD_MASK (0x1 << 13) 1659 #define RT5665_EQ_CD_SFT 13 1660 #define RT5665_EQ_CD_DIS (0x0 << 13) 1661 #define RT5665_EQ_CD_EN (0x1 << 13) 1662 #define RT5665_EQ_DITH_MASK (0x3 << 8) 1663 #define RT5665_EQ_DITH_SFT 8 1664 #define RT5665_EQ_DITH_NOR (0x0 << 8) 1665 #define RT5665_EQ_DITH_LSB (0x1 << 8) 1666 #define RT5665_EQ_DITH_LSB_1 (0x2 << 8) 1667 #define RT5665_EQ_DITH_LSB_2 (0x3 << 8) 1668 1669 /* IRQ Control 1 (0x00b7) */ 1670 #define RT5665_JD1_1_EN_MASK (0x1 << 15) 1671 #define RT5665_JD1_1_EN_SFT 15 1672 #define RT5665_JD1_1_DIS (0x0 << 15) 1673 #define RT5665_JD1_1_EN (0x1 << 15) 1674 #define RT5665_JD1_2_EN_MASK (0x1 << 12) 1675 #define RT5665_JD1_2_EN_SFT 12 1676 #define RT5665_JD1_2_DIS (0x0 << 12) 1677 #define RT5665_JD1_2_EN (0x1 << 12) 1678 1679 /* IRQ Control 2 (0x00b8) */ 1680 #define RT5665_IL_IRQ_MASK (0x1 << 6) 1681 #define RT5665_IL_IRQ_DIS (0x0 << 6) 1682 #define RT5665_IL_IRQ_EN (0x1 << 6) 1683 1684 /* IRQ Control 5 (0x00ba) */ 1685 #define RT5665_IRQ_JD_EN (0x1 << 3) 1686 #define RT5665_IRQ_JD_EN_SFT 3 1687 1688 /* GPIO Control 1 (0x00c0) */ 1689 #define RT5665_GP1_PIN_MASK (0x1 << 15) 1690 #define RT5665_GP1_PIN_SFT 15 1691 #define RT5665_GP1_PIN_GPIO1 (0x0 << 15) 1692 #define RT5665_GP1_PIN_IRQ (0x1 << 15) 1693 #define RT5665_GP2_PIN_MASK (0x3 << 13) 1694 #define RT5665_GP2_PIN_SFT 13 1695 #define RT5665_GP2_PIN_GPIO2 (0x0 << 13) 1696 #define RT5665_GP2_PIN_BCLK2 (0x1 << 13) 1697 #define RT5665_GP2_PIN_PDM_SCL (0x2 << 13) 1698 #define RT5665_GP3_PIN_MASK (0x3 << 11) 1699 #define RT5665_GP3_PIN_SFT 11 1700 #define RT5665_GP3_PIN_GPIO3 (0x0 << 11) 1701 #define RT5665_GP3_PIN_LRCK2 (0x1 << 11) 1702 #define RT5665_GP3_PIN_PDM_SDA (0x2 << 11) 1703 #define RT5665_GP4_PIN_MASK (0x3 << 9) 1704 #define RT5665_GP4_PIN_SFT 9 1705 #define RT5665_GP4_PIN_GPIO4 (0x0 << 9) 1706 #define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9) 1707 #define RT5665_GP4_PIN_DMIC1_SDA (0x2 << 9) 1708 #define RT5665_GP5_PIN_MASK (0x3 << 7) 1709 #define RT5665_GP5_PIN_SFT 7 1710 #define RT5665_GP5_PIN_GPIO5 (0x0 << 7) 1711 #define RT5665_GP5_PIN_ADCDAT2_1 (0x1 << 7) 1712 #define RT5665_GP5_PIN_DMIC2_SDA (0x2 << 7) 1713 #define RT5665_GP6_PIN_MASK (0x3 << 5) 1714 #define RT5665_GP6_PIN_SFT 5 1715 #define RT5665_GP6_PIN_GPIO6 (0x0 << 5) 1716 #define RT5665_GP6_PIN_BCLK3 (0x1 << 5) 1717 #define RT5665_GP6_PIN_PDM_SCL (0x2 << 5) 1718 #define RT5665_GP7_PIN_MASK (0x3 << 3) 1719 #define RT5665_GP7_PIN_SFT 3 1720 #define RT5665_GP7_PIN_GPIO7 (0x0 << 3) 1721 #define RT5665_GP7_PIN_LRCK3 (0x1 << 3) 1722 #define RT5665_GP7_PIN_PDM_SDA (0x2 << 3) 1723 #define RT5665_GP8_PIN_MASK (0x3 << 1) 1724 #define RT5665_GP8_PIN_SFT 1 1725 #define RT5665_GP8_PIN_GPIO8 (0x0 << 1) 1726 #define RT5665_GP8_PIN_DACDAT3 (0x1 << 1) 1727 #define RT5665_GP8_PIN_DMIC2_SCL (0x2 << 1) 1728 #define RT5665_GP8_PIN_DACDAT2_2 (0x3 << 1) 1729 1730 1731 /* GPIO Control 2 (0x00c1)*/ 1732 #define RT5665_GP9_PIN_MASK (0x3 << 14) 1733 #define RT5665_GP9_PIN_SFT 14 1734 #define RT5665_GP9_PIN_GPIO9 (0x0 << 14) 1735 #define RT5665_GP9_PIN_ADCDAT3 (0x1 << 14) 1736 #define RT5665_GP9_PIN_DMIC1_SCL (0x2 << 14) 1737 #define RT5665_GP9_PIN_ADCDAT2_2 (0x3 << 14) 1738 #define RT5665_GP10_PIN_MASK (0x3 << 12) 1739 #define RT5665_GP10_PIN_SFT 12 1740 #define RT5665_GP10_PIN_GPIO10 (0x0 << 12) 1741 #define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12) 1742 #define RT5665_GP10_PIN_LPD (0x2 << 12) 1743 #define RT5665_GP1_PF_MASK (0x1 << 11) 1744 #define RT5665_GP1_PF_IN (0x0 << 11) 1745 #define RT5665_GP1_PF_OUT (0x1 << 11) 1746 #define RT5665_GP1_OUT_MASK (0x1 << 10) 1747 #define RT5665_GP1_OUT_H (0x0 << 10) 1748 #define RT5665_GP1_OUT_L (0x1 << 10) 1749 #define RT5665_GP2_PF_MASK (0x1 << 9) 1750 #define RT5665_GP2_PF_IN (0x0 << 9) 1751 #define RT5665_GP2_PF_OUT (0x1 << 9) 1752 #define RT5665_GP2_OUT_MASK (0x1 << 8) 1753 #define RT5665_GP2_OUT_H (0x0 << 8) 1754 #define RT5665_GP2_OUT_L (0x1 << 8) 1755 #define RT5665_GP3_PF_MASK (0x1 << 7) 1756 #define RT5665_GP3_PF_IN (0x0 << 7) 1757 #define RT5665_GP3_PF_OUT (0x1 << 7) 1758 #define RT5665_GP3_OUT_MASK (0x1 << 6) 1759 #define RT5665_GP3_OUT_H (0x0 << 6) 1760 #define RT5665_GP3_OUT_L (0x1 << 6) 1761 #define RT5665_GP4_PF_MASK (0x1 << 5) 1762 #define RT5665_GP4_PF_IN (0x0 << 5) 1763 #define RT5665_GP4_PF_OUT (0x1 << 5) 1764 #define RT5665_GP4_OUT_MASK (0x1 << 4) 1765 #define RT5665_GP4_OUT_H (0x0 << 4) 1766 #define RT5665_GP4_OUT_L (0x1 << 4) 1767 #define RT5665_GP5_PF_MASK (0x1 << 3) 1768 #define RT5665_GP5_PF_IN (0x0 << 3) 1769 #define RT5665_GP5_PF_OUT (0x1 << 3) 1770 #define RT5665_GP5_OUT_MASK (0x1 << 2) 1771 #define RT5665_GP5_OUT_H (0x0 << 2) 1772 #define RT5665_GP5_OUT_L (0x1 << 2) 1773 #define RT5665_GP6_PF_MASK (0x1 << 1) 1774 #define RT5665_GP6_PF_IN (0x0 << 1) 1775 #define RT5665_GP6_PF_OUT (0x1 << 1) 1776 #define RT5665_GP6_OUT_MASK (0x1) 1777 #define RT5665_GP6_OUT_H (0x0) 1778 #define RT5665_GP6_OUT_L (0x1) 1779 1780 1781 /* GPIO Control 3 (0x00c2) */ 1782 #define RT5665_GP7_PF_MASK (0x1 << 15) 1783 #define RT5665_GP7_PF_IN (0x0 << 15) 1784 #define RT5665_GP7_PF_OUT (0x1 << 15) 1785 #define RT5665_GP7_OUT_MASK (0x1 << 14) 1786 #define RT5665_GP7_OUT_H (0x0 << 14) 1787 #define RT5665_GP7_OUT_L (0x1 << 14) 1788 #define RT5665_GP8_PF_MASK (0x1 << 13) 1789 #define RT5665_GP8_PF_IN (0x0 << 13) 1790 #define RT5665_GP8_PF_OUT (0x1 << 13) 1791 #define RT5665_GP8_OUT_MASK (0x1 << 12) 1792 #define RT5665_GP8_OUT_H (0x0 << 12) 1793 #define RT5665_GP8_OUT_L (0x1 << 12) 1794 #define RT5665_GP9_PF_MASK (0x1 << 11) 1795 #define RT5665_GP9_PF_IN (0x0 << 11) 1796 #define RT5665_GP9_PF_OUT (0x1 << 11) 1797 #define RT5665_GP9_OUT_MASK (0x1 << 10) 1798 #define RT5665_GP9_OUT_H (0x0 << 10) 1799 #define RT5665_GP9_OUT_L (0x1 << 10) 1800 #define RT5665_GP10_PF_MASK (0x1 << 9) 1801 #define RT5665_GP10_PF_IN (0x0 << 9) 1802 #define RT5665_GP10_PF_OUT (0x1 << 9) 1803 #define RT5665_GP10_OUT_MASK (0x1 << 8) 1804 #define RT5665_GP10_OUT_H (0x0 << 8) 1805 #define RT5665_GP10_OUT_L (0x1 << 8) 1806 #define RT5665_GP11_PF_MASK (0x1 << 7) 1807 #define RT5665_GP11_PF_IN (0x0 << 7) 1808 #define RT5665_GP11_PF_OUT (0x1 << 7) 1809 #define RT5665_GP11_OUT_MASK (0x1 << 6) 1810 #define RT5665_GP11_OUT_H (0x0 << 6) 1811 #define RT5665_GP11_OUT_L (0x1 << 6) 1812 1813 /* Soft volume and zero cross control 1 (0x00d9) */ 1814 #define RT5665_SV_MASK (0x1 << 15) 1815 #define RT5665_SV_SFT 15 1816 #define RT5665_SV_DIS (0x0 << 15) 1817 #define RT5665_SV_EN (0x1 << 15) 1818 #define RT5665_OUT_SV_MASK (0x1 << 13) 1819 #define RT5665_OUT_SV_SFT 13 1820 #define RT5665_OUT_SV_DIS (0x0 << 13) 1821 #define RT5665_OUT_SV_EN (0x1 << 13) 1822 #define RT5665_HP_SV_MASK (0x1 << 12) 1823 #define RT5665_HP_SV_SFT 12 1824 #define RT5665_HP_SV_DIS (0x0 << 12) 1825 #define RT5665_HP_SV_EN (0x1 << 12) 1826 #define RT5665_ZCD_DIG_MASK (0x1 << 11) 1827 #define RT5665_ZCD_DIG_SFT 11 1828 #define RT5665_ZCD_DIG_DIS (0x0 << 11) 1829 #define RT5665_ZCD_DIG_EN (0x1 << 11) 1830 #define RT5665_ZCD_MASK (0x1 << 10) 1831 #define RT5665_ZCD_SFT 10 1832 #define RT5665_ZCD_PD (0x0 << 10) 1833 #define RT5665_ZCD_PU (0x1 << 10) 1834 #define RT5665_SV_DLY_MASK (0xf) 1835 #define RT5665_SV_DLY_SFT 0 1836 1837 /* Soft volume and zero cross control 2 (0x00da) */ 1838 #define RT5665_ZCD_HP_MASK (0x1 << 15) 1839 #define RT5665_ZCD_HP_SFT 15 1840 #define RT5665_ZCD_HP_DIS (0x0 << 15) 1841 #define RT5665_ZCD_HP_EN (0x1 << 15) 1842 1843 /* 4 Button Inline Command Control 2 (0x00e0) */ 1844 #define RT5665_4BTN_IL_MASK (0x1 << 15) 1845 #define RT5665_4BTN_IL_EN (0x1 << 15) 1846 #define RT5665_4BTN_IL_DIS (0x0 << 15) 1847 #define RT5665_4BTN_IL_RST_MASK (0x1 << 14) 1848 #define RT5665_4BTN_IL_NOR (0x1 << 14) 1849 #define RT5665_4BTN_IL_RST (0x0 << 14) 1850 1851 /* Analog JD Control 1 (0x00f0) */ 1852 #define RT5665_JD1_MODE_MASK (0x3 << 0) 1853 #define RT5665_JD1_MODE_0 (0x0 << 0) 1854 #define RT5665_JD1_MODE_1 (0x1 << 0) 1855 #define RT5665_JD1_MODE_2 (0x2 << 0) 1856 1857 /* Jack Detect Control 3 (0x00f8) */ 1858 #define RT5665_JD_TRI_HPO_SEL_MASK (0x7) 1859 #define RT5665_JD_TRI_HPO_SEL_SFT (0) 1860 #define RT5665_JD_HPO_GPIO_JD1 (0x0) 1861 #define RT5665_JD_HPO_JD1_1 (0x1) 1862 #define RT5665_JD_HPO_JD1_2 (0x2) 1863 #define RT5665_JD_HPO_JD2 (0x3) 1864 #define RT5665_JD_HPO_GPIO_JD2 (0x4) 1865 #define RT5665_JD_HPO_JD3 (0x5) 1866 #define RT5665_JD_HPO_JD_D (0x6) 1867 1868 /* Digital Misc Control (0x00fa) */ 1869 #define RT5665_AM_MASK (0x1 << 7) 1870 #define RT5665_AM_EN (0x1 << 7) 1871 #define RT5665_AM_DIS (0x1 << 7) 1872 #define RT5665_DIG_GATE_CTRL 0x1 1873 #define RT5665_DIG_GATE_CTRL_SFT (0) 1874 1875 /* Chopper and Clock control for ADC (0x011c)*/ 1876 #define RT5665_M_RF_DIG_MASK (0x1 << 12) 1877 #define RT5665_M_RF_DIG_SFT 12 1878 #define RT5665_M_RI_DIG (0x1 << 11) 1879 1880 /* Chopper and Clock control for DAC (0x013a)*/ 1881 #define RT5665_CKXEN_DAC1_MASK (0x1 << 13) 1882 #define RT5665_CKXEN_DAC1_SFT 13 1883 #define RT5665_CKGEN_DAC1_MASK (0x1 << 12) 1884 #define RT5665_CKGEN_DAC1_SFT 12 1885 #define RT5665_CKXEN_DAC2_MASK (0x1 << 5) 1886 #define RT5665_CKXEN_DAC2_SFT 5 1887 #define RT5665_CKGEN_DAC2_MASK (0x1 << 4) 1888 #define RT5665_CKGEN_DAC2_SFT 4 1889 1890 /* Chopper and Clock control for ADC (0x013b)*/ 1891 #define RT5665_CKXEN_ADC1_MASK (0x1 << 13) 1892 #define RT5665_CKXEN_ADC1_SFT 13 1893 #define RT5665_CKGEN_ADC1_MASK (0x1 << 12) 1894 #define RT5665_CKGEN_ADC1_SFT 12 1895 #define RT5665_CKXEN_ADC2_MASK (0x1 << 5) 1896 #define RT5665_CKXEN_ADC2_SFT 5 1897 #define RT5665_CKGEN_ADC2_MASK (0x1 << 4) 1898 #define RT5665_CKGEN_ADC2_SFT 4 1899 1900 /* Volume test (0x013f)*/ 1901 #define RT5665_SEL_CLK_VOL_MASK (0x1 << 15) 1902 #define RT5665_SEL_CLK_VOL_EN (0x1 << 15) 1903 #define RT5665_SEL_CLK_VOL_DIS (0x0 << 15) 1904 1905 /* Test Mode Control 1 (0x0145) */ 1906 #define RT5665_AD2DA_LB_MASK (0x1 << 9) 1907 #define RT5665_AD2DA_LB_SFT 9 1908 1909 /* Stereo Noise Gate Control 1 (0x0160) */ 1910 #define RT5665_NG2_EN_MASK (0x1 << 15) 1911 #define RT5665_NG2_EN (0x1 << 15) 1912 #define RT5665_NG2_DIS (0x0 << 15) 1913 1914 /* Stereo1 DAC Silence Detection Control (0x0190) */ 1915 #define RT5665_DEB_STO_DAC_MASK (0x7 << 4) 1916 #define RT5665_DEB_80_MS (0x0 << 4) 1917 1918 /* SAR ADC Inline Command Control 1 (0x0210) */ 1919 #define RT5665_SAR_BUTT_DET_MASK (0x1 << 15) 1920 #define RT5665_SAR_BUTT_DET_EN (0x1 << 15) 1921 #define RT5665_SAR_BUTT_DET_DIS (0x0 << 15) 1922 #define RT5665_SAR_BUTDET_MODE_MASK (0x1 << 14) 1923 #define RT5665_SAR_BUTDET_POW_SAV (0x1 << 14) 1924 #define RT5665_SAR_BUTDET_POW_NORM (0x0 << 14) 1925 #define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13) 1926 #define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13) 1927 #define RT5665_SAR_BUTDET_RST (0x0 << 13) 1928 #define RT5665_SAR_POW_MASK (0x1 << 12) 1929 #define RT5665_SAR_POW_EN (0x1 << 12) 1930 #define RT5665_SAR_POW_DIS (0x0 << 12) 1931 #define RT5665_SAR_RST_MASK (0x1 << 11) 1932 #define RT5665_SAR_RST_NORMAL (0x1 << 11) 1933 #define RT5665_SAR_RST (0x0 << 11) 1934 #define RT5665_SAR_BYPASS_MASK (0x1 << 10) 1935 #define RT5665_SAR_BYPASS_EN (0x1 << 10) 1936 #define RT5665_SAR_BYPASS_DIS (0x0 << 10) 1937 #define RT5665_SAR_SEL_MB1_MASK (0x1 << 9) 1938 #define RT5665_SAR_SEL_MB1_SEL (0x1 << 9) 1939 #define RT5665_SAR_SEL_MB1_NOSEL (0x0 << 9) 1940 #define RT5665_SAR_SEL_MB2_MASK (0x1 << 8) 1941 #define RT5665_SAR_SEL_MB2_SEL (0x1 << 8) 1942 #define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8) 1943 #define RT5665_SAR_SEL_MODE_MASK (0x1 << 7) 1944 #define RT5665_SAR_SEL_MODE_CMP (0x1 << 7) 1945 #define RT5665_SAR_SEL_MODE_ADC (0x0 << 7) 1946 #define RT5665_SAR_SEL_MB1_MB2_MASK (0x1 << 5) 1947 #define RT5665_SAR_SEL_MB1_MB2_AUTO (0x1 << 5) 1948 #define RT5665_SAR_SEL_MB1_MB2_MANU (0x0 << 5) 1949 #define RT5665_SAR_SEL_SIGNAL_MASK (0x1 << 4) 1950 #define RT5665_SAR_SEL_SIGNAL_AUTO (0x1 << 4) 1951 #define RT5665_SAR_SEL_SIGNAL_MANU (0x0 << 4) 1952 1953 /* System Clock Source */ 1954 enum { 1955 RT5665_SCLK_S_MCLK, 1956 RT5665_SCLK_S_PLL1, 1957 RT5665_SCLK_S_RCCLK, 1958 }; 1959 1960 /* PLL1 Source */ 1961 enum { 1962 RT5665_PLL1_S_MCLK, 1963 RT5665_PLL1_S_BCLK1, 1964 RT5665_PLL1_S_BCLK2, 1965 RT5665_PLL1_S_BCLK3, 1966 RT5665_PLL1_S_BCLK4, 1967 }; 1968 1969 enum { 1970 RT5665_AIF1_1, 1971 RT5665_AIF1_2, 1972 RT5665_AIF2_1, 1973 RT5665_AIF2_2, 1974 RT5665_AIF3, 1975 RT5665_AIFS 1976 }; 1977 1978 enum { 1979 CODEC_5665, 1980 CODEC_5666, 1981 }; 1982 1983 /* filter mask */ 1984 enum { 1985 RT5665_DA_STEREO1_FILTER = 0x1, 1986 RT5665_DA_STEREO2_FILTER = (0x1 << 1), 1987 RT5665_DA_MONO_L_FILTER = (0x1 << 2), 1988 RT5665_DA_MONO_R_FILTER = (0x1 << 3), 1989 RT5665_AD_STEREO1_FILTER = (0x1 << 4), 1990 RT5665_AD_STEREO2_FILTER = (0x1 << 5), 1991 RT5665_AD_MONO_L_FILTER = (0x1 << 6), 1992 RT5665_AD_MONO_R_FILTER = (0x1 << 7), 1993 }; 1994 1995 enum { 1996 RT5665_CLK_SEL_SYS, 1997 RT5665_CLK_SEL_I2S1_ASRC, 1998 RT5665_CLK_SEL_I2S2_ASRC, 1999 RT5665_CLK_SEL_I2S3_ASRC, 2000 RT5665_CLK_SEL_SYS2, 2001 RT5665_CLK_SEL_SYS3, 2002 RT5665_CLK_SEL_SYS4, 2003 }; 2004 2005 int rt5665_sel_asrc_clk_src(struct snd_soc_component *component, 2006 unsigned int filter_mask, unsigned int clk_src); 2007 2008 #endif /* __RT5665_H__ */ 2009