1 /* 2 * rt5663.c -- RT5663 ALSA SoC audio codec driver 3 * 4 * Copyright 2016 Realtek Semiconductor Corp. 5 * Author: Jack Yu <jack.yu@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/platform_device.h> 18 #include <linux/spi/spi.h> 19 #include <linux/acpi.h> 20 #include <linux/workqueue.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rt5663.h" 31 #include "rl6231.h" 32 33 #define RT5663_DEVICE_ID_2 0x6451 34 #define RT5663_DEVICE_ID_1 0x6406 35 36 enum { 37 CODEC_VER_1, 38 CODEC_VER_0, 39 }; 40 41 struct rt5663_priv { 42 struct snd_soc_codec *codec; 43 struct regmap *regmap; 44 struct delayed_work jack_detect_work; 45 struct snd_soc_jack *hs_jack; 46 struct timer_list btn_check_timer; 47 48 int codec_ver; 49 int sysclk; 50 int sysclk_src; 51 int lrck; 52 53 int pll_src; 54 int pll_in; 55 int pll_out; 56 57 int jack_type; 58 }; 59 60 static const struct reg_default rt5663_v2_reg[] = { 61 { 0x0000, 0x0000 }, 62 { 0x0001, 0xc8c8 }, 63 { 0x0002, 0x8080 }, 64 { 0x0003, 0x8000 }, 65 { 0x0004, 0xc80a }, 66 { 0x0005, 0x0000 }, 67 { 0x0006, 0x0000 }, 68 { 0x0007, 0x0000 }, 69 { 0x000a, 0x0000 }, 70 { 0x000b, 0x0000 }, 71 { 0x000c, 0x0000 }, 72 { 0x000d, 0x0000 }, 73 { 0x000f, 0x0808 }, 74 { 0x0010, 0x4000 }, 75 { 0x0011, 0x0000 }, 76 { 0x0012, 0x1404 }, 77 { 0x0013, 0x1000 }, 78 { 0x0014, 0xa00a }, 79 { 0x0015, 0x0404 }, 80 { 0x0016, 0x0404 }, 81 { 0x0017, 0x0011 }, 82 { 0x0018, 0xafaf }, 83 { 0x0019, 0xafaf }, 84 { 0x001a, 0xafaf }, 85 { 0x001b, 0x0011 }, 86 { 0x001c, 0x2f2f }, 87 { 0x001d, 0x2f2f }, 88 { 0x001e, 0x2f2f }, 89 { 0x001f, 0x0000 }, 90 { 0x0020, 0x0000 }, 91 { 0x0021, 0x0000 }, 92 { 0x0022, 0x5757 }, 93 { 0x0023, 0x0039 }, 94 { 0x0024, 0x000b }, 95 { 0x0026, 0xc0c0 }, 96 { 0x0027, 0xc0c0 }, 97 { 0x0028, 0xc0c0 }, 98 { 0x0029, 0x8080 }, 99 { 0x002a, 0xaaaa }, 100 { 0x002b, 0xaaaa }, 101 { 0x002c, 0xaba8 }, 102 { 0x002d, 0x0000 }, 103 { 0x002e, 0x0000 }, 104 { 0x002f, 0x0000 }, 105 { 0x0030, 0x0000 }, 106 { 0x0031, 0x5000 }, 107 { 0x0032, 0x0000 }, 108 { 0x0033, 0x0000 }, 109 { 0x0034, 0x0000 }, 110 { 0x0035, 0x0000 }, 111 { 0x003a, 0x0000 }, 112 { 0x003b, 0x0000 }, 113 { 0x003c, 0x00ff }, 114 { 0x003d, 0x0000 }, 115 { 0x003e, 0x00ff }, 116 { 0x003f, 0x0000 }, 117 { 0x0040, 0x0000 }, 118 { 0x0041, 0x00ff }, 119 { 0x0042, 0x0000 }, 120 { 0x0043, 0x00ff }, 121 { 0x0044, 0x0c0c }, 122 { 0x0049, 0xc00b }, 123 { 0x004a, 0x0000 }, 124 { 0x004b, 0x031f }, 125 { 0x004d, 0x0000 }, 126 { 0x004e, 0x001f }, 127 { 0x004f, 0x0000 }, 128 { 0x0050, 0x001f }, 129 { 0x0052, 0xf000 }, 130 { 0x0061, 0x0000 }, 131 { 0x0062, 0x0000 }, 132 { 0x0063, 0x003e }, 133 { 0x0064, 0x0000 }, 134 { 0x0065, 0x0000 }, 135 { 0x0066, 0x003f }, 136 { 0x0067, 0x0000 }, 137 { 0x006b, 0x0000 }, 138 { 0x006d, 0xff00 }, 139 { 0x006e, 0x2808 }, 140 { 0x006f, 0x000a }, 141 { 0x0070, 0x8000 }, 142 { 0x0071, 0x8000 }, 143 { 0x0072, 0x8000 }, 144 { 0x0073, 0x7000 }, 145 { 0x0074, 0x7770 }, 146 { 0x0075, 0x0002 }, 147 { 0x0076, 0x0001 }, 148 { 0x0078, 0x00f0 }, 149 { 0x0079, 0x0000 }, 150 { 0x007a, 0x0000 }, 151 { 0x007b, 0x0000 }, 152 { 0x007c, 0x0000 }, 153 { 0x007d, 0x0123 }, 154 { 0x007e, 0x4500 }, 155 { 0x007f, 0x8003 }, 156 { 0x0080, 0x0000 }, 157 { 0x0081, 0x0000 }, 158 { 0x0082, 0x0000 }, 159 { 0x0083, 0x0000 }, 160 { 0x0084, 0x0000 }, 161 { 0x0085, 0x0000 }, 162 { 0x0086, 0x0008 }, 163 { 0x0087, 0x0000 }, 164 { 0x0088, 0x0000 }, 165 { 0x0089, 0x0000 }, 166 { 0x008a, 0x0000 }, 167 { 0x008b, 0x0000 }, 168 { 0x008c, 0x0003 }, 169 { 0x008e, 0x0060 }, 170 { 0x008f, 0x1000 }, 171 { 0x0091, 0x0c26 }, 172 { 0x0092, 0x0073 }, 173 { 0x0093, 0x0000 }, 174 { 0x0094, 0x0080 }, 175 { 0x0098, 0x0000 }, 176 { 0x0099, 0x0000 }, 177 { 0x009a, 0x0007 }, 178 { 0x009f, 0x0000 }, 179 { 0x00a0, 0x0000 }, 180 { 0x00a1, 0x0002 }, 181 { 0x00a2, 0x0001 }, 182 { 0x00a3, 0x0002 }, 183 { 0x00a4, 0x0001 }, 184 { 0x00ae, 0x2040 }, 185 { 0x00af, 0x0000 }, 186 { 0x00b6, 0x0000 }, 187 { 0x00b7, 0x0000 }, 188 { 0x00b8, 0x0000 }, 189 { 0x00b9, 0x0000 }, 190 { 0x00ba, 0x0002 }, 191 { 0x00bb, 0x0000 }, 192 { 0x00be, 0x0000 }, 193 { 0x00c0, 0x0000 }, 194 { 0x00c1, 0x0aaa }, 195 { 0x00c2, 0xaa80 }, 196 { 0x00c3, 0x0003 }, 197 { 0x00c4, 0x0000 }, 198 { 0x00d0, 0x0000 }, 199 { 0x00d1, 0x2244 }, 200 { 0x00d2, 0x0000 }, 201 { 0x00d3, 0x3300 }, 202 { 0x00d4, 0x2200 }, 203 { 0x00d9, 0x0809 }, 204 { 0x00da, 0x0000 }, 205 { 0x00db, 0x0008 }, 206 { 0x00dc, 0x00c0 }, 207 { 0x00dd, 0x6724 }, 208 { 0x00de, 0x3131 }, 209 { 0x00df, 0x0008 }, 210 { 0x00e0, 0x4000 }, 211 { 0x00e1, 0x3131 }, 212 { 0x00e2, 0x600c }, 213 { 0x00ea, 0xb320 }, 214 { 0x00eb, 0x0000 }, 215 { 0x00ec, 0xb300 }, 216 { 0x00ed, 0x0000 }, 217 { 0x00ee, 0xb320 }, 218 { 0x00ef, 0x0000 }, 219 { 0x00f0, 0x0201 }, 220 { 0x00f1, 0x0ddd }, 221 { 0x00f2, 0x0ddd }, 222 { 0x00f6, 0x0000 }, 223 { 0x00f7, 0x0000 }, 224 { 0x00f8, 0x0000 }, 225 { 0x00fa, 0x0000 }, 226 { 0x00fb, 0x0000 }, 227 { 0x00fc, 0x0000 }, 228 { 0x00fd, 0x0000 }, 229 { 0x00fe, 0x10ec }, 230 { 0x00ff, 0x6451 }, 231 { 0x0100, 0xaaaa }, 232 { 0x0101, 0x000a }, 233 { 0x010a, 0xaaaa }, 234 { 0x010b, 0xa0a0 }, 235 { 0x010c, 0xaeae }, 236 { 0x010d, 0xaaaa }, 237 { 0x010e, 0xaaaa }, 238 { 0x010f, 0xaaaa }, 239 { 0x0110, 0xe002 }, 240 { 0x0111, 0xa602 }, 241 { 0x0112, 0xaaaa }, 242 { 0x0113, 0x2000 }, 243 { 0x0117, 0x0f00 }, 244 { 0x0125, 0x0420 }, 245 { 0x0132, 0x0000 }, 246 { 0x0133, 0x0000 }, 247 { 0x0136, 0x5555 }, 248 { 0x0137, 0x5540 }, 249 { 0x0138, 0x3700 }, 250 { 0x0139, 0x79a1 }, 251 { 0x013a, 0x2020 }, 252 { 0x013b, 0x2020 }, 253 { 0x013c, 0x2005 }, 254 { 0x013f, 0x0000 }, 255 { 0x0145, 0x0002 }, 256 { 0x0146, 0x0000 }, 257 { 0x0147, 0x0000 }, 258 { 0x0148, 0x0000 }, 259 { 0x0160, 0x4ec0 }, 260 { 0x0161, 0x0080 }, 261 { 0x0162, 0x0200 }, 262 { 0x0163, 0x0800 }, 263 { 0x0164, 0x0000 }, 264 { 0x0165, 0x0000 }, 265 { 0x0166, 0x0000 }, 266 { 0x0167, 0x000f }, 267 { 0x0168, 0x000f }, 268 { 0x0170, 0x4e80 }, 269 { 0x0171, 0x0080 }, 270 { 0x0172, 0x0200 }, 271 { 0x0173, 0x0800 }, 272 { 0x0174, 0x00ff }, 273 { 0x0175, 0x0000 }, 274 { 0x0190, 0x4131 }, 275 { 0x0191, 0x4131 }, 276 { 0x0192, 0x4131 }, 277 { 0x0193, 0x4131 }, 278 { 0x0194, 0x0000 }, 279 { 0x0195, 0x0000 }, 280 { 0x0196, 0x0000 }, 281 { 0x0197, 0x0000 }, 282 { 0x0198, 0x0000 }, 283 { 0x0199, 0x0000 }, 284 { 0x01a0, 0x1e64 }, 285 { 0x01a1, 0x06a3 }, 286 { 0x01a2, 0x0000 }, 287 { 0x01a3, 0x0000 }, 288 { 0x01a4, 0x0000 }, 289 { 0x01a5, 0x0000 }, 290 { 0x01a6, 0x0000 }, 291 { 0x01a7, 0x0000 }, 292 { 0x01a8, 0x0000 }, 293 { 0x01a9, 0x0000 }, 294 { 0x01aa, 0x0000 }, 295 { 0x01ab, 0x0000 }, 296 { 0x01b5, 0x0000 }, 297 { 0x01b6, 0x01c3 }, 298 { 0x01b7, 0x02a0 }, 299 { 0x01b8, 0x03e9 }, 300 { 0x01b9, 0x1389 }, 301 { 0x01ba, 0xc351 }, 302 { 0x01bb, 0x0009 }, 303 { 0x01bc, 0x0018 }, 304 { 0x01bd, 0x002a }, 305 { 0x01be, 0x004c }, 306 { 0x01bf, 0x0097 }, 307 { 0x01c0, 0x433d }, 308 { 0x01c1, 0x0000 }, 309 { 0x01c2, 0x0000 }, 310 { 0x01c3, 0x0000 }, 311 { 0x01c4, 0x0000 }, 312 { 0x01c5, 0x0000 }, 313 { 0x01c6, 0x0000 }, 314 { 0x01c7, 0x0000 }, 315 { 0x01c8, 0x40af }, 316 { 0x01c9, 0x0702 }, 317 { 0x01ca, 0x0000 }, 318 { 0x01cb, 0x0000 }, 319 { 0x01cc, 0x5757 }, 320 { 0x01cd, 0x5757 }, 321 { 0x01ce, 0x5757 }, 322 { 0x01cf, 0x5757 }, 323 { 0x01d0, 0x5757 }, 324 { 0x01d1, 0x5757 }, 325 { 0x01d2, 0x5757 }, 326 { 0x01d3, 0x5757 }, 327 { 0x01d4, 0x5757 }, 328 { 0x01d5, 0x5757 }, 329 { 0x01d6, 0x003c }, 330 { 0x01da, 0x0000 }, 331 { 0x01db, 0x0000 }, 332 { 0x01dc, 0x0000 }, 333 { 0x01de, 0x7c00 }, 334 { 0x01df, 0x0320 }, 335 { 0x01e0, 0x06a1 }, 336 { 0x01e1, 0x0000 }, 337 { 0x01e2, 0x0000 }, 338 { 0x01e3, 0x0000 }, 339 { 0x01e4, 0x0000 }, 340 { 0x01e5, 0x0000 }, 341 { 0x01e6, 0x0001 }, 342 { 0x01e7, 0x0000 }, 343 { 0x01e8, 0x0000 }, 344 { 0x01ea, 0x0000 }, 345 { 0x01eb, 0x0000 }, 346 { 0x01ec, 0x0000 }, 347 { 0x01ed, 0x0000 }, 348 { 0x01ee, 0x0000 }, 349 { 0x01ef, 0x0000 }, 350 { 0x01f0, 0x0000 }, 351 { 0x01f1, 0x0000 }, 352 { 0x01f2, 0x0000 }, 353 { 0x01f3, 0x0000 }, 354 { 0x01f4, 0x0000 }, 355 { 0x0200, 0x0000 }, 356 { 0x0201, 0x0000 }, 357 { 0x0202, 0x0000 }, 358 { 0x0203, 0x0000 }, 359 { 0x0204, 0x0000 }, 360 { 0x0205, 0x0000 }, 361 { 0x0206, 0x0000 }, 362 { 0x0207, 0x0000 }, 363 { 0x0208, 0x0000 }, 364 { 0x0210, 0x60b1 }, 365 { 0x0211, 0xa000 }, 366 { 0x0212, 0x024c }, 367 { 0x0213, 0xf7ff }, 368 { 0x0214, 0x024c }, 369 { 0x0215, 0x0102 }, 370 { 0x0216, 0x00a3 }, 371 { 0x0217, 0x0048 }, 372 { 0x0218, 0x92c0 }, 373 { 0x0219, 0x0000 }, 374 { 0x021a, 0x00c8 }, 375 { 0x021b, 0x0020 }, 376 { 0x02fa, 0x0000 }, 377 { 0x02fb, 0x0000 }, 378 { 0x02fc, 0x0000 }, 379 { 0x02ff, 0x0110 }, 380 { 0x0300, 0x001f }, 381 { 0x0301, 0x032c }, 382 { 0x0302, 0x5f21 }, 383 { 0x0303, 0x4000 }, 384 { 0x0304, 0x4000 }, 385 { 0x0305, 0x06d5 }, 386 { 0x0306, 0x8000 }, 387 { 0x0307, 0x0700 }, 388 { 0x0310, 0x4560 }, 389 { 0x0311, 0xa4a8 }, 390 { 0x0312, 0x7418 }, 391 { 0x0313, 0x0000 }, 392 { 0x0314, 0x0006 }, 393 { 0x0315, 0xffff }, 394 { 0x0316, 0xc400 }, 395 { 0x0317, 0x0000 }, 396 { 0x0330, 0x00a6 }, 397 { 0x0331, 0x04c3 }, 398 { 0x0332, 0x27c8 }, 399 { 0x0333, 0xbf50 }, 400 { 0x0334, 0x0045 }, 401 { 0x0335, 0x0007 }, 402 { 0x0336, 0x7418 }, 403 { 0x0337, 0x0501 }, 404 { 0x0338, 0x0000 }, 405 { 0x0339, 0x0010 }, 406 { 0x033a, 0x1010 }, 407 { 0x03c0, 0x7e00 }, 408 { 0x03c1, 0x8000 }, 409 { 0x03c2, 0x8000 }, 410 { 0x03c3, 0x8000 }, 411 { 0x03c4, 0x8000 }, 412 { 0x03c5, 0x8000 }, 413 { 0x03c6, 0x8000 }, 414 { 0x03c7, 0x8000 }, 415 { 0x03c8, 0x8000 }, 416 { 0x03c9, 0x8000 }, 417 { 0x03ca, 0x8000 }, 418 { 0x03cb, 0x8000 }, 419 { 0x03cc, 0x8000 }, 420 { 0x03d0, 0x0000 }, 421 { 0x03d1, 0x0000 }, 422 { 0x03d2, 0x0000 }, 423 { 0x03d3, 0x0000 }, 424 { 0x03d4, 0x2000 }, 425 { 0x03d5, 0x2000 }, 426 { 0x03d6, 0x0000 }, 427 { 0x03d7, 0x0000 }, 428 { 0x03d8, 0x2000 }, 429 { 0x03d9, 0x2000 }, 430 { 0x03da, 0x2000 }, 431 { 0x03db, 0x2000 }, 432 { 0x03dc, 0x0000 }, 433 { 0x03dd, 0x0000 }, 434 { 0x03de, 0x0000 }, 435 { 0x03df, 0x2000 }, 436 { 0x03e0, 0x0000 }, 437 { 0x03e1, 0x0000 }, 438 { 0x03e2, 0x0000 }, 439 { 0x03e3, 0x0000 }, 440 { 0x03e4, 0x0000 }, 441 { 0x03e5, 0x0000 }, 442 { 0x03e6, 0x0000 }, 443 { 0x03e7, 0x0000 }, 444 { 0x03e8, 0x0000 }, 445 { 0x03e9, 0x0000 }, 446 { 0x03ea, 0x0000 }, 447 { 0x03eb, 0x0000 }, 448 { 0x03ec, 0x0000 }, 449 { 0x03ed, 0x0000 }, 450 { 0x03ee, 0x0000 }, 451 { 0x03ef, 0x0000 }, 452 { 0x03f0, 0x0800 }, 453 { 0x03f1, 0x0800 }, 454 { 0x03f2, 0x0800 }, 455 { 0x03f3, 0x0800 }, 456 { 0x03fe, 0x0000 }, 457 { 0x03ff, 0x0000 }, 458 { 0x07f0, 0x0000 }, 459 { 0x07fa, 0x0000 }, 460 }; 461 462 static const struct reg_default rt5663_reg[] = { 463 { 0x0000, 0x0000 }, 464 { 0x0002, 0x0008 }, 465 { 0x0005, 0x1000 }, 466 { 0x0006, 0x1000 }, 467 { 0x000a, 0x0000 }, 468 { 0x0010, 0x000f }, 469 { 0x0015, 0x42c1 }, 470 { 0x0016, 0x0000 }, 471 { 0x0018, 0x000b }, 472 { 0x0019, 0xafaf }, 473 { 0x001c, 0x2f2f }, 474 { 0x001f, 0x0000 }, 475 { 0x0022, 0x5757 }, 476 { 0x0023, 0x0039 }, 477 { 0x0026, 0xc0c0 }, 478 { 0x0029, 0x8080 }, 479 { 0x002a, 0xa0a0 }, 480 { 0x002c, 0x000c }, 481 { 0x002d, 0x0000 }, 482 { 0x0040, 0x0808 }, 483 { 0x0061, 0x0000 }, 484 { 0x0062, 0x0000 }, 485 { 0x0063, 0x003e }, 486 { 0x0064, 0x0000 }, 487 { 0x0065, 0x0000 }, 488 { 0x0066, 0x0000 }, 489 { 0x006b, 0x0000 }, 490 { 0x006e, 0x0000 }, 491 { 0x006f, 0x0000 }, 492 { 0x0070, 0x8020 }, 493 { 0x0073, 0x1000 }, 494 { 0x0074, 0xe400 }, 495 { 0x0075, 0x0002 }, 496 { 0x0076, 0x0001 }, 497 { 0x0077, 0x00f0 }, 498 { 0x0078, 0x0000 }, 499 { 0x0079, 0x0000 }, 500 { 0x007a, 0x0123 }, 501 { 0x007b, 0x8003 }, 502 { 0x0080, 0x0000 }, 503 { 0x0081, 0x0000 }, 504 { 0x0082, 0x0000 }, 505 { 0x0083, 0x0000 }, 506 { 0x0084, 0x0000 }, 507 { 0x0086, 0x0008 }, 508 { 0x0087, 0x0000 }, 509 { 0x008a, 0x0000 }, 510 { 0x008b, 0x0000 }, 511 { 0x008c, 0x0003 }, 512 { 0x008e, 0x0004 }, 513 { 0x008f, 0x1000 }, 514 { 0x0090, 0x0646 }, 515 { 0x0091, 0x0e3e }, 516 { 0x0092, 0x1071 }, 517 { 0x0093, 0x0000 }, 518 { 0x0094, 0x0080 }, 519 { 0x0097, 0x0000 }, 520 { 0x0098, 0x0000 }, 521 { 0x009a, 0x0000 }, 522 { 0x009f, 0x0000 }, 523 { 0x00ae, 0x2000 }, 524 { 0x00af, 0x0000 }, 525 { 0x00b6, 0x0000 }, 526 { 0x00b7, 0x0000 }, 527 { 0x00b8, 0x0000 }, 528 { 0x00ba, 0x0000 }, 529 { 0x00bb, 0x0000 }, 530 { 0x00be, 0x0000 }, 531 { 0x00bf, 0x0000 }, 532 { 0x00c0, 0x0000 }, 533 { 0x00c1, 0x0000 }, 534 { 0x00c5, 0x0000 }, 535 { 0x00cb, 0xa02f }, 536 { 0x00cc, 0x0000 }, 537 { 0x00cd, 0x0e02 }, 538 { 0x00d9, 0x08f9 }, 539 { 0x00db, 0x0008 }, 540 { 0x00dc, 0x00c0 }, 541 { 0x00dd, 0x6724 }, 542 { 0x00de, 0x3131 }, 543 { 0x00df, 0x0008 }, 544 { 0x00e0, 0x4000 }, 545 { 0x00e1, 0x3131 }, 546 { 0x00e2, 0x0043 }, 547 { 0x00e4, 0x400b }, 548 { 0x00e5, 0x8031 }, 549 { 0x00e6, 0x3080 }, 550 { 0x00e7, 0x4100 }, 551 { 0x00e8, 0x1400 }, 552 { 0x00e9, 0xe00a }, 553 { 0x00ea, 0x0404 }, 554 { 0x00eb, 0x0404 }, 555 { 0x00ec, 0xb320 }, 556 { 0x00ed, 0x0000 }, 557 { 0x00f4, 0x0000 }, 558 { 0x00f6, 0x0000 }, 559 { 0x00f8, 0x0000 }, 560 { 0x00fa, 0x8000 }, 561 { 0x00fd, 0x0001 }, 562 { 0x00fe, 0x10ec }, 563 { 0x00ff, 0x6406 }, 564 { 0x0100, 0xa0a0 }, 565 { 0x0108, 0x4444 }, 566 { 0x0109, 0x4444 }, 567 { 0x010a, 0xaaaa }, 568 { 0x010b, 0x00a0 }, 569 { 0x010c, 0x8aaa }, 570 { 0x010d, 0xaaaa }, 571 { 0x010e, 0x2aaa }, 572 { 0x010f, 0x002a }, 573 { 0x0110, 0xa0a4 }, 574 { 0x0111, 0x4602 }, 575 { 0x0112, 0x0101 }, 576 { 0x0113, 0x2000 }, 577 { 0x0114, 0x0000 }, 578 { 0x0116, 0x0000 }, 579 { 0x0117, 0x0f00 }, 580 { 0x0118, 0x0006 }, 581 { 0x0125, 0x2224 }, 582 { 0x0126, 0x5550 }, 583 { 0x0127, 0x0400 }, 584 { 0x0128, 0x7711 }, 585 { 0x0132, 0x0004 }, 586 { 0x0137, 0x5441 }, 587 { 0x0139, 0x79a1 }, 588 { 0x013a, 0x30c0 }, 589 { 0x013b, 0x2000 }, 590 { 0x013c, 0x2005 }, 591 { 0x013d, 0x30c0 }, 592 { 0x013e, 0x0000 }, 593 { 0x0140, 0x3700 }, 594 { 0x0141, 0x1f00 }, 595 { 0x0144, 0x0000 }, 596 { 0x0145, 0x0002 }, 597 { 0x0146, 0x0000 }, 598 { 0x0160, 0x0e80 }, 599 { 0x0161, 0x0020 }, 600 { 0x0162, 0x0080 }, 601 { 0x0163, 0x0800 }, 602 { 0x0164, 0x0000 }, 603 { 0x0165, 0x0000 }, 604 { 0x0166, 0x0000 }, 605 { 0x0167, 0x1417 }, 606 { 0x0168, 0x0017 }, 607 { 0x0169, 0x0017 }, 608 { 0x0180, 0x2000 }, 609 { 0x0181, 0x0000 }, 610 { 0x0182, 0x0000 }, 611 { 0x0183, 0x2000 }, 612 { 0x0184, 0x0000 }, 613 { 0x0185, 0x0000 }, 614 { 0x01b0, 0x4b30 }, 615 { 0x01b1, 0x0000 }, 616 { 0x01b2, 0xd870 }, 617 { 0x01b3, 0x0000 }, 618 { 0x01b4, 0x0030 }, 619 { 0x01b5, 0x5757 }, 620 { 0x01b6, 0x5757 }, 621 { 0x01b7, 0x5757 }, 622 { 0x01b8, 0x5757 }, 623 { 0x01c0, 0x433d }, 624 { 0x01c1, 0x0540 }, 625 { 0x01c2, 0x0000 }, 626 { 0x01c3, 0x0000 }, 627 { 0x01c4, 0x0000 }, 628 { 0x01c5, 0x0009 }, 629 { 0x01c6, 0x0018 }, 630 { 0x01c7, 0x002a }, 631 { 0x01c8, 0x004c }, 632 { 0x01c9, 0x0097 }, 633 { 0x01ca, 0x01c3 }, 634 { 0x01cb, 0x03e9 }, 635 { 0x01cc, 0x1389 }, 636 { 0x01cd, 0xc351 }, 637 { 0x01ce, 0x0000 }, 638 { 0x01cf, 0x0000 }, 639 { 0x01d0, 0x0000 }, 640 { 0x01d1, 0x0000 }, 641 { 0x01d2, 0x0000 }, 642 { 0x01d3, 0x003c }, 643 { 0x01d4, 0x5757 }, 644 { 0x01d5, 0x5757 }, 645 { 0x01d6, 0x5757 }, 646 { 0x01d7, 0x5757 }, 647 { 0x01d8, 0x5757 }, 648 { 0x01d9, 0x5757 }, 649 { 0x01da, 0x0000 }, 650 { 0x01db, 0x0000 }, 651 { 0x01dd, 0x0009 }, 652 { 0x01de, 0x7f00 }, 653 { 0x01df, 0x00c8 }, 654 { 0x01e0, 0x0691 }, 655 { 0x01e1, 0x0000 }, 656 { 0x01e2, 0x0000 }, 657 { 0x01e3, 0x0000 }, 658 { 0x01e4, 0x0000 }, 659 { 0x01e5, 0x0040 }, 660 { 0x01e6, 0x0000 }, 661 { 0x01e7, 0x0000 }, 662 { 0x01e8, 0x0000 }, 663 { 0x01ea, 0x0000 }, 664 { 0x01eb, 0x0000 }, 665 { 0x01ec, 0x0000 }, 666 { 0x01ed, 0x0000 }, 667 { 0x01ee, 0x0000 }, 668 { 0x01ef, 0x0000 }, 669 { 0x01f0, 0x0000 }, 670 { 0x01f1, 0x0000 }, 671 { 0x01f2, 0x0000 }, 672 { 0x0200, 0x0000 }, 673 { 0x0201, 0x2244 }, 674 { 0x0202, 0xaaaa }, 675 { 0x0250, 0x8010 }, 676 { 0x0251, 0x0000 }, 677 { 0x0252, 0x028a }, 678 { 0x02fa, 0x0000 }, 679 { 0x02fb, 0x0000 }, 680 { 0x02fc, 0x0000 }, 681 { 0x0300, 0x0000 }, 682 { 0x03d0, 0x0000 }, 683 { 0x03d1, 0x0000 }, 684 { 0x03d2, 0x0000 }, 685 { 0x03d3, 0x0000 }, 686 { 0x03d4, 0x2000 }, 687 { 0x03d5, 0x2000 }, 688 { 0x03d6, 0x0000 }, 689 { 0x03d7, 0x0000 }, 690 { 0x03d8, 0x2000 }, 691 { 0x03d9, 0x2000 }, 692 { 0x03da, 0x2000 }, 693 { 0x03db, 0x2000 }, 694 { 0x03dc, 0x0000 }, 695 { 0x03dd, 0x0000 }, 696 { 0x03de, 0x0000 }, 697 { 0x03df, 0x2000 }, 698 { 0x03e0, 0x0000 }, 699 { 0x03e1, 0x0000 }, 700 { 0x03e2, 0x0000 }, 701 { 0x03e3, 0x0000 }, 702 { 0x03e4, 0x0000 }, 703 { 0x03e5, 0x0000 }, 704 { 0x03e6, 0x0000 }, 705 { 0x03e7, 0x0000 }, 706 { 0x03e8, 0x0000 }, 707 { 0x03e9, 0x0000 }, 708 { 0x03ea, 0x0000 }, 709 { 0x03eb, 0x0000 }, 710 { 0x03ec, 0x0000 }, 711 { 0x03ed, 0x0000 }, 712 { 0x03ee, 0x0000 }, 713 { 0x03ef, 0x0000 }, 714 { 0x03f0, 0x0800 }, 715 { 0x03f1, 0x0800 }, 716 { 0x03f2, 0x0800 }, 717 { 0x03f3, 0x0800 }, 718 }; 719 720 static bool rt5663_volatile_register(struct device *dev, unsigned int reg) 721 { 722 switch (reg) { 723 case RT5663_RESET: 724 case RT5663_SIL_DET_CTL: 725 case RT5663_HP_IMP_GAIN_2: 726 case RT5663_AD_DA_MIXER: 727 case RT5663_FRAC_DIV_2: 728 case RT5663_MICBIAS_1: 729 case RT5663_ASRC_11_2: 730 case RT5663_ADC_EQ_1: 731 case RT5663_INT_ST_1: 732 case RT5663_INT_ST_2: 733 case RT5663_GPIO_STA1: 734 case RT5663_SIN_GEN_1: 735 case RT5663_IL_CMD_1: 736 case RT5663_IL_CMD_5: 737 case RT5663_IL_CMD_PWRSAV1: 738 case RT5663_EM_JACK_TYPE_1: 739 case RT5663_EM_JACK_TYPE_2: 740 case RT5663_EM_JACK_TYPE_3: 741 case RT5663_JD_CTRL2: 742 case RT5663_VENDOR_ID: 743 case RT5663_VENDOR_ID_1: 744 case RT5663_VENDOR_ID_2: 745 case RT5663_PLL_INT_REG: 746 case RT5663_SOFT_RAMP: 747 case RT5663_STO_DRE_1: 748 case RT5663_STO_DRE_5: 749 case RT5663_STO_DRE_6: 750 case RT5663_STO_DRE_7: 751 case RT5663_MIC_DECRO_1: 752 case RT5663_MIC_DECRO_4: 753 case RT5663_HP_IMP_SEN_1: 754 case RT5663_HP_IMP_SEN_3: 755 case RT5663_HP_IMP_SEN_4: 756 case RT5663_HP_IMP_SEN_5: 757 case RT5663_HP_CALIB_1_1: 758 case RT5663_HP_CALIB_9: 759 case RT5663_HP_CALIB_ST1: 760 case RT5663_HP_CALIB_ST2: 761 case RT5663_HP_CALIB_ST3: 762 case RT5663_HP_CALIB_ST4: 763 case RT5663_HP_CALIB_ST5: 764 case RT5663_HP_CALIB_ST6: 765 case RT5663_HP_CALIB_ST7: 766 case RT5663_HP_CALIB_ST8: 767 case RT5663_HP_CALIB_ST9: 768 case RT5663_ANA_JD: 769 return true; 770 default: 771 return false; 772 } 773 } 774 775 static bool rt5663_readable_register(struct device *dev, unsigned int reg) 776 { 777 switch (reg) { 778 case RT5663_RESET: 779 case RT5663_HP_OUT_EN: 780 case RT5663_HP_LCH_DRE: 781 case RT5663_HP_RCH_DRE: 782 case RT5663_CALIB_BST: 783 case RT5663_RECMIX: 784 case RT5663_SIL_DET_CTL: 785 case RT5663_PWR_SAV_SILDET: 786 case RT5663_SIDETONE_CTL: 787 case RT5663_STO1_DAC_DIG_VOL: 788 case RT5663_STO1_ADC_DIG_VOL: 789 case RT5663_STO1_BOOST: 790 case RT5663_HP_IMP_GAIN_1: 791 case RT5663_HP_IMP_GAIN_2: 792 case RT5663_STO1_ADC_MIXER: 793 case RT5663_AD_DA_MIXER: 794 case RT5663_STO_DAC_MIXER: 795 case RT5663_DIG_SIDE_MIXER: 796 case RT5663_BYPASS_STO_DAC: 797 case RT5663_CALIB_REC_MIX: 798 case RT5663_PWR_DIG_1: 799 case RT5663_PWR_DIG_2: 800 case RT5663_PWR_ANLG_1: 801 case RT5663_PWR_ANLG_2: 802 case RT5663_PWR_ANLG_3: 803 case RT5663_PWR_MIXER: 804 case RT5663_SIG_CLK_DET: 805 case RT5663_PRE_DIV_GATING_1: 806 case RT5663_PRE_DIV_GATING_2: 807 case RT5663_I2S1_SDP: 808 case RT5663_ADDA_CLK_1: 809 case RT5663_ADDA_RST: 810 case RT5663_FRAC_DIV_1: 811 case RT5663_FRAC_DIV_2: 812 case RT5663_TDM_1: 813 case RT5663_TDM_2: 814 case RT5663_TDM_3: 815 case RT5663_TDM_4: 816 case RT5663_TDM_5: 817 case RT5663_GLB_CLK: 818 case RT5663_PLL_1: 819 case RT5663_PLL_2: 820 case RT5663_ASRC_1: 821 case RT5663_ASRC_2: 822 case RT5663_ASRC_4: 823 case RT5663_DUMMY_REG: 824 case RT5663_ASRC_8: 825 case RT5663_ASRC_9: 826 case RT5663_ASRC_11: 827 case RT5663_DEPOP_1: 828 case RT5663_DEPOP_2: 829 case RT5663_DEPOP_3: 830 case RT5663_HP_CHARGE_PUMP_1: 831 case RT5663_HP_CHARGE_PUMP_2: 832 case RT5663_MICBIAS_1: 833 case RT5663_RC_CLK: 834 case RT5663_ASRC_11_2: 835 case RT5663_DUMMY_REG_2: 836 case RT5663_REC_PATH_GAIN: 837 case RT5663_AUTO_1MRC_CLK: 838 case RT5663_ADC_EQ_1: 839 case RT5663_ADC_EQ_2: 840 case RT5663_IRQ_1: 841 case RT5663_IRQ_2: 842 case RT5663_IRQ_3: 843 case RT5663_IRQ_4: 844 case RT5663_IRQ_5: 845 case RT5663_INT_ST_1: 846 case RT5663_INT_ST_2: 847 case RT5663_GPIO_1: 848 case RT5663_GPIO_2: 849 case RT5663_GPIO_STA1: 850 case RT5663_SIN_GEN_1: 851 case RT5663_SIN_GEN_2: 852 case RT5663_SIN_GEN_3: 853 case RT5663_SOF_VOL_ZC1: 854 case RT5663_IL_CMD_1: 855 case RT5663_IL_CMD_2: 856 case RT5663_IL_CMD_3: 857 case RT5663_IL_CMD_4: 858 case RT5663_IL_CMD_5: 859 case RT5663_IL_CMD_6: 860 case RT5663_IL_CMD_7: 861 case RT5663_IL_CMD_8: 862 case RT5663_IL_CMD_PWRSAV1: 863 case RT5663_IL_CMD_PWRSAV2: 864 case RT5663_EM_JACK_TYPE_1: 865 case RT5663_EM_JACK_TYPE_2: 866 case RT5663_EM_JACK_TYPE_3: 867 case RT5663_EM_JACK_TYPE_4: 868 case RT5663_EM_JACK_TYPE_5: 869 case RT5663_EM_JACK_TYPE_6: 870 case RT5663_STO1_HPF_ADJ1: 871 case RT5663_STO1_HPF_ADJ2: 872 case RT5663_FAST_OFF_MICBIAS: 873 case RT5663_JD_CTRL1: 874 case RT5663_JD_CTRL2: 875 case RT5663_DIG_MISC: 876 case RT5663_VENDOR_ID: 877 case RT5663_VENDOR_ID_1: 878 case RT5663_VENDOR_ID_2: 879 case RT5663_DIG_VOL_ZCD: 880 case RT5663_ANA_BIAS_CUR_1: 881 case RT5663_ANA_BIAS_CUR_2: 882 case RT5663_ANA_BIAS_CUR_3: 883 case RT5663_ANA_BIAS_CUR_4: 884 case RT5663_ANA_BIAS_CUR_5: 885 case RT5663_ANA_BIAS_CUR_6: 886 case RT5663_BIAS_CUR_5: 887 case RT5663_BIAS_CUR_6: 888 case RT5663_BIAS_CUR_7: 889 case RT5663_BIAS_CUR_8: 890 case RT5663_DACREF_LDO: 891 case RT5663_DUMMY_REG_3: 892 case RT5663_BIAS_CUR_9: 893 case RT5663_DUMMY_REG_4: 894 case RT5663_VREFADJ_OP: 895 case RT5663_VREF_RECMIX: 896 case RT5663_CHARGE_PUMP_1: 897 case RT5663_CHARGE_PUMP_1_2: 898 case RT5663_CHARGE_PUMP_1_3: 899 case RT5663_CHARGE_PUMP_2: 900 case RT5663_DIG_IN_PIN1: 901 case RT5663_PAD_DRV_CTL: 902 case RT5663_PLL_INT_REG: 903 case RT5663_CHOP_DAC_L: 904 case RT5663_CHOP_ADC: 905 case RT5663_CALIB_ADC: 906 case RT5663_CHOP_DAC_R: 907 case RT5663_DUMMY_CTL_DACLR: 908 case RT5663_DUMMY_REG_5: 909 case RT5663_SOFT_RAMP: 910 case RT5663_TEST_MODE_1: 911 case RT5663_TEST_MODE_2: 912 case RT5663_TEST_MODE_3: 913 case RT5663_STO_DRE_1: 914 case RT5663_STO_DRE_2: 915 case RT5663_STO_DRE_3: 916 case RT5663_STO_DRE_4: 917 case RT5663_STO_DRE_5: 918 case RT5663_STO_DRE_6: 919 case RT5663_STO_DRE_7: 920 case RT5663_STO_DRE_8: 921 case RT5663_STO_DRE_9: 922 case RT5663_STO_DRE_10: 923 case RT5663_MIC_DECRO_1: 924 case RT5663_MIC_DECRO_2: 925 case RT5663_MIC_DECRO_3: 926 case RT5663_MIC_DECRO_4: 927 case RT5663_MIC_DECRO_5: 928 case RT5663_MIC_DECRO_6: 929 case RT5663_HP_DECRO_1: 930 case RT5663_HP_DECRO_2: 931 case RT5663_HP_DECRO_3: 932 case RT5663_HP_DECRO_4: 933 case RT5663_HP_DECOUP: 934 case RT5663_HP_IMP_SEN_MAP8: 935 case RT5663_HP_IMP_SEN_MAP9: 936 case RT5663_HP_IMP_SEN_MAP10: 937 case RT5663_HP_IMP_SEN_MAP11: 938 case RT5663_HP_IMP_SEN_1: 939 case RT5663_HP_IMP_SEN_2: 940 case RT5663_HP_IMP_SEN_3: 941 case RT5663_HP_IMP_SEN_4: 942 case RT5663_HP_IMP_SEN_5: 943 case RT5663_HP_IMP_SEN_6: 944 case RT5663_HP_IMP_SEN_7: 945 case RT5663_HP_IMP_SEN_8: 946 case RT5663_HP_IMP_SEN_9: 947 case RT5663_HP_IMP_SEN_10: 948 case RT5663_HP_IMP_SEN_11: 949 case RT5663_HP_IMP_SEN_12: 950 case RT5663_HP_IMP_SEN_13: 951 case RT5663_HP_IMP_SEN_14: 952 case RT5663_HP_IMP_SEN_15: 953 case RT5663_HP_IMP_SEN_16: 954 case RT5663_HP_IMP_SEN_17: 955 case RT5663_HP_IMP_SEN_18: 956 case RT5663_HP_IMP_SEN_19: 957 case RT5663_HP_IMPSEN_DIG5: 958 case RT5663_HP_IMPSEN_MAP1: 959 case RT5663_HP_IMPSEN_MAP2: 960 case RT5663_HP_IMPSEN_MAP3: 961 case RT5663_HP_IMPSEN_MAP4: 962 case RT5663_HP_IMPSEN_MAP5: 963 case RT5663_HP_IMPSEN_MAP7: 964 case RT5663_HP_LOGIC_1: 965 case RT5663_HP_LOGIC_2: 966 case RT5663_HP_CALIB_1: 967 case RT5663_HP_CALIB_1_1: 968 case RT5663_HP_CALIB_2: 969 case RT5663_HP_CALIB_3: 970 case RT5663_HP_CALIB_4: 971 case RT5663_HP_CALIB_5: 972 case RT5663_HP_CALIB_5_1: 973 case RT5663_HP_CALIB_6: 974 case RT5663_HP_CALIB_7: 975 case RT5663_HP_CALIB_9: 976 case RT5663_HP_CALIB_10: 977 case RT5663_HP_CALIB_11: 978 case RT5663_HP_CALIB_ST1: 979 case RT5663_HP_CALIB_ST2: 980 case RT5663_HP_CALIB_ST3: 981 case RT5663_HP_CALIB_ST4: 982 case RT5663_HP_CALIB_ST5: 983 case RT5663_HP_CALIB_ST6: 984 case RT5663_HP_CALIB_ST7: 985 case RT5663_HP_CALIB_ST8: 986 case RT5663_HP_CALIB_ST9: 987 case RT5663_HP_AMP_DET: 988 case RT5663_DUMMY_REG_6: 989 case RT5663_HP_BIAS: 990 case RT5663_CBJ_1: 991 case RT5663_CBJ_2: 992 case RT5663_CBJ_3: 993 case RT5663_DUMMY_1: 994 case RT5663_DUMMY_2: 995 case RT5663_DUMMY_3: 996 case RT5663_ANA_JD: 997 case RT5663_ADC_LCH_LPF1_A1: 998 case RT5663_ADC_RCH_LPF1_A1: 999 case RT5663_ADC_LCH_LPF1_H0: 1000 case RT5663_ADC_RCH_LPF1_H0: 1001 case RT5663_ADC_LCH_BPF1_A1: 1002 case RT5663_ADC_RCH_BPF1_A1: 1003 case RT5663_ADC_LCH_BPF1_A2: 1004 case RT5663_ADC_RCH_BPF1_A2: 1005 case RT5663_ADC_LCH_BPF1_H0: 1006 case RT5663_ADC_RCH_BPF1_H0: 1007 case RT5663_ADC_LCH_BPF2_A1: 1008 case RT5663_ADC_RCH_BPF2_A1: 1009 case RT5663_ADC_LCH_BPF2_A2: 1010 case RT5663_ADC_RCH_BPF2_A2: 1011 case RT5663_ADC_LCH_BPF2_H0: 1012 case RT5663_ADC_RCH_BPF2_H0: 1013 case RT5663_ADC_LCH_BPF3_A1: 1014 case RT5663_ADC_RCH_BPF3_A1: 1015 case RT5663_ADC_LCH_BPF3_A2: 1016 case RT5663_ADC_RCH_BPF3_A2: 1017 case RT5663_ADC_LCH_BPF3_H0: 1018 case RT5663_ADC_RCH_BPF3_H0: 1019 case RT5663_ADC_LCH_BPF4_A1: 1020 case RT5663_ADC_RCH_BPF4_A1: 1021 case RT5663_ADC_LCH_BPF4_A2: 1022 case RT5663_ADC_RCH_BPF4_A2: 1023 case RT5663_ADC_LCH_BPF4_H0: 1024 case RT5663_ADC_RCH_BPF4_H0: 1025 case RT5663_ADC_LCH_HPF1_A1: 1026 case RT5663_ADC_RCH_HPF1_A1: 1027 case RT5663_ADC_LCH_HPF1_H0: 1028 case RT5663_ADC_RCH_HPF1_H0: 1029 case RT5663_ADC_EQ_PRE_VOL_L: 1030 case RT5663_ADC_EQ_PRE_VOL_R: 1031 case RT5663_ADC_EQ_POST_VOL_L: 1032 case RT5663_ADC_EQ_POST_VOL_R: 1033 return true; 1034 default: 1035 return false; 1036 } 1037 } 1038 1039 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg) 1040 { 1041 switch (reg) { 1042 case RT5663_RESET: 1043 case RT5663_CBJ_TYPE_2: 1044 case RT5663_PDM_OUT_CTL: 1045 case RT5663_PDM_I2C_DATA_CTL1: 1046 case RT5663_PDM_I2C_DATA_CTL4: 1047 case RT5663_ALC_BK_GAIN: 1048 case RT5663_PLL_2: 1049 case RT5663_MICBIAS_1: 1050 case RT5663_ADC_EQ_1: 1051 case RT5663_INT_ST_1: 1052 case RT5663_GPIO_STA2: 1053 case RT5663_IL_CMD_1: 1054 case RT5663_IL_CMD_5: 1055 case RT5663_A_JD_CTRL: 1056 case RT5663_JD_CTRL2: 1057 case RT5663_VENDOR_ID: 1058 case RT5663_VENDOR_ID_1: 1059 case RT5663_VENDOR_ID_2: 1060 case RT5663_STO_DRE_1: 1061 case RT5663_STO_DRE_5: 1062 case RT5663_STO_DRE_6: 1063 case RT5663_STO_DRE_7: 1064 case RT5663_MONO_DYNA_6: 1065 case RT5663_STO1_SIL_DET: 1066 case RT5663_MONOL_SIL_DET: 1067 case RT5663_MONOR_SIL_DET: 1068 case RT5663_STO2_DAC_SIL: 1069 case RT5663_MONO_AMP_CAL_ST1: 1070 case RT5663_MONO_AMP_CAL_ST2: 1071 case RT5663_MONO_AMP_CAL_ST3: 1072 case RT5663_MONO_AMP_CAL_ST4: 1073 case RT5663_HP_IMP_SEN_2: 1074 case RT5663_HP_IMP_SEN_3: 1075 case RT5663_HP_IMP_SEN_4: 1076 case RT5663_HP_IMP_SEN_10: 1077 case RT5663_HP_CALIB_1: 1078 case RT5663_HP_CALIB_10: 1079 case RT5663_HP_CALIB_ST1: 1080 case RT5663_HP_CALIB_ST4: 1081 case RT5663_HP_CALIB_ST5: 1082 case RT5663_HP_CALIB_ST6: 1083 case RT5663_HP_CALIB_ST7: 1084 case RT5663_HP_CALIB_ST8: 1085 case RT5663_HP_CALIB_ST9: 1086 case RT5663_HP_CALIB_ST10: 1087 case RT5663_HP_CALIB_ST11: 1088 return true; 1089 default: 1090 return false; 1091 } 1092 } 1093 1094 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg) 1095 { 1096 switch (reg) { 1097 case RT5663_LOUT_CTRL: 1098 case RT5663_HP_AMP_2: 1099 case RT5663_MONO_OUT: 1100 case RT5663_MONO_GAIN: 1101 case RT5663_AEC_BST: 1102 case RT5663_IN1_IN2: 1103 case RT5663_IN3_IN4: 1104 case RT5663_INL1_INR1: 1105 case RT5663_CBJ_TYPE_2: 1106 case RT5663_CBJ_TYPE_3: 1107 case RT5663_CBJ_TYPE_4: 1108 case RT5663_CBJ_TYPE_5: 1109 case RT5663_CBJ_TYPE_8: 1110 case RT5663_DAC3_DIG_VOL: 1111 case RT5663_DAC3_CTRL: 1112 case RT5663_MONO_ADC_DIG_VOL: 1113 case RT5663_STO2_ADC_DIG_VOL: 1114 case RT5663_MONO_ADC_BST_GAIN: 1115 case RT5663_STO2_ADC_BST_GAIN: 1116 case RT5663_SIDETONE_CTRL: 1117 case RT5663_MONO1_ADC_MIXER: 1118 case RT5663_STO2_ADC_MIXER: 1119 case RT5663_MONO_DAC_MIXER: 1120 case RT5663_DAC2_SRC_CTRL: 1121 case RT5663_IF_3_4_DATA_CTL: 1122 case RT5663_IF_5_DATA_CTL: 1123 case RT5663_PDM_OUT_CTL: 1124 case RT5663_PDM_I2C_DATA_CTL1: 1125 case RT5663_PDM_I2C_DATA_CTL2: 1126 case RT5663_PDM_I2C_DATA_CTL3: 1127 case RT5663_PDM_I2C_DATA_CTL4: 1128 case RT5663_RECMIX1_NEW: 1129 case RT5663_RECMIX1L_0: 1130 case RT5663_RECMIX1L: 1131 case RT5663_RECMIX1R_0: 1132 case RT5663_RECMIX1R: 1133 case RT5663_RECMIX2_NEW: 1134 case RT5663_RECMIX2_L_2: 1135 case RT5663_RECMIX2_R: 1136 case RT5663_RECMIX2_R_2: 1137 case RT5663_CALIB_REC_LR: 1138 case RT5663_ALC_BK_GAIN: 1139 case RT5663_MONOMIX_GAIN: 1140 case RT5663_MONOMIX_IN_GAIN: 1141 case RT5663_OUT_MIXL_GAIN: 1142 case RT5663_OUT_LMIX_IN_GAIN: 1143 case RT5663_OUT_RMIX_IN_GAIN: 1144 case RT5663_OUT_RMIX_IN_GAIN1: 1145 case RT5663_LOUT_MIXER_CTRL: 1146 case RT5663_PWR_VOL: 1147 case RT5663_ADCDAC_RST: 1148 case RT5663_I2S34_SDP: 1149 case RT5663_I2S5_SDP: 1150 case RT5663_TDM_6: 1151 case RT5663_TDM_7: 1152 case RT5663_TDM_8: 1153 case RT5663_TDM_9: 1154 case RT5663_ASRC_3: 1155 case RT5663_ASRC_6: 1156 case RT5663_ASRC_7: 1157 case RT5663_PLL_TRK_13: 1158 case RT5663_I2S_M_CLK_CTL: 1159 case RT5663_FDIV_I2S34_M_CLK: 1160 case RT5663_FDIV_I2S34_M_CLK2: 1161 case RT5663_FDIV_I2S5_M_CLK: 1162 case RT5663_FDIV_I2S5_M_CLK2: 1163 case RT5663_V2_IRQ_4: 1164 case RT5663_GPIO_3: 1165 case RT5663_GPIO_4: 1166 case RT5663_GPIO_STA2: 1167 case RT5663_HP_AMP_DET1: 1168 case RT5663_HP_AMP_DET2: 1169 case RT5663_HP_AMP_DET3: 1170 case RT5663_MID_BD_HP_AMP: 1171 case RT5663_LOW_BD_HP_AMP: 1172 case RT5663_SOF_VOL_ZC2: 1173 case RT5663_ADC_STO2_ADJ1: 1174 case RT5663_ADC_STO2_ADJ2: 1175 case RT5663_A_JD_CTRL: 1176 case RT5663_JD1_TRES_CTRL: 1177 case RT5663_JD2_TRES_CTRL: 1178 case RT5663_V2_JD_CTRL2: 1179 case RT5663_DUM_REG_2: 1180 case RT5663_DUM_REG_3: 1181 case RT5663_VENDOR_ID: 1182 case RT5663_VENDOR_ID_1: 1183 case RT5663_VENDOR_ID_2: 1184 case RT5663_DACADC_DIG_VOL2: 1185 case RT5663_DIG_IN_PIN2: 1186 case RT5663_PAD_DRV_CTL1: 1187 case RT5663_SOF_RAM_DEPOP: 1188 case RT5663_VOL_TEST: 1189 case RT5663_TEST_MODE_4: 1190 case RT5663_TEST_MODE_5: 1191 case RT5663_STO_DRE_9: 1192 case RT5663_MONO_DYNA_1: 1193 case RT5663_MONO_DYNA_2: 1194 case RT5663_MONO_DYNA_3: 1195 case RT5663_MONO_DYNA_4: 1196 case RT5663_MONO_DYNA_5: 1197 case RT5663_MONO_DYNA_6: 1198 case RT5663_STO1_SIL_DET: 1199 case RT5663_MONOL_SIL_DET: 1200 case RT5663_MONOR_SIL_DET: 1201 case RT5663_STO2_DAC_SIL: 1202 case RT5663_PWR_SAV_CTL1: 1203 case RT5663_PWR_SAV_CTL2: 1204 case RT5663_PWR_SAV_CTL3: 1205 case RT5663_PWR_SAV_CTL4: 1206 case RT5663_PWR_SAV_CTL5: 1207 case RT5663_PWR_SAV_CTL6: 1208 case RT5663_MONO_AMP_CAL1: 1209 case RT5663_MONO_AMP_CAL2: 1210 case RT5663_MONO_AMP_CAL3: 1211 case RT5663_MONO_AMP_CAL4: 1212 case RT5663_MONO_AMP_CAL5: 1213 case RT5663_MONO_AMP_CAL6: 1214 case RT5663_MONO_AMP_CAL7: 1215 case RT5663_MONO_AMP_CAL_ST1: 1216 case RT5663_MONO_AMP_CAL_ST2: 1217 case RT5663_MONO_AMP_CAL_ST3: 1218 case RT5663_MONO_AMP_CAL_ST4: 1219 case RT5663_MONO_AMP_CAL_ST5: 1220 case RT5663_V2_HP_IMP_SEN_13: 1221 case RT5663_V2_HP_IMP_SEN_14: 1222 case RT5663_V2_HP_IMP_SEN_6: 1223 case RT5663_V2_HP_IMP_SEN_7: 1224 case RT5663_V2_HP_IMP_SEN_8: 1225 case RT5663_V2_HP_IMP_SEN_9: 1226 case RT5663_V2_HP_IMP_SEN_10: 1227 case RT5663_HP_LOGIC_3: 1228 case RT5663_HP_CALIB_ST10: 1229 case RT5663_HP_CALIB_ST11: 1230 case RT5663_PRO_REG_TBL_4: 1231 case RT5663_PRO_REG_TBL_5: 1232 case RT5663_PRO_REG_TBL_6: 1233 case RT5663_PRO_REG_TBL_7: 1234 case RT5663_PRO_REG_TBL_8: 1235 case RT5663_PRO_REG_TBL_9: 1236 case RT5663_SAR_ADC_INL_1: 1237 case RT5663_SAR_ADC_INL_2: 1238 case RT5663_SAR_ADC_INL_3: 1239 case RT5663_SAR_ADC_INL_4: 1240 case RT5663_SAR_ADC_INL_5: 1241 case RT5663_SAR_ADC_INL_6: 1242 case RT5663_SAR_ADC_INL_7: 1243 case RT5663_SAR_ADC_INL_8: 1244 case RT5663_SAR_ADC_INL_9: 1245 case RT5663_SAR_ADC_INL_10: 1246 case RT5663_SAR_ADC_INL_11: 1247 case RT5663_SAR_ADC_INL_12: 1248 case RT5663_DRC_CTRL_1: 1249 case RT5663_DRC1_CTRL_2: 1250 case RT5663_DRC1_CTRL_3: 1251 case RT5663_DRC1_CTRL_4: 1252 case RT5663_DRC1_CTRL_5: 1253 case RT5663_DRC1_CTRL_6: 1254 case RT5663_DRC1_HD_CTRL_1: 1255 case RT5663_DRC1_HD_CTRL_2: 1256 case RT5663_DRC1_PRI_REG_1: 1257 case RT5663_DRC1_PRI_REG_2: 1258 case RT5663_DRC1_PRI_REG_3: 1259 case RT5663_DRC1_PRI_REG_4: 1260 case RT5663_DRC1_PRI_REG_5: 1261 case RT5663_DRC1_PRI_REG_6: 1262 case RT5663_DRC1_PRI_REG_7: 1263 case RT5663_DRC1_PRI_REG_8: 1264 case RT5663_ALC_PGA_CTL_1: 1265 case RT5663_ALC_PGA_CTL_2: 1266 case RT5663_ALC_PGA_CTL_3: 1267 case RT5663_ALC_PGA_CTL_4: 1268 case RT5663_ALC_PGA_CTL_5: 1269 case RT5663_ALC_PGA_CTL_6: 1270 case RT5663_ALC_PGA_CTL_7: 1271 case RT5663_ALC_PGA_CTL_8: 1272 case RT5663_ALC_PGA_REG_1: 1273 case RT5663_ALC_PGA_REG_2: 1274 case RT5663_ALC_PGA_REG_3: 1275 case RT5663_ADC_EQ_RECOV_1: 1276 case RT5663_ADC_EQ_RECOV_2: 1277 case RT5663_ADC_EQ_RECOV_3: 1278 case RT5663_ADC_EQ_RECOV_4: 1279 case RT5663_ADC_EQ_RECOV_5: 1280 case RT5663_ADC_EQ_RECOV_6: 1281 case RT5663_ADC_EQ_RECOV_7: 1282 case RT5663_ADC_EQ_RECOV_8: 1283 case RT5663_ADC_EQ_RECOV_9: 1284 case RT5663_ADC_EQ_RECOV_10: 1285 case RT5663_ADC_EQ_RECOV_11: 1286 case RT5663_ADC_EQ_RECOV_12: 1287 case RT5663_ADC_EQ_RECOV_13: 1288 case RT5663_VID_HIDDEN: 1289 case RT5663_VID_CUSTOMER: 1290 case RT5663_SCAN_MODE: 1291 case RT5663_I2C_BYPA: 1292 return true; 1293 case RT5663_TDM_1: 1294 case RT5663_DEPOP_3: 1295 case RT5663_ASRC_11_2: 1296 case RT5663_INT_ST_2: 1297 case RT5663_GPIO_STA1: 1298 case RT5663_SIN_GEN_1: 1299 case RT5663_SIN_GEN_2: 1300 case RT5663_SIN_GEN_3: 1301 case RT5663_IL_CMD_PWRSAV1: 1302 case RT5663_IL_CMD_PWRSAV2: 1303 case RT5663_EM_JACK_TYPE_1: 1304 case RT5663_EM_JACK_TYPE_2: 1305 case RT5663_EM_JACK_TYPE_3: 1306 case RT5663_EM_JACK_TYPE_4: 1307 case RT5663_FAST_OFF_MICBIAS: 1308 case RT5663_ANA_BIAS_CUR_1: 1309 case RT5663_ANA_BIAS_CUR_2: 1310 case RT5663_BIAS_CUR_9: 1311 case RT5663_DUMMY_REG_4: 1312 case RT5663_VREF_RECMIX: 1313 case RT5663_CHARGE_PUMP_1_2: 1314 case RT5663_CHARGE_PUMP_1_3: 1315 case RT5663_CHARGE_PUMP_2: 1316 case RT5663_CHOP_DAC_R: 1317 case RT5663_DUMMY_CTL_DACLR: 1318 case RT5663_DUMMY_REG_5: 1319 case RT5663_SOFT_RAMP: 1320 case RT5663_TEST_MODE_1: 1321 case RT5663_STO_DRE_10: 1322 case RT5663_MIC_DECRO_1: 1323 case RT5663_MIC_DECRO_2: 1324 case RT5663_MIC_DECRO_3: 1325 case RT5663_MIC_DECRO_4: 1326 case RT5663_MIC_DECRO_5: 1327 case RT5663_MIC_DECRO_6: 1328 case RT5663_HP_DECRO_1: 1329 case RT5663_HP_DECRO_2: 1330 case RT5663_HP_DECRO_3: 1331 case RT5663_HP_DECRO_4: 1332 case RT5663_HP_DECOUP: 1333 case RT5663_HP_IMPSEN_MAP4: 1334 case RT5663_HP_IMPSEN_MAP5: 1335 case RT5663_HP_IMPSEN_MAP7: 1336 case RT5663_HP_CALIB_1: 1337 case RT5663_CBJ_1: 1338 case RT5663_CBJ_2: 1339 case RT5663_CBJ_3: 1340 return false; 1341 default: 1342 return rt5663_readable_register(dev, reg); 1343 } 1344 } 1345 1346 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0); 1347 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0); 1348 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 1349 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 1350 1351 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 1352 static const DECLARE_TLV_DB_RANGE(in_bst_tlv, 1353 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 1354 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 1355 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 1356 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 1357 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 1358 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 1359 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 1360 ); 1361 1362 /* Interface data select */ 1363 static const char * const rt5663_if1_adc_data_select[] = { 1364 "L/R", "R/L", "L/L", "R/R" 1365 }; 1366 1367 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2, 1368 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select); 1369 1370 static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec, 1371 bool enable) 1372 { 1373 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1374 1375 if (enable) { 1376 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1377 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN); 1378 /* reset in-line command */ 1379 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1380 RT5663_RESET_4BTN_INL_MASK, 1381 RT5663_RESET_4BTN_INL_RESET); 1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1383 RT5663_RESET_4BTN_INL_MASK, 1384 RT5663_RESET_4BTN_INL_NOR); 1385 switch (rt5663->codec_ver) { 1386 case CODEC_VER_1: 1387 snd_soc_update_bits(codec, RT5663_IRQ_3, 1388 RT5663_V2_EN_IRQ_INLINE_MASK, 1389 RT5663_V2_EN_IRQ_INLINE_NOR); 1390 break; 1391 case CODEC_VER_0: 1392 snd_soc_update_bits(codec, RT5663_IRQ_2, 1393 RT5663_EN_IRQ_INLINE_MASK, 1394 RT5663_EN_IRQ_INLINE_NOR); 1395 break; 1396 default: 1397 dev_err(codec->dev, "Unknown CODEC Version\n"); 1398 } 1399 } else { 1400 switch (rt5663->codec_ver) { 1401 case CODEC_VER_1: 1402 snd_soc_update_bits(codec, RT5663_IRQ_3, 1403 RT5663_V2_EN_IRQ_INLINE_MASK, 1404 RT5663_V2_EN_IRQ_INLINE_BYP); 1405 break; 1406 case CODEC_VER_0: 1407 snd_soc_update_bits(codec, RT5663_IRQ_2, 1408 RT5663_EN_IRQ_INLINE_MASK, 1409 RT5663_EN_IRQ_INLINE_BYP); 1410 break; 1411 default: 1412 dev_err(codec->dev, "Unknown CODEC Version\n"); 1413 } 1414 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1415 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS); 1416 /* reset in-line command */ 1417 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1418 RT5663_RESET_4BTN_INL_MASK, 1419 RT5663_RESET_4BTN_INL_RESET); 1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1421 RT5663_RESET_4BTN_INL_MASK, 1422 RT5663_RESET_4BTN_INL_NOR); 1423 } 1424 } 1425 1426 /** 1427 * rt5663_v2_jack_detect - Detect headset. 1428 * @codec: SoC audio codec device. 1429 * @jack_insert: Jack insert or not. 1430 * 1431 * Detect whether is headset or not when jack inserted. 1432 * 1433 * Returns detect status. 1434 */ 1435 1436 static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert) 1437 { 1438 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1439 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1440 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; 1441 1442 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1443 if (jack_insert) { 1444 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040); 1445 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484); 1446 1447 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 1448 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 1449 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 1450 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 1451 snd_soc_dapm_sync(dapm); 1452 snd_soc_update_bits(codec, RT5663_RC_CLK, 1453 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN); 1454 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8); 1455 1456 while (i < 5) { 1457 msleep(sleep_time[i]); 1458 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003; 1459 if (val == 0x1 || val == 0x2 || val == 0x3) 1460 break; 1461 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n", 1462 __func__, val, sleep_time[i]); 1463 i++; 1464 } 1465 dev_dbg(codec->dev, "%s val = %d\n", __func__, val); 1466 switch (val) { 1467 case 1: 1468 case 2: 1469 rt5663->jack_type = SND_JACK_HEADSET; 1470 rt5663_enable_push_button_irq(codec, true); 1471 break; 1472 default: 1473 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1474 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1475 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1476 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1477 snd_soc_dapm_sync(dapm); 1478 rt5663->jack_type = SND_JACK_HEADPHONE; 1479 break; 1480 } 1481 } else { 1482 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0); 1483 1484 if (rt5663->jack_type == SND_JACK_HEADSET) { 1485 rt5663_enable_push_button_irq(codec, false); 1486 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1487 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1488 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1489 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1490 snd_soc_dapm_sync(dapm); 1491 } 1492 rt5663->jack_type = 0; 1493 } 1494 1495 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type); 1496 return rt5663->jack_type; 1497 } 1498 1499 /** 1500 * rt5663_jack_detect - Detect headset. 1501 * @codec: SoC audio codec device. 1502 * @jack_insert: Jack insert or not. 1503 * 1504 * Detect whether is headset or not when jack inserted. 1505 * 1506 * Returns detect status. 1507 */ 1508 static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert) 1509 { 1510 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1511 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; 1512 1513 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1514 1515 if (jack_insert) { 1516 snd_soc_update_bits(codec, RT5663_DIG_MISC, 1517 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 1518 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 1519 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK | 1520 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN | 1521 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS); 1522 snd_soc_update_bits(codec, RT5663_DUMMY_1, 1523 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK | 1524 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN | 1525 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1); 1526 snd_soc_update_bits(codec, RT5663_CBJ_1, 1527 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK, 1528 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L); 1529 snd_soc_update_bits(codec, RT5663_IL_CMD_2, 1530 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON); 1531 /* BST1 power on for JD */ 1532 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 1533 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON); 1534 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1, 1535 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK | 1536 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN | 1537 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN); 1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 1539 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK | 1540 RT5663_AMP_HP_MASK, RT5663_PWR_MB | 1541 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 1542 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK, 1543 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN); 1544 snd_soc_update_bits(codec, RT5663_IRQ_1, 1545 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 1546 while (i < 5) { 1547 msleep(sleep_time[i]); 1548 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 1549 0x0003; 1550 dev_dbg(codec->dev, "%s: MX-00e7 val=%x sleep %d\n", 1551 __func__, val, sleep_time[i]); 1552 i++; 1553 if (val == 0x1 || val == 0x2 || val == 0x3) 1554 break; 1555 } 1556 dev_dbg(codec->dev, "%s val = %d\n", __func__, val); 1557 switch (val) { 1558 case 1: 1559 case 2: 1560 rt5663->jack_type = SND_JACK_HEADSET; 1561 rt5663_enable_push_button_irq(codec, true); 1562 break; 1563 default: 1564 rt5663->jack_type = SND_JACK_HEADPHONE; 1565 break; 1566 } 1567 } else { 1568 if (rt5663->jack_type == SND_JACK_HEADSET) 1569 rt5663_enable_push_button_irq(codec, false); 1570 rt5663->jack_type = 0; 1571 } 1572 1573 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type); 1574 return rt5663->jack_type; 1575 } 1576 1577 static int rt5663_button_detect(struct snd_soc_codec *codec) 1578 { 1579 int btn_type, val; 1580 1581 val = snd_soc_read(codec, RT5663_IL_CMD_5); 1582 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val); 1583 btn_type = val & 0xfff0; 1584 snd_soc_write(codec, RT5663_IL_CMD_5, val); 1585 1586 return btn_type; 1587 } 1588 1589 static irqreturn_t rt5663_irq(int irq, void *data) 1590 { 1591 struct rt5663_priv *rt5663 = data; 1592 1593 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__); 1594 1595 queue_delayed_work(system_wq, &rt5663->jack_detect_work, 1596 msecs_to_jiffies(250)); 1597 1598 return IRQ_HANDLED; 1599 } 1600 1601 int rt5663_set_jack_detect(struct snd_soc_codec *codec, 1602 struct snd_soc_jack *hs_jack) 1603 { 1604 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1605 1606 rt5663->hs_jack = hs_jack; 1607 1608 rt5663_irq(0, rt5663); 1609 1610 return 0; 1611 } 1612 EXPORT_SYMBOL_GPL(rt5663_set_jack_detect); 1613 1614 static bool rt5663_check_jd_status(struct snd_soc_codec *codec) 1615 { 1616 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1617 int val = snd_soc_read(codec, RT5663_INT_ST_1); 1618 1619 dev_dbg(codec->dev, "%s val=%x\n", __func__, val); 1620 1621 /* JD1 */ 1622 switch (rt5663->codec_ver) { 1623 case CODEC_VER_1: 1624 return !(val & 0x2000); 1625 case CODEC_VER_0: 1626 return !(val & 0x1000); 1627 default: 1628 dev_err(codec->dev, "Unknown CODEC Version\n"); 1629 } 1630 1631 return false; 1632 } 1633 1634 static void rt5663_jack_detect_work(struct work_struct *work) 1635 { 1636 struct rt5663_priv *rt5663 = 1637 container_of(work, struct rt5663_priv, jack_detect_work.work); 1638 struct snd_soc_codec *codec = rt5663->codec; 1639 int btn_type, report = 0; 1640 1641 if (!codec) 1642 return; 1643 1644 if (rt5663_check_jd_status(codec)) { 1645 /* jack in */ 1646 if (rt5663->jack_type == 0) { 1647 /* jack was out, report jack type */ 1648 switch (rt5663->codec_ver) { 1649 case CODEC_VER_1: 1650 report = rt5663_v2_jack_detect( 1651 rt5663->codec, 1); 1652 break; 1653 case CODEC_VER_0: 1654 report = rt5663_jack_detect(rt5663->codec, 1); 1655 break; 1656 default: 1657 dev_err(codec->dev, "Unknown CODEC Version\n"); 1658 } 1659 } else { 1660 /* jack is already in, report button event */ 1661 report = SND_JACK_HEADSET; 1662 btn_type = rt5663_button_detect(rt5663->codec); 1663 /** 1664 * rt5663 can report three kinds of button behavior, 1665 * one click, double click and hold. However, 1666 * currently we will report button pressed/released 1667 * event. So all the three button behaviors are 1668 * treated as button pressed. 1669 */ 1670 switch (btn_type) { 1671 case 0x8000: 1672 case 0x4000: 1673 case 0x2000: 1674 report |= SND_JACK_BTN_0; 1675 break; 1676 case 0x1000: 1677 case 0x0800: 1678 case 0x0400: 1679 report |= SND_JACK_BTN_1; 1680 break; 1681 case 0x0200: 1682 case 0x0100: 1683 case 0x0080: 1684 report |= SND_JACK_BTN_2; 1685 break; 1686 case 0x0040: 1687 case 0x0020: 1688 case 0x0010: 1689 report |= SND_JACK_BTN_3; 1690 break; 1691 case 0x0000: /* unpressed */ 1692 break; 1693 default: 1694 btn_type = 0; 1695 dev_err(rt5663->codec->dev, 1696 "Unexpected button code 0x%04x\n", 1697 btn_type); 1698 break; 1699 } 1700 /* button release or spurious interrput*/ 1701 if (btn_type == 0) 1702 report = rt5663->jack_type; 1703 } 1704 } else { 1705 /* jack out */ 1706 switch (rt5663->codec_ver) { 1707 case CODEC_VER_1: 1708 report = rt5663_v2_jack_detect(rt5663->codec, 0); 1709 break; 1710 case CODEC_VER_0: 1711 report = rt5663_jack_detect(rt5663->codec, 0); 1712 break; 1713 default: 1714 dev_err(codec->dev, "Unknown CODEC Version\n"); 1715 } 1716 } 1717 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report); 1718 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET | 1719 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1720 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1721 } 1722 1723 static const struct snd_kcontrol_new rt5663_snd_controls[] = { 1724 /* DAC Digital Volume */ 1725 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL, 1726 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1, 1727 87, 0, dac_vol_tlv), 1728 /* ADC Digital Volume Control */ 1729 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL, 1730 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1), 1731 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL, 1732 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1, 1733 63, 0, adc_vol_tlv), 1734 }; 1735 1736 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = { 1737 /* Headphone Output Volume */ 1738 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE, 1739 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1, 1740 rt5663_v2_hp_vol_tlv), 1741 /* Mic Boost Volume */ 1742 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST, 1743 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv), 1744 }; 1745 1746 static const struct snd_kcontrol_new rt5663_specific_controls[] = { 1747 /* Headphone Output Volume */ 1748 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9, 1749 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1, 1750 rt5663_hp_vol_tlv), 1751 /* Mic Boost Volume*/ 1752 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2, 1753 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv), 1754 /* Data Swap for Slot0/1 in ADCDAT1 */ 1755 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum), 1756 }; 1757 1758 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, 1759 struct snd_soc_dapm_widget *sink) 1760 { 1761 unsigned int val; 1762 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1763 1764 val = snd_soc_read(codec, RT5663_GLB_CLK); 1765 val &= RT5663_SCLK_SRC_MASK; 1766 if (val == RT5663_SCLK_SRC_PLL1) 1767 return 1; 1768 else 1769 return 0; 1770 } 1771 1772 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w, 1773 struct snd_soc_dapm_widget *sink) 1774 { 1775 unsigned int reg, shift, val; 1776 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1777 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1778 1779 if (rt5663->codec_ver == CODEC_VER_1) { 1780 switch (w->shift) { 1781 case RT5663_ADC_STO1_ASRC_SHIFT: 1782 reg = RT5663_ASRC_3; 1783 shift = RT5663_V2_AD_STO1_TRACK_SHIFT; 1784 break; 1785 case RT5663_DAC_STO1_ASRC_SHIFT: 1786 reg = RT5663_ASRC_2; 1787 shift = RT5663_DA_STO1_TRACK_SHIFT; 1788 break; 1789 default: 1790 return 0; 1791 } 1792 } else { 1793 switch (w->shift) { 1794 case RT5663_ADC_STO1_ASRC_SHIFT: 1795 reg = RT5663_ASRC_2; 1796 shift = RT5663_AD_STO1_TRACK_SHIFT; 1797 break; 1798 case RT5663_DAC_STO1_ASRC_SHIFT: 1799 reg = RT5663_ASRC_2; 1800 shift = RT5663_DA_STO1_TRACK_SHIFT; 1801 break; 1802 default: 1803 return 0; 1804 } 1805 } 1806 1807 val = (snd_soc_read(codec, reg) >> shift) & 0x7; 1808 1809 if (val) 1810 return 1; 1811 1812 return 0; 1813 } 1814 1815 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source, 1816 struct snd_soc_dapm_widget *sink) 1817 { 1818 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 1819 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1820 int da_asrc_en, ad_asrc_en; 1821 1822 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) & 1823 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0; 1824 switch (rt5663->codec_ver) { 1825 case CODEC_VER_1: 1826 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) & 1827 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0; 1828 break; 1829 case CODEC_VER_0: 1830 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) & 1831 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0; 1832 break; 1833 default: 1834 dev_err(codec->dev, "Unknown CODEC Version\n"); 1835 return 1; 1836 } 1837 1838 if (da_asrc_en || ad_asrc_en) 1839 if (rt5663->sysclk > rt5663->lrck * 384) 1840 return 1; 1841 1842 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n"); 1843 1844 return 0; 1845 } 1846 1847 /** 1848 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters 1849 * @codec: SoC audio codec device. 1850 * @filter_mask: mask of filters. 1851 * @clk_src: clock source 1852 * 1853 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can 1854 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1855 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1856 * ASRC function will track i2s clock and generate a corresponding system clock 1857 * for codec. This function provides an API to select the clock source for a 1858 * set of filters specified by the mask. And the codec driver will turn on ASRC 1859 * for these filters if ASRC is selected as their clock source. 1860 */ 1861 int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec, 1862 unsigned int filter_mask, unsigned int clk_src) 1863 { 1864 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1865 unsigned int asrc2_mask = 0; 1866 unsigned int asrc2_value = 0; 1867 unsigned int asrc3_mask = 0; 1868 unsigned int asrc3_value = 0; 1869 1870 switch (clk_src) { 1871 case RT5663_CLK_SEL_SYS: 1872 case RT5663_CLK_SEL_I2S1_ASRC: 1873 break; 1874 1875 default: 1876 return -EINVAL; 1877 } 1878 1879 if (filter_mask & RT5663_DA_STEREO_FILTER) { 1880 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK; 1881 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT; 1882 } 1883 1884 if (filter_mask & RT5663_AD_STEREO_FILTER) { 1885 switch (rt5663->codec_ver) { 1886 case CODEC_VER_1: 1887 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK; 1888 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT; 1889 break; 1890 case CODEC_VER_0: 1891 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK; 1892 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT; 1893 break; 1894 default: 1895 dev_err(codec->dev, "Unknown CODEC Version\n"); 1896 } 1897 } 1898 1899 if (asrc2_mask) 1900 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask, 1901 asrc2_value); 1902 1903 if (asrc3_mask) 1904 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask, 1905 asrc3_value); 1906 1907 return 0; 1908 } 1909 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src); 1910 1911 /* Analog Mixer */ 1912 static const struct snd_kcontrol_new rt5663_recmix1l[] = { 1913 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L, 1914 RT5663_RECMIX1L_BST2_SHIFT, 1, 1), 1915 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L, 1916 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1), 1917 }; 1918 1919 static const struct snd_kcontrol_new rt5663_recmix1r[] = { 1920 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R, 1921 RT5663_RECMIX1R_BST2_SHIFT, 1, 1), 1922 }; 1923 1924 /* Digital Mixer */ 1925 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = { 1926 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 1927 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1), 1928 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 1929 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1), 1930 }; 1931 1932 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = { 1933 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 1934 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1), 1935 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 1936 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1), 1937 }; 1938 1939 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = { 1940 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER, 1941 RT5663_M_ADCMIX_L_SHIFT, 1, 1), 1942 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER, 1943 RT5663_M_DAC1_L_SHIFT, 1, 1), 1944 }; 1945 1946 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = { 1947 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER, 1948 RT5663_M_ADCMIX_R_SHIFT, 1, 1), 1949 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER, 1950 RT5663_M_DAC1_R_SHIFT, 1, 1), 1951 }; 1952 1953 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = { 1954 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER, 1955 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1), 1956 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER, 1957 RT5663_M_DAC_R1_STO_L_SHIFT, 1, 1), 1958 }; 1959 1960 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = { 1961 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER, 1962 RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1), 1963 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER, 1964 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1), 1965 }; 1966 1967 /* Out Switch */ 1968 static const struct snd_kcontrol_new rt5663_hpo_switch = 1969 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2, 1970 RT5663_EN_DAC_HPO_SHIFT, 1, 0); 1971 1972 /* Stereo ADC source */ 1973 static const char * const rt5663_sto1_adc_src[] = { 1974 "ADC L", "ADC R" 1975 }; 1976 1977 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER, 1978 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src); 1979 1980 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux = 1981 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum); 1982 1983 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER, 1984 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src); 1985 1986 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux = 1987 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum); 1988 1989 /* RT5663: Analog DACL1 input source */ 1990 static const char * const rt5663_alg_dacl_src[] = { 1991 "DAC L", "STO DAC MIXL" 1992 }; 1993 1994 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC, 1995 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src); 1996 1997 static const struct snd_kcontrol_new rt5663_alg_dacl_mux = 1998 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum); 1999 2000 /* RT5663: Analog DACR1 input source */ 2001 static const char * const rt5663_alg_dacr_src[] = { 2002 "DAC R", "STO DAC MIXR" 2003 }; 2004 2005 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC, 2006 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src); 2007 2008 static const struct snd_kcontrol_new rt5663_alg_dacr_mux = 2009 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum); 2010 2011 static int rt5663_hp_event(struct snd_soc_dapm_widget *w, 2012 struct snd_kcontrol *kcontrol, int event) 2013 { 2014 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2015 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2016 2017 switch (event) { 2018 case SND_SOC_DAPM_POST_PMU: 2019 if (rt5663->codec_ver == CODEC_VER_1) { 2020 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2021 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH); 2022 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2, 2023 RT5663_HP_SIG_SRC1_MASK, 2024 RT5663_HP_SIG_SRC1_SILENCE); 2025 } else { 2026 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003); 2027 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b, 2028 0x000b); 2029 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 2030 0x0030); 2031 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2032 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS); 2033 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371); 2034 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba); 2035 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224); 2036 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766); 2037 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa); 2038 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777); 2039 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 2040 0x3000); 2041 } 2042 break; 2043 2044 case SND_SOC_DAPM_PRE_PMD: 2045 if (rt5663->codec_ver == CODEC_VER_1) { 2046 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2, 2047 RT5663_HP_SIG_SRC1_MASK, 2048 RT5663_HP_SIG_SRC1_REG); 2049 } else { 2050 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0); 2051 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2052 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN); 2053 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0); 2054 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b, 2055 0x000b); 2056 } 2057 break; 2058 2059 default: 2060 return 0; 2061 } 2062 2063 return 0; 2064 } 2065 2066 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w, 2067 struct snd_kcontrol *kcontrol, int event) 2068 { 2069 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2070 2071 switch (event) { 2072 case SND_SOC_DAPM_POST_PMU: 2073 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 2074 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 2075 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP); 2076 break; 2077 2078 case SND_SOC_DAPM_PRE_PMD: 2079 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 2080 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0); 2081 break; 2082 2083 default: 2084 return 0; 2085 } 2086 2087 return 0; 2088 } 2089 2090 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w, 2091 struct snd_kcontrol *kcontrol, int event) 2092 { 2093 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2094 2095 switch (event) { 2096 case SND_SOC_DAPM_POST_PMU: 2097 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00); 2098 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc); 2099 break; 2100 2101 case SND_SOC_DAPM_PRE_PMD: 2102 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000); 2103 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000); 2104 break; 2105 2106 default: 2107 return 0; 2108 } 2109 2110 return 0; 2111 } 2112 2113 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = { 2114 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0, 2115 NULL, 0), 2116 2117 /* micbias */ 2118 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2, 2119 RT5663_PWR_MB1_SHIFT, 0), 2120 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2, 2121 RT5663_PWR_MB2_SHIFT, 0), 2122 2123 /* Input Lines */ 2124 SND_SOC_DAPM_INPUT("IN1P"), 2125 SND_SOC_DAPM_INPUT("IN1N"), 2126 2127 /* REC Mixer Power */ 2128 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2, 2129 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0), 2130 2131 /* ADCs */ 2132 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2133 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1, 2134 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0), 2135 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC, 2136 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0), 2137 2138 /* ADC Mixer */ 2139 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM, 2140 0, 0, rt5663_sto1_adc_l_mix, 2141 ARRAY_SIZE(rt5663_sto1_adc_l_mix)), 2142 2143 /* ADC Filter Power */ 2144 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2, 2145 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0), 2146 2147 /* Digital Interface */ 2148 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0, 2149 NULL, 0), 2150 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2151 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2152 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2153 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2154 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2155 2156 /* Audio Interface */ 2157 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 2158 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0), 2159 2160 /* DAC mixer before sound effect */ 2161 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix, 2162 ARRAY_SIZE(rt5663_adda_l_mix)), 2163 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix, 2164 ARRAY_SIZE(rt5663_adda_r_mix)), 2165 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2166 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0), 2167 2168 /* DAC Mixer */ 2169 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2, 2170 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0), 2171 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0, 2172 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)), 2173 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0, 2174 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)), 2175 2176 /* DACs */ 2177 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1, 2178 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0), 2179 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1, 2180 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0), 2181 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0), 2182 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0), 2183 2184 /* Headphone*/ 2185 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event, 2186 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2187 2188 /* Output Lines */ 2189 SND_SOC_DAPM_OUTPUT("HPOL"), 2190 SND_SOC_DAPM_OUTPUT("HPOR"), 2191 }; 2192 2193 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = { 2194 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3, 2195 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0), 2196 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL, 2197 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0), 2198 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1, 2199 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2200 2201 /* ASRC */ 2202 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2203 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2204 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2205 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2206 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2207 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2208 2209 /* Input Lines */ 2210 SND_SOC_DAPM_INPUT("IN2P"), 2211 SND_SOC_DAPM_INPUT("IN2N"), 2212 2213 /* Boost */ 2214 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0), 2215 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3, 2216 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0), 2217 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0), 2218 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0, 2219 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD | 2220 SND_SOC_DAPM_POST_PMU), 2221 2222 /* REC Mixer */ 2223 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l, 2224 ARRAY_SIZE(rt5663_recmix1l)), 2225 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r, 2226 ARRAY_SIZE(rt5663_recmix1r)), 2227 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2, 2228 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0), 2229 2230 /* ADC */ 2231 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2232 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1, 2233 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0), 2234 2235 /* ADC Mux */ 2236 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER, 2237 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0), 2238 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER, 2239 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0), 2240 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER, 2241 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0), 2242 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER, 2243 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0), 2244 2245 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0, 2246 &rt5663_sto1_adcl_mux), 2247 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0, 2248 &rt5663_sto1_adcr_mux), 2249 2250 /* ADC Mix */ 2251 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2252 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)), 2253 2254 /* Analog DAC Clock */ 2255 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L, 2256 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0), 2257 2258 /* Headphone out */ 2259 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0, 2260 &rt5663_hpo_switch), 2261 }; 2262 2263 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = { 2264 /* System Clock Pre Divider Gating */ 2265 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0, 2266 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU | 2267 SND_SOC_DAPM_PRE_PMD), 2268 2269 /* LDO */ 2270 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1, 2271 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2272 2273 /* ASRC */ 2274 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2275 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2276 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2277 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2278 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2279 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2280 2281 /* Boost */ 2282 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0), 2283 2284 /* STO ADC */ 2285 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2286 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0), 2287 2288 /* Analog DAC source */ 2289 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux), 2290 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux), 2291 }; 2292 2293 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = { 2294 /* PLL */ 2295 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll }, 2296 2297 /* ASRC */ 2298 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc }, 2299 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc }, 2300 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc }, 2301 2302 { "ADC L", NULL, "ADC L Power" }, 2303 { "ADC L", NULL, "ADC Clock" }, 2304 2305 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" }, 2306 2307 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" }, 2308 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" }, 2309 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" }, 2310 2311 { "IF1 ADC1", NULL, "STO1 ADC MIXL" }, 2312 { "IF ADC", NULL, "IF1 ADC1" }, 2313 { "AIFTX", NULL, "IF ADC" }, 2314 { "AIFTX", NULL, "I2S" }, 2315 2316 { "AIFRX", NULL, "I2S" }, 2317 { "IF DAC", NULL, "AIFRX" }, 2318 { "IF1 DAC1 L", NULL, "IF DAC" }, 2319 { "IF1 DAC1 R", NULL, "IF DAC" }, 2320 2321 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" }, 2322 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" }, 2323 { "ADDA MIXL", NULL, "STO1 DAC Filter" }, 2324 { "ADDA MIXL", NULL, "STO1 DAC L Power" }, 2325 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" }, 2326 { "ADDA MIXR", NULL, "STO1 DAC Filter" }, 2327 { "ADDA MIXR", NULL, "STO1 DAC R Power" }, 2328 2329 { "DAC L1", NULL, "ADDA MIXL" }, 2330 { "DAC R1", NULL, "ADDA MIXR" }, 2331 2332 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" }, 2333 { "STO1 DAC MIXL", "DAC R Switch", "DAC R1" }, 2334 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" }, 2335 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" }, 2336 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" }, 2337 { "STO1 DAC MIXR", "DAC L Switch", "DAC L1" }, 2338 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" }, 2339 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" }, 2340 2341 { "HP Amp", NULL, "DAC L" }, 2342 { "HP Amp", NULL, "DAC R" }, 2343 }; 2344 2345 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = { 2346 { "MICBIAS1", NULL, "LDO2" }, 2347 { "MICBIAS2", NULL, "LDO2" }, 2348 2349 { "BST1 CBJ", NULL, "IN1P" }, 2350 { "BST1 CBJ", NULL, "IN1N" }, 2351 { "BST1 CBJ", NULL, "CBJ Power" }, 2352 2353 { "BST2", NULL, "IN2P" }, 2354 { "BST2", NULL, "IN2N" }, 2355 { "BST2", NULL, "BST2 Power" }, 2356 2357 { "RECMIX1L", "BST2 Switch", "BST2" }, 2358 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" }, 2359 { "RECMIX1L", NULL, "RECMIX1L Power" }, 2360 { "RECMIX1R", "BST2 Switch", "BST2" }, 2361 { "RECMIX1R", NULL, "RECMIX1R Power" }, 2362 2363 { "ADC L", NULL, "RECMIX1L" }, 2364 { "ADC R", NULL, "RECMIX1R" }, 2365 { "ADC R", NULL, "ADC R Power" }, 2366 { "ADC R", NULL, "ADC Clock" }, 2367 2368 { "STO1 ADC L Mux", "ADC L", "ADC L" }, 2369 { "STO1 ADC L Mux", "ADC R", "ADC R" }, 2370 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" }, 2371 2372 { "STO1 ADC R Mux", "ADC L", "ADC L" }, 2373 { "STO1 ADC R Mux", "ADC R", "ADC R" }, 2374 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" }, 2375 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" }, 2376 2377 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" }, 2378 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" }, 2379 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" }, 2380 2381 { "IF1 ADC1", NULL, "STO1 ADC MIXR" }, 2382 2383 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" }, 2384 2385 { "DAC L", NULL, "STO1 DAC MIXL" }, 2386 { "DAC L", NULL, "LDO DAC" }, 2387 { "DAC L", NULL, "DAC Clock" }, 2388 { "DAC R", NULL, "STO1 DAC MIXR" }, 2389 { "DAC R", NULL, "LDO DAC" }, 2390 { "DAC R", NULL, "DAC Clock" }, 2391 2392 { "HPO Playback", "Switch", "HP Amp" }, 2393 { "HPOL", NULL, "HPO Playback" }, 2394 { "HPOR", NULL, "HPO Playback" }, 2395 }; 2396 2397 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = { 2398 { "I2S", NULL, "Pre Div Power" }, 2399 2400 { "BST1", NULL, "IN1P" }, 2401 { "BST1", NULL, "IN1N" }, 2402 { "BST1", NULL, "RECMIX1L Power" }, 2403 2404 { "ADC L", NULL, "BST1" }, 2405 2406 { "STO1 ADC L1", NULL, "ADC L" }, 2407 2408 { "DAC L Mux", "DAC L", "DAC L1" }, 2409 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" }, 2410 { "DAC R Mux", "DAC R", "DAC R1"}, 2411 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" }, 2412 2413 { "DAC L", NULL, "DAC L Mux" }, 2414 { "DAC R", NULL, "DAC R Mux" }, 2415 2416 { "HPOL", NULL, "HP Amp" }, 2417 { "HPOR", NULL, "HP Amp" }, 2418 }; 2419 2420 static int rt5663_hw_params(struct snd_pcm_substream *substream, 2421 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2422 { 2423 struct snd_soc_codec *codec = dai->codec; 2424 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2425 unsigned int val_len = 0; 2426 int pre_div; 2427 2428 rt5663->lrck = params_rate(params); 2429 2430 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n", 2431 rt5663->lrck, rt5663->sysclk); 2432 2433 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck); 2434 if (pre_div < 0) { 2435 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n", 2436 rt5663->lrck, dai->id); 2437 return -EINVAL; 2438 } 2439 2440 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id); 2441 2442 switch (params_width(params)) { 2443 case 8: 2444 val_len = RT5663_I2S_DL_8; 2445 break; 2446 case 16: 2447 val_len = RT5663_I2S_DL_16; 2448 break; 2449 case 20: 2450 val_len = RT5663_I2S_DL_20; 2451 break; 2452 case 24: 2453 val_len = RT5663_I2S_DL_24; 2454 break; 2455 default: 2456 return -EINVAL; 2457 } 2458 2459 snd_soc_update_bits(codec, RT5663_I2S1_SDP, 2460 RT5663_I2S_DL_MASK, val_len); 2461 2462 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1, 2463 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT); 2464 2465 return 0; 2466 } 2467 2468 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2469 { 2470 struct snd_soc_codec *codec = dai->codec; 2471 unsigned int reg_val = 0; 2472 2473 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2474 case SND_SOC_DAIFMT_CBM_CFM: 2475 break; 2476 case SND_SOC_DAIFMT_CBS_CFS: 2477 reg_val |= RT5663_I2S_MS_S; 2478 break; 2479 default: 2480 return -EINVAL; 2481 } 2482 2483 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2484 case SND_SOC_DAIFMT_NB_NF: 2485 break; 2486 case SND_SOC_DAIFMT_IB_NF: 2487 reg_val |= RT5663_I2S_BP_INV; 2488 break; 2489 default: 2490 return -EINVAL; 2491 } 2492 2493 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2494 case SND_SOC_DAIFMT_I2S: 2495 break; 2496 case SND_SOC_DAIFMT_LEFT_J: 2497 reg_val |= RT5663_I2S_DF_LEFT; 2498 break; 2499 case SND_SOC_DAIFMT_DSP_A: 2500 reg_val |= RT5663_I2S_DF_PCM_A; 2501 break; 2502 case SND_SOC_DAIFMT_DSP_B: 2503 reg_val |= RT5663_I2S_DF_PCM_B; 2504 break; 2505 default: 2506 return -EINVAL; 2507 } 2508 2509 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK | 2510 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val); 2511 2512 return 0; 2513 } 2514 2515 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 2516 unsigned int freq, int dir) 2517 { 2518 struct snd_soc_codec *codec = dai->codec; 2519 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2520 unsigned int reg_val = 0; 2521 2522 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src) 2523 return 0; 2524 2525 switch (clk_id) { 2526 case RT5663_SCLK_S_MCLK: 2527 reg_val |= RT5663_SCLK_SRC_MCLK; 2528 break; 2529 case RT5663_SCLK_S_PLL1: 2530 reg_val |= RT5663_SCLK_SRC_PLL1; 2531 break; 2532 case RT5663_SCLK_S_RCCLK: 2533 reg_val |= RT5663_SCLK_SRC_RCCLK; 2534 break; 2535 default: 2536 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 2537 return -EINVAL; 2538 } 2539 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK, 2540 reg_val); 2541 rt5663->sysclk = freq; 2542 rt5663->sysclk_src = clk_id; 2543 2544 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", 2545 freq, clk_id); 2546 2547 return 0; 2548 } 2549 2550 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2551 unsigned int freq_in, unsigned int freq_out) 2552 { 2553 struct snd_soc_codec *codec = dai->codec; 2554 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2555 struct rl6231_pll_code pll_code; 2556 int ret; 2557 int mask, shift, val; 2558 2559 if (source == rt5663->pll_src && freq_in == rt5663->pll_in && 2560 freq_out == rt5663->pll_out) 2561 return 0; 2562 2563 if (!freq_in || !freq_out) { 2564 dev_dbg(codec->dev, "PLL disabled\n"); 2565 2566 rt5663->pll_in = 0; 2567 rt5663->pll_out = 0; 2568 snd_soc_update_bits(codec, RT5663_GLB_CLK, 2569 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK); 2570 return 0; 2571 } 2572 2573 switch (rt5663->codec_ver) { 2574 case CODEC_VER_1: 2575 mask = RT5663_V2_PLL1_SRC_MASK; 2576 shift = RT5663_V2_PLL1_SRC_SHIFT; 2577 break; 2578 case CODEC_VER_0: 2579 mask = RT5663_PLL1_SRC_MASK; 2580 shift = RT5663_PLL1_SRC_SHIFT; 2581 break; 2582 default: 2583 dev_err(codec->dev, "Unknown CODEC Version\n"); 2584 return -EINVAL; 2585 } 2586 2587 switch (source) { 2588 case RT5663_PLL1_S_MCLK: 2589 val = 0x0; 2590 break; 2591 case RT5663_PLL1_S_BCLK1: 2592 val = 0x1; 2593 break; 2594 default: 2595 dev_err(codec->dev, "Unknown PLL source %d\n", source); 2596 return -EINVAL; 2597 } 2598 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift)); 2599 2600 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2601 if (ret < 0) { 2602 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 2603 return ret; 2604 } 2605 2606 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp, 2607 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code, 2608 pll_code.k_code); 2609 2610 snd_soc_write(codec, RT5663_PLL_1, 2611 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code); 2612 snd_soc_write(codec, RT5663_PLL_2, 2613 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT | 2614 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT); 2615 2616 rt5663->pll_in = freq_in; 2617 rt5663->pll_out = freq_out; 2618 rt5663->pll_src = source; 2619 2620 return 0; 2621 } 2622 2623 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2624 unsigned int rx_mask, int slots, int slot_width) 2625 { 2626 struct snd_soc_codec *codec = dai->codec; 2627 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2628 unsigned int val = 0, reg; 2629 2630 if (rx_mask || tx_mask) 2631 val |= RT5663_TDM_MODE_TDM; 2632 2633 switch (slots) { 2634 case 4: 2635 val |= RT5663_TDM_IN_CH_4; 2636 val |= RT5663_TDM_OUT_CH_4; 2637 break; 2638 case 6: 2639 val |= RT5663_TDM_IN_CH_6; 2640 val |= RT5663_TDM_OUT_CH_6; 2641 break; 2642 case 8: 2643 val |= RT5663_TDM_IN_CH_8; 2644 val |= RT5663_TDM_OUT_CH_8; 2645 break; 2646 case 2: 2647 break; 2648 default: 2649 return -EINVAL; 2650 } 2651 2652 switch (slot_width) { 2653 case 20: 2654 val |= RT5663_TDM_IN_LEN_20; 2655 val |= RT5663_TDM_OUT_LEN_20; 2656 break; 2657 case 24: 2658 val |= RT5663_TDM_IN_LEN_24; 2659 val |= RT5663_TDM_OUT_LEN_24; 2660 break; 2661 case 32: 2662 val |= RT5663_TDM_IN_LEN_32; 2663 val |= RT5663_TDM_OUT_LEN_32; 2664 break; 2665 case 16: 2666 break; 2667 default: 2668 return -EINVAL; 2669 } 2670 2671 switch (rt5663->codec_ver) { 2672 case CODEC_VER_1: 2673 reg = RT5663_TDM_2; 2674 break; 2675 case CODEC_VER_0: 2676 reg = RT5663_TDM_1; 2677 break; 2678 default: 2679 dev_err(codec->dev, "Unknown CODEC Version\n"); 2680 return -EINVAL; 2681 } 2682 2683 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK | 2684 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK | 2685 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val); 2686 2687 return 0; 2688 } 2689 2690 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2691 { 2692 struct snd_soc_codec *codec = dai->codec; 2693 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2694 unsigned int reg; 2695 2696 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio); 2697 2698 if (rt5663->codec_ver == CODEC_VER_1) 2699 reg = RT5663_TDM_9; 2700 else 2701 reg = RT5663_TDM_5; 2702 2703 switch (ratio) { 2704 case 32: 2705 snd_soc_update_bits(codec, reg, 2706 RT5663_TDM_LENGTN_MASK, 2707 RT5663_TDM_LENGTN_16); 2708 break; 2709 case 40: 2710 snd_soc_update_bits(codec, reg, 2711 RT5663_TDM_LENGTN_MASK, 2712 RT5663_TDM_LENGTN_20); 2713 break; 2714 case 48: 2715 snd_soc_update_bits(codec, reg, 2716 RT5663_TDM_LENGTN_MASK, 2717 RT5663_TDM_LENGTN_24); 2718 break; 2719 case 64: 2720 snd_soc_update_bits(codec, reg, 2721 RT5663_TDM_LENGTN_MASK, 2722 RT5663_TDM_LENGTN_32); 2723 break; 2724 default: 2725 dev_err(codec->dev, "Invalid ratio!\n"); 2726 return -EINVAL; 2727 } 2728 2729 return 0; 2730 } 2731 2732 static int rt5663_set_bias_level(struct snd_soc_codec *codec, 2733 enum snd_soc_bias_level level) 2734 { 2735 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2736 2737 switch (level) { 2738 case SND_SOC_BIAS_ON: 2739 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2740 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 2741 RT5663_PWR_FV1 | RT5663_PWR_FV2); 2742 break; 2743 2744 case SND_SOC_BIAS_PREPARE: 2745 if (rt5663->codec_ver == CODEC_VER_1) { 2746 snd_soc_update_bits(codec, RT5663_DIG_MISC, 2747 RT5663_DIG_GATE_CTRL_MASK, 2748 RT5663_DIG_GATE_CTRL_EN); 2749 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET, 2750 RT5663_EN_ANA_CLK_DET_MASK | 2751 RT5663_PWR_CLK_DET_MASK, 2752 RT5663_EN_ANA_CLK_DET_AUTO | 2753 RT5663_PWR_CLK_DET_EN); 2754 } 2755 break; 2756 2757 case SND_SOC_BIAS_STANDBY: 2758 if (rt5663->codec_ver == CODEC_VER_1) 2759 snd_soc_update_bits(codec, RT5663_DIG_MISC, 2760 RT5663_DIG_GATE_CTRL_MASK, 2761 RT5663_DIG_GATE_CTRL_DIS); 2762 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2763 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 2764 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK | 2765 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 | 2766 RT5663_PWR_VREF2 | RT5663_PWR_MB); 2767 usleep_range(10000, 10005); 2768 if (rt5663->codec_ver == CODEC_VER_1) { 2769 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET, 2770 RT5663_EN_ANA_CLK_DET_MASK | 2771 RT5663_PWR_CLK_DET_MASK, 2772 RT5663_EN_ANA_CLK_DET_DIS | 2773 RT5663_PWR_CLK_DET_DIS); 2774 } 2775 break; 2776 2777 case SND_SOC_BIAS_OFF: 2778 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2779 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 2780 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0); 2781 break; 2782 2783 default: 2784 break; 2785 } 2786 2787 return 0; 2788 } 2789 2790 static int rt5663_probe(struct snd_soc_codec *codec) 2791 { 2792 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 2793 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2794 2795 rt5663->codec = codec; 2796 2797 switch (rt5663->codec_ver) { 2798 case CODEC_VER_1: 2799 snd_soc_dapm_new_controls(dapm, 2800 rt5663_v2_specific_dapm_widgets, 2801 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets)); 2802 snd_soc_dapm_add_routes(dapm, 2803 rt5663_v2_specific_dapm_routes, 2804 ARRAY_SIZE(rt5663_v2_specific_dapm_routes)); 2805 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls, 2806 ARRAY_SIZE(rt5663_v2_specific_controls)); 2807 break; 2808 case CODEC_VER_0: 2809 snd_soc_dapm_new_controls(dapm, 2810 rt5663_specific_dapm_widgets, 2811 ARRAY_SIZE(rt5663_specific_dapm_widgets)); 2812 snd_soc_dapm_add_routes(dapm, 2813 rt5663_specific_dapm_routes, 2814 ARRAY_SIZE(rt5663_specific_dapm_routes)); 2815 snd_soc_add_codec_controls(codec, rt5663_specific_controls, 2816 ARRAY_SIZE(rt5663_specific_controls)); 2817 break; 2818 } 2819 2820 return 0; 2821 } 2822 2823 static int rt5663_remove(struct snd_soc_codec *codec) 2824 { 2825 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2826 2827 regmap_write(rt5663->regmap, RT5663_RESET, 0); 2828 2829 return 0; 2830 } 2831 2832 #ifdef CONFIG_PM 2833 static int rt5663_suspend(struct snd_soc_codec *codec) 2834 { 2835 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2836 2837 regcache_cache_only(rt5663->regmap, true); 2838 regcache_mark_dirty(rt5663->regmap); 2839 2840 return 0; 2841 } 2842 2843 static int rt5663_resume(struct snd_soc_codec *codec) 2844 { 2845 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2846 2847 regcache_cache_only(rt5663->regmap, false); 2848 regcache_sync(rt5663->regmap); 2849 2850 return 0; 2851 } 2852 #else 2853 #define rt5663_suspend NULL 2854 #define rt5663_resume NULL 2855 #endif 2856 2857 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2858 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2859 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2860 2861 static struct snd_soc_dai_ops rt5663_aif_dai_ops = { 2862 .hw_params = rt5663_hw_params, 2863 .set_fmt = rt5663_set_dai_fmt, 2864 .set_sysclk = rt5663_set_dai_sysclk, 2865 .set_pll = rt5663_set_dai_pll, 2866 .set_tdm_slot = rt5663_set_tdm_slot, 2867 .set_bclk_ratio = rt5663_set_bclk_ratio, 2868 }; 2869 2870 static struct snd_soc_dai_driver rt5663_dai[] = { 2871 { 2872 .name = "rt5663-aif", 2873 .id = RT5663_AIF, 2874 .playback = { 2875 .stream_name = "AIF Playback", 2876 .channels_min = 1, 2877 .channels_max = 2, 2878 .rates = RT5663_STEREO_RATES, 2879 .formats = RT5663_FORMATS, 2880 }, 2881 .capture = { 2882 .stream_name = "AIF Capture", 2883 .channels_min = 1, 2884 .channels_max = 2, 2885 .rates = RT5663_STEREO_RATES, 2886 .formats = RT5663_FORMATS, 2887 }, 2888 .ops = &rt5663_aif_dai_ops, 2889 }, 2890 }; 2891 2892 static struct snd_soc_codec_driver soc_codec_dev_rt5663 = { 2893 .probe = rt5663_probe, 2894 .remove = rt5663_remove, 2895 .suspend = rt5663_suspend, 2896 .resume = rt5663_resume, 2897 .set_bias_level = rt5663_set_bias_level, 2898 .idle_bias_off = true, 2899 .component_driver = { 2900 .controls = rt5663_snd_controls, 2901 .num_controls = ARRAY_SIZE(rt5663_snd_controls), 2902 .dapm_widgets = rt5663_dapm_widgets, 2903 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets), 2904 .dapm_routes = rt5663_dapm_routes, 2905 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes), 2906 } 2907 }; 2908 2909 static const struct regmap_config rt5663_v2_regmap = { 2910 .reg_bits = 16, 2911 .val_bits = 16, 2912 .use_single_rw = true, 2913 .max_register = 0x07fa, 2914 .volatile_reg = rt5663_v2_volatile_register, 2915 .readable_reg = rt5663_v2_readable_register, 2916 .cache_type = REGCACHE_RBTREE, 2917 .reg_defaults = rt5663_v2_reg, 2918 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg), 2919 }; 2920 2921 static const struct regmap_config rt5663_regmap = { 2922 .reg_bits = 16, 2923 .val_bits = 16, 2924 .use_single_rw = true, 2925 .max_register = 0x03f3, 2926 .volatile_reg = rt5663_volatile_register, 2927 .readable_reg = rt5663_readable_register, 2928 .cache_type = REGCACHE_RBTREE, 2929 .reg_defaults = rt5663_reg, 2930 .num_reg_defaults = ARRAY_SIZE(rt5663_reg), 2931 }; 2932 2933 static const struct regmap_config temp_regmap = { 2934 .name = "nocache", 2935 .reg_bits = 16, 2936 .val_bits = 16, 2937 .use_single_rw = true, 2938 .max_register = 0x03f3, 2939 .cache_type = REGCACHE_NONE, 2940 }; 2941 2942 static const struct i2c_device_id rt5663_i2c_id[] = { 2943 { "rt5663", 0 }, 2944 {} 2945 }; 2946 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id); 2947 2948 #if defined(CONFIG_OF) 2949 static const struct of_device_id rt5663_of_match[] = { 2950 { .compatible = "realtek,rt5663", }, 2951 {}, 2952 }; 2953 MODULE_DEVICE_TABLE(of, rt5663_of_match); 2954 #endif 2955 2956 #ifdef CONFIG_ACPI 2957 static struct acpi_device_id rt5663_acpi_match[] = { 2958 { "10EC5663", 0}, 2959 {}, 2960 }; 2961 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match); 2962 #endif 2963 2964 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663) 2965 { 2966 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 2967 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100); 2968 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040); 2969 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001); 2970 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380); 2971 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 2972 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000); 2973 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030); 2974 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05); 2975 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e); 2976 msleep(40); 2977 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e); 2978 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321); 2979 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00); 2980 msleep(500); 2981 } 2982 2983 static void rt5663_calibrate(struct rt5663_priv *rt5663) 2984 { 2985 int value, count; 2986 2987 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0280); 2988 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 2989 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001); 2990 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 2991 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be); 2992 msleep(20); 2993 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be); 2994 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400); 2995 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000); 2996 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b); 2997 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8); 2998 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0003); 2999 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c); 3000 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1111); 3001 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff); 3002 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff); 3003 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003); 3004 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b); 3005 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32); 3006 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371); 3007 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b); 3008 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x2080); 3009 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c); 3010 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xabba); 3011 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224); 3012 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088); 3013 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017); 3014 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017); 3015 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040); 3016 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005); 3017 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000); 3018 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320); 3019 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9); 3020 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c); 3021 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766); 3022 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4702); 3023 msleep(200); 3024 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069); 3025 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06c2); 3026 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x7b00); 3027 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xfb00); 3028 count = 0; 3029 while (true) { 3030 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value); 3031 if (value & 0x8000) 3032 usleep_range(10000, 10005); 3033 else 3034 break; 3035 3036 if (count > 200) 3037 return; 3038 count++; 3039 } 3040 } 3041 3042 static int rt5663_i2c_probe(struct i2c_client *i2c, 3043 const struct i2c_device_id *id) 3044 { 3045 struct rt5663_priv *rt5663; 3046 int ret; 3047 unsigned int val; 3048 struct regmap *regmap; 3049 3050 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv), 3051 GFP_KERNEL); 3052 3053 if (rt5663 == NULL) 3054 return -ENOMEM; 3055 3056 i2c_set_clientdata(i2c, rt5663); 3057 3058 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 3059 if (IS_ERR(regmap)) { 3060 ret = PTR_ERR(regmap); 3061 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 3062 ret); 3063 return ret; 3064 } 3065 regmap_read(regmap, RT5663_VENDOR_ID_2, &val); 3066 switch (val) { 3067 case RT5663_DEVICE_ID_2: 3068 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap); 3069 rt5663->codec_ver = CODEC_VER_1; 3070 break; 3071 case RT5663_DEVICE_ID_1: 3072 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap); 3073 rt5663->codec_ver = CODEC_VER_0; 3074 break; 3075 default: 3076 dev_err(&i2c->dev, 3077 "Device with ID register %#x is not rt5663\n", 3078 val); 3079 return -ENODEV; 3080 } 3081 3082 if (IS_ERR(rt5663->regmap)) { 3083 ret = PTR_ERR(rt5663->regmap); 3084 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3085 ret); 3086 return ret; 3087 } 3088 3089 /* reset and calibrate */ 3090 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3091 regcache_cache_bypass(rt5663->regmap, true); 3092 switch (rt5663->codec_ver) { 3093 case CODEC_VER_1: 3094 rt5663_v2_calibrate(rt5663); 3095 break; 3096 case CODEC_VER_0: 3097 rt5663_calibrate(rt5663); 3098 break; 3099 default: 3100 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3101 } 3102 regcache_cache_bypass(rt5663->regmap, false); 3103 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3104 dev_dbg(&i2c->dev, "calibrate done\n"); 3105 3106 /* GPIO1 as IRQ */ 3107 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK, 3108 RT5663_GP1_PIN_IRQ); 3109 /* 4btn inline command debounce */ 3110 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5, 3111 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS); 3112 3113 switch (rt5663->codec_ver) { 3114 case CODEC_VER_1: 3115 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3116 /* JD1 */ 3117 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3118 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK, 3119 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN); 3120 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2, 3121 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1); 3122 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3123 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN); 3124 3125 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2, 3126 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG); 3127 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3128 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK | 3129 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG | 3130 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN); 3131 /* Set GPIO4 and GPIO8 as input for combo jack */ 3132 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3133 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT); 3134 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3, 3135 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT); 3136 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1, 3137 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK, 3138 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 3139 break; 3140 case CODEC_VER_0: 3141 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC, 3142 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 3143 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3144 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN); 3145 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3146 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 3147 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, 3148 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN); 3149 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 3150 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be); 3151 msleep(20); 3152 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be); 3153 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3154 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK, 3155 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN); 3156 /* DACREF LDO control */ 3157 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e, 3158 0x3a0a); 3159 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3160 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON); 3161 regmap_update_bits(rt5663->regmap, RT5663_TDM_2, 3162 RT5663_DATA_SWAP_ADCDAT1_MASK, 3163 RT5663_DATA_SWAP_ADCDAT1_LL); 3164 break; 3165 default: 3166 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3167 } 3168 3169 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work); 3170 3171 if (i2c->irq) { 3172 ret = request_irq(i2c->irq, rt5663_irq, 3173 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 3174 | IRQF_ONESHOT, "rt5663", rt5663); 3175 if (ret) 3176 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n", 3177 __func__, ret); 3178 } 3179 3180 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663, 3181 rt5663_dai, ARRAY_SIZE(rt5663_dai)); 3182 3183 if (ret) { 3184 if (i2c->irq) 3185 free_irq(i2c->irq, rt5663); 3186 } 3187 3188 return ret; 3189 } 3190 3191 static int rt5663_i2c_remove(struct i2c_client *i2c) 3192 { 3193 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c); 3194 3195 if (i2c->irq) 3196 free_irq(i2c->irq, rt5663); 3197 3198 snd_soc_unregister_codec(&i2c->dev); 3199 3200 return 0; 3201 } 3202 3203 static void rt5663_i2c_shutdown(struct i2c_client *client) 3204 { 3205 struct rt5663_priv *rt5663 = i2c_get_clientdata(client); 3206 3207 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3208 } 3209 3210 static struct i2c_driver rt5663_i2c_driver = { 3211 .driver = { 3212 .name = "rt5663", 3213 .acpi_match_table = ACPI_PTR(rt5663_acpi_match), 3214 .of_match_table = of_match_ptr(rt5663_of_match), 3215 }, 3216 .probe = rt5663_i2c_probe, 3217 .remove = rt5663_i2c_remove, 3218 .shutdown = rt5663_i2c_shutdown, 3219 .id_table = rt5663_i2c_id, 3220 }; 3221 module_i2c_driver(rt5663_i2c_driver); 3222 3223 MODULE_DESCRIPTION("ASoC RT5663 driver"); 3224 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 3225 MODULE_LICENSE("GPL v2"); 3226