1 /* 2 * rt5663.c -- RT5663 ALSA SoC audio codec driver 3 * 4 * Copyright 2016 Realtek Semiconductor Corp. 5 * Author: Jack Yu <jack.yu@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/platform_device.h> 18 #include <linux/spi/spi.h> 19 #include <linux/acpi.h> 20 #include <linux/workqueue.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rt5663.h" 31 #include "rl6231.h" 32 33 #define RT5663_DEVICE_ID_2 0x6451 34 #define RT5663_DEVICE_ID_1 0x6406 35 36 enum { 37 CODEC_VER_1, 38 CODEC_VER_0, 39 }; 40 41 struct rt5663_priv { 42 struct snd_soc_codec *codec; 43 struct rt5663_platform_data pdata; 44 struct regmap *regmap; 45 struct delayed_work jack_detect_work; 46 struct snd_soc_jack *hs_jack; 47 struct timer_list btn_check_timer; 48 49 int codec_ver; 50 int sysclk; 51 int sysclk_src; 52 int lrck; 53 54 int pll_src; 55 int pll_in; 56 int pll_out; 57 58 int jack_type; 59 }; 60 61 static const struct reg_sequence rt5663_patch_list[] = { 62 { 0x002a, 0x8020 }, 63 { 0x0086, 0x0028 }, 64 }; 65 66 static const struct reg_default rt5663_v2_reg[] = { 67 { 0x0000, 0x0000 }, 68 { 0x0001, 0xc8c8 }, 69 { 0x0002, 0x8080 }, 70 { 0x0003, 0x8000 }, 71 { 0x0004, 0xc80a }, 72 { 0x0005, 0x0000 }, 73 { 0x0006, 0x0000 }, 74 { 0x0007, 0x0000 }, 75 { 0x000a, 0x0000 }, 76 { 0x000b, 0x0000 }, 77 { 0x000c, 0x0000 }, 78 { 0x000d, 0x0000 }, 79 { 0x000f, 0x0808 }, 80 { 0x0010, 0x4000 }, 81 { 0x0011, 0x0000 }, 82 { 0x0012, 0x1404 }, 83 { 0x0013, 0x1000 }, 84 { 0x0014, 0xa00a }, 85 { 0x0015, 0x0404 }, 86 { 0x0016, 0x0404 }, 87 { 0x0017, 0x0011 }, 88 { 0x0018, 0xafaf }, 89 { 0x0019, 0xafaf }, 90 { 0x001a, 0xafaf }, 91 { 0x001b, 0x0011 }, 92 { 0x001c, 0x2f2f }, 93 { 0x001d, 0x2f2f }, 94 { 0x001e, 0x2f2f }, 95 { 0x001f, 0x0000 }, 96 { 0x0020, 0x0000 }, 97 { 0x0021, 0x0000 }, 98 { 0x0022, 0x5757 }, 99 { 0x0023, 0x0039 }, 100 { 0x0024, 0x000b }, 101 { 0x0026, 0xc0c0 }, 102 { 0x0027, 0xc0c0 }, 103 { 0x0028, 0xc0c0 }, 104 { 0x0029, 0x8080 }, 105 { 0x002a, 0xaaaa }, 106 { 0x002b, 0xaaaa }, 107 { 0x002c, 0xaba8 }, 108 { 0x002d, 0x0000 }, 109 { 0x002e, 0x0000 }, 110 { 0x002f, 0x0000 }, 111 { 0x0030, 0x0000 }, 112 { 0x0031, 0x5000 }, 113 { 0x0032, 0x0000 }, 114 { 0x0033, 0x0000 }, 115 { 0x0034, 0x0000 }, 116 { 0x0035, 0x0000 }, 117 { 0x003a, 0x0000 }, 118 { 0x003b, 0x0000 }, 119 { 0x003c, 0x00ff }, 120 { 0x003d, 0x0000 }, 121 { 0x003e, 0x00ff }, 122 { 0x003f, 0x0000 }, 123 { 0x0040, 0x0000 }, 124 { 0x0041, 0x00ff }, 125 { 0x0042, 0x0000 }, 126 { 0x0043, 0x00ff }, 127 { 0x0044, 0x0c0c }, 128 { 0x0049, 0xc00b }, 129 { 0x004a, 0x0000 }, 130 { 0x004b, 0x031f }, 131 { 0x004d, 0x0000 }, 132 { 0x004e, 0x001f }, 133 { 0x004f, 0x0000 }, 134 { 0x0050, 0x001f }, 135 { 0x0052, 0xf000 }, 136 { 0x0061, 0x0000 }, 137 { 0x0062, 0x0000 }, 138 { 0x0063, 0x003e }, 139 { 0x0064, 0x0000 }, 140 { 0x0065, 0x0000 }, 141 { 0x0066, 0x003f }, 142 { 0x0067, 0x0000 }, 143 { 0x006b, 0x0000 }, 144 { 0x006d, 0xff00 }, 145 { 0x006e, 0x2808 }, 146 { 0x006f, 0x000a }, 147 { 0x0070, 0x8000 }, 148 { 0x0071, 0x8000 }, 149 { 0x0072, 0x8000 }, 150 { 0x0073, 0x7000 }, 151 { 0x0074, 0x7770 }, 152 { 0x0075, 0x0002 }, 153 { 0x0076, 0x0001 }, 154 { 0x0078, 0x00f0 }, 155 { 0x0079, 0x0000 }, 156 { 0x007a, 0x0000 }, 157 { 0x007b, 0x0000 }, 158 { 0x007c, 0x0000 }, 159 { 0x007d, 0x0123 }, 160 { 0x007e, 0x4500 }, 161 { 0x007f, 0x8003 }, 162 { 0x0080, 0x0000 }, 163 { 0x0081, 0x0000 }, 164 { 0x0082, 0x0000 }, 165 { 0x0083, 0x0000 }, 166 { 0x0084, 0x0000 }, 167 { 0x0085, 0x0000 }, 168 { 0x0086, 0x0008 }, 169 { 0x0087, 0x0000 }, 170 { 0x0088, 0x0000 }, 171 { 0x0089, 0x0000 }, 172 { 0x008a, 0x0000 }, 173 { 0x008b, 0x0000 }, 174 { 0x008c, 0x0003 }, 175 { 0x008e, 0x0060 }, 176 { 0x008f, 0x1000 }, 177 { 0x0091, 0x0c26 }, 178 { 0x0092, 0x0073 }, 179 { 0x0093, 0x0000 }, 180 { 0x0094, 0x0080 }, 181 { 0x0098, 0x0000 }, 182 { 0x0099, 0x0000 }, 183 { 0x009a, 0x0007 }, 184 { 0x009f, 0x0000 }, 185 { 0x00a0, 0x0000 }, 186 { 0x00a1, 0x0002 }, 187 { 0x00a2, 0x0001 }, 188 { 0x00a3, 0x0002 }, 189 { 0x00a4, 0x0001 }, 190 { 0x00ae, 0x2040 }, 191 { 0x00af, 0x0000 }, 192 { 0x00b6, 0x0000 }, 193 { 0x00b7, 0x0000 }, 194 { 0x00b8, 0x0000 }, 195 { 0x00b9, 0x0000 }, 196 { 0x00ba, 0x0002 }, 197 { 0x00bb, 0x0000 }, 198 { 0x00be, 0x0000 }, 199 { 0x00c0, 0x0000 }, 200 { 0x00c1, 0x0aaa }, 201 { 0x00c2, 0xaa80 }, 202 { 0x00c3, 0x0003 }, 203 { 0x00c4, 0x0000 }, 204 { 0x00d0, 0x0000 }, 205 { 0x00d1, 0x2244 }, 206 { 0x00d2, 0x0000 }, 207 { 0x00d3, 0x3300 }, 208 { 0x00d4, 0x2200 }, 209 { 0x00d9, 0x0809 }, 210 { 0x00da, 0x0000 }, 211 { 0x00db, 0x0008 }, 212 { 0x00dc, 0x00c0 }, 213 { 0x00dd, 0x6724 }, 214 { 0x00de, 0x3131 }, 215 { 0x00df, 0x0008 }, 216 { 0x00e0, 0x4000 }, 217 { 0x00e1, 0x3131 }, 218 { 0x00e2, 0x600c }, 219 { 0x00ea, 0xb320 }, 220 { 0x00eb, 0x0000 }, 221 { 0x00ec, 0xb300 }, 222 { 0x00ed, 0x0000 }, 223 { 0x00ee, 0xb320 }, 224 { 0x00ef, 0x0000 }, 225 { 0x00f0, 0x0201 }, 226 { 0x00f1, 0x0ddd }, 227 { 0x00f2, 0x0ddd }, 228 { 0x00f6, 0x0000 }, 229 { 0x00f7, 0x0000 }, 230 { 0x00f8, 0x0000 }, 231 { 0x00fa, 0x0000 }, 232 { 0x00fb, 0x0000 }, 233 { 0x00fc, 0x0000 }, 234 { 0x00fd, 0x0000 }, 235 { 0x00fe, 0x10ec }, 236 { 0x00ff, 0x6451 }, 237 { 0x0100, 0xaaaa }, 238 { 0x0101, 0x000a }, 239 { 0x010a, 0xaaaa }, 240 { 0x010b, 0xa0a0 }, 241 { 0x010c, 0xaeae }, 242 { 0x010d, 0xaaaa }, 243 { 0x010e, 0xaaaa }, 244 { 0x010f, 0xaaaa }, 245 { 0x0110, 0xe002 }, 246 { 0x0111, 0xa602 }, 247 { 0x0112, 0xaaaa }, 248 { 0x0113, 0x2000 }, 249 { 0x0117, 0x0f00 }, 250 { 0x0125, 0x0420 }, 251 { 0x0132, 0x0000 }, 252 { 0x0133, 0x0000 }, 253 { 0x0136, 0x5555 }, 254 { 0x0137, 0x5540 }, 255 { 0x0138, 0x3700 }, 256 { 0x0139, 0x79a1 }, 257 { 0x013a, 0x2020 }, 258 { 0x013b, 0x2020 }, 259 { 0x013c, 0x2005 }, 260 { 0x013f, 0x0000 }, 261 { 0x0145, 0x0002 }, 262 { 0x0146, 0x0000 }, 263 { 0x0147, 0x0000 }, 264 { 0x0148, 0x0000 }, 265 { 0x0160, 0x4ec0 }, 266 { 0x0161, 0x0080 }, 267 { 0x0162, 0x0200 }, 268 { 0x0163, 0x0800 }, 269 { 0x0164, 0x0000 }, 270 { 0x0165, 0x0000 }, 271 { 0x0166, 0x0000 }, 272 { 0x0167, 0x000f }, 273 { 0x0168, 0x000f }, 274 { 0x0170, 0x4e80 }, 275 { 0x0171, 0x0080 }, 276 { 0x0172, 0x0200 }, 277 { 0x0173, 0x0800 }, 278 { 0x0174, 0x00ff }, 279 { 0x0175, 0x0000 }, 280 { 0x0190, 0x4131 }, 281 { 0x0191, 0x4131 }, 282 { 0x0192, 0x4131 }, 283 { 0x0193, 0x4131 }, 284 { 0x0194, 0x0000 }, 285 { 0x0195, 0x0000 }, 286 { 0x0196, 0x0000 }, 287 { 0x0197, 0x0000 }, 288 { 0x0198, 0x0000 }, 289 { 0x0199, 0x0000 }, 290 { 0x01a0, 0x1e64 }, 291 { 0x01a1, 0x06a3 }, 292 { 0x01a2, 0x0000 }, 293 { 0x01a3, 0x0000 }, 294 { 0x01a4, 0x0000 }, 295 { 0x01a5, 0x0000 }, 296 { 0x01a6, 0x0000 }, 297 { 0x01a7, 0x0000 }, 298 { 0x01a8, 0x0000 }, 299 { 0x01a9, 0x0000 }, 300 { 0x01aa, 0x0000 }, 301 { 0x01ab, 0x0000 }, 302 { 0x01b5, 0x0000 }, 303 { 0x01b6, 0x01c3 }, 304 { 0x01b7, 0x02a0 }, 305 { 0x01b8, 0x03e9 }, 306 { 0x01b9, 0x1389 }, 307 { 0x01ba, 0xc351 }, 308 { 0x01bb, 0x0009 }, 309 { 0x01bc, 0x0018 }, 310 { 0x01bd, 0x002a }, 311 { 0x01be, 0x004c }, 312 { 0x01bf, 0x0097 }, 313 { 0x01c0, 0x433d }, 314 { 0x01c1, 0x0000 }, 315 { 0x01c2, 0x0000 }, 316 { 0x01c3, 0x0000 }, 317 { 0x01c4, 0x0000 }, 318 { 0x01c5, 0x0000 }, 319 { 0x01c6, 0x0000 }, 320 { 0x01c7, 0x0000 }, 321 { 0x01c8, 0x40af }, 322 { 0x01c9, 0x0702 }, 323 { 0x01ca, 0x0000 }, 324 { 0x01cb, 0x0000 }, 325 { 0x01cc, 0x5757 }, 326 { 0x01cd, 0x5757 }, 327 { 0x01ce, 0x5757 }, 328 { 0x01cf, 0x5757 }, 329 { 0x01d0, 0x5757 }, 330 { 0x01d1, 0x5757 }, 331 { 0x01d2, 0x5757 }, 332 { 0x01d3, 0x5757 }, 333 { 0x01d4, 0x5757 }, 334 { 0x01d5, 0x5757 }, 335 { 0x01d6, 0x003c }, 336 { 0x01da, 0x0000 }, 337 { 0x01db, 0x0000 }, 338 { 0x01dc, 0x0000 }, 339 { 0x01de, 0x7c00 }, 340 { 0x01df, 0x0320 }, 341 { 0x01e0, 0x06a1 }, 342 { 0x01e1, 0x0000 }, 343 { 0x01e2, 0x0000 }, 344 { 0x01e3, 0x0000 }, 345 { 0x01e4, 0x0000 }, 346 { 0x01e5, 0x0000 }, 347 { 0x01e6, 0x0001 }, 348 { 0x01e7, 0x0000 }, 349 { 0x01e8, 0x0000 }, 350 { 0x01ea, 0x0000 }, 351 { 0x01eb, 0x0000 }, 352 { 0x01ec, 0x0000 }, 353 { 0x01ed, 0x0000 }, 354 { 0x01ee, 0x0000 }, 355 { 0x01ef, 0x0000 }, 356 { 0x01f0, 0x0000 }, 357 { 0x01f1, 0x0000 }, 358 { 0x01f2, 0x0000 }, 359 { 0x01f3, 0x0000 }, 360 { 0x01f4, 0x0000 }, 361 { 0x0200, 0x0000 }, 362 { 0x0201, 0x0000 }, 363 { 0x0202, 0x0000 }, 364 { 0x0203, 0x0000 }, 365 { 0x0204, 0x0000 }, 366 { 0x0205, 0x0000 }, 367 { 0x0206, 0x0000 }, 368 { 0x0207, 0x0000 }, 369 { 0x0208, 0x0000 }, 370 { 0x0210, 0x60b1 }, 371 { 0x0211, 0xa000 }, 372 { 0x0212, 0x024c }, 373 { 0x0213, 0xf7ff }, 374 { 0x0214, 0x024c }, 375 { 0x0215, 0x0102 }, 376 { 0x0216, 0x00a3 }, 377 { 0x0217, 0x0048 }, 378 { 0x0218, 0x92c0 }, 379 { 0x0219, 0x0000 }, 380 { 0x021a, 0x00c8 }, 381 { 0x021b, 0x0020 }, 382 { 0x02fa, 0x0000 }, 383 { 0x02fb, 0x0000 }, 384 { 0x02fc, 0x0000 }, 385 { 0x02ff, 0x0110 }, 386 { 0x0300, 0x001f }, 387 { 0x0301, 0x032c }, 388 { 0x0302, 0x5f21 }, 389 { 0x0303, 0x4000 }, 390 { 0x0304, 0x4000 }, 391 { 0x0305, 0x06d5 }, 392 { 0x0306, 0x8000 }, 393 { 0x0307, 0x0700 }, 394 { 0x0310, 0x4560 }, 395 { 0x0311, 0xa4a8 }, 396 { 0x0312, 0x7418 }, 397 { 0x0313, 0x0000 }, 398 { 0x0314, 0x0006 }, 399 { 0x0315, 0xffff }, 400 { 0x0316, 0xc400 }, 401 { 0x0317, 0x0000 }, 402 { 0x0330, 0x00a6 }, 403 { 0x0331, 0x04c3 }, 404 { 0x0332, 0x27c8 }, 405 { 0x0333, 0xbf50 }, 406 { 0x0334, 0x0045 }, 407 { 0x0335, 0x0007 }, 408 { 0x0336, 0x7418 }, 409 { 0x0337, 0x0501 }, 410 { 0x0338, 0x0000 }, 411 { 0x0339, 0x0010 }, 412 { 0x033a, 0x1010 }, 413 { 0x03c0, 0x7e00 }, 414 { 0x03c1, 0x8000 }, 415 { 0x03c2, 0x8000 }, 416 { 0x03c3, 0x8000 }, 417 { 0x03c4, 0x8000 }, 418 { 0x03c5, 0x8000 }, 419 { 0x03c6, 0x8000 }, 420 { 0x03c7, 0x8000 }, 421 { 0x03c8, 0x8000 }, 422 { 0x03c9, 0x8000 }, 423 { 0x03ca, 0x8000 }, 424 { 0x03cb, 0x8000 }, 425 { 0x03cc, 0x8000 }, 426 { 0x03d0, 0x0000 }, 427 { 0x03d1, 0x0000 }, 428 { 0x03d2, 0x0000 }, 429 { 0x03d3, 0x0000 }, 430 { 0x03d4, 0x2000 }, 431 { 0x03d5, 0x2000 }, 432 { 0x03d6, 0x0000 }, 433 { 0x03d7, 0x0000 }, 434 { 0x03d8, 0x2000 }, 435 { 0x03d9, 0x2000 }, 436 { 0x03da, 0x2000 }, 437 { 0x03db, 0x2000 }, 438 { 0x03dc, 0x0000 }, 439 { 0x03dd, 0x0000 }, 440 { 0x03de, 0x0000 }, 441 { 0x03df, 0x2000 }, 442 { 0x03e0, 0x0000 }, 443 { 0x03e1, 0x0000 }, 444 { 0x03e2, 0x0000 }, 445 { 0x03e3, 0x0000 }, 446 { 0x03e4, 0x0000 }, 447 { 0x03e5, 0x0000 }, 448 { 0x03e6, 0x0000 }, 449 { 0x03e7, 0x0000 }, 450 { 0x03e8, 0x0000 }, 451 { 0x03e9, 0x0000 }, 452 { 0x03ea, 0x0000 }, 453 { 0x03eb, 0x0000 }, 454 { 0x03ec, 0x0000 }, 455 { 0x03ed, 0x0000 }, 456 { 0x03ee, 0x0000 }, 457 { 0x03ef, 0x0000 }, 458 { 0x03f0, 0x0800 }, 459 { 0x03f1, 0x0800 }, 460 { 0x03f2, 0x0800 }, 461 { 0x03f3, 0x0800 }, 462 { 0x03fe, 0x0000 }, 463 { 0x03ff, 0x0000 }, 464 { 0x07f0, 0x0000 }, 465 { 0x07fa, 0x0000 }, 466 }; 467 468 static const struct reg_default rt5663_reg[] = { 469 { 0x0000, 0x0000 }, 470 { 0x0002, 0x0008 }, 471 { 0x0005, 0x1000 }, 472 { 0x0006, 0x1000 }, 473 { 0x000a, 0x0000 }, 474 { 0x0010, 0x000f }, 475 { 0x0015, 0x42f1 }, 476 { 0x0016, 0x0000 }, 477 { 0x0018, 0x000b }, 478 { 0x0019, 0xafaf }, 479 { 0x001c, 0x2f2f }, 480 { 0x001f, 0x0000 }, 481 { 0x0022, 0x5757 }, 482 { 0x0023, 0x0039 }, 483 { 0x0026, 0xc0c0 }, 484 { 0x0029, 0x8080 }, 485 { 0x002a, 0x8020 }, 486 { 0x002c, 0x000c }, 487 { 0x002d, 0x0000 }, 488 { 0x0040, 0x0808 }, 489 { 0x0061, 0x0000 }, 490 { 0x0062, 0x0000 }, 491 { 0x0063, 0x003e }, 492 { 0x0064, 0x0000 }, 493 { 0x0065, 0x0000 }, 494 { 0x0066, 0x0000 }, 495 { 0x006b, 0x0000 }, 496 { 0x006e, 0x0000 }, 497 { 0x006f, 0x0000 }, 498 { 0x0070, 0x8020 }, 499 { 0x0073, 0x1000 }, 500 { 0x0074, 0xe400 }, 501 { 0x0075, 0x0002 }, 502 { 0x0076, 0x0001 }, 503 { 0x0077, 0x00f0 }, 504 { 0x0078, 0x0000 }, 505 { 0x0079, 0x0000 }, 506 { 0x007a, 0x0123 }, 507 { 0x007b, 0x8003 }, 508 { 0x0080, 0x0000 }, 509 { 0x0081, 0x0000 }, 510 { 0x0082, 0x0000 }, 511 { 0x0083, 0x0000 }, 512 { 0x0084, 0x0000 }, 513 { 0x0086, 0x0028 }, 514 { 0x0087, 0x0000 }, 515 { 0x008a, 0x0000 }, 516 { 0x008b, 0x0000 }, 517 { 0x008c, 0x0003 }, 518 { 0x008e, 0x0008 }, 519 { 0x008f, 0x1000 }, 520 { 0x0090, 0x0646 }, 521 { 0x0091, 0x0e3e }, 522 { 0x0092, 0x1071 }, 523 { 0x0093, 0x0000 }, 524 { 0x0094, 0x0080 }, 525 { 0x0097, 0x0000 }, 526 { 0x0098, 0x0000 }, 527 { 0x009a, 0x0000 }, 528 { 0x009f, 0x0000 }, 529 { 0x00ae, 0x6000 }, 530 { 0x00af, 0x0000 }, 531 { 0x00b6, 0x0000 }, 532 { 0x00b7, 0x0000 }, 533 { 0x00b8, 0x0000 }, 534 { 0x00ba, 0x0000 }, 535 { 0x00bb, 0x0000 }, 536 { 0x00be, 0x0000 }, 537 { 0x00bf, 0x0000 }, 538 { 0x00c0, 0x0000 }, 539 { 0x00c1, 0x0000 }, 540 { 0x00c5, 0x0000 }, 541 { 0x00cb, 0xa02f }, 542 { 0x00cc, 0x0000 }, 543 { 0x00cd, 0x0e02 }, 544 { 0x00d9, 0x08f9 }, 545 { 0x00db, 0x0008 }, 546 { 0x00dc, 0x00c0 }, 547 { 0x00dd, 0x6729 }, 548 { 0x00de, 0x3131 }, 549 { 0x00df, 0x0008 }, 550 { 0x00e0, 0x4000 }, 551 { 0x00e1, 0x3131 }, 552 { 0x00e2, 0x0043 }, 553 { 0x00e4, 0x400b }, 554 { 0x00e5, 0x8031 }, 555 { 0x00e6, 0x3080 }, 556 { 0x00e7, 0x4100 }, 557 { 0x00e8, 0x1400 }, 558 { 0x00e9, 0xe00a }, 559 { 0x00ea, 0x0404 }, 560 { 0x00eb, 0x0404 }, 561 { 0x00ec, 0xb320 }, 562 { 0x00ed, 0x0000 }, 563 { 0x00f4, 0x0000 }, 564 { 0x00f6, 0x0000 }, 565 { 0x00f8, 0x0000 }, 566 { 0x00fa, 0x8000 }, 567 { 0x00fd, 0x0001 }, 568 { 0x00fe, 0x10ec }, 569 { 0x00ff, 0x6406 }, 570 { 0x0100, 0xa0a0 }, 571 { 0x0108, 0x4444 }, 572 { 0x0109, 0x4444 }, 573 { 0x010a, 0xaaaa }, 574 { 0x010b, 0x00a0 }, 575 { 0x010c, 0x8aaa }, 576 { 0x010d, 0xaaaa }, 577 { 0x010e, 0x2aaa }, 578 { 0x010f, 0x002a }, 579 { 0x0110, 0xa0a4 }, 580 { 0x0111, 0x4602 }, 581 { 0x0112, 0x0101 }, 582 { 0x0113, 0x2000 }, 583 { 0x0114, 0x0000 }, 584 { 0x0116, 0x0000 }, 585 { 0x0117, 0x0f00 }, 586 { 0x0118, 0x0006 }, 587 { 0x0125, 0x2424 }, 588 { 0x0126, 0x5550 }, 589 { 0x0127, 0x0400 }, 590 { 0x0128, 0x7711 }, 591 { 0x0132, 0x0004 }, 592 { 0x0137, 0x5441 }, 593 { 0x0139, 0x79a1 }, 594 { 0x013a, 0x30c0 }, 595 { 0x013b, 0x2000 }, 596 { 0x013c, 0x2005 }, 597 { 0x013d, 0x30c0 }, 598 { 0x013e, 0x0000 }, 599 { 0x0140, 0x3700 }, 600 { 0x0141, 0x1f00 }, 601 { 0x0144, 0x0000 }, 602 { 0x0145, 0x0002 }, 603 { 0x0146, 0x0000 }, 604 { 0x0160, 0x0e80 }, 605 { 0x0161, 0x0080 }, 606 { 0x0162, 0x0200 }, 607 { 0x0163, 0x0800 }, 608 { 0x0164, 0x0000 }, 609 { 0x0165, 0x0000 }, 610 { 0x0166, 0x0000 }, 611 { 0x0167, 0x1417 }, 612 { 0x0168, 0x0017 }, 613 { 0x0169, 0x0017 }, 614 { 0x0180, 0x2000 }, 615 { 0x0181, 0x0000 }, 616 { 0x0182, 0x0000 }, 617 { 0x0183, 0x2000 }, 618 { 0x0184, 0x0000 }, 619 { 0x0185, 0x0000 }, 620 { 0x01b0, 0x4b30 }, 621 { 0x01b1, 0x0000 }, 622 { 0x01b2, 0xd870 }, 623 { 0x01b3, 0x0000 }, 624 { 0x01b4, 0x0030 }, 625 { 0x01b5, 0x5757 }, 626 { 0x01b6, 0x5757 }, 627 { 0x01b7, 0x5757 }, 628 { 0x01b8, 0x5757 }, 629 { 0x01c0, 0x433d }, 630 { 0x01c1, 0x0540 }, 631 { 0x01c2, 0x0000 }, 632 { 0x01c3, 0x0000 }, 633 { 0x01c4, 0x0000 }, 634 { 0x01c5, 0x0009 }, 635 { 0x01c6, 0x0018 }, 636 { 0x01c7, 0x002a }, 637 { 0x01c8, 0x004c }, 638 { 0x01c9, 0x0097 }, 639 { 0x01ca, 0x01c3 }, 640 { 0x01cb, 0x03e9 }, 641 { 0x01cc, 0x1389 }, 642 { 0x01cd, 0xc351 }, 643 { 0x01ce, 0x0000 }, 644 { 0x01cf, 0x0000 }, 645 { 0x01d0, 0x0000 }, 646 { 0x01d1, 0x0000 }, 647 { 0x01d2, 0x0000 }, 648 { 0x01d3, 0x003c }, 649 { 0x01d4, 0x5757 }, 650 { 0x01d5, 0x5757 }, 651 { 0x01d6, 0x5757 }, 652 { 0x01d7, 0x5757 }, 653 { 0x01d8, 0x5757 }, 654 { 0x01d9, 0x5757 }, 655 { 0x01da, 0x0000 }, 656 { 0x01db, 0x0000 }, 657 { 0x01dd, 0x0009 }, 658 { 0x01de, 0x7f00 }, 659 { 0x01df, 0x00c8 }, 660 { 0x01e0, 0x0691 }, 661 { 0x01e1, 0x0000 }, 662 { 0x01e2, 0x0000 }, 663 { 0x01e3, 0x0000 }, 664 { 0x01e4, 0x0000 }, 665 { 0x01e5, 0x0040 }, 666 { 0x01e6, 0x0000 }, 667 { 0x01e7, 0x0000 }, 668 { 0x01e8, 0x0000 }, 669 { 0x01ea, 0x0000 }, 670 { 0x01eb, 0x0000 }, 671 { 0x01ec, 0x0000 }, 672 { 0x01ed, 0x0000 }, 673 { 0x01ee, 0x0000 }, 674 { 0x01ef, 0x0000 }, 675 { 0x01f0, 0x0000 }, 676 { 0x01f1, 0x0000 }, 677 { 0x01f2, 0x0000 }, 678 { 0x0200, 0x0000 }, 679 { 0x0201, 0x2244 }, 680 { 0x0202, 0xaaaa }, 681 { 0x0250, 0x8010 }, 682 { 0x0251, 0x0000 }, 683 { 0x0252, 0x028a }, 684 { 0x02fa, 0x0000 }, 685 { 0x02fb, 0x00a4 }, 686 { 0x02fc, 0x0300 }, 687 { 0x0300, 0x0000 }, 688 { 0x03d0, 0x0000 }, 689 { 0x03d1, 0x0000 }, 690 { 0x03d2, 0x0000 }, 691 { 0x03d3, 0x0000 }, 692 { 0x03d4, 0x2000 }, 693 { 0x03d5, 0x2000 }, 694 { 0x03d6, 0x0000 }, 695 { 0x03d7, 0x0000 }, 696 { 0x03d8, 0x2000 }, 697 { 0x03d9, 0x2000 }, 698 { 0x03da, 0x2000 }, 699 { 0x03db, 0x2000 }, 700 { 0x03dc, 0x0000 }, 701 { 0x03dd, 0x0000 }, 702 { 0x03de, 0x0000 }, 703 { 0x03df, 0x2000 }, 704 { 0x03e0, 0x0000 }, 705 { 0x03e1, 0x0000 }, 706 { 0x03e2, 0x0000 }, 707 { 0x03e3, 0x0000 }, 708 { 0x03e4, 0x0000 }, 709 { 0x03e5, 0x0000 }, 710 { 0x03e6, 0x0000 }, 711 { 0x03e7, 0x0000 }, 712 { 0x03e8, 0x0000 }, 713 { 0x03e9, 0x0000 }, 714 { 0x03ea, 0x0000 }, 715 { 0x03eb, 0x0000 }, 716 { 0x03ec, 0x0000 }, 717 { 0x03ed, 0x0000 }, 718 { 0x03ee, 0x0000 }, 719 { 0x03ef, 0x0000 }, 720 { 0x03f0, 0x0800 }, 721 { 0x03f1, 0x0800 }, 722 { 0x03f2, 0x0800 }, 723 { 0x03f3, 0x0800 }, 724 }; 725 726 static bool rt5663_volatile_register(struct device *dev, unsigned int reg) 727 { 728 switch (reg) { 729 case RT5663_RESET: 730 case RT5663_SIL_DET_CTL: 731 case RT5663_HP_IMP_GAIN_2: 732 case RT5663_AD_DA_MIXER: 733 case RT5663_FRAC_DIV_2: 734 case RT5663_MICBIAS_1: 735 case RT5663_ASRC_11_2: 736 case RT5663_ADC_EQ_1: 737 case RT5663_INT_ST_1: 738 case RT5663_INT_ST_2: 739 case RT5663_GPIO_STA1: 740 case RT5663_SIN_GEN_1: 741 case RT5663_IL_CMD_1: 742 case RT5663_IL_CMD_5: 743 case RT5663_IL_CMD_PWRSAV1: 744 case RT5663_EM_JACK_TYPE_1: 745 case RT5663_EM_JACK_TYPE_2: 746 case RT5663_EM_JACK_TYPE_3: 747 case RT5663_JD_CTRL2: 748 case RT5663_VENDOR_ID: 749 case RT5663_VENDOR_ID_1: 750 case RT5663_VENDOR_ID_2: 751 case RT5663_PLL_INT_REG: 752 case RT5663_SOFT_RAMP: 753 case RT5663_STO_DRE_1: 754 case RT5663_STO_DRE_5: 755 case RT5663_STO_DRE_6: 756 case RT5663_STO_DRE_7: 757 case RT5663_MIC_DECRO_1: 758 case RT5663_MIC_DECRO_4: 759 case RT5663_HP_IMP_SEN_1: 760 case RT5663_HP_IMP_SEN_3: 761 case RT5663_HP_IMP_SEN_4: 762 case RT5663_HP_IMP_SEN_5: 763 case RT5663_HP_CALIB_1_1: 764 case RT5663_HP_CALIB_9: 765 case RT5663_HP_CALIB_ST1: 766 case RT5663_HP_CALIB_ST2: 767 case RT5663_HP_CALIB_ST3: 768 case RT5663_HP_CALIB_ST4: 769 case RT5663_HP_CALIB_ST5: 770 case RT5663_HP_CALIB_ST6: 771 case RT5663_HP_CALIB_ST7: 772 case RT5663_HP_CALIB_ST8: 773 case RT5663_HP_CALIB_ST9: 774 case RT5663_ANA_JD: 775 return true; 776 default: 777 return false; 778 } 779 } 780 781 static bool rt5663_readable_register(struct device *dev, unsigned int reg) 782 { 783 switch (reg) { 784 case RT5663_RESET: 785 case RT5663_HP_OUT_EN: 786 case RT5663_HP_LCH_DRE: 787 case RT5663_HP_RCH_DRE: 788 case RT5663_CALIB_BST: 789 case RT5663_RECMIX: 790 case RT5663_SIL_DET_CTL: 791 case RT5663_PWR_SAV_SILDET: 792 case RT5663_SIDETONE_CTL: 793 case RT5663_STO1_DAC_DIG_VOL: 794 case RT5663_STO1_ADC_DIG_VOL: 795 case RT5663_STO1_BOOST: 796 case RT5663_HP_IMP_GAIN_1: 797 case RT5663_HP_IMP_GAIN_2: 798 case RT5663_STO1_ADC_MIXER: 799 case RT5663_AD_DA_MIXER: 800 case RT5663_STO_DAC_MIXER: 801 case RT5663_DIG_SIDE_MIXER: 802 case RT5663_BYPASS_STO_DAC: 803 case RT5663_CALIB_REC_MIX: 804 case RT5663_PWR_DIG_1: 805 case RT5663_PWR_DIG_2: 806 case RT5663_PWR_ANLG_1: 807 case RT5663_PWR_ANLG_2: 808 case RT5663_PWR_ANLG_3: 809 case RT5663_PWR_MIXER: 810 case RT5663_SIG_CLK_DET: 811 case RT5663_PRE_DIV_GATING_1: 812 case RT5663_PRE_DIV_GATING_2: 813 case RT5663_I2S1_SDP: 814 case RT5663_ADDA_CLK_1: 815 case RT5663_ADDA_RST: 816 case RT5663_FRAC_DIV_1: 817 case RT5663_FRAC_DIV_2: 818 case RT5663_TDM_1: 819 case RT5663_TDM_2: 820 case RT5663_TDM_3: 821 case RT5663_TDM_4: 822 case RT5663_TDM_5: 823 case RT5663_GLB_CLK: 824 case RT5663_PLL_1: 825 case RT5663_PLL_2: 826 case RT5663_ASRC_1: 827 case RT5663_ASRC_2: 828 case RT5663_ASRC_4: 829 case RT5663_DUMMY_REG: 830 case RT5663_ASRC_8: 831 case RT5663_ASRC_9: 832 case RT5663_ASRC_11: 833 case RT5663_DEPOP_1: 834 case RT5663_DEPOP_2: 835 case RT5663_DEPOP_3: 836 case RT5663_HP_CHARGE_PUMP_1: 837 case RT5663_HP_CHARGE_PUMP_2: 838 case RT5663_MICBIAS_1: 839 case RT5663_RC_CLK: 840 case RT5663_ASRC_11_2: 841 case RT5663_DUMMY_REG_2: 842 case RT5663_REC_PATH_GAIN: 843 case RT5663_AUTO_1MRC_CLK: 844 case RT5663_ADC_EQ_1: 845 case RT5663_ADC_EQ_2: 846 case RT5663_IRQ_1: 847 case RT5663_IRQ_2: 848 case RT5663_IRQ_3: 849 case RT5663_IRQ_4: 850 case RT5663_IRQ_5: 851 case RT5663_INT_ST_1: 852 case RT5663_INT_ST_2: 853 case RT5663_GPIO_1: 854 case RT5663_GPIO_2: 855 case RT5663_GPIO_STA1: 856 case RT5663_SIN_GEN_1: 857 case RT5663_SIN_GEN_2: 858 case RT5663_SIN_GEN_3: 859 case RT5663_SOF_VOL_ZC1: 860 case RT5663_IL_CMD_1: 861 case RT5663_IL_CMD_2: 862 case RT5663_IL_CMD_3: 863 case RT5663_IL_CMD_4: 864 case RT5663_IL_CMD_5: 865 case RT5663_IL_CMD_6: 866 case RT5663_IL_CMD_7: 867 case RT5663_IL_CMD_8: 868 case RT5663_IL_CMD_PWRSAV1: 869 case RT5663_IL_CMD_PWRSAV2: 870 case RT5663_EM_JACK_TYPE_1: 871 case RT5663_EM_JACK_TYPE_2: 872 case RT5663_EM_JACK_TYPE_3: 873 case RT5663_EM_JACK_TYPE_4: 874 case RT5663_EM_JACK_TYPE_5: 875 case RT5663_EM_JACK_TYPE_6: 876 case RT5663_STO1_HPF_ADJ1: 877 case RT5663_STO1_HPF_ADJ2: 878 case RT5663_FAST_OFF_MICBIAS: 879 case RT5663_JD_CTRL1: 880 case RT5663_JD_CTRL2: 881 case RT5663_DIG_MISC: 882 case RT5663_VENDOR_ID: 883 case RT5663_VENDOR_ID_1: 884 case RT5663_VENDOR_ID_2: 885 case RT5663_DIG_VOL_ZCD: 886 case RT5663_ANA_BIAS_CUR_1: 887 case RT5663_ANA_BIAS_CUR_2: 888 case RT5663_ANA_BIAS_CUR_3: 889 case RT5663_ANA_BIAS_CUR_4: 890 case RT5663_ANA_BIAS_CUR_5: 891 case RT5663_ANA_BIAS_CUR_6: 892 case RT5663_BIAS_CUR_5: 893 case RT5663_BIAS_CUR_6: 894 case RT5663_BIAS_CUR_7: 895 case RT5663_BIAS_CUR_8: 896 case RT5663_DACREF_LDO: 897 case RT5663_DUMMY_REG_3: 898 case RT5663_BIAS_CUR_9: 899 case RT5663_DUMMY_REG_4: 900 case RT5663_VREFADJ_OP: 901 case RT5663_VREF_RECMIX: 902 case RT5663_CHARGE_PUMP_1: 903 case RT5663_CHARGE_PUMP_1_2: 904 case RT5663_CHARGE_PUMP_1_3: 905 case RT5663_CHARGE_PUMP_2: 906 case RT5663_DIG_IN_PIN1: 907 case RT5663_PAD_DRV_CTL: 908 case RT5663_PLL_INT_REG: 909 case RT5663_CHOP_DAC_L: 910 case RT5663_CHOP_ADC: 911 case RT5663_CALIB_ADC: 912 case RT5663_CHOP_DAC_R: 913 case RT5663_DUMMY_CTL_DACLR: 914 case RT5663_DUMMY_REG_5: 915 case RT5663_SOFT_RAMP: 916 case RT5663_TEST_MODE_1: 917 case RT5663_TEST_MODE_2: 918 case RT5663_TEST_MODE_3: 919 case RT5663_STO_DRE_1: 920 case RT5663_STO_DRE_2: 921 case RT5663_STO_DRE_3: 922 case RT5663_STO_DRE_4: 923 case RT5663_STO_DRE_5: 924 case RT5663_STO_DRE_6: 925 case RT5663_STO_DRE_7: 926 case RT5663_STO_DRE_8: 927 case RT5663_STO_DRE_9: 928 case RT5663_STO_DRE_10: 929 case RT5663_MIC_DECRO_1: 930 case RT5663_MIC_DECRO_2: 931 case RT5663_MIC_DECRO_3: 932 case RT5663_MIC_DECRO_4: 933 case RT5663_MIC_DECRO_5: 934 case RT5663_MIC_DECRO_6: 935 case RT5663_HP_DECRO_1: 936 case RT5663_HP_DECRO_2: 937 case RT5663_HP_DECRO_3: 938 case RT5663_HP_DECRO_4: 939 case RT5663_HP_DECOUP: 940 case RT5663_HP_IMP_SEN_MAP8: 941 case RT5663_HP_IMP_SEN_MAP9: 942 case RT5663_HP_IMP_SEN_MAP10: 943 case RT5663_HP_IMP_SEN_MAP11: 944 case RT5663_HP_IMP_SEN_1: 945 case RT5663_HP_IMP_SEN_2: 946 case RT5663_HP_IMP_SEN_3: 947 case RT5663_HP_IMP_SEN_4: 948 case RT5663_HP_IMP_SEN_5: 949 case RT5663_HP_IMP_SEN_6: 950 case RT5663_HP_IMP_SEN_7: 951 case RT5663_HP_IMP_SEN_8: 952 case RT5663_HP_IMP_SEN_9: 953 case RT5663_HP_IMP_SEN_10: 954 case RT5663_HP_IMP_SEN_11: 955 case RT5663_HP_IMP_SEN_12: 956 case RT5663_HP_IMP_SEN_13: 957 case RT5663_HP_IMP_SEN_14: 958 case RT5663_HP_IMP_SEN_15: 959 case RT5663_HP_IMP_SEN_16: 960 case RT5663_HP_IMP_SEN_17: 961 case RT5663_HP_IMP_SEN_18: 962 case RT5663_HP_IMP_SEN_19: 963 case RT5663_HP_IMPSEN_DIG5: 964 case RT5663_HP_IMPSEN_MAP1: 965 case RT5663_HP_IMPSEN_MAP2: 966 case RT5663_HP_IMPSEN_MAP3: 967 case RT5663_HP_IMPSEN_MAP4: 968 case RT5663_HP_IMPSEN_MAP5: 969 case RT5663_HP_IMPSEN_MAP7: 970 case RT5663_HP_LOGIC_1: 971 case RT5663_HP_LOGIC_2: 972 case RT5663_HP_CALIB_1: 973 case RT5663_HP_CALIB_1_1: 974 case RT5663_HP_CALIB_2: 975 case RT5663_HP_CALIB_3: 976 case RT5663_HP_CALIB_4: 977 case RT5663_HP_CALIB_5: 978 case RT5663_HP_CALIB_5_1: 979 case RT5663_HP_CALIB_6: 980 case RT5663_HP_CALIB_7: 981 case RT5663_HP_CALIB_9: 982 case RT5663_HP_CALIB_10: 983 case RT5663_HP_CALIB_11: 984 case RT5663_HP_CALIB_ST1: 985 case RT5663_HP_CALIB_ST2: 986 case RT5663_HP_CALIB_ST3: 987 case RT5663_HP_CALIB_ST4: 988 case RT5663_HP_CALIB_ST5: 989 case RT5663_HP_CALIB_ST6: 990 case RT5663_HP_CALIB_ST7: 991 case RT5663_HP_CALIB_ST8: 992 case RT5663_HP_CALIB_ST9: 993 case RT5663_HP_AMP_DET: 994 case RT5663_DUMMY_REG_6: 995 case RT5663_HP_BIAS: 996 case RT5663_CBJ_1: 997 case RT5663_CBJ_2: 998 case RT5663_CBJ_3: 999 case RT5663_DUMMY_1: 1000 case RT5663_DUMMY_2: 1001 case RT5663_DUMMY_3: 1002 case RT5663_ANA_JD: 1003 case RT5663_ADC_LCH_LPF1_A1: 1004 case RT5663_ADC_RCH_LPF1_A1: 1005 case RT5663_ADC_LCH_LPF1_H0: 1006 case RT5663_ADC_RCH_LPF1_H0: 1007 case RT5663_ADC_LCH_BPF1_A1: 1008 case RT5663_ADC_RCH_BPF1_A1: 1009 case RT5663_ADC_LCH_BPF1_A2: 1010 case RT5663_ADC_RCH_BPF1_A2: 1011 case RT5663_ADC_LCH_BPF1_H0: 1012 case RT5663_ADC_RCH_BPF1_H0: 1013 case RT5663_ADC_LCH_BPF2_A1: 1014 case RT5663_ADC_RCH_BPF2_A1: 1015 case RT5663_ADC_LCH_BPF2_A2: 1016 case RT5663_ADC_RCH_BPF2_A2: 1017 case RT5663_ADC_LCH_BPF2_H0: 1018 case RT5663_ADC_RCH_BPF2_H0: 1019 case RT5663_ADC_LCH_BPF3_A1: 1020 case RT5663_ADC_RCH_BPF3_A1: 1021 case RT5663_ADC_LCH_BPF3_A2: 1022 case RT5663_ADC_RCH_BPF3_A2: 1023 case RT5663_ADC_LCH_BPF3_H0: 1024 case RT5663_ADC_RCH_BPF3_H0: 1025 case RT5663_ADC_LCH_BPF4_A1: 1026 case RT5663_ADC_RCH_BPF4_A1: 1027 case RT5663_ADC_LCH_BPF4_A2: 1028 case RT5663_ADC_RCH_BPF4_A2: 1029 case RT5663_ADC_LCH_BPF4_H0: 1030 case RT5663_ADC_RCH_BPF4_H0: 1031 case RT5663_ADC_LCH_HPF1_A1: 1032 case RT5663_ADC_RCH_HPF1_A1: 1033 case RT5663_ADC_LCH_HPF1_H0: 1034 case RT5663_ADC_RCH_HPF1_H0: 1035 case RT5663_ADC_EQ_PRE_VOL_L: 1036 case RT5663_ADC_EQ_PRE_VOL_R: 1037 case RT5663_ADC_EQ_POST_VOL_L: 1038 case RT5663_ADC_EQ_POST_VOL_R: 1039 return true; 1040 default: 1041 return false; 1042 } 1043 } 1044 1045 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg) 1046 { 1047 switch (reg) { 1048 case RT5663_RESET: 1049 case RT5663_CBJ_TYPE_2: 1050 case RT5663_PDM_OUT_CTL: 1051 case RT5663_PDM_I2C_DATA_CTL1: 1052 case RT5663_PDM_I2C_DATA_CTL4: 1053 case RT5663_ALC_BK_GAIN: 1054 case RT5663_PLL_2: 1055 case RT5663_MICBIAS_1: 1056 case RT5663_ADC_EQ_1: 1057 case RT5663_INT_ST_1: 1058 case RT5663_GPIO_STA2: 1059 case RT5663_IL_CMD_1: 1060 case RT5663_IL_CMD_5: 1061 case RT5663_A_JD_CTRL: 1062 case RT5663_JD_CTRL2: 1063 case RT5663_VENDOR_ID: 1064 case RT5663_VENDOR_ID_1: 1065 case RT5663_VENDOR_ID_2: 1066 case RT5663_STO_DRE_1: 1067 case RT5663_STO_DRE_5: 1068 case RT5663_STO_DRE_6: 1069 case RT5663_STO_DRE_7: 1070 case RT5663_MONO_DYNA_6: 1071 case RT5663_STO1_SIL_DET: 1072 case RT5663_MONOL_SIL_DET: 1073 case RT5663_MONOR_SIL_DET: 1074 case RT5663_STO2_DAC_SIL: 1075 case RT5663_MONO_AMP_CAL_ST1: 1076 case RT5663_MONO_AMP_CAL_ST2: 1077 case RT5663_MONO_AMP_CAL_ST3: 1078 case RT5663_MONO_AMP_CAL_ST4: 1079 case RT5663_HP_IMP_SEN_2: 1080 case RT5663_HP_IMP_SEN_3: 1081 case RT5663_HP_IMP_SEN_4: 1082 case RT5663_HP_IMP_SEN_10: 1083 case RT5663_HP_CALIB_1: 1084 case RT5663_HP_CALIB_10: 1085 case RT5663_HP_CALIB_ST1: 1086 case RT5663_HP_CALIB_ST4: 1087 case RT5663_HP_CALIB_ST5: 1088 case RT5663_HP_CALIB_ST6: 1089 case RT5663_HP_CALIB_ST7: 1090 case RT5663_HP_CALIB_ST8: 1091 case RT5663_HP_CALIB_ST9: 1092 case RT5663_HP_CALIB_ST10: 1093 case RT5663_HP_CALIB_ST11: 1094 return true; 1095 default: 1096 return false; 1097 } 1098 } 1099 1100 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg) 1101 { 1102 switch (reg) { 1103 case RT5663_LOUT_CTRL: 1104 case RT5663_HP_AMP_2: 1105 case RT5663_MONO_OUT: 1106 case RT5663_MONO_GAIN: 1107 case RT5663_AEC_BST: 1108 case RT5663_IN1_IN2: 1109 case RT5663_IN3_IN4: 1110 case RT5663_INL1_INR1: 1111 case RT5663_CBJ_TYPE_2: 1112 case RT5663_CBJ_TYPE_3: 1113 case RT5663_CBJ_TYPE_4: 1114 case RT5663_CBJ_TYPE_5: 1115 case RT5663_CBJ_TYPE_8: 1116 case RT5663_DAC3_DIG_VOL: 1117 case RT5663_DAC3_CTRL: 1118 case RT5663_MONO_ADC_DIG_VOL: 1119 case RT5663_STO2_ADC_DIG_VOL: 1120 case RT5663_MONO_ADC_BST_GAIN: 1121 case RT5663_STO2_ADC_BST_GAIN: 1122 case RT5663_SIDETONE_CTRL: 1123 case RT5663_MONO1_ADC_MIXER: 1124 case RT5663_STO2_ADC_MIXER: 1125 case RT5663_MONO_DAC_MIXER: 1126 case RT5663_DAC2_SRC_CTRL: 1127 case RT5663_IF_3_4_DATA_CTL: 1128 case RT5663_IF_5_DATA_CTL: 1129 case RT5663_PDM_OUT_CTL: 1130 case RT5663_PDM_I2C_DATA_CTL1: 1131 case RT5663_PDM_I2C_DATA_CTL2: 1132 case RT5663_PDM_I2C_DATA_CTL3: 1133 case RT5663_PDM_I2C_DATA_CTL4: 1134 case RT5663_RECMIX1_NEW: 1135 case RT5663_RECMIX1L_0: 1136 case RT5663_RECMIX1L: 1137 case RT5663_RECMIX1R_0: 1138 case RT5663_RECMIX1R: 1139 case RT5663_RECMIX2_NEW: 1140 case RT5663_RECMIX2_L_2: 1141 case RT5663_RECMIX2_R: 1142 case RT5663_RECMIX2_R_2: 1143 case RT5663_CALIB_REC_LR: 1144 case RT5663_ALC_BK_GAIN: 1145 case RT5663_MONOMIX_GAIN: 1146 case RT5663_MONOMIX_IN_GAIN: 1147 case RT5663_OUT_MIXL_GAIN: 1148 case RT5663_OUT_LMIX_IN_GAIN: 1149 case RT5663_OUT_RMIX_IN_GAIN: 1150 case RT5663_OUT_RMIX_IN_GAIN1: 1151 case RT5663_LOUT_MIXER_CTRL: 1152 case RT5663_PWR_VOL: 1153 case RT5663_ADCDAC_RST: 1154 case RT5663_I2S34_SDP: 1155 case RT5663_I2S5_SDP: 1156 case RT5663_TDM_6: 1157 case RT5663_TDM_7: 1158 case RT5663_TDM_8: 1159 case RT5663_TDM_9: 1160 case RT5663_ASRC_3: 1161 case RT5663_ASRC_6: 1162 case RT5663_ASRC_7: 1163 case RT5663_PLL_TRK_13: 1164 case RT5663_I2S_M_CLK_CTL: 1165 case RT5663_FDIV_I2S34_M_CLK: 1166 case RT5663_FDIV_I2S34_M_CLK2: 1167 case RT5663_FDIV_I2S5_M_CLK: 1168 case RT5663_FDIV_I2S5_M_CLK2: 1169 case RT5663_V2_IRQ_4: 1170 case RT5663_GPIO_3: 1171 case RT5663_GPIO_4: 1172 case RT5663_GPIO_STA2: 1173 case RT5663_HP_AMP_DET1: 1174 case RT5663_HP_AMP_DET2: 1175 case RT5663_HP_AMP_DET3: 1176 case RT5663_MID_BD_HP_AMP: 1177 case RT5663_LOW_BD_HP_AMP: 1178 case RT5663_SOF_VOL_ZC2: 1179 case RT5663_ADC_STO2_ADJ1: 1180 case RT5663_ADC_STO2_ADJ2: 1181 case RT5663_A_JD_CTRL: 1182 case RT5663_JD1_TRES_CTRL: 1183 case RT5663_JD2_TRES_CTRL: 1184 case RT5663_V2_JD_CTRL2: 1185 case RT5663_DUM_REG_2: 1186 case RT5663_DUM_REG_3: 1187 case RT5663_VENDOR_ID: 1188 case RT5663_VENDOR_ID_1: 1189 case RT5663_VENDOR_ID_2: 1190 case RT5663_DACADC_DIG_VOL2: 1191 case RT5663_DIG_IN_PIN2: 1192 case RT5663_PAD_DRV_CTL1: 1193 case RT5663_SOF_RAM_DEPOP: 1194 case RT5663_VOL_TEST: 1195 case RT5663_TEST_MODE_4: 1196 case RT5663_TEST_MODE_5: 1197 case RT5663_STO_DRE_9: 1198 case RT5663_MONO_DYNA_1: 1199 case RT5663_MONO_DYNA_2: 1200 case RT5663_MONO_DYNA_3: 1201 case RT5663_MONO_DYNA_4: 1202 case RT5663_MONO_DYNA_5: 1203 case RT5663_MONO_DYNA_6: 1204 case RT5663_STO1_SIL_DET: 1205 case RT5663_MONOL_SIL_DET: 1206 case RT5663_MONOR_SIL_DET: 1207 case RT5663_STO2_DAC_SIL: 1208 case RT5663_PWR_SAV_CTL1: 1209 case RT5663_PWR_SAV_CTL2: 1210 case RT5663_PWR_SAV_CTL3: 1211 case RT5663_PWR_SAV_CTL4: 1212 case RT5663_PWR_SAV_CTL5: 1213 case RT5663_PWR_SAV_CTL6: 1214 case RT5663_MONO_AMP_CAL1: 1215 case RT5663_MONO_AMP_CAL2: 1216 case RT5663_MONO_AMP_CAL3: 1217 case RT5663_MONO_AMP_CAL4: 1218 case RT5663_MONO_AMP_CAL5: 1219 case RT5663_MONO_AMP_CAL6: 1220 case RT5663_MONO_AMP_CAL7: 1221 case RT5663_MONO_AMP_CAL_ST1: 1222 case RT5663_MONO_AMP_CAL_ST2: 1223 case RT5663_MONO_AMP_CAL_ST3: 1224 case RT5663_MONO_AMP_CAL_ST4: 1225 case RT5663_MONO_AMP_CAL_ST5: 1226 case RT5663_V2_HP_IMP_SEN_13: 1227 case RT5663_V2_HP_IMP_SEN_14: 1228 case RT5663_V2_HP_IMP_SEN_6: 1229 case RT5663_V2_HP_IMP_SEN_7: 1230 case RT5663_V2_HP_IMP_SEN_8: 1231 case RT5663_V2_HP_IMP_SEN_9: 1232 case RT5663_V2_HP_IMP_SEN_10: 1233 case RT5663_HP_LOGIC_3: 1234 case RT5663_HP_CALIB_ST10: 1235 case RT5663_HP_CALIB_ST11: 1236 case RT5663_PRO_REG_TBL_4: 1237 case RT5663_PRO_REG_TBL_5: 1238 case RT5663_PRO_REG_TBL_6: 1239 case RT5663_PRO_REG_TBL_7: 1240 case RT5663_PRO_REG_TBL_8: 1241 case RT5663_PRO_REG_TBL_9: 1242 case RT5663_SAR_ADC_INL_1: 1243 case RT5663_SAR_ADC_INL_2: 1244 case RT5663_SAR_ADC_INL_3: 1245 case RT5663_SAR_ADC_INL_4: 1246 case RT5663_SAR_ADC_INL_5: 1247 case RT5663_SAR_ADC_INL_6: 1248 case RT5663_SAR_ADC_INL_7: 1249 case RT5663_SAR_ADC_INL_8: 1250 case RT5663_SAR_ADC_INL_9: 1251 case RT5663_SAR_ADC_INL_10: 1252 case RT5663_SAR_ADC_INL_11: 1253 case RT5663_SAR_ADC_INL_12: 1254 case RT5663_DRC_CTRL_1: 1255 case RT5663_DRC1_CTRL_2: 1256 case RT5663_DRC1_CTRL_3: 1257 case RT5663_DRC1_CTRL_4: 1258 case RT5663_DRC1_CTRL_5: 1259 case RT5663_DRC1_CTRL_6: 1260 case RT5663_DRC1_HD_CTRL_1: 1261 case RT5663_DRC1_HD_CTRL_2: 1262 case RT5663_DRC1_PRI_REG_1: 1263 case RT5663_DRC1_PRI_REG_2: 1264 case RT5663_DRC1_PRI_REG_3: 1265 case RT5663_DRC1_PRI_REG_4: 1266 case RT5663_DRC1_PRI_REG_5: 1267 case RT5663_DRC1_PRI_REG_6: 1268 case RT5663_DRC1_PRI_REG_7: 1269 case RT5663_DRC1_PRI_REG_8: 1270 case RT5663_ALC_PGA_CTL_1: 1271 case RT5663_ALC_PGA_CTL_2: 1272 case RT5663_ALC_PGA_CTL_3: 1273 case RT5663_ALC_PGA_CTL_4: 1274 case RT5663_ALC_PGA_CTL_5: 1275 case RT5663_ALC_PGA_CTL_6: 1276 case RT5663_ALC_PGA_CTL_7: 1277 case RT5663_ALC_PGA_CTL_8: 1278 case RT5663_ALC_PGA_REG_1: 1279 case RT5663_ALC_PGA_REG_2: 1280 case RT5663_ALC_PGA_REG_3: 1281 case RT5663_ADC_EQ_RECOV_1: 1282 case RT5663_ADC_EQ_RECOV_2: 1283 case RT5663_ADC_EQ_RECOV_3: 1284 case RT5663_ADC_EQ_RECOV_4: 1285 case RT5663_ADC_EQ_RECOV_5: 1286 case RT5663_ADC_EQ_RECOV_6: 1287 case RT5663_ADC_EQ_RECOV_7: 1288 case RT5663_ADC_EQ_RECOV_8: 1289 case RT5663_ADC_EQ_RECOV_9: 1290 case RT5663_ADC_EQ_RECOV_10: 1291 case RT5663_ADC_EQ_RECOV_11: 1292 case RT5663_ADC_EQ_RECOV_12: 1293 case RT5663_ADC_EQ_RECOV_13: 1294 case RT5663_VID_HIDDEN: 1295 case RT5663_VID_CUSTOMER: 1296 case RT5663_SCAN_MODE: 1297 case RT5663_I2C_BYPA: 1298 return true; 1299 case RT5663_TDM_1: 1300 case RT5663_DEPOP_3: 1301 case RT5663_ASRC_11_2: 1302 case RT5663_INT_ST_2: 1303 case RT5663_GPIO_STA1: 1304 case RT5663_SIN_GEN_1: 1305 case RT5663_SIN_GEN_2: 1306 case RT5663_SIN_GEN_3: 1307 case RT5663_IL_CMD_PWRSAV1: 1308 case RT5663_IL_CMD_PWRSAV2: 1309 case RT5663_EM_JACK_TYPE_1: 1310 case RT5663_EM_JACK_TYPE_2: 1311 case RT5663_EM_JACK_TYPE_3: 1312 case RT5663_EM_JACK_TYPE_4: 1313 case RT5663_FAST_OFF_MICBIAS: 1314 case RT5663_ANA_BIAS_CUR_1: 1315 case RT5663_ANA_BIAS_CUR_2: 1316 case RT5663_BIAS_CUR_9: 1317 case RT5663_DUMMY_REG_4: 1318 case RT5663_VREF_RECMIX: 1319 case RT5663_CHARGE_PUMP_1_2: 1320 case RT5663_CHARGE_PUMP_1_3: 1321 case RT5663_CHARGE_PUMP_2: 1322 case RT5663_CHOP_DAC_R: 1323 case RT5663_DUMMY_CTL_DACLR: 1324 case RT5663_DUMMY_REG_5: 1325 case RT5663_SOFT_RAMP: 1326 case RT5663_TEST_MODE_1: 1327 case RT5663_STO_DRE_10: 1328 case RT5663_MIC_DECRO_1: 1329 case RT5663_MIC_DECRO_2: 1330 case RT5663_MIC_DECRO_3: 1331 case RT5663_MIC_DECRO_4: 1332 case RT5663_MIC_DECRO_5: 1333 case RT5663_MIC_DECRO_6: 1334 case RT5663_HP_DECRO_1: 1335 case RT5663_HP_DECRO_2: 1336 case RT5663_HP_DECRO_3: 1337 case RT5663_HP_DECRO_4: 1338 case RT5663_HP_DECOUP: 1339 case RT5663_HP_IMPSEN_MAP4: 1340 case RT5663_HP_IMPSEN_MAP5: 1341 case RT5663_HP_IMPSEN_MAP7: 1342 case RT5663_HP_CALIB_1: 1343 case RT5663_CBJ_1: 1344 case RT5663_CBJ_2: 1345 case RT5663_CBJ_3: 1346 return false; 1347 default: 1348 return rt5663_readable_register(dev, reg); 1349 } 1350 } 1351 1352 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0); 1353 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0); 1354 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 1355 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 1356 1357 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 1358 static const DECLARE_TLV_DB_RANGE(in_bst_tlv, 1359 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 1360 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 1361 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 1362 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 1363 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 1364 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 1365 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 1366 ); 1367 1368 /* Interface data select */ 1369 static const char * const rt5663_if1_adc_data_select[] = { 1370 "L/R", "R/L", "L/L", "R/R" 1371 }; 1372 1373 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2, 1374 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select); 1375 1376 static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec, 1377 bool enable) 1378 { 1379 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1380 1381 if (enable) { 1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1383 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN); 1384 /* reset in-line command */ 1385 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1386 RT5663_RESET_4BTN_INL_MASK, 1387 RT5663_RESET_4BTN_INL_RESET); 1388 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1389 RT5663_RESET_4BTN_INL_MASK, 1390 RT5663_RESET_4BTN_INL_NOR); 1391 switch (rt5663->codec_ver) { 1392 case CODEC_VER_1: 1393 snd_soc_update_bits(codec, RT5663_IRQ_3, 1394 RT5663_V2_EN_IRQ_INLINE_MASK, 1395 RT5663_V2_EN_IRQ_INLINE_NOR); 1396 break; 1397 case CODEC_VER_0: 1398 snd_soc_update_bits(codec, RT5663_IRQ_2, 1399 RT5663_EN_IRQ_INLINE_MASK, 1400 RT5663_EN_IRQ_INLINE_NOR); 1401 break; 1402 default: 1403 dev_err(codec->dev, "Unknown CODEC Version\n"); 1404 } 1405 } else { 1406 switch (rt5663->codec_ver) { 1407 case CODEC_VER_1: 1408 snd_soc_update_bits(codec, RT5663_IRQ_3, 1409 RT5663_V2_EN_IRQ_INLINE_MASK, 1410 RT5663_V2_EN_IRQ_INLINE_BYP); 1411 break; 1412 case CODEC_VER_0: 1413 snd_soc_update_bits(codec, RT5663_IRQ_2, 1414 RT5663_EN_IRQ_INLINE_MASK, 1415 RT5663_EN_IRQ_INLINE_BYP); 1416 break; 1417 default: 1418 dev_err(codec->dev, "Unknown CODEC Version\n"); 1419 } 1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1421 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS); 1422 /* reset in-line command */ 1423 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1424 RT5663_RESET_4BTN_INL_MASK, 1425 RT5663_RESET_4BTN_INL_RESET); 1426 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1427 RT5663_RESET_4BTN_INL_MASK, 1428 RT5663_RESET_4BTN_INL_NOR); 1429 } 1430 } 1431 1432 /** 1433 * rt5663_v2_jack_detect - Detect headset. 1434 * @codec: SoC audio codec device. 1435 * @jack_insert: Jack insert or not. 1436 * 1437 * Detect whether is headset or not when jack inserted. 1438 * 1439 * Returns detect status. 1440 */ 1441 1442 static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert) 1443 { 1444 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1445 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1446 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; 1447 1448 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1449 if (jack_insert) { 1450 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040); 1451 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484); 1452 1453 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 1454 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 1455 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 1456 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 1457 snd_soc_dapm_sync(dapm); 1458 snd_soc_update_bits(codec, RT5663_RC_CLK, 1459 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN); 1460 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8); 1461 1462 while (i < 5) { 1463 msleep(sleep_time[i]); 1464 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003; 1465 if (val == 0x1 || val == 0x2 || val == 0x3) 1466 break; 1467 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n", 1468 __func__, val, sleep_time[i]); 1469 i++; 1470 } 1471 dev_dbg(codec->dev, "%s val = %d\n", __func__, val); 1472 switch (val) { 1473 case 1: 1474 case 2: 1475 rt5663->jack_type = SND_JACK_HEADSET; 1476 rt5663_enable_push_button_irq(codec, true); 1477 break; 1478 default: 1479 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1480 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1481 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1482 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1483 snd_soc_dapm_sync(dapm); 1484 rt5663->jack_type = SND_JACK_HEADPHONE; 1485 break; 1486 } 1487 } else { 1488 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0); 1489 1490 if (rt5663->jack_type == SND_JACK_HEADSET) { 1491 rt5663_enable_push_button_irq(codec, false); 1492 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1493 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1494 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1495 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1496 snd_soc_dapm_sync(dapm); 1497 } 1498 rt5663->jack_type = 0; 1499 } 1500 1501 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type); 1502 return rt5663->jack_type; 1503 } 1504 1505 /** 1506 * rt5663_jack_detect - Detect headset. 1507 * @codec: SoC audio codec device. 1508 * @jack_insert: Jack insert or not. 1509 * 1510 * Detect whether is headset or not when jack inserted. 1511 * 1512 * Returns detect status. 1513 */ 1514 static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert) 1515 { 1516 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1517 int val, i = 0; 1518 1519 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1520 1521 if (jack_insert) { 1522 snd_soc_update_bits(codec, RT5663_DIG_MISC, 1523 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 1524 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 1525 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK | 1526 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN | 1527 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS); 1528 snd_soc_update_bits(codec, RT5663_DUMMY_1, 1529 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK | 1530 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN | 1531 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1); 1532 snd_soc_update_bits(codec, RT5663_CBJ_1, 1533 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK, 1534 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L); 1535 snd_soc_update_bits(codec, RT5663_IL_CMD_2, 1536 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON); 1537 /* BST1 power on for JD */ 1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 1539 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON); 1540 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1, 1541 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK | 1542 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN | 1543 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN); 1544 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 1545 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK | 1546 RT5663_AMP_HP_MASK, RT5663_PWR_MB | 1547 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 1548 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK, 1549 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN); 1550 snd_soc_update_bits(codec, RT5663_IRQ_1, 1551 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 1552 1553 while (true) { 1554 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val); 1555 if (!(val & 0x80)) 1556 usleep_range(10000, 10005); 1557 else 1558 break; 1559 1560 if (i > 200) 1561 break; 1562 i++; 1563 } 1564 1565 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003; 1566 dev_dbg(codec->dev, "%s val = %d\n", __func__, val); 1567 1568 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 1569 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK, 1570 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN); 1571 1572 switch (val) { 1573 case 1: 1574 case 2: 1575 rt5663->jack_type = SND_JACK_HEADSET; 1576 rt5663_enable_push_button_irq(codec, true); 1577 1578 if (rt5663->pdata.dc_offset_l_manual_mic) { 1579 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, 1580 rt5663->pdata.dc_offset_l_manual_mic >> 1581 16); 1582 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3, 1583 rt5663->pdata.dc_offset_l_manual_mic & 1584 0xffff); 1585 } 1586 1587 if (rt5663->pdata.dc_offset_r_manual_mic) { 1588 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5, 1589 rt5663->pdata.dc_offset_r_manual_mic >> 1590 16); 1591 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6, 1592 rt5663->pdata.dc_offset_r_manual_mic & 1593 0xffff); 1594 } 1595 break; 1596 default: 1597 rt5663->jack_type = SND_JACK_HEADPHONE; 1598 1599 if (rt5663->pdata.dc_offset_l_manual) { 1600 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, 1601 rt5663->pdata.dc_offset_l_manual >> 16); 1602 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3, 1603 rt5663->pdata.dc_offset_l_manual & 1604 0xffff); 1605 } 1606 1607 if (rt5663->pdata.dc_offset_r_manual) { 1608 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5, 1609 rt5663->pdata.dc_offset_r_manual >> 16); 1610 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6, 1611 rt5663->pdata.dc_offset_r_manual & 1612 0xffff); 1613 } 1614 break; 1615 } 1616 } else { 1617 if (rt5663->jack_type == SND_JACK_HEADSET) 1618 rt5663_enable_push_button_irq(codec, false); 1619 rt5663->jack_type = 0; 1620 } 1621 1622 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type); 1623 return rt5663->jack_type; 1624 } 1625 1626 static int rt5663_button_detect(struct snd_soc_codec *codec) 1627 { 1628 int btn_type, val; 1629 1630 val = snd_soc_read(codec, RT5663_IL_CMD_5); 1631 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val); 1632 btn_type = val & 0xfff0; 1633 snd_soc_write(codec, RT5663_IL_CMD_5, val); 1634 1635 return btn_type; 1636 } 1637 1638 static irqreturn_t rt5663_irq(int irq, void *data) 1639 { 1640 struct rt5663_priv *rt5663 = data; 1641 1642 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__); 1643 1644 queue_delayed_work(system_wq, &rt5663->jack_detect_work, 1645 msecs_to_jiffies(250)); 1646 1647 return IRQ_HANDLED; 1648 } 1649 1650 int rt5663_set_jack_detect(struct snd_soc_codec *codec, 1651 struct snd_soc_jack *hs_jack) 1652 { 1653 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1654 1655 rt5663->hs_jack = hs_jack; 1656 1657 rt5663_irq(0, rt5663); 1658 1659 return 0; 1660 } 1661 EXPORT_SYMBOL_GPL(rt5663_set_jack_detect); 1662 1663 static bool rt5663_check_jd_status(struct snd_soc_codec *codec) 1664 { 1665 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1666 int val = snd_soc_read(codec, RT5663_INT_ST_1); 1667 1668 dev_dbg(codec->dev, "%s val=%x\n", __func__, val); 1669 1670 /* JD1 */ 1671 switch (rt5663->codec_ver) { 1672 case CODEC_VER_1: 1673 return !(val & 0x2000); 1674 case CODEC_VER_0: 1675 return !(val & 0x1000); 1676 default: 1677 dev_err(codec->dev, "Unknown CODEC Version\n"); 1678 } 1679 1680 return false; 1681 } 1682 1683 static void rt5663_jack_detect_work(struct work_struct *work) 1684 { 1685 struct rt5663_priv *rt5663 = 1686 container_of(work, struct rt5663_priv, jack_detect_work.work); 1687 struct snd_soc_codec *codec = rt5663->codec; 1688 int btn_type, report = 0; 1689 1690 if (!codec) 1691 return; 1692 1693 if (rt5663_check_jd_status(codec)) { 1694 /* jack in */ 1695 if (rt5663->jack_type == 0) { 1696 /* jack was out, report jack type */ 1697 switch (rt5663->codec_ver) { 1698 case CODEC_VER_1: 1699 report = rt5663_v2_jack_detect( 1700 rt5663->codec, 1); 1701 break; 1702 case CODEC_VER_0: 1703 report = rt5663_jack_detect(rt5663->codec, 1); 1704 break; 1705 default: 1706 dev_err(codec->dev, "Unknown CODEC Version\n"); 1707 } 1708 1709 /* Delay the jack insert report to avoid pop noise */ 1710 msleep(30); 1711 } else { 1712 /* jack is already in, report button event */ 1713 report = SND_JACK_HEADSET; 1714 btn_type = rt5663_button_detect(rt5663->codec); 1715 /** 1716 * rt5663 can report three kinds of button behavior, 1717 * one click, double click and hold. However, 1718 * currently we will report button pressed/released 1719 * event. So all the three button behaviors are 1720 * treated as button pressed. 1721 */ 1722 switch (btn_type) { 1723 case 0x8000: 1724 case 0x4000: 1725 case 0x2000: 1726 report |= SND_JACK_BTN_0; 1727 break; 1728 case 0x1000: 1729 case 0x0800: 1730 case 0x0400: 1731 report |= SND_JACK_BTN_1; 1732 break; 1733 case 0x0200: 1734 case 0x0100: 1735 case 0x0080: 1736 report |= SND_JACK_BTN_2; 1737 break; 1738 case 0x0040: 1739 case 0x0020: 1740 case 0x0010: 1741 report |= SND_JACK_BTN_3; 1742 break; 1743 case 0x0000: /* unpressed */ 1744 break; 1745 default: 1746 btn_type = 0; 1747 dev_err(rt5663->codec->dev, 1748 "Unexpected button code 0x%04x\n", 1749 btn_type); 1750 break; 1751 } 1752 /* button release or spurious interrput*/ 1753 if (btn_type == 0) 1754 report = rt5663->jack_type; 1755 } 1756 } else { 1757 /* jack out */ 1758 switch (rt5663->codec_ver) { 1759 case CODEC_VER_1: 1760 report = rt5663_v2_jack_detect(rt5663->codec, 0); 1761 break; 1762 case CODEC_VER_0: 1763 report = rt5663_jack_detect(rt5663->codec, 0); 1764 break; 1765 default: 1766 dev_err(codec->dev, "Unknown CODEC Version\n"); 1767 } 1768 } 1769 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report); 1770 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET | 1771 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1772 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1773 } 1774 1775 static const struct snd_kcontrol_new rt5663_snd_controls[] = { 1776 /* DAC Digital Volume */ 1777 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL, 1778 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1, 1779 87, 0, dac_vol_tlv), 1780 /* ADC Digital Volume Control */ 1781 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL, 1782 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1), 1783 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL, 1784 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1, 1785 63, 0, adc_vol_tlv), 1786 }; 1787 1788 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = { 1789 /* Headphone Output Volume */ 1790 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE, 1791 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1, 1792 rt5663_v2_hp_vol_tlv), 1793 /* Mic Boost Volume */ 1794 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST, 1795 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv), 1796 }; 1797 1798 static const struct snd_kcontrol_new rt5663_specific_controls[] = { 1799 /* Headphone Output Volume */ 1800 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9, 1801 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1, 1802 rt5663_hp_vol_tlv), 1803 /* Mic Boost Volume*/ 1804 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2, 1805 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv), 1806 /* Data Swap for Slot0/1 in ADCDAT1 */ 1807 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum), 1808 }; 1809 1810 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, 1811 struct snd_soc_dapm_widget *sink) 1812 { 1813 unsigned int val; 1814 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1815 1816 val = snd_soc_read(codec, RT5663_GLB_CLK); 1817 val &= RT5663_SCLK_SRC_MASK; 1818 if (val == RT5663_SCLK_SRC_PLL1) 1819 return 1; 1820 else 1821 return 0; 1822 } 1823 1824 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w, 1825 struct snd_soc_dapm_widget *sink) 1826 { 1827 unsigned int reg, shift, val; 1828 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1829 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1830 1831 if (rt5663->codec_ver == CODEC_VER_1) { 1832 switch (w->shift) { 1833 case RT5663_ADC_STO1_ASRC_SHIFT: 1834 reg = RT5663_ASRC_3; 1835 shift = RT5663_V2_AD_STO1_TRACK_SHIFT; 1836 break; 1837 case RT5663_DAC_STO1_ASRC_SHIFT: 1838 reg = RT5663_ASRC_2; 1839 shift = RT5663_DA_STO1_TRACK_SHIFT; 1840 break; 1841 default: 1842 return 0; 1843 } 1844 } else { 1845 switch (w->shift) { 1846 case RT5663_ADC_STO1_ASRC_SHIFT: 1847 reg = RT5663_ASRC_2; 1848 shift = RT5663_AD_STO1_TRACK_SHIFT; 1849 break; 1850 case RT5663_DAC_STO1_ASRC_SHIFT: 1851 reg = RT5663_ASRC_2; 1852 shift = RT5663_DA_STO1_TRACK_SHIFT; 1853 break; 1854 default: 1855 return 0; 1856 } 1857 } 1858 1859 val = (snd_soc_read(codec, reg) >> shift) & 0x7; 1860 1861 if (val) 1862 return 1; 1863 1864 return 0; 1865 } 1866 1867 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source, 1868 struct snd_soc_dapm_widget *sink) 1869 { 1870 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 1871 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1872 int da_asrc_en, ad_asrc_en; 1873 1874 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) & 1875 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0; 1876 switch (rt5663->codec_ver) { 1877 case CODEC_VER_1: 1878 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) & 1879 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0; 1880 break; 1881 case CODEC_VER_0: 1882 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) & 1883 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0; 1884 break; 1885 default: 1886 dev_err(codec->dev, "Unknown CODEC Version\n"); 1887 return 1; 1888 } 1889 1890 if (da_asrc_en || ad_asrc_en) 1891 if (rt5663->sysclk > rt5663->lrck * 384) 1892 return 1; 1893 1894 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n"); 1895 1896 return 0; 1897 } 1898 1899 /** 1900 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters 1901 * @codec: SoC audio codec device. 1902 * @filter_mask: mask of filters. 1903 * @clk_src: clock source 1904 * 1905 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can 1906 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1907 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1908 * ASRC function will track i2s clock and generate a corresponding system clock 1909 * for codec. This function provides an API to select the clock source for a 1910 * set of filters specified by the mask. And the codec driver will turn on ASRC 1911 * for these filters if ASRC is selected as their clock source. 1912 */ 1913 int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec, 1914 unsigned int filter_mask, unsigned int clk_src) 1915 { 1916 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1917 unsigned int asrc2_mask = 0; 1918 unsigned int asrc2_value = 0; 1919 unsigned int asrc3_mask = 0; 1920 unsigned int asrc3_value = 0; 1921 1922 switch (clk_src) { 1923 case RT5663_CLK_SEL_SYS: 1924 case RT5663_CLK_SEL_I2S1_ASRC: 1925 break; 1926 1927 default: 1928 return -EINVAL; 1929 } 1930 1931 if (filter_mask & RT5663_DA_STEREO_FILTER) { 1932 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK; 1933 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT; 1934 } 1935 1936 if (filter_mask & RT5663_AD_STEREO_FILTER) { 1937 switch (rt5663->codec_ver) { 1938 case CODEC_VER_1: 1939 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK; 1940 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT; 1941 break; 1942 case CODEC_VER_0: 1943 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK; 1944 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT; 1945 break; 1946 default: 1947 dev_err(codec->dev, "Unknown CODEC Version\n"); 1948 } 1949 } 1950 1951 if (asrc2_mask) 1952 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask, 1953 asrc2_value); 1954 1955 if (asrc3_mask) 1956 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask, 1957 asrc3_value); 1958 1959 return 0; 1960 } 1961 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src); 1962 1963 /* Analog Mixer */ 1964 static const struct snd_kcontrol_new rt5663_recmix1l[] = { 1965 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L, 1966 RT5663_RECMIX1L_BST2_SHIFT, 1, 1), 1967 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L, 1968 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1), 1969 }; 1970 1971 static const struct snd_kcontrol_new rt5663_recmix1r[] = { 1972 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R, 1973 RT5663_RECMIX1R_BST2_SHIFT, 1, 1), 1974 }; 1975 1976 /* Digital Mixer */ 1977 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = { 1978 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 1979 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1), 1980 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 1981 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1), 1982 }; 1983 1984 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = { 1985 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 1986 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1), 1987 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 1988 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1), 1989 }; 1990 1991 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = { 1992 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER, 1993 RT5663_M_ADCMIX_L_SHIFT, 1, 1), 1994 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER, 1995 RT5663_M_DAC1_L_SHIFT, 1, 1), 1996 }; 1997 1998 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = { 1999 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER, 2000 RT5663_M_ADCMIX_R_SHIFT, 1, 1), 2001 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER, 2002 RT5663_M_DAC1_R_SHIFT, 1, 1), 2003 }; 2004 2005 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = { 2006 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER, 2007 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1), 2008 }; 2009 2010 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = { 2011 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER, 2012 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1), 2013 }; 2014 2015 /* Out Switch */ 2016 static const struct snd_kcontrol_new rt5663_hpo_switch = 2017 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2, 2018 RT5663_EN_DAC_HPO_SHIFT, 1, 0); 2019 2020 /* Stereo ADC source */ 2021 static const char * const rt5663_sto1_adc_src[] = { 2022 "ADC L", "ADC R" 2023 }; 2024 2025 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER, 2026 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src); 2027 2028 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux = 2029 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum); 2030 2031 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER, 2032 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src); 2033 2034 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux = 2035 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum); 2036 2037 /* RT5663: Analog DACL1 input source */ 2038 static const char * const rt5663_alg_dacl_src[] = { 2039 "DAC L", "STO DAC MIXL" 2040 }; 2041 2042 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC, 2043 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src); 2044 2045 static const struct snd_kcontrol_new rt5663_alg_dacl_mux = 2046 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum); 2047 2048 /* RT5663: Analog DACR1 input source */ 2049 static const char * const rt5663_alg_dacr_src[] = { 2050 "DAC R", "STO DAC MIXR" 2051 }; 2052 2053 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC, 2054 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src); 2055 2056 static const struct snd_kcontrol_new rt5663_alg_dacr_mux = 2057 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum); 2058 2059 static int rt5663_hp_event(struct snd_soc_dapm_widget *w, 2060 struct snd_kcontrol *kcontrol, int event) 2061 { 2062 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2063 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2064 2065 switch (event) { 2066 case SND_SOC_DAPM_POST_PMU: 2067 if (rt5663->codec_ver == CODEC_VER_1) { 2068 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2069 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH); 2070 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2, 2071 RT5663_HP_SIG_SRC1_MASK, 2072 RT5663_HP_SIG_SRC1_SILENCE); 2073 } else { 2074 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003); 2075 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2076 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS); 2077 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371); 2078 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba); 2079 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224); 2080 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766); 2081 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa); 2082 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777); 2083 snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000, 2084 0x8000); 2085 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 2086 0x3000); 2087 } 2088 break; 2089 2090 case SND_SOC_DAPM_PRE_PMD: 2091 if (rt5663->codec_ver == CODEC_VER_1) { 2092 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2, 2093 RT5663_HP_SIG_SRC1_MASK, 2094 RT5663_HP_SIG_SRC1_REG); 2095 } else { 2096 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0); 2097 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2098 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN); 2099 } 2100 break; 2101 2102 default: 2103 return 0; 2104 } 2105 2106 return 0; 2107 } 2108 2109 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w, 2110 struct snd_kcontrol *kcontrol, int event) 2111 { 2112 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2113 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2114 2115 switch (event) { 2116 case SND_SOC_DAPM_PRE_PMU: 2117 if (rt5663->codec_ver == CODEC_VER_0) { 2118 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 2119 0x0030); 2120 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 2121 0x0003); 2122 } 2123 break; 2124 2125 case SND_SOC_DAPM_POST_PMD: 2126 if (rt5663->codec_ver == CODEC_VER_0) { 2127 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0); 2128 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0); 2129 } 2130 break; 2131 2132 default: 2133 return 0; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w, 2140 struct snd_kcontrol *kcontrol, int event) 2141 { 2142 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2143 2144 switch (event) { 2145 case SND_SOC_DAPM_POST_PMU: 2146 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 2147 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 2148 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP); 2149 break; 2150 2151 case SND_SOC_DAPM_PRE_PMD: 2152 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 2153 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0); 2154 break; 2155 2156 default: 2157 return 0; 2158 } 2159 2160 return 0; 2161 } 2162 2163 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w, 2164 struct snd_kcontrol *kcontrol, int event) 2165 { 2166 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2167 2168 switch (event) { 2169 case SND_SOC_DAPM_POST_PMU: 2170 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00); 2171 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc); 2172 break; 2173 2174 case SND_SOC_DAPM_PRE_PMD: 2175 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000); 2176 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000); 2177 break; 2178 2179 default: 2180 return 0; 2181 } 2182 2183 return 0; 2184 } 2185 2186 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = { 2187 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0, 2188 NULL, 0), 2189 2190 /* micbias */ 2191 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2, 2192 RT5663_PWR_MB1_SHIFT, 0), 2193 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2, 2194 RT5663_PWR_MB2_SHIFT, 0), 2195 2196 /* Input Lines */ 2197 SND_SOC_DAPM_INPUT("IN1P"), 2198 SND_SOC_DAPM_INPUT("IN1N"), 2199 2200 /* REC Mixer Power */ 2201 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2, 2202 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0), 2203 2204 /* ADCs */ 2205 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2206 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1, 2207 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0), 2208 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC, 2209 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0), 2210 2211 /* ADC Mixer */ 2212 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM, 2213 0, 0, rt5663_sto1_adc_l_mix, 2214 ARRAY_SIZE(rt5663_sto1_adc_l_mix)), 2215 2216 /* ADC Filter Power */ 2217 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2, 2218 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0), 2219 2220 /* Digital Interface */ 2221 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0, 2222 NULL, 0), 2223 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2224 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2225 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2226 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2227 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2228 2229 /* Audio Interface */ 2230 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 2231 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0), 2232 2233 /* DAC mixer before sound effect */ 2234 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix, 2235 ARRAY_SIZE(rt5663_adda_l_mix)), 2236 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix, 2237 ARRAY_SIZE(rt5663_adda_r_mix)), 2238 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2239 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0), 2240 2241 /* DAC Mixer */ 2242 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2, 2243 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0), 2244 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0, 2245 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)), 2246 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0, 2247 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)), 2248 2249 /* DACs */ 2250 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1, 2251 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0), 2252 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1, 2253 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0), 2254 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0), 2255 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0), 2256 2257 /* Headphone*/ 2258 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0, 2259 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU | 2260 SND_SOC_DAPM_POST_PMD), 2261 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event, 2262 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2263 2264 /* Output Lines */ 2265 SND_SOC_DAPM_OUTPUT("HPOL"), 2266 SND_SOC_DAPM_OUTPUT("HPOR"), 2267 }; 2268 2269 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = { 2270 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3, 2271 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0), 2272 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL, 2273 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0), 2274 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1, 2275 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2276 2277 /* ASRC */ 2278 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2279 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2280 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2281 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2282 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2283 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2284 2285 /* Input Lines */ 2286 SND_SOC_DAPM_INPUT("IN2P"), 2287 SND_SOC_DAPM_INPUT("IN2N"), 2288 2289 /* Boost */ 2290 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0), 2291 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3, 2292 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0), 2293 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0), 2294 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0, 2295 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD | 2296 SND_SOC_DAPM_POST_PMU), 2297 2298 /* REC Mixer */ 2299 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l, 2300 ARRAY_SIZE(rt5663_recmix1l)), 2301 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r, 2302 ARRAY_SIZE(rt5663_recmix1r)), 2303 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2, 2304 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0), 2305 2306 /* ADC */ 2307 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2308 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1, 2309 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0), 2310 2311 /* ADC Mux */ 2312 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER, 2313 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0), 2314 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER, 2315 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0), 2316 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER, 2317 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0), 2318 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER, 2319 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0), 2320 2321 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0, 2322 &rt5663_sto1_adcl_mux), 2323 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0, 2324 &rt5663_sto1_adcr_mux), 2325 2326 /* ADC Mix */ 2327 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2328 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)), 2329 2330 /* Analog DAC Clock */ 2331 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L, 2332 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0), 2333 2334 /* Headphone out */ 2335 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0, 2336 &rt5663_hpo_switch), 2337 }; 2338 2339 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = { 2340 /* System Clock Pre Divider Gating */ 2341 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0, 2342 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU | 2343 SND_SOC_DAPM_PRE_PMD), 2344 2345 /* LDO */ 2346 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1, 2347 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2348 2349 /* ASRC */ 2350 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2351 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2352 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2353 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2354 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2355 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2356 2357 /* Boost */ 2358 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0), 2359 2360 /* STO ADC */ 2361 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2362 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0), 2363 2364 /* Analog DAC source */ 2365 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux), 2366 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux), 2367 }; 2368 2369 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = { 2370 /* PLL */ 2371 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll }, 2372 2373 /* ASRC */ 2374 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc }, 2375 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc }, 2376 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc }, 2377 2378 { "ADC L", NULL, "ADC L Power" }, 2379 { "ADC L", NULL, "ADC Clock" }, 2380 2381 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" }, 2382 2383 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" }, 2384 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" }, 2385 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" }, 2386 2387 { "IF1 ADC1", NULL, "STO1 ADC MIXL" }, 2388 { "IF ADC", NULL, "IF1 ADC1" }, 2389 { "AIFTX", NULL, "IF ADC" }, 2390 { "AIFTX", NULL, "I2S" }, 2391 2392 { "AIFRX", NULL, "I2S" }, 2393 { "IF DAC", NULL, "AIFRX" }, 2394 { "IF1 DAC1 L", NULL, "IF DAC" }, 2395 { "IF1 DAC1 R", NULL, "IF DAC" }, 2396 2397 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" }, 2398 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" }, 2399 { "ADDA MIXL", NULL, "STO1 DAC Filter" }, 2400 { "ADDA MIXL", NULL, "STO1 DAC L Power" }, 2401 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" }, 2402 { "ADDA MIXR", NULL, "STO1 DAC Filter" }, 2403 { "ADDA MIXR", NULL, "STO1 DAC R Power" }, 2404 2405 { "DAC L1", NULL, "ADDA MIXL" }, 2406 { "DAC R1", NULL, "ADDA MIXR" }, 2407 2408 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" }, 2409 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" }, 2410 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" }, 2411 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" }, 2412 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" }, 2413 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" }, 2414 2415 { "HP Amp", NULL, "HP Charge Pump" }, 2416 { "HP Amp", NULL, "DAC L" }, 2417 { "HP Amp", NULL, "DAC R" }, 2418 }; 2419 2420 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = { 2421 { "MICBIAS1", NULL, "LDO2" }, 2422 { "MICBIAS2", NULL, "LDO2" }, 2423 2424 { "BST1 CBJ", NULL, "IN1P" }, 2425 { "BST1 CBJ", NULL, "IN1N" }, 2426 { "BST1 CBJ", NULL, "CBJ Power" }, 2427 2428 { "BST2", NULL, "IN2P" }, 2429 { "BST2", NULL, "IN2N" }, 2430 { "BST2", NULL, "BST2 Power" }, 2431 2432 { "RECMIX1L", "BST2 Switch", "BST2" }, 2433 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" }, 2434 { "RECMIX1L", NULL, "RECMIX1L Power" }, 2435 { "RECMIX1R", "BST2 Switch", "BST2" }, 2436 { "RECMIX1R", NULL, "RECMIX1R Power" }, 2437 2438 { "ADC L", NULL, "RECMIX1L" }, 2439 { "ADC R", NULL, "RECMIX1R" }, 2440 { "ADC R", NULL, "ADC R Power" }, 2441 { "ADC R", NULL, "ADC Clock" }, 2442 2443 { "STO1 ADC L Mux", "ADC L", "ADC L" }, 2444 { "STO1 ADC L Mux", "ADC R", "ADC R" }, 2445 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" }, 2446 2447 { "STO1 ADC R Mux", "ADC L", "ADC L" }, 2448 { "STO1 ADC R Mux", "ADC R", "ADC R" }, 2449 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" }, 2450 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" }, 2451 2452 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" }, 2453 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" }, 2454 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" }, 2455 2456 { "IF1 ADC1", NULL, "STO1 ADC MIXR" }, 2457 2458 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" }, 2459 2460 { "DAC L", NULL, "STO1 DAC MIXL" }, 2461 { "DAC L", NULL, "LDO DAC" }, 2462 { "DAC L", NULL, "DAC Clock" }, 2463 { "DAC R", NULL, "STO1 DAC MIXR" }, 2464 { "DAC R", NULL, "LDO DAC" }, 2465 { "DAC R", NULL, "DAC Clock" }, 2466 2467 { "HPO Playback", "Switch", "HP Amp" }, 2468 { "HPOL", NULL, "HPO Playback" }, 2469 { "HPOR", NULL, "HPO Playback" }, 2470 }; 2471 2472 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = { 2473 { "I2S", NULL, "Pre Div Power" }, 2474 2475 { "BST1", NULL, "IN1P" }, 2476 { "BST1", NULL, "IN1N" }, 2477 { "BST1", NULL, "RECMIX1L Power" }, 2478 2479 { "ADC L", NULL, "BST1" }, 2480 2481 { "STO1 ADC L1", NULL, "ADC L" }, 2482 2483 { "DAC L Mux", "DAC L", "DAC L1" }, 2484 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" }, 2485 { "DAC R Mux", "DAC R", "DAC R1"}, 2486 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" }, 2487 2488 { "DAC L", NULL, "DAC L Mux" }, 2489 { "DAC R", NULL, "DAC R Mux" }, 2490 2491 { "HPOL", NULL, "HP Amp" }, 2492 { "HPOR", NULL, "HP Amp" }, 2493 }; 2494 2495 static int rt5663_hw_params(struct snd_pcm_substream *substream, 2496 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2497 { 2498 struct snd_soc_codec *codec = dai->codec; 2499 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2500 unsigned int val_len = 0; 2501 int pre_div; 2502 2503 rt5663->lrck = params_rate(params); 2504 2505 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n", 2506 rt5663->lrck, rt5663->sysclk); 2507 2508 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck); 2509 if (pre_div < 0) { 2510 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n", 2511 rt5663->lrck, dai->id); 2512 return -EINVAL; 2513 } 2514 2515 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id); 2516 2517 switch (params_width(params)) { 2518 case 8: 2519 val_len = RT5663_I2S_DL_8; 2520 break; 2521 case 16: 2522 val_len = RT5663_I2S_DL_16; 2523 break; 2524 case 20: 2525 val_len = RT5663_I2S_DL_20; 2526 break; 2527 case 24: 2528 val_len = RT5663_I2S_DL_24; 2529 break; 2530 default: 2531 return -EINVAL; 2532 } 2533 2534 snd_soc_update_bits(codec, RT5663_I2S1_SDP, 2535 RT5663_I2S_DL_MASK, val_len); 2536 2537 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1, 2538 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT); 2539 2540 return 0; 2541 } 2542 2543 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2544 { 2545 struct snd_soc_codec *codec = dai->codec; 2546 unsigned int reg_val = 0; 2547 2548 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2549 case SND_SOC_DAIFMT_CBM_CFM: 2550 break; 2551 case SND_SOC_DAIFMT_CBS_CFS: 2552 reg_val |= RT5663_I2S_MS_S; 2553 break; 2554 default: 2555 return -EINVAL; 2556 } 2557 2558 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2559 case SND_SOC_DAIFMT_NB_NF: 2560 break; 2561 case SND_SOC_DAIFMT_IB_NF: 2562 reg_val |= RT5663_I2S_BP_INV; 2563 break; 2564 default: 2565 return -EINVAL; 2566 } 2567 2568 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2569 case SND_SOC_DAIFMT_I2S: 2570 break; 2571 case SND_SOC_DAIFMT_LEFT_J: 2572 reg_val |= RT5663_I2S_DF_LEFT; 2573 break; 2574 case SND_SOC_DAIFMT_DSP_A: 2575 reg_val |= RT5663_I2S_DF_PCM_A; 2576 break; 2577 case SND_SOC_DAIFMT_DSP_B: 2578 reg_val |= RT5663_I2S_DF_PCM_B; 2579 break; 2580 default: 2581 return -EINVAL; 2582 } 2583 2584 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK | 2585 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val); 2586 2587 return 0; 2588 } 2589 2590 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 2591 unsigned int freq, int dir) 2592 { 2593 struct snd_soc_codec *codec = dai->codec; 2594 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2595 unsigned int reg_val = 0; 2596 2597 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src) 2598 return 0; 2599 2600 switch (clk_id) { 2601 case RT5663_SCLK_S_MCLK: 2602 reg_val |= RT5663_SCLK_SRC_MCLK; 2603 break; 2604 case RT5663_SCLK_S_PLL1: 2605 reg_val |= RT5663_SCLK_SRC_PLL1; 2606 break; 2607 case RT5663_SCLK_S_RCCLK: 2608 reg_val |= RT5663_SCLK_SRC_RCCLK; 2609 break; 2610 default: 2611 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 2612 return -EINVAL; 2613 } 2614 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK, 2615 reg_val); 2616 rt5663->sysclk = freq; 2617 rt5663->sysclk_src = clk_id; 2618 2619 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", 2620 freq, clk_id); 2621 2622 return 0; 2623 } 2624 2625 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2626 unsigned int freq_in, unsigned int freq_out) 2627 { 2628 struct snd_soc_codec *codec = dai->codec; 2629 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2630 struct rl6231_pll_code pll_code; 2631 int ret; 2632 int mask, shift, val; 2633 2634 if (source == rt5663->pll_src && freq_in == rt5663->pll_in && 2635 freq_out == rt5663->pll_out) 2636 return 0; 2637 2638 if (!freq_in || !freq_out) { 2639 dev_dbg(codec->dev, "PLL disabled\n"); 2640 2641 rt5663->pll_in = 0; 2642 rt5663->pll_out = 0; 2643 snd_soc_update_bits(codec, RT5663_GLB_CLK, 2644 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK); 2645 return 0; 2646 } 2647 2648 switch (rt5663->codec_ver) { 2649 case CODEC_VER_1: 2650 mask = RT5663_V2_PLL1_SRC_MASK; 2651 shift = RT5663_V2_PLL1_SRC_SHIFT; 2652 break; 2653 case CODEC_VER_0: 2654 mask = RT5663_PLL1_SRC_MASK; 2655 shift = RT5663_PLL1_SRC_SHIFT; 2656 break; 2657 default: 2658 dev_err(codec->dev, "Unknown CODEC Version\n"); 2659 return -EINVAL; 2660 } 2661 2662 switch (source) { 2663 case RT5663_PLL1_S_MCLK: 2664 val = 0x0; 2665 break; 2666 case RT5663_PLL1_S_BCLK1: 2667 val = 0x1; 2668 break; 2669 default: 2670 dev_err(codec->dev, "Unknown PLL source %d\n", source); 2671 return -EINVAL; 2672 } 2673 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift)); 2674 2675 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2676 if (ret < 0) { 2677 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 2678 return ret; 2679 } 2680 2681 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp, 2682 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code, 2683 pll_code.k_code); 2684 2685 snd_soc_write(codec, RT5663_PLL_1, 2686 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code); 2687 snd_soc_write(codec, RT5663_PLL_2, 2688 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT | 2689 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT); 2690 2691 rt5663->pll_in = freq_in; 2692 rt5663->pll_out = freq_out; 2693 rt5663->pll_src = source; 2694 2695 return 0; 2696 } 2697 2698 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2699 unsigned int rx_mask, int slots, int slot_width) 2700 { 2701 struct snd_soc_codec *codec = dai->codec; 2702 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2703 unsigned int val = 0, reg; 2704 2705 if (rx_mask || tx_mask) 2706 val |= RT5663_TDM_MODE_TDM; 2707 2708 switch (slots) { 2709 case 4: 2710 val |= RT5663_TDM_IN_CH_4; 2711 val |= RT5663_TDM_OUT_CH_4; 2712 break; 2713 case 6: 2714 val |= RT5663_TDM_IN_CH_6; 2715 val |= RT5663_TDM_OUT_CH_6; 2716 break; 2717 case 8: 2718 val |= RT5663_TDM_IN_CH_8; 2719 val |= RT5663_TDM_OUT_CH_8; 2720 break; 2721 case 2: 2722 break; 2723 default: 2724 return -EINVAL; 2725 } 2726 2727 switch (slot_width) { 2728 case 20: 2729 val |= RT5663_TDM_IN_LEN_20; 2730 val |= RT5663_TDM_OUT_LEN_20; 2731 break; 2732 case 24: 2733 val |= RT5663_TDM_IN_LEN_24; 2734 val |= RT5663_TDM_OUT_LEN_24; 2735 break; 2736 case 32: 2737 val |= RT5663_TDM_IN_LEN_32; 2738 val |= RT5663_TDM_OUT_LEN_32; 2739 break; 2740 case 16: 2741 break; 2742 default: 2743 return -EINVAL; 2744 } 2745 2746 switch (rt5663->codec_ver) { 2747 case CODEC_VER_1: 2748 reg = RT5663_TDM_2; 2749 break; 2750 case CODEC_VER_0: 2751 reg = RT5663_TDM_1; 2752 break; 2753 default: 2754 dev_err(codec->dev, "Unknown CODEC Version\n"); 2755 return -EINVAL; 2756 } 2757 2758 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK | 2759 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK | 2760 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val); 2761 2762 return 0; 2763 } 2764 2765 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2766 { 2767 struct snd_soc_codec *codec = dai->codec; 2768 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2769 unsigned int reg; 2770 2771 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio); 2772 2773 if (rt5663->codec_ver == CODEC_VER_1) 2774 reg = RT5663_TDM_9; 2775 else 2776 reg = RT5663_TDM_5; 2777 2778 switch (ratio) { 2779 case 32: 2780 snd_soc_update_bits(codec, reg, 2781 RT5663_TDM_LENGTN_MASK, 2782 RT5663_TDM_LENGTN_16); 2783 break; 2784 case 40: 2785 snd_soc_update_bits(codec, reg, 2786 RT5663_TDM_LENGTN_MASK, 2787 RT5663_TDM_LENGTN_20); 2788 break; 2789 case 48: 2790 snd_soc_update_bits(codec, reg, 2791 RT5663_TDM_LENGTN_MASK, 2792 RT5663_TDM_LENGTN_24); 2793 break; 2794 case 64: 2795 snd_soc_update_bits(codec, reg, 2796 RT5663_TDM_LENGTN_MASK, 2797 RT5663_TDM_LENGTN_32); 2798 break; 2799 default: 2800 dev_err(codec->dev, "Invalid ratio!\n"); 2801 return -EINVAL; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static int rt5663_set_bias_level(struct snd_soc_codec *codec, 2808 enum snd_soc_bias_level level) 2809 { 2810 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2811 2812 switch (level) { 2813 case SND_SOC_BIAS_ON: 2814 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2815 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 2816 RT5663_PWR_FV1 | RT5663_PWR_FV2); 2817 break; 2818 2819 case SND_SOC_BIAS_PREPARE: 2820 if (rt5663->codec_ver == CODEC_VER_1) { 2821 snd_soc_update_bits(codec, RT5663_DIG_MISC, 2822 RT5663_DIG_GATE_CTRL_MASK, 2823 RT5663_DIG_GATE_CTRL_EN); 2824 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET, 2825 RT5663_EN_ANA_CLK_DET_MASK | 2826 RT5663_PWR_CLK_DET_MASK, 2827 RT5663_EN_ANA_CLK_DET_AUTO | 2828 RT5663_PWR_CLK_DET_EN); 2829 } 2830 break; 2831 2832 case SND_SOC_BIAS_STANDBY: 2833 if (rt5663->codec_ver == CODEC_VER_1) 2834 snd_soc_update_bits(codec, RT5663_DIG_MISC, 2835 RT5663_DIG_GATE_CTRL_MASK, 2836 RT5663_DIG_GATE_CTRL_DIS); 2837 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2838 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 2839 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK | 2840 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 | 2841 RT5663_PWR_VREF2 | RT5663_PWR_MB); 2842 usleep_range(10000, 10005); 2843 if (rt5663->codec_ver == CODEC_VER_1) { 2844 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET, 2845 RT5663_EN_ANA_CLK_DET_MASK | 2846 RT5663_PWR_CLK_DET_MASK, 2847 RT5663_EN_ANA_CLK_DET_DIS | 2848 RT5663_PWR_CLK_DET_DIS); 2849 } 2850 break; 2851 2852 case SND_SOC_BIAS_OFF: 2853 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2854 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 2855 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0); 2856 break; 2857 2858 default: 2859 break; 2860 } 2861 2862 return 0; 2863 } 2864 2865 static int rt5663_probe(struct snd_soc_codec *codec) 2866 { 2867 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 2868 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2869 2870 rt5663->codec = codec; 2871 2872 switch (rt5663->codec_ver) { 2873 case CODEC_VER_1: 2874 snd_soc_dapm_new_controls(dapm, 2875 rt5663_v2_specific_dapm_widgets, 2876 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets)); 2877 snd_soc_dapm_add_routes(dapm, 2878 rt5663_v2_specific_dapm_routes, 2879 ARRAY_SIZE(rt5663_v2_specific_dapm_routes)); 2880 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls, 2881 ARRAY_SIZE(rt5663_v2_specific_controls)); 2882 break; 2883 case CODEC_VER_0: 2884 snd_soc_dapm_new_controls(dapm, 2885 rt5663_specific_dapm_widgets, 2886 ARRAY_SIZE(rt5663_specific_dapm_widgets)); 2887 snd_soc_dapm_add_routes(dapm, 2888 rt5663_specific_dapm_routes, 2889 ARRAY_SIZE(rt5663_specific_dapm_routes)); 2890 snd_soc_add_codec_controls(codec, rt5663_specific_controls, 2891 ARRAY_SIZE(rt5663_specific_controls)); 2892 break; 2893 } 2894 2895 return 0; 2896 } 2897 2898 static int rt5663_remove(struct snd_soc_codec *codec) 2899 { 2900 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2901 2902 regmap_write(rt5663->regmap, RT5663_RESET, 0); 2903 2904 return 0; 2905 } 2906 2907 #ifdef CONFIG_PM 2908 static int rt5663_suspend(struct snd_soc_codec *codec) 2909 { 2910 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2911 2912 regcache_cache_only(rt5663->regmap, true); 2913 regcache_mark_dirty(rt5663->regmap); 2914 2915 return 0; 2916 } 2917 2918 static int rt5663_resume(struct snd_soc_codec *codec) 2919 { 2920 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 2921 2922 regcache_cache_only(rt5663->regmap, false); 2923 regcache_sync(rt5663->regmap); 2924 2925 rt5663_irq(0, rt5663); 2926 2927 return 0; 2928 } 2929 #else 2930 #define rt5663_suspend NULL 2931 #define rt5663_resume NULL 2932 #endif 2933 2934 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2935 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2936 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2937 2938 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = { 2939 .hw_params = rt5663_hw_params, 2940 .set_fmt = rt5663_set_dai_fmt, 2941 .set_sysclk = rt5663_set_dai_sysclk, 2942 .set_pll = rt5663_set_dai_pll, 2943 .set_tdm_slot = rt5663_set_tdm_slot, 2944 .set_bclk_ratio = rt5663_set_bclk_ratio, 2945 }; 2946 2947 static struct snd_soc_dai_driver rt5663_dai[] = { 2948 { 2949 .name = "rt5663-aif", 2950 .id = RT5663_AIF, 2951 .playback = { 2952 .stream_name = "AIF Playback", 2953 .channels_min = 1, 2954 .channels_max = 2, 2955 .rates = RT5663_STEREO_RATES, 2956 .formats = RT5663_FORMATS, 2957 }, 2958 .capture = { 2959 .stream_name = "AIF Capture", 2960 .channels_min = 1, 2961 .channels_max = 2, 2962 .rates = RT5663_STEREO_RATES, 2963 .formats = RT5663_FORMATS, 2964 }, 2965 .ops = &rt5663_aif_dai_ops, 2966 }, 2967 }; 2968 2969 static const struct snd_soc_codec_driver soc_codec_dev_rt5663 = { 2970 .probe = rt5663_probe, 2971 .remove = rt5663_remove, 2972 .suspend = rt5663_suspend, 2973 .resume = rt5663_resume, 2974 .set_bias_level = rt5663_set_bias_level, 2975 .idle_bias_off = true, 2976 .component_driver = { 2977 .controls = rt5663_snd_controls, 2978 .num_controls = ARRAY_SIZE(rt5663_snd_controls), 2979 .dapm_widgets = rt5663_dapm_widgets, 2980 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets), 2981 .dapm_routes = rt5663_dapm_routes, 2982 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes), 2983 } 2984 }; 2985 2986 static const struct regmap_config rt5663_v2_regmap = { 2987 .reg_bits = 16, 2988 .val_bits = 16, 2989 .use_single_rw = true, 2990 .max_register = 0x07fa, 2991 .volatile_reg = rt5663_v2_volatile_register, 2992 .readable_reg = rt5663_v2_readable_register, 2993 .cache_type = REGCACHE_RBTREE, 2994 .reg_defaults = rt5663_v2_reg, 2995 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg), 2996 }; 2997 2998 static const struct regmap_config rt5663_regmap = { 2999 .reg_bits = 16, 3000 .val_bits = 16, 3001 .use_single_rw = true, 3002 .max_register = 0x03f3, 3003 .volatile_reg = rt5663_volatile_register, 3004 .readable_reg = rt5663_readable_register, 3005 .cache_type = REGCACHE_RBTREE, 3006 .reg_defaults = rt5663_reg, 3007 .num_reg_defaults = ARRAY_SIZE(rt5663_reg), 3008 }; 3009 3010 static const struct regmap_config temp_regmap = { 3011 .name = "nocache", 3012 .reg_bits = 16, 3013 .val_bits = 16, 3014 .use_single_rw = true, 3015 .max_register = 0x03f3, 3016 .cache_type = REGCACHE_NONE, 3017 }; 3018 3019 static const struct i2c_device_id rt5663_i2c_id[] = { 3020 { "rt5663", 0 }, 3021 {} 3022 }; 3023 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id); 3024 3025 #if defined(CONFIG_OF) 3026 static const struct of_device_id rt5663_of_match[] = { 3027 { .compatible = "realtek,rt5663", }, 3028 {}, 3029 }; 3030 MODULE_DEVICE_TABLE(of, rt5663_of_match); 3031 #endif 3032 3033 #ifdef CONFIG_ACPI 3034 static const struct acpi_device_id rt5663_acpi_match[] = { 3035 { "10EC5663", 0}, 3036 {}, 3037 }; 3038 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match); 3039 #endif 3040 3041 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663) 3042 { 3043 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3044 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100); 3045 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040); 3046 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001); 3047 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380); 3048 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 3049 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000); 3050 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030); 3051 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05); 3052 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e); 3053 msleep(40); 3054 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e); 3055 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321); 3056 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00); 3057 msleep(500); 3058 } 3059 3060 static void rt5663_calibrate(struct rt5663_priv *rt5663) 3061 { 3062 int value, count; 3063 3064 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000); 3065 msleep(20); 3066 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1); 3067 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380); 3068 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 3069 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000); 3070 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 3071 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c); 3072 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324); 3073 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001); 3074 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b); 3075 msleep(30); 3076 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b); 3077 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000); 3078 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008); 3079 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff); 3080 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff); 3081 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10); 3082 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1); 3083 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880); 3084 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110); 3085 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118); 3086 3087 count = 0; 3088 while (true) { 3089 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value); 3090 if (!(value & 0x80)) 3091 usleep_range(10000, 10005); 3092 else 3093 break; 3094 3095 if (++count > 200) 3096 break; 3097 } 3098 3099 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000); 3100 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003); 3101 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038); 3102 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b); 3103 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400); 3104 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8); 3105 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003); 3106 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c); 3107 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32); 3108 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b); 3109 msleep(40); 3110 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000); 3111 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c); 3112 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa); 3113 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224); 3114 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088); 3115 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017); 3116 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017); 3117 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040); 3118 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000); 3119 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005); 3120 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000); 3121 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320); 3122 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9); 3123 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c); 3124 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111); 3125 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402); 3126 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311); 3127 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069); 3128 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce); 3129 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800); 3130 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100); 3131 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057); 3132 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800); 3133 3134 count = 0; 3135 while (true) { 3136 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value); 3137 if (value & 0x8000) 3138 usleep_range(10000, 10005); 3139 else 3140 break; 3141 3142 if (count > 200) 3143 return; 3144 count++; 3145 } 3146 3147 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200); 3148 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059); 3149 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200); 3150 3151 count = 0; 3152 while (true) { 3153 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value); 3154 if (value & 0x8000) 3155 usleep_range(10000, 10005); 3156 else 3157 break; 3158 3159 if (count > 200) 3160 return; 3161 count++; 3162 } 3163 3164 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0); 3165 usleep_range(10000, 10005); 3166 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b); 3167 usleep_range(10000, 10005); 3168 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000); 3169 usleep_range(10000, 10005); 3170 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b); 3171 usleep_range(10000, 10005); 3172 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008); 3173 usleep_range(10000, 10005); 3174 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000); 3175 usleep_range(10000, 10005); 3176 } 3177 3178 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev) 3179 { 3180 device_property_read_u32(dev, "realtek,dc_offset_l_manual", 3181 &rt5663->pdata.dc_offset_l_manual); 3182 device_property_read_u32(dev, "realtek,dc_offset_r_manual", 3183 &rt5663->pdata.dc_offset_r_manual); 3184 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic", 3185 &rt5663->pdata.dc_offset_l_manual_mic); 3186 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic", 3187 &rt5663->pdata.dc_offset_r_manual_mic); 3188 3189 return 0; 3190 } 3191 3192 static int rt5663_i2c_probe(struct i2c_client *i2c, 3193 const struct i2c_device_id *id) 3194 { 3195 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev); 3196 struct rt5663_priv *rt5663; 3197 int ret; 3198 unsigned int val; 3199 struct regmap *regmap; 3200 3201 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv), 3202 GFP_KERNEL); 3203 3204 if (rt5663 == NULL) 3205 return -ENOMEM; 3206 3207 i2c_set_clientdata(i2c, rt5663); 3208 3209 if (pdata) 3210 rt5663->pdata = *pdata; 3211 else 3212 rt5663_parse_dp(rt5663, &i2c->dev); 3213 3214 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 3215 if (IS_ERR(regmap)) { 3216 ret = PTR_ERR(regmap); 3217 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 3218 ret); 3219 return ret; 3220 } 3221 regmap_read(regmap, RT5663_VENDOR_ID_2, &val); 3222 switch (val) { 3223 case RT5663_DEVICE_ID_2: 3224 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap); 3225 rt5663->codec_ver = CODEC_VER_1; 3226 break; 3227 case RT5663_DEVICE_ID_1: 3228 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap); 3229 rt5663->codec_ver = CODEC_VER_0; 3230 break; 3231 default: 3232 dev_err(&i2c->dev, 3233 "Device with ID register %#x is not rt5663\n", 3234 val); 3235 return -ENODEV; 3236 } 3237 3238 if (IS_ERR(rt5663->regmap)) { 3239 ret = PTR_ERR(rt5663->regmap); 3240 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3241 ret); 3242 return ret; 3243 } 3244 3245 /* reset and calibrate */ 3246 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3247 regcache_cache_bypass(rt5663->regmap, true); 3248 switch (rt5663->codec_ver) { 3249 case CODEC_VER_1: 3250 rt5663_v2_calibrate(rt5663); 3251 break; 3252 case CODEC_VER_0: 3253 rt5663_calibrate(rt5663); 3254 break; 3255 default: 3256 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3257 } 3258 regcache_cache_bypass(rt5663->regmap, false); 3259 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3260 dev_dbg(&i2c->dev, "calibrate done\n"); 3261 3262 switch (rt5663->codec_ver) { 3263 case CODEC_VER_1: 3264 break; 3265 case CODEC_VER_0: 3266 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list, 3267 ARRAY_SIZE(rt5663_patch_list)); 3268 if (ret != 0) 3269 dev_warn(&i2c->dev, 3270 "Failed to apply regmap patch: %d\n", ret); 3271 break; 3272 default: 3273 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3274 } 3275 3276 /* GPIO1 as IRQ */ 3277 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK, 3278 RT5663_GP1_PIN_IRQ); 3279 /* 4btn inline command debounce */ 3280 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5, 3281 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS); 3282 3283 switch (rt5663->codec_ver) { 3284 case CODEC_VER_1: 3285 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3286 /* JD1 */ 3287 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3288 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK, 3289 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN); 3290 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2, 3291 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1); 3292 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3293 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN); 3294 3295 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2, 3296 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG); 3297 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3298 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK | 3299 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG | 3300 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN); 3301 /* Set GPIO4 and GPIO8 as input for combo jack */ 3302 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3303 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT); 3304 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3, 3305 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT); 3306 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1, 3307 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK, 3308 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 3309 break; 3310 case CODEC_VER_0: 3311 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC, 3312 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 3313 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3314 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN); 3315 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3316 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 3317 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, 3318 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN); 3319 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 3320 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be); 3321 msleep(20); 3322 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be); 3323 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3324 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK, 3325 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN); 3326 /* DACREF LDO control */ 3327 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e, 3328 0x3a0a); 3329 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3330 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON); 3331 regmap_update_bits(rt5663->regmap, RT5663_TDM_2, 3332 RT5663_DATA_SWAP_ADCDAT1_MASK, 3333 RT5663_DATA_SWAP_ADCDAT1_LL); 3334 break; 3335 default: 3336 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3337 } 3338 3339 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work); 3340 3341 if (i2c->irq) { 3342 ret = request_irq(i2c->irq, rt5663_irq, 3343 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 3344 | IRQF_ONESHOT, "rt5663", rt5663); 3345 if (ret) 3346 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n", 3347 __func__, ret); 3348 } 3349 3350 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663, 3351 rt5663_dai, ARRAY_SIZE(rt5663_dai)); 3352 3353 if (ret) { 3354 if (i2c->irq) 3355 free_irq(i2c->irq, rt5663); 3356 } 3357 3358 return ret; 3359 } 3360 3361 static int rt5663_i2c_remove(struct i2c_client *i2c) 3362 { 3363 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c); 3364 3365 if (i2c->irq) 3366 free_irq(i2c->irq, rt5663); 3367 3368 snd_soc_unregister_codec(&i2c->dev); 3369 3370 return 0; 3371 } 3372 3373 static void rt5663_i2c_shutdown(struct i2c_client *client) 3374 { 3375 struct rt5663_priv *rt5663 = i2c_get_clientdata(client); 3376 3377 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3378 } 3379 3380 static struct i2c_driver rt5663_i2c_driver = { 3381 .driver = { 3382 .name = "rt5663", 3383 .acpi_match_table = ACPI_PTR(rt5663_acpi_match), 3384 .of_match_table = of_match_ptr(rt5663_of_match), 3385 }, 3386 .probe = rt5663_i2c_probe, 3387 .remove = rt5663_i2c_remove, 3388 .shutdown = rt5663_i2c_shutdown, 3389 .id_table = rt5663_i2c_id, 3390 }; 3391 module_i2c_driver(rt5663_i2c_driver); 3392 3393 MODULE_DESCRIPTION("ASoC RT5663 driver"); 3394 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 3395 MODULE_LICENSE("GPL v2"); 3396