1 /* 2 * rt5645.c -- RT5645 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/acpi.h> 23 #include <linux/dmi.h> 24 #include <linux/regulator/consumer.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/jack.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 34 #include "rl6231.h" 35 #include "rt5645.h" 36 37 #define RT5645_DEVICE_ID 0x6308 38 #define RT5650_DEVICE_ID 0x6419 39 40 #define RT5645_PR_RANGE_BASE (0xff + 1) 41 #define RT5645_PR_SPACING 0x100 42 43 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) 44 45 #define RT5645_HWEQ_NUM 57 46 47 static const struct regmap_range_cfg rt5645_ranges[] = { 48 { 49 .name = "PR", 50 .range_min = RT5645_PR_BASE, 51 .range_max = RT5645_PR_BASE + 0xf8, 52 .selector_reg = RT5645_PRIV_INDEX, 53 .selector_mask = 0xff, 54 .selector_shift = 0x0, 55 .window_start = RT5645_PRIV_DATA, 56 .window_len = 0x1, 57 }, 58 }; 59 60 static const struct reg_sequence init_list[] = { 61 {RT5645_PR_BASE + 0x3d, 0x3600}, 62 {RT5645_PR_BASE + 0x1c, 0xfd20}, 63 {RT5645_PR_BASE + 0x20, 0x611f}, 64 {RT5645_PR_BASE + 0x21, 0x4040}, 65 {RT5645_PR_BASE + 0x23, 0x0004}, 66 }; 67 #define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list) 68 69 static const struct reg_sequence rt5650_init_list[] = { 70 {0xf6, 0x0100}, 71 }; 72 73 static const struct reg_default rt5645_reg[] = { 74 { 0x00, 0x0000 }, 75 { 0x01, 0xc8c8 }, 76 { 0x02, 0xc8c8 }, 77 { 0x03, 0xc8c8 }, 78 { 0x0a, 0x0002 }, 79 { 0x0b, 0x2827 }, 80 { 0x0c, 0xe000 }, 81 { 0x0d, 0x0000 }, 82 { 0x0e, 0x0000 }, 83 { 0x0f, 0x0808 }, 84 { 0x14, 0x3333 }, 85 { 0x16, 0x4b00 }, 86 { 0x18, 0x018b }, 87 { 0x19, 0xafaf }, 88 { 0x1a, 0xafaf }, 89 { 0x1b, 0x0001 }, 90 { 0x1c, 0x2f2f }, 91 { 0x1d, 0x2f2f }, 92 { 0x1e, 0x0000 }, 93 { 0x20, 0x0000 }, 94 { 0x27, 0x7060 }, 95 { 0x28, 0x7070 }, 96 { 0x29, 0x8080 }, 97 { 0x2a, 0x5656 }, 98 { 0x2b, 0x5454 }, 99 { 0x2c, 0xaaa0 }, 100 { 0x2d, 0x0000 }, 101 { 0x2f, 0x1002 }, 102 { 0x31, 0x5000 }, 103 { 0x32, 0x0000 }, 104 { 0x33, 0x0000 }, 105 { 0x34, 0x0000 }, 106 { 0x35, 0x0000 }, 107 { 0x3b, 0x0000 }, 108 { 0x3c, 0x007f }, 109 { 0x3d, 0x0000 }, 110 { 0x3e, 0x007f }, 111 { 0x3f, 0x0000 }, 112 { 0x40, 0x001f }, 113 { 0x41, 0x0000 }, 114 { 0x42, 0x001f }, 115 { 0x45, 0x6000 }, 116 { 0x46, 0x003e }, 117 { 0x47, 0x003e }, 118 { 0x48, 0xf807 }, 119 { 0x4a, 0x0004 }, 120 { 0x4d, 0x0000 }, 121 { 0x4e, 0x0000 }, 122 { 0x4f, 0x01ff }, 123 { 0x50, 0x0000 }, 124 { 0x51, 0x0000 }, 125 { 0x52, 0x01ff }, 126 { 0x53, 0xf000 }, 127 { 0x56, 0x0111 }, 128 { 0x57, 0x0064 }, 129 { 0x58, 0xef0e }, 130 { 0x59, 0xf0f0 }, 131 { 0x5a, 0xef0e }, 132 { 0x5b, 0xf0f0 }, 133 { 0x5c, 0xef0e }, 134 { 0x5d, 0xf0f0 }, 135 { 0x5e, 0xf000 }, 136 { 0x5f, 0x0000 }, 137 { 0x61, 0x0300 }, 138 { 0x62, 0x0000 }, 139 { 0x63, 0x00c2 }, 140 { 0x64, 0x0000 }, 141 { 0x65, 0x0000 }, 142 { 0x66, 0x0000 }, 143 { 0x6a, 0x0000 }, 144 { 0x6c, 0x0aaa }, 145 { 0x70, 0x8000 }, 146 { 0x71, 0x8000 }, 147 { 0x72, 0x8000 }, 148 { 0x73, 0x7770 }, 149 { 0x74, 0x3e00 }, 150 { 0x75, 0x2409 }, 151 { 0x76, 0x000a }, 152 { 0x77, 0x0c00 }, 153 { 0x78, 0x0000 }, 154 { 0x79, 0x0123 }, 155 { 0x80, 0x0000 }, 156 { 0x81, 0x0000 }, 157 { 0x82, 0x0000 }, 158 { 0x83, 0x0000 }, 159 { 0x84, 0x0000 }, 160 { 0x85, 0x0000 }, 161 { 0x8a, 0x0000 }, 162 { 0x8e, 0x0004 }, 163 { 0x8f, 0x1100 }, 164 { 0x90, 0x0646 }, 165 { 0x91, 0x0c06 }, 166 { 0x93, 0x0000 }, 167 { 0x94, 0x0200 }, 168 { 0x95, 0x0000 }, 169 { 0x9a, 0x2184 }, 170 { 0x9b, 0x010a }, 171 { 0x9c, 0x0aea }, 172 { 0x9d, 0x000c }, 173 { 0x9e, 0x0400 }, 174 { 0xa0, 0xa0a8 }, 175 { 0xa1, 0x0059 }, 176 { 0xa2, 0x0001 }, 177 { 0xae, 0x6000 }, 178 { 0xaf, 0x0000 }, 179 { 0xb0, 0x6000 }, 180 { 0xb1, 0x0000 }, 181 { 0xb2, 0x0000 }, 182 { 0xb3, 0x001f }, 183 { 0xb4, 0x020c }, 184 { 0xb5, 0x1f00 }, 185 { 0xb6, 0x0000 }, 186 { 0xbb, 0x0000 }, 187 { 0xbc, 0x0000 }, 188 { 0xbd, 0x0000 }, 189 { 0xbe, 0x0000 }, 190 { 0xbf, 0x3100 }, 191 { 0xc0, 0x0000 }, 192 { 0xc1, 0x0000 }, 193 { 0xc2, 0x0000 }, 194 { 0xc3, 0x2000 }, 195 { 0xcd, 0x0000 }, 196 { 0xce, 0x0000 }, 197 { 0xcf, 0x1813 }, 198 { 0xd0, 0x0690 }, 199 { 0xd1, 0x1c17 }, 200 { 0xd3, 0xb320 }, 201 { 0xd4, 0x0000 }, 202 { 0xd6, 0x0400 }, 203 { 0xd9, 0x0809 }, 204 { 0xda, 0x0000 }, 205 { 0xdb, 0x0003 }, 206 { 0xdc, 0x0049 }, 207 { 0xdd, 0x001b }, 208 { 0xdf, 0x0008 }, 209 { 0xe0, 0x4000 }, 210 { 0xe6, 0x8000 }, 211 { 0xe7, 0x0200 }, 212 { 0xec, 0xb300 }, 213 { 0xed, 0x0000 }, 214 { 0xf0, 0x001f }, 215 { 0xf1, 0x020c }, 216 { 0xf2, 0x1f00 }, 217 { 0xf3, 0x0000 }, 218 { 0xf4, 0x4000 }, 219 { 0xf8, 0x0000 }, 220 { 0xf9, 0x0000 }, 221 { 0xfa, 0x2060 }, 222 { 0xfb, 0x4040 }, 223 { 0xfc, 0x0000 }, 224 { 0xfd, 0x0002 }, 225 { 0xfe, 0x10ec }, 226 { 0xff, 0x6308 }, 227 }; 228 229 struct rt5645_eq_param_s { 230 unsigned short reg; 231 unsigned short val; 232 }; 233 234 static const char *const rt5645_supply_names[] = { 235 "avdd", 236 "cpvdd", 237 }; 238 239 struct rt5645_priv { 240 struct snd_soc_codec *codec; 241 struct rt5645_platform_data pdata; 242 struct regmap *regmap; 243 struct i2c_client *i2c; 244 struct gpio_desc *gpiod_hp_det; 245 struct snd_soc_jack *hp_jack; 246 struct snd_soc_jack *mic_jack; 247 struct snd_soc_jack *btn_jack; 248 struct delayed_work jack_detect_work, rcclock_work; 249 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; 250 struct rt5645_eq_param_s *eq_param; 251 252 int codec_type; 253 int sysclk; 254 int sysclk_src; 255 int lrck[RT5645_AIFS]; 256 int bclk[RT5645_AIFS]; 257 int master[RT5645_AIFS]; 258 259 int pll_src; 260 int pll_in; 261 int pll_out; 262 263 int jack_type; 264 bool en_button_func; 265 bool hp_on; 266 }; 267 268 static int rt5645_reset(struct snd_soc_codec *codec) 269 { 270 return snd_soc_write(codec, RT5645_RESET, 0); 271 } 272 273 static bool rt5645_volatile_register(struct device *dev, unsigned int reg) 274 { 275 int i; 276 277 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 278 if (reg >= rt5645_ranges[i].range_min && 279 reg <= rt5645_ranges[i].range_max) { 280 return true; 281 } 282 } 283 284 switch (reg) { 285 case RT5645_RESET: 286 case RT5645_PRIV_DATA: 287 case RT5645_IN1_CTRL1: 288 case RT5645_IN1_CTRL2: 289 case RT5645_IN1_CTRL3: 290 case RT5645_A_JD_CTRL1: 291 case RT5645_ADC_EQ_CTRL1: 292 case RT5645_EQ_CTRL1: 293 case RT5645_ALC_CTRL_1: 294 case RT5645_IRQ_CTRL2: 295 case RT5645_IRQ_CTRL3: 296 case RT5645_INT_IRQ_ST: 297 case RT5645_IL_CMD: 298 case RT5650_4BTN_IL_CMD1: 299 case RT5645_VENDOR_ID: 300 case RT5645_VENDOR_ID1: 301 case RT5645_VENDOR_ID2: 302 return true; 303 default: 304 return false; 305 } 306 } 307 308 static bool rt5645_readable_register(struct device *dev, unsigned int reg) 309 { 310 int i; 311 312 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 313 if (reg >= rt5645_ranges[i].range_min && 314 reg <= rt5645_ranges[i].range_max) { 315 return true; 316 } 317 } 318 319 switch (reg) { 320 case RT5645_RESET: 321 case RT5645_SPK_VOL: 322 case RT5645_HP_VOL: 323 case RT5645_LOUT1: 324 case RT5645_IN1_CTRL1: 325 case RT5645_IN1_CTRL2: 326 case RT5645_IN1_CTRL3: 327 case RT5645_IN2_CTRL: 328 case RT5645_INL1_INR1_VOL: 329 case RT5645_SPK_FUNC_LIM: 330 case RT5645_ADJ_HPF_CTRL: 331 case RT5645_DAC1_DIG_VOL: 332 case RT5645_DAC2_DIG_VOL: 333 case RT5645_DAC_CTRL: 334 case RT5645_STO1_ADC_DIG_VOL: 335 case RT5645_MONO_ADC_DIG_VOL: 336 case RT5645_ADC_BST_VOL1: 337 case RT5645_ADC_BST_VOL2: 338 case RT5645_STO1_ADC_MIXER: 339 case RT5645_MONO_ADC_MIXER: 340 case RT5645_AD_DA_MIXER: 341 case RT5645_STO_DAC_MIXER: 342 case RT5645_MONO_DAC_MIXER: 343 case RT5645_DIG_MIXER: 344 case RT5650_A_DAC_SOUR: 345 case RT5645_DIG_INF1_DATA: 346 case RT5645_PDM_OUT_CTRL: 347 case RT5645_REC_L1_MIXER: 348 case RT5645_REC_L2_MIXER: 349 case RT5645_REC_R1_MIXER: 350 case RT5645_REC_R2_MIXER: 351 case RT5645_HPMIXL_CTRL: 352 case RT5645_HPOMIXL_CTRL: 353 case RT5645_HPMIXR_CTRL: 354 case RT5645_HPOMIXR_CTRL: 355 case RT5645_HPO_MIXER: 356 case RT5645_SPK_L_MIXER: 357 case RT5645_SPK_R_MIXER: 358 case RT5645_SPO_MIXER: 359 case RT5645_SPO_CLSD_RATIO: 360 case RT5645_OUT_L1_MIXER: 361 case RT5645_OUT_R1_MIXER: 362 case RT5645_OUT_L_GAIN1: 363 case RT5645_OUT_L_GAIN2: 364 case RT5645_OUT_R_GAIN1: 365 case RT5645_OUT_R_GAIN2: 366 case RT5645_LOUT_MIXER: 367 case RT5645_HAPTIC_CTRL1: 368 case RT5645_HAPTIC_CTRL2: 369 case RT5645_HAPTIC_CTRL3: 370 case RT5645_HAPTIC_CTRL4: 371 case RT5645_HAPTIC_CTRL5: 372 case RT5645_HAPTIC_CTRL6: 373 case RT5645_HAPTIC_CTRL7: 374 case RT5645_HAPTIC_CTRL8: 375 case RT5645_HAPTIC_CTRL9: 376 case RT5645_HAPTIC_CTRL10: 377 case RT5645_PWR_DIG1: 378 case RT5645_PWR_DIG2: 379 case RT5645_PWR_ANLG1: 380 case RT5645_PWR_ANLG2: 381 case RT5645_PWR_MIXER: 382 case RT5645_PWR_VOL: 383 case RT5645_PRIV_INDEX: 384 case RT5645_PRIV_DATA: 385 case RT5645_I2S1_SDP: 386 case RT5645_I2S2_SDP: 387 case RT5645_ADDA_CLK1: 388 case RT5645_ADDA_CLK2: 389 case RT5645_DMIC_CTRL1: 390 case RT5645_DMIC_CTRL2: 391 case RT5645_TDM_CTRL_1: 392 case RT5645_TDM_CTRL_2: 393 case RT5645_TDM_CTRL_3: 394 case RT5650_TDM_CTRL_4: 395 case RT5645_GLB_CLK: 396 case RT5645_PLL_CTRL1: 397 case RT5645_PLL_CTRL2: 398 case RT5645_ASRC_1: 399 case RT5645_ASRC_2: 400 case RT5645_ASRC_3: 401 case RT5645_ASRC_4: 402 case RT5645_DEPOP_M1: 403 case RT5645_DEPOP_M2: 404 case RT5645_DEPOP_M3: 405 case RT5645_CHARGE_PUMP: 406 case RT5645_MICBIAS: 407 case RT5645_A_JD_CTRL1: 408 case RT5645_VAD_CTRL4: 409 case RT5645_CLSD_OUT_CTRL: 410 case RT5645_ADC_EQ_CTRL1: 411 case RT5645_ADC_EQ_CTRL2: 412 case RT5645_EQ_CTRL1: 413 case RT5645_EQ_CTRL2: 414 case RT5645_ALC_CTRL_1: 415 case RT5645_ALC_CTRL_2: 416 case RT5645_ALC_CTRL_3: 417 case RT5645_ALC_CTRL_4: 418 case RT5645_ALC_CTRL_5: 419 case RT5645_JD_CTRL: 420 case RT5645_IRQ_CTRL1: 421 case RT5645_IRQ_CTRL2: 422 case RT5645_IRQ_CTRL3: 423 case RT5645_INT_IRQ_ST: 424 case RT5645_GPIO_CTRL1: 425 case RT5645_GPIO_CTRL2: 426 case RT5645_GPIO_CTRL3: 427 case RT5645_BASS_BACK: 428 case RT5645_MP3_PLUS1: 429 case RT5645_MP3_PLUS2: 430 case RT5645_ADJ_HPF1: 431 case RT5645_ADJ_HPF2: 432 case RT5645_HP_CALIB_AMP_DET: 433 case RT5645_SV_ZCD1: 434 case RT5645_SV_ZCD2: 435 case RT5645_IL_CMD: 436 case RT5645_IL_CMD2: 437 case RT5645_IL_CMD3: 438 case RT5650_4BTN_IL_CMD1: 439 case RT5650_4BTN_IL_CMD2: 440 case RT5645_DRC1_HL_CTRL1: 441 case RT5645_DRC2_HL_CTRL1: 442 case RT5645_ADC_MONO_HP_CTRL1: 443 case RT5645_ADC_MONO_HP_CTRL2: 444 case RT5645_DRC2_CTRL1: 445 case RT5645_DRC2_CTRL2: 446 case RT5645_DRC2_CTRL3: 447 case RT5645_DRC2_CTRL4: 448 case RT5645_DRC2_CTRL5: 449 case RT5645_JD_CTRL3: 450 case RT5645_JD_CTRL4: 451 case RT5645_GEN_CTRL1: 452 case RT5645_GEN_CTRL2: 453 case RT5645_GEN_CTRL3: 454 case RT5645_VENDOR_ID: 455 case RT5645_VENDOR_ID1: 456 case RT5645_VENDOR_ID2: 457 return true; 458 default: 459 return false; 460 } 461 } 462 463 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 464 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 465 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 466 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 467 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 468 469 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 470 static const DECLARE_TLV_DB_RANGE(bst_tlv, 471 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 472 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 473 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 474 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 475 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 476 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 477 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 478 ); 479 480 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ 481 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, 482 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), 483 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), 484 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), 485 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) 486 ); 487 488 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, 489 struct snd_ctl_elem_info *uinfo) 490 { 491 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 492 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); 493 494 return 0; 495 } 496 497 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, 498 struct snd_ctl_elem_value *ucontrol) 499 { 500 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 501 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 502 struct rt5645_eq_param_s *eq_param = 503 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data; 504 int i; 505 506 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 507 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); 508 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); 509 } 510 511 return 0; 512 } 513 514 static bool rt5645_validate_hweq(unsigned short reg) 515 { 516 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) | 517 (reg == RT5645_EQ_CTRL2)) 518 return true; 519 520 return false; 521 } 522 523 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, 524 struct snd_ctl_elem_value *ucontrol) 525 { 526 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 527 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 528 struct rt5645_eq_param_s *eq_param = 529 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data; 530 int i; 531 532 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 533 eq_param[i].reg = be16_to_cpu(eq_param[i].reg); 534 eq_param[i].val = be16_to_cpu(eq_param[i].val); 535 } 536 537 /* The final setting of the table should be RT5645_EQ_CTRL2 */ 538 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { 539 if (eq_param[i].reg == 0) 540 continue; 541 else if (eq_param[i].reg != RT5645_EQ_CTRL2) 542 return 0; 543 else 544 break; 545 } 546 547 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 548 if (!rt5645_validate_hweq(eq_param[i].reg) && 549 eq_param[i].reg != 0) 550 return 0; 551 else if (eq_param[i].reg == 0) 552 break; 553 } 554 555 memcpy(rt5645->eq_param, eq_param, 556 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s)); 557 558 return 0; 559 } 560 561 #define RT5645_HWEQ(xname) \ 562 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 563 .info = rt5645_hweq_info, \ 564 .get = rt5645_hweq_get, \ 565 .put = rt5645_hweq_put \ 566 } 567 568 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, 569 struct snd_ctl_elem_value *ucontrol) 570 { 571 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 572 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 573 int ret; 574 575 cancel_delayed_work_sync(&rt5645->rcclock_work); 576 577 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 578 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); 579 580 ret = snd_soc_put_volsw(kcontrol, ucontrol); 581 582 queue_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work, 583 msecs_to_jiffies(200)); 584 585 return ret; 586 } 587 588 static const struct snd_kcontrol_new rt5645_snd_controls[] = { 589 /* Speaker Output Volume */ 590 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 591 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 592 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL, 593 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, 594 rt5645_spk_put_volsw, out_vol_tlv), 595 596 /* ClassD modulator Speaker Gain Ratio */ 597 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, 598 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), 599 600 /* Headphone Output Volume */ 601 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, 602 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 603 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, 604 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 605 606 /* OUTPUT Control */ 607 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, 608 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 609 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, 610 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 611 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, 612 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 613 614 /* DAC Digital Volume */ 615 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 616 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 617 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 618 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 619 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 620 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 621 622 /* IN1/IN2 Control */ 623 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 624 RT5645_BST_SFT1, 8, 0, bst_tlv), 625 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, 626 RT5645_BST_SFT2, 8, 0, bst_tlv), 627 628 /* INL/INR Volume Control */ 629 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, 630 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), 631 632 /* ADC Digital Volume Control */ 633 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 634 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 635 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 636 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 637 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 638 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 639 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 640 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 641 642 /* ADC Boost Volume Control */ 643 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, 644 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, 645 adc_bst_tlv), 646 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, 647 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, 648 adc_bst_tlv), 649 650 /* I2S2 function select */ 651 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 652 1, 1), 653 RT5645_HWEQ("Speaker HWEQ"), 654 }; 655 656 /** 657 * set_dmic_clk - Set parameter of dmic. 658 * 659 * @w: DAPM widget. 660 * @kcontrol: The kcontrol of this widget. 661 * @event: Event id. 662 * 663 */ 664 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 665 struct snd_kcontrol *kcontrol, int event) 666 { 667 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 668 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 669 int idx, rate; 670 671 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, 672 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); 673 idx = rl6231_calc_dmic_clk(rate); 674 if (idx < 0) 675 dev_err(codec->dev, "Failed to set DMIC clock\n"); 676 else 677 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1, 678 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); 679 return idx; 680 } 681 682 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 683 struct snd_soc_dapm_widget *sink) 684 { 685 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 686 unsigned int val; 687 688 val = snd_soc_read(codec, RT5645_GLB_CLK); 689 val &= RT5645_SCLK_SRC_MASK; 690 if (val == RT5645_SCLK_SRC_PLL1) 691 return 1; 692 else 693 return 0; 694 } 695 696 static int is_using_asrc(struct snd_soc_dapm_widget *source, 697 struct snd_soc_dapm_widget *sink) 698 { 699 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 700 unsigned int reg, shift, val; 701 702 switch (source->shift) { 703 case 0: 704 reg = RT5645_ASRC_3; 705 shift = 0; 706 break; 707 case 1: 708 reg = RT5645_ASRC_3; 709 shift = 4; 710 break; 711 case 3: 712 reg = RT5645_ASRC_2; 713 shift = 0; 714 break; 715 case 8: 716 reg = RT5645_ASRC_2; 717 shift = 4; 718 break; 719 case 9: 720 reg = RT5645_ASRC_2; 721 shift = 8; 722 break; 723 case 10: 724 reg = RT5645_ASRC_2; 725 shift = 12; 726 break; 727 default: 728 return 0; 729 } 730 731 val = (snd_soc_read(codec, reg) >> shift) & 0xf; 732 switch (val) { 733 case 1: 734 case 2: 735 case 3: 736 case 4: 737 return 1; 738 default: 739 return 0; 740 } 741 742 } 743 744 static int rt5645_enable_hweq(struct snd_soc_codec *codec) 745 { 746 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 747 int i; 748 749 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 750 if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) 751 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, 752 rt5645->eq_param[i].val); 753 else 754 break; 755 } 756 757 return 0; 758 } 759 760 /** 761 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters 762 * @codec: SoC audio codec device. 763 * @filter_mask: mask of filters. 764 * @clk_src: clock source 765 * 766 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can 767 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 768 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 769 * ASRC function will track i2s clock and generate a corresponding system clock 770 * for codec. This function provides an API to select the clock source for a 771 * set of filters specified by the mask. And the codec driver will turn on ASRC 772 * for these filters if ASRC is selected as their clock source. 773 */ 774 int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, 775 unsigned int filter_mask, unsigned int clk_src) 776 { 777 unsigned int asrc2_mask = 0; 778 unsigned int asrc2_value = 0; 779 unsigned int asrc3_mask = 0; 780 unsigned int asrc3_value = 0; 781 782 switch (clk_src) { 783 case RT5645_CLK_SEL_SYS: 784 case RT5645_CLK_SEL_I2S1_ASRC: 785 case RT5645_CLK_SEL_I2S2_ASRC: 786 case RT5645_CLK_SEL_SYS2: 787 break; 788 789 default: 790 return -EINVAL; 791 } 792 793 if (filter_mask & RT5645_DA_STEREO_FILTER) { 794 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; 795 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) 796 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); 797 } 798 799 if (filter_mask & RT5645_DA_MONO_L_FILTER) { 800 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; 801 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) 802 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); 803 } 804 805 if (filter_mask & RT5645_DA_MONO_R_FILTER) { 806 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; 807 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) 808 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); 809 } 810 811 if (filter_mask & RT5645_AD_STEREO_FILTER) { 812 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; 813 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) 814 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); 815 } 816 817 if (filter_mask & RT5645_AD_MONO_L_FILTER) { 818 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; 819 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) 820 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); 821 } 822 823 if (filter_mask & RT5645_AD_MONO_R_FILTER) { 824 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; 825 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) 826 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); 827 } 828 829 if (asrc2_mask) 830 snd_soc_update_bits(codec, RT5645_ASRC_2, 831 asrc2_mask, asrc2_value); 832 833 if (asrc3_mask) 834 snd_soc_update_bits(codec, RT5645_ASRC_3, 835 asrc3_mask, asrc3_value); 836 837 return 0; 838 } 839 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); 840 841 /* Digital Mixer */ 842 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { 843 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 844 RT5645_M_ADC_L1_SFT, 1, 1), 845 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 846 RT5645_M_ADC_L2_SFT, 1, 1), 847 }; 848 849 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { 850 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 851 RT5645_M_ADC_R1_SFT, 1, 1), 852 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 853 RT5645_M_ADC_R2_SFT, 1, 1), 854 }; 855 856 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { 857 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 858 RT5645_M_MONO_ADC_L1_SFT, 1, 1), 859 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 860 RT5645_M_MONO_ADC_L2_SFT, 1, 1), 861 }; 862 863 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { 864 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 865 RT5645_M_MONO_ADC_R1_SFT, 1, 1), 866 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 867 RT5645_M_MONO_ADC_R2_SFT, 1, 1), 868 }; 869 870 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { 871 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 872 RT5645_M_ADCMIX_L_SFT, 1, 1), 873 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 874 RT5645_M_DAC1_L_SFT, 1, 1), 875 }; 876 877 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { 878 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 879 RT5645_M_ADCMIX_R_SFT, 1, 1), 880 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 881 RT5645_M_DAC1_R_SFT, 1, 1), 882 }; 883 884 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { 885 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 886 RT5645_M_DAC_L1_SFT, 1, 1), 887 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, 888 RT5645_M_DAC_L2_SFT, 1, 1), 889 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 890 RT5645_M_DAC_R1_STO_L_SFT, 1, 1), 891 }; 892 893 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { 894 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 895 RT5645_M_DAC_R1_SFT, 1, 1), 896 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, 897 RT5645_M_DAC_R2_SFT, 1, 1), 898 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 899 RT5645_M_DAC_L1_STO_R_SFT, 1, 1), 900 }; 901 902 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { 903 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, 904 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), 905 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 906 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), 907 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 908 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), 909 }; 910 911 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { 912 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, 913 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), 914 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 915 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), 916 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 917 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), 918 }; 919 920 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { 921 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, 922 RT5645_M_STO_L_DAC_L_SFT, 1, 1), 923 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 924 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), 925 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 926 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), 927 }; 928 929 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { 930 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, 931 RT5645_M_STO_R_DAC_R_SFT, 1, 1), 932 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 933 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), 934 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 935 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), 936 }; 937 938 /* Analog Input Mixer */ 939 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { 940 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, 941 RT5645_M_HP_L_RM_L_SFT, 1, 1), 942 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, 943 RT5645_M_IN_L_RM_L_SFT, 1, 1), 944 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, 945 RT5645_M_BST2_RM_L_SFT, 1, 1), 946 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, 947 RT5645_M_BST1_RM_L_SFT, 1, 1), 948 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, 949 RT5645_M_OM_L_RM_L_SFT, 1, 1), 950 }; 951 952 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { 953 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, 954 RT5645_M_HP_R_RM_R_SFT, 1, 1), 955 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, 956 RT5645_M_IN_R_RM_R_SFT, 1, 1), 957 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, 958 RT5645_M_BST2_RM_R_SFT, 1, 1), 959 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, 960 RT5645_M_BST1_RM_R_SFT, 1, 1), 961 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, 962 RT5645_M_OM_R_RM_R_SFT, 1, 1), 963 }; 964 965 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { 966 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, 967 RT5645_M_DAC_L1_SM_L_SFT, 1, 1), 968 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, 969 RT5645_M_DAC_L2_SM_L_SFT, 1, 1), 970 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, 971 RT5645_M_IN_L_SM_L_SFT, 1, 1), 972 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, 973 RT5645_M_BST1_L_SM_L_SFT, 1, 1), 974 }; 975 976 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { 977 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, 978 RT5645_M_DAC_R1_SM_R_SFT, 1, 1), 979 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, 980 RT5645_M_DAC_R2_SM_R_SFT, 1, 1), 981 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, 982 RT5645_M_IN_R_SM_R_SFT, 1, 1), 983 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, 984 RT5645_M_BST2_R_SM_R_SFT, 1, 1), 985 }; 986 987 static const struct snd_kcontrol_new rt5645_out_l_mix[] = { 988 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, 989 RT5645_M_BST1_OM_L_SFT, 1, 1), 990 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, 991 RT5645_M_IN_L_OM_L_SFT, 1, 1), 992 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, 993 RT5645_M_DAC_L2_OM_L_SFT, 1, 1), 994 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, 995 RT5645_M_DAC_L1_OM_L_SFT, 1, 1), 996 }; 997 998 static const struct snd_kcontrol_new rt5645_out_r_mix[] = { 999 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, 1000 RT5645_M_BST2_OM_R_SFT, 1, 1), 1001 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, 1002 RT5645_M_IN_R_OM_R_SFT, 1, 1), 1003 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, 1004 RT5645_M_DAC_R2_OM_R_SFT, 1, 1), 1005 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, 1006 RT5645_M_DAC_R1_OM_R_SFT, 1, 1), 1007 }; 1008 1009 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { 1010 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1011 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), 1012 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, 1013 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), 1014 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1015 RT5645_M_SV_R_SPM_L_SFT, 1, 1), 1016 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, 1017 RT5645_M_SV_L_SPM_L_SFT, 1, 1), 1018 }; 1019 1020 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { 1021 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1022 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), 1023 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1024 RT5645_M_SV_R_SPM_R_SFT, 1, 1), 1025 }; 1026 1027 static const struct snd_kcontrol_new rt5645_hpo_mix[] = { 1028 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, 1029 RT5645_M_DAC1_HM_SFT, 1, 1), 1030 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, 1031 RT5645_M_HPVOL_HM_SFT, 1, 1), 1032 }; 1033 1034 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { 1035 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, 1036 RT5645_M_DAC1_HV_SFT, 1, 1), 1037 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, 1038 RT5645_M_DAC2_HV_SFT, 1, 1), 1039 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, 1040 RT5645_M_IN_HV_SFT, 1, 1), 1041 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, 1042 RT5645_M_BST1_HV_SFT, 1, 1), 1043 }; 1044 1045 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { 1046 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, 1047 RT5645_M_DAC1_HV_SFT, 1, 1), 1048 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, 1049 RT5645_M_DAC2_HV_SFT, 1, 1), 1050 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, 1051 RT5645_M_IN_HV_SFT, 1, 1), 1052 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, 1053 RT5645_M_BST2_HV_SFT, 1, 1), 1054 }; 1055 1056 static const struct snd_kcontrol_new rt5645_lout_mix[] = { 1057 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, 1058 RT5645_M_DAC_L1_LM_SFT, 1, 1), 1059 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, 1060 RT5645_M_DAC_R1_LM_SFT, 1, 1), 1061 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, 1062 RT5645_M_OV_L_LM_SFT, 1, 1), 1063 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, 1064 RT5645_M_OV_R_LM_SFT, 1, 1), 1065 }; 1066 1067 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ 1068 static const char * const rt5645_dac1_src[] = { 1069 "IF1 DAC", "IF2 DAC", "IF3 DAC" 1070 }; 1071 1072 static SOC_ENUM_SINGLE_DECL( 1073 rt5645_dac1l_enum, RT5645_AD_DA_MIXER, 1074 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); 1075 1076 static const struct snd_kcontrol_new rt5645_dac1l_mux = 1077 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); 1078 1079 static SOC_ENUM_SINGLE_DECL( 1080 rt5645_dac1r_enum, RT5645_AD_DA_MIXER, 1081 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); 1082 1083 static const struct snd_kcontrol_new rt5645_dac1r_mux = 1084 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); 1085 1086 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 1087 static const char * const rt5645_dac12_src[] = { 1088 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" 1089 }; 1090 1091 static SOC_ENUM_SINGLE_DECL( 1092 rt5645_dac2l_enum, RT5645_DAC_CTRL, 1093 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); 1094 1095 static const struct snd_kcontrol_new rt5645_dac_l2_mux = 1096 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); 1097 1098 static const char * const rt5645_dacr2_src[] = { 1099 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" 1100 }; 1101 1102 static SOC_ENUM_SINGLE_DECL( 1103 rt5645_dac2r_enum, RT5645_DAC_CTRL, 1104 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); 1105 1106 static const struct snd_kcontrol_new rt5645_dac_r2_mux = 1107 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); 1108 1109 1110 /* INL/R source */ 1111 static const char * const rt5645_inl_src[] = { 1112 "IN2P", "MonoP" 1113 }; 1114 1115 static SOC_ENUM_SINGLE_DECL( 1116 rt5645_inl_enum, RT5645_INL1_INR1_VOL, 1117 RT5645_INL_SEL_SFT, rt5645_inl_src); 1118 1119 static const struct snd_kcontrol_new rt5645_inl_mux = 1120 SOC_DAPM_ENUM("INL source", rt5645_inl_enum); 1121 1122 static const char * const rt5645_inr_src[] = { 1123 "IN2N", "MonoN" 1124 }; 1125 1126 static SOC_ENUM_SINGLE_DECL( 1127 rt5645_inr_enum, RT5645_INL1_INR1_VOL, 1128 RT5645_INR_SEL_SFT, rt5645_inr_src); 1129 1130 static const struct snd_kcontrol_new rt5645_inr_mux = 1131 SOC_DAPM_ENUM("INR source", rt5645_inr_enum); 1132 1133 /* Stereo1 ADC source */ 1134 /* MX-27 [12] */ 1135 static const char * const rt5645_stereo_adc1_src[] = { 1136 "DAC MIX", "ADC" 1137 }; 1138 1139 static SOC_ENUM_SINGLE_DECL( 1140 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, 1141 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); 1142 1143 static const struct snd_kcontrol_new rt5645_sto_adc1_mux = 1144 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); 1145 1146 /* MX-27 [11] */ 1147 static const char * const rt5645_stereo_adc2_src[] = { 1148 "DAC MIX", "DMIC" 1149 }; 1150 1151 static SOC_ENUM_SINGLE_DECL( 1152 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, 1153 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); 1154 1155 static const struct snd_kcontrol_new rt5645_sto_adc2_mux = 1156 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); 1157 1158 /* MX-27 [8] */ 1159 static const char * const rt5645_stereo_dmic_src[] = { 1160 "DMIC1", "DMIC2" 1161 }; 1162 1163 static SOC_ENUM_SINGLE_DECL( 1164 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, 1165 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); 1166 1167 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = 1168 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); 1169 1170 /* Mono ADC source */ 1171 /* MX-28 [12] */ 1172 static const char * const rt5645_mono_adc_l1_src[] = { 1173 "Mono DAC MIXL", "ADC" 1174 }; 1175 1176 static SOC_ENUM_SINGLE_DECL( 1177 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, 1178 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); 1179 1180 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = 1181 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); 1182 /* MX-28 [11] */ 1183 static const char * const rt5645_mono_adc_l2_src[] = { 1184 "Mono DAC MIXL", "DMIC" 1185 }; 1186 1187 static SOC_ENUM_SINGLE_DECL( 1188 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, 1189 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); 1190 1191 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = 1192 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); 1193 1194 /* MX-28 [8] */ 1195 static const char * const rt5645_mono_dmic_src[] = { 1196 "DMIC1", "DMIC2" 1197 }; 1198 1199 static SOC_ENUM_SINGLE_DECL( 1200 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, 1201 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); 1202 1203 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = 1204 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); 1205 /* MX-28 [1:0] */ 1206 static SOC_ENUM_SINGLE_DECL( 1207 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, 1208 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); 1209 1210 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = 1211 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); 1212 /* MX-28 [4] */ 1213 static const char * const rt5645_mono_adc_r1_src[] = { 1214 "Mono DAC MIXR", "ADC" 1215 }; 1216 1217 static SOC_ENUM_SINGLE_DECL( 1218 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, 1219 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); 1220 1221 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = 1222 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); 1223 /* MX-28 [3] */ 1224 static const char * const rt5645_mono_adc_r2_src[] = { 1225 "Mono DAC MIXR", "DMIC" 1226 }; 1227 1228 static SOC_ENUM_SINGLE_DECL( 1229 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, 1230 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); 1231 1232 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = 1233 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); 1234 1235 /* MX-77 [9:8] */ 1236 static const char * const rt5645_if1_adc_in_src[] = { 1237 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", 1238 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" 1239 }; 1240 1241 static SOC_ENUM_SINGLE_DECL( 1242 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, 1243 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); 1244 1245 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1246 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1247 1248 /* MX-78 [4:0] */ 1249 static const char * const rt5650_if1_adc_in_src[] = { 1250 "IF_ADC1/IF_ADC2/DAC_REF/Null", 1251 "IF_ADC1/IF_ADC2/Null/DAC_REF", 1252 "IF_ADC1/DAC_REF/IF_ADC2/Null", 1253 "IF_ADC1/DAC_REF/Null/IF_ADC2", 1254 "IF_ADC1/Null/DAC_REF/IF_ADC2", 1255 "IF_ADC1/Null/IF_ADC2/DAC_REF", 1256 1257 "IF_ADC2/IF_ADC1/DAC_REF/Null", 1258 "IF_ADC2/IF_ADC1/Null/DAC_REF", 1259 "IF_ADC2/DAC_REF/IF_ADC1/Null", 1260 "IF_ADC2/DAC_REF/Null/IF_ADC1", 1261 "IF_ADC2/Null/DAC_REF/IF_ADC1", 1262 "IF_ADC2/Null/IF_ADC1/DAC_REF", 1263 1264 "DAC_REF/IF_ADC1/IF_ADC2/Null", 1265 "DAC_REF/IF_ADC1/Null/IF_ADC2", 1266 "DAC_REF/IF_ADC2/IF_ADC1/Null", 1267 "DAC_REF/IF_ADC2/Null/IF_ADC1", 1268 "DAC_REF/Null/IF_ADC1/IF_ADC2", 1269 "DAC_REF/Null/IF_ADC2/IF_ADC1", 1270 1271 "Null/IF_ADC1/IF_ADC2/DAC_REF", 1272 "Null/IF_ADC1/DAC_REF/IF_ADC2", 1273 "Null/IF_ADC2/IF_ADC1/DAC_REF", 1274 "Null/IF_ADC2/DAC_REF/IF_ADC1", 1275 "Null/DAC_REF/IF_ADC1/IF_ADC2", 1276 "Null/DAC_REF/IF_ADC2/IF_ADC1", 1277 }; 1278 1279 static SOC_ENUM_SINGLE_DECL( 1280 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, 1281 0, rt5650_if1_adc_in_src); 1282 1283 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = 1284 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); 1285 1286 /* MX-78 [15:14][13:12][11:10] */ 1287 static const char * const rt5645_tdm_adc_swap_select[] = { 1288 "L/R", "R/L", "L/L", "R/R" 1289 }; 1290 1291 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, 1292 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); 1293 1294 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = 1295 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); 1296 1297 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, 1298 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); 1299 1300 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = 1301 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); 1302 1303 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, 1304 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); 1305 1306 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = 1307 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); 1308 1309 /* MX-77 [7:6][5:4][3:2] */ 1310 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, 1311 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); 1312 1313 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = 1314 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); 1315 1316 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, 1317 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); 1318 1319 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = 1320 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); 1321 1322 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, 1323 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); 1324 1325 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = 1326 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); 1327 1328 /* MX-79 [14:12][10:8][6:4][2:0] */ 1329 static const char * const rt5645_tdm_dac_swap_select[] = { 1330 "Slot0", "Slot1", "Slot2", "Slot3" 1331 }; 1332 1333 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, 1334 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); 1335 1336 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = 1337 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); 1338 1339 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, 1340 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); 1341 1342 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = 1343 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); 1344 1345 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, 1346 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); 1347 1348 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = 1349 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); 1350 1351 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, 1352 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); 1353 1354 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = 1355 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); 1356 1357 /* MX-7a [14:12][10:8][6:4][2:0] */ 1358 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, 1359 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); 1360 1361 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = 1362 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); 1363 1364 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, 1365 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); 1366 1367 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = 1368 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); 1369 1370 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, 1371 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); 1372 1373 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = 1374 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); 1375 1376 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, 1377 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); 1378 1379 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = 1380 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); 1381 1382 /* MX-2d [3] [2] */ 1383 static const char * const rt5650_a_dac1_src[] = { 1384 "DAC1", "Stereo DAC Mixer" 1385 }; 1386 1387 static SOC_ENUM_SINGLE_DECL( 1388 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, 1389 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); 1390 1391 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = 1392 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); 1393 1394 static SOC_ENUM_SINGLE_DECL( 1395 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, 1396 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); 1397 1398 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = 1399 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); 1400 1401 /* MX-2d [1] [0] */ 1402 static const char * const rt5650_a_dac2_src[] = { 1403 "Stereo DAC Mixer", "Mono DAC Mixer" 1404 }; 1405 1406 static SOC_ENUM_SINGLE_DECL( 1407 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, 1408 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); 1409 1410 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = 1411 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); 1412 1413 static SOC_ENUM_SINGLE_DECL( 1414 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, 1415 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); 1416 1417 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = 1418 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); 1419 1420 /* MX-2F [13:12] */ 1421 static const char * const rt5645_if2_adc_in_src[] = { 1422 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1423 }; 1424 1425 static SOC_ENUM_SINGLE_DECL( 1426 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, 1427 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); 1428 1429 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = 1430 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); 1431 1432 /* MX-2F [1:0] */ 1433 static const char * const rt5645_if3_adc_in_src[] = { 1434 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1435 }; 1436 1437 static SOC_ENUM_SINGLE_DECL( 1438 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA, 1439 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src); 1440 1441 static const struct snd_kcontrol_new rt5645_if3_adc_in_mux = 1442 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum); 1443 1444 /* MX-31 [15] [13] [11] [9] */ 1445 static const char * const rt5645_pdm_src[] = { 1446 "Mono DAC", "Stereo DAC" 1447 }; 1448 1449 static SOC_ENUM_SINGLE_DECL( 1450 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, 1451 RT5645_PDM1_L_SFT, rt5645_pdm_src); 1452 1453 static const struct snd_kcontrol_new rt5645_pdm1_l_mux = 1454 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); 1455 1456 static SOC_ENUM_SINGLE_DECL( 1457 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, 1458 RT5645_PDM1_R_SFT, rt5645_pdm_src); 1459 1460 static const struct snd_kcontrol_new rt5645_pdm1_r_mux = 1461 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); 1462 1463 /* MX-9D [9:8] */ 1464 static const char * const rt5645_vad_adc_src[] = { 1465 "Sto1 ADC L", "Mono ADC L", "Mono ADC R" 1466 }; 1467 1468 static SOC_ENUM_SINGLE_DECL( 1469 rt5645_vad_adc_enum, RT5645_VAD_CTRL4, 1470 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); 1471 1472 static const struct snd_kcontrol_new rt5645_vad_adc_mux = 1473 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); 1474 1475 static const struct snd_kcontrol_new spk_l_vol_control = 1476 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1477 RT5645_L_MUTE_SFT, 1, 1); 1478 1479 static const struct snd_kcontrol_new spk_r_vol_control = 1480 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1481 RT5645_R_MUTE_SFT, 1, 1); 1482 1483 static const struct snd_kcontrol_new hp_l_vol_control = 1484 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1485 RT5645_L_MUTE_SFT, 1, 1); 1486 1487 static const struct snd_kcontrol_new hp_r_vol_control = 1488 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1489 RT5645_R_MUTE_SFT, 1, 1); 1490 1491 static const struct snd_kcontrol_new pdm1_l_vol_control = 1492 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1493 RT5645_M_PDM1_L, 1, 1); 1494 1495 static const struct snd_kcontrol_new pdm1_r_vol_control = 1496 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1497 RT5645_M_PDM1_R, 1, 1); 1498 1499 static void hp_amp_power(struct snd_soc_codec *codec, int on) 1500 { 1501 static int hp_amp_power_count; 1502 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 1503 1504 if (on) { 1505 if (hp_amp_power_count <= 0) { 1506 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1507 snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100); 1508 snd_soc_write(codec, RT5645_CHARGE_PUMP, 1509 0x0e06); 1510 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); 1511 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1512 RT5645_HP_DCC_INT1, 0x9f01); 1513 msleep(20); 1514 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1515 RT5645_HP_CO_MASK, RT5645_HP_CO_EN); 1516 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1517 0x3e, 0x7400); 1518 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); 1519 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1520 RT5645_MAMP_INT_REG2, 0xfc00); 1521 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); 1522 msleep(70); 1523 rt5645->hp_on = true; 1524 } else { 1525 /* depop parameters */ 1526 snd_soc_update_bits(codec, RT5645_DEPOP_M2, 1527 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1528 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); 1529 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1530 RT5645_HP_DCC_INT1, 0x9f01); 1531 mdelay(150); 1532 /* headphone amp power on */ 1533 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1534 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); 1535 snd_soc_update_bits(codec, RT5645_PWR_VOL, 1536 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1537 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1538 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1539 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1540 RT5645_PWR_HA, 1541 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1542 RT5645_PWR_HA); 1543 mdelay(5); 1544 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1545 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1546 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1547 1548 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1549 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1550 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1551 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1552 0x14, 0x1aaa); 1553 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1554 0x24, 0x0430); 1555 } 1556 } 1557 hp_amp_power_count++; 1558 } else { 1559 hp_amp_power_count--; 1560 if (hp_amp_power_count <= 0) { 1561 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1562 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1563 0x3e, 0x7400); 1564 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); 1565 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1566 RT5645_MAMP_INT_REG2, 0xfc00); 1567 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); 1568 msleep(100); 1569 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001); 1570 1571 } else { 1572 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1573 RT5645_HP_SG_MASK | 1574 RT5645_HP_L_SMT_MASK | 1575 RT5645_HP_R_SMT_MASK, 1576 RT5645_HP_SG_DIS | 1577 RT5645_HP_L_SMT_DIS | 1578 RT5645_HP_R_SMT_DIS); 1579 /* headphone amp power down */ 1580 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000); 1581 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1582 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1583 RT5645_PWR_HA, 0); 1584 snd_soc_update_bits(codec, RT5645_DEPOP_M2, 1585 RT5645_DEPOP_MASK, 0); 1586 } 1587 } 1588 } 1589 } 1590 1591 static int rt5645_hp_event(struct snd_soc_dapm_widget *w, 1592 struct snd_kcontrol *kcontrol, int event) 1593 { 1594 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1595 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 1596 1597 switch (event) { 1598 case SND_SOC_DAPM_POST_PMU: 1599 hp_amp_power(codec, 1); 1600 /* headphone unmute sequence */ 1601 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1602 snd_soc_update_bits(codec, RT5645_DEPOP_M3, 1603 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1604 RT5645_CP_FQ3_MASK, 1605 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1606 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1607 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1608 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1609 RT5645_MAMP_INT_REG2, 0xfc00); 1610 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1611 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); 1612 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1613 RT5645_RSTN_MASK, RT5645_RSTN_EN); 1614 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1615 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | 1616 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | 1617 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1618 msleep(40); 1619 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1620 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1621 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1622 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1623 } 1624 break; 1625 1626 case SND_SOC_DAPM_PRE_PMD: 1627 /* headphone mute sequence */ 1628 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1629 snd_soc_update_bits(codec, RT5645_DEPOP_M3, 1630 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1631 RT5645_CP_FQ3_MASK, 1632 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1633 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1634 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1635 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1636 RT5645_MAMP_INT_REG2, 0xfc00); 1637 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1638 RT5645_HP_SG_MASK, RT5645_HP_SG_EN); 1639 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1640 RT5645_RSTP_MASK, RT5645_RSTP_EN); 1641 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1642 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | 1643 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | 1644 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1645 msleep(30); 1646 } 1647 hp_amp_power(codec, 0); 1648 break; 1649 1650 default: 1651 return 0; 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int rt5645_spk_event(struct snd_soc_dapm_widget *w, 1658 struct snd_kcontrol *kcontrol, int event) 1659 { 1660 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1661 1662 switch (event) { 1663 case SND_SOC_DAPM_POST_PMU: 1664 rt5645_enable_hweq(codec); 1665 snd_soc_update_bits(codec, RT5645_PWR_DIG1, 1666 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1667 RT5645_PWR_CLS_D_L, 1668 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1669 RT5645_PWR_CLS_D_L); 1670 break; 1671 1672 case SND_SOC_DAPM_PRE_PMD: 1673 snd_soc_write(codec, RT5645_EQ_CTRL2, 0); 1674 snd_soc_update_bits(codec, RT5645_PWR_DIG1, 1675 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1676 RT5645_PWR_CLS_D_L, 0); 1677 break; 1678 1679 default: 1680 return 0; 1681 } 1682 1683 return 0; 1684 } 1685 1686 static int rt5645_lout_event(struct snd_soc_dapm_widget *w, 1687 struct snd_kcontrol *kcontrol, int event) 1688 { 1689 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1690 1691 switch (event) { 1692 case SND_SOC_DAPM_POST_PMU: 1693 hp_amp_power(codec, 1); 1694 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1695 RT5645_PWR_LM, RT5645_PWR_LM); 1696 snd_soc_update_bits(codec, RT5645_LOUT1, 1697 RT5645_L_MUTE | RT5645_R_MUTE, 0); 1698 break; 1699 1700 case SND_SOC_DAPM_PRE_PMD: 1701 snd_soc_update_bits(codec, RT5645_LOUT1, 1702 RT5645_L_MUTE | RT5645_R_MUTE, 1703 RT5645_L_MUTE | RT5645_R_MUTE); 1704 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1705 RT5645_PWR_LM, 0); 1706 hp_amp_power(codec, 0); 1707 break; 1708 1709 default: 1710 return 0; 1711 } 1712 1713 return 0; 1714 } 1715 1716 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, 1717 struct snd_kcontrol *kcontrol, int event) 1718 { 1719 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1720 1721 switch (event) { 1722 case SND_SOC_DAPM_POST_PMU: 1723 snd_soc_update_bits(codec, RT5645_PWR_ANLG2, 1724 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); 1725 break; 1726 1727 case SND_SOC_DAPM_PRE_PMD: 1728 snd_soc_update_bits(codec, RT5645_PWR_ANLG2, 1729 RT5645_PWR_BST2_P, 0); 1730 break; 1731 1732 default: 1733 return 0; 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int rt5650_hp_event(struct snd_soc_dapm_widget *w, 1740 struct snd_kcontrol *k, int event) 1741 { 1742 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1743 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 1744 1745 switch (event) { 1746 case SND_SOC_DAPM_POST_PMU: 1747 if (rt5645->hp_on) { 1748 msleep(100); 1749 rt5645->hp_on = false; 1750 } 1751 break; 1752 1753 default: 1754 return 0; 1755 } 1756 1757 return 0; 1758 } 1759 1760 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { 1761 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, 1762 RT5645_PWR_LDO2_BIT, 0, NULL, 0), 1763 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, 1764 RT5645_PWR_PLL_BIT, 0, NULL, 0), 1765 1766 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, 1767 RT5645_PWR_JD1_BIT, 0, NULL, 0), 1768 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, 1769 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), 1770 1771 /* ASRC */ 1772 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, 1773 11, 0, NULL, 0), 1774 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, 1775 12, 0, NULL, 0), 1776 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, 1777 10, 0, NULL, 0), 1778 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, 1779 9, 0, NULL, 0), 1780 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, 1781 8, 0, NULL, 0), 1782 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, 1783 7, 0, NULL, 0), 1784 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, 1785 5, 0, NULL, 0), 1786 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, 1787 4, 0, NULL, 0), 1788 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, 1789 3, 0, NULL, 0), 1790 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, 1791 1, 0, NULL, 0), 1792 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, 1793 0, 0, NULL, 0), 1794 1795 /* Input Side */ 1796 /* micbias */ 1797 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2, 1798 RT5645_PWR_MB1_BIT, 0), 1799 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2, 1800 RT5645_PWR_MB2_BIT, 0), 1801 /* Input Lines */ 1802 SND_SOC_DAPM_INPUT("DMIC L1"), 1803 SND_SOC_DAPM_INPUT("DMIC R1"), 1804 SND_SOC_DAPM_INPUT("DMIC L2"), 1805 SND_SOC_DAPM_INPUT("DMIC R2"), 1806 1807 SND_SOC_DAPM_INPUT("IN1P"), 1808 SND_SOC_DAPM_INPUT("IN1N"), 1809 SND_SOC_DAPM_INPUT("IN2P"), 1810 SND_SOC_DAPM_INPUT("IN2N"), 1811 1812 SND_SOC_DAPM_INPUT("Haptic Generator"), 1813 1814 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1815 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1816 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1817 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1818 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, 1819 RT5645_DMIC_1_EN_SFT, 0, NULL, 0), 1820 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, 1821 RT5645_DMIC_2_EN_SFT, 0, NULL, 0), 1822 /* Boost */ 1823 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, 1824 RT5645_PWR_BST1_BIT, 0, NULL, 0), 1825 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, 1826 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, 1827 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 1828 /* Input Volume */ 1829 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, 1830 RT5645_PWR_IN_L_BIT, 0, NULL, 0), 1831 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, 1832 RT5645_PWR_IN_R_BIT, 0, NULL, 0), 1833 /* REC Mixer */ 1834 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, 1835 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), 1836 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, 1837 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), 1838 /* ADCs */ 1839 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 1840 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 1841 1842 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, 1843 RT5645_PWR_ADC_L_BIT, 0, NULL, 0), 1844 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, 1845 RT5645_PWR_ADC_R_BIT, 0, NULL, 0), 1846 1847 /* ADC Mux */ 1848 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 1849 &rt5645_sto1_dmic_mux), 1850 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1851 &rt5645_sto_adc2_mux), 1852 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1853 &rt5645_sto_adc2_mux), 1854 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1855 &rt5645_sto_adc1_mux), 1856 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1857 &rt5645_sto_adc1_mux), 1858 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 1859 &rt5645_mono_dmic_l_mux), 1860 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 1861 &rt5645_mono_dmic_r_mux), 1862 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1863 &rt5645_mono_adc_l2_mux), 1864 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1865 &rt5645_mono_adc_l1_mux), 1866 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1867 &rt5645_mono_adc_r1_mux), 1868 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1869 &rt5645_mono_adc_r2_mux), 1870 /* ADC Mixer */ 1871 1872 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, 1873 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), 1874 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 1875 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), 1876 NULL, 0), 1877 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 1878 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), 1879 NULL, 0), 1880 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, 1881 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), 1882 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 1883 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), 1884 NULL, 0), 1885 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, 1886 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), 1887 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 1888 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), 1889 NULL, 0), 1890 1891 /* ADC PGA */ 1892 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 1893 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 1894 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1895 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 1896 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1897 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1898 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1899 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1900 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 1901 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 1902 1903 /* IF1 2 Mux */ 1904 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 1905 0, 0, &rt5645_if2_adc_in_mux), 1906 1907 /* Digital Interface */ 1908 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 1909 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 1910 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 1911 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1912 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1913 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 1914 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 1915 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1916 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1917 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, 1918 RT5645_PWR_I2S2_BIT, 0, NULL, 0), 1919 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 1920 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1921 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1922 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 1923 1924 /* Digital Interface Select */ 1925 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 1926 0, 0, &rt5645_vad_adc_mux), 1927 1928 /* Audio Interface */ 1929 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1930 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 1931 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1932 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1933 1934 /* Output Side */ 1935 /* DAC mixer before sound effect */ 1936 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1937 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), 1938 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1939 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), 1940 1941 /* DAC2 channel Mux */ 1942 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), 1943 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), 1944 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, 1945 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), 1946 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, 1947 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), 1948 1949 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), 1950 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), 1951 1952 /* DAC Mixer */ 1953 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, 1954 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), 1955 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, 1956 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), 1957 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, 1958 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), 1959 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 1960 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), 1961 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 1962 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), 1963 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 1964 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), 1965 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 1966 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), 1967 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 1968 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), 1969 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 1970 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), 1971 1972 /* DACs */ 1973 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, 1974 0), 1975 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, 1976 0), 1977 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, 1978 0), 1979 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, 1980 0), 1981 /* OUT Mixer */ 1982 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, 1983 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), 1984 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, 1985 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), 1986 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, 1987 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), 1988 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, 1989 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), 1990 /* Ouput Volume */ 1991 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, 1992 &spk_l_vol_control), 1993 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, 1994 &spk_r_vol_control), 1995 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, 1996 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), 1997 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, 1998 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), 1999 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, 2000 RT5645_PWR_HM_L_BIT, 0, NULL, 0), 2001 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, 2002 RT5645_PWR_HM_R_BIT, 0, NULL, 0), 2003 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), 2004 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), 2005 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), 2006 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), 2007 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), 2008 2009 /* HPO/LOUT/Mono Mixer */ 2010 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, 2011 ARRAY_SIZE(rt5645_spo_l_mix)), 2012 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, 2013 ARRAY_SIZE(rt5645_spo_r_mix)), 2014 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, 2015 ARRAY_SIZE(rt5645_hpo_mix)), 2016 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, 2017 ARRAY_SIZE(rt5645_lout_mix)), 2018 2019 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, 2020 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2021 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, 2022 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2023 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, 2024 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2025 2026 /* PDM */ 2027 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, 2028 0, NULL, 0), 2029 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), 2030 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), 2031 2032 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), 2033 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), 2034 2035 /* Output Lines */ 2036 SND_SOC_DAPM_OUTPUT("HPOL"), 2037 SND_SOC_DAPM_OUTPUT("HPOR"), 2038 SND_SOC_DAPM_OUTPUT("LOUTL"), 2039 SND_SOC_DAPM_OUTPUT("LOUTR"), 2040 SND_SOC_DAPM_OUTPUT("PDM1L"), 2041 SND_SOC_DAPM_OUTPUT("PDM1R"), 2042 SND_SOC_DAPM_OUTPUT("SPOL"), 2043 SND_SOC_DAPM_OUTPUT("SPOR"), 2044 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event), 2045 }; 2046 2047 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { 2048 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2049 &rt5645_if1_dac0_tdm_sel_mux), 2050 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2051 &rt5645_if1_dac1_tdm_sel_mux), 2052 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2053 &rt5645_if1_dac2_tdm_sel_mux), 2054 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2055 &rt5645_if1_dac3_tdm_sel_mux), 2056 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, 2057 0, 0, &rt5645_if1_adc_in_mux), 2058 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2059 0, 0, &rt5645_if1_adc1_in_mux), 2060 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2061 0, 0, &rt5645_if1_adc2_in_mux), 2062 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2063 0, 0, &rt5645_if1_adc3_in_mux), 2064 }; 2065 2066 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { 2067 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, 2068 0, 0, &rt5650_a_dac1_l_mux), 2069 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, 2070 0, 0, &rt5650_a_dac1_r_mux), 2071 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, 2072 0, 0, &rt5650_a_dac2_l_mux), 2073 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, 2074 0, 0, &rt5650_a_dac2_r_mux), 2075 2076 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2077 0, 0, &rt5650_if1_adc1_in_mux), 2078 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2079 0, 0, &rt5650_if1_adc2_in_mux), 2080 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2081 0, 0, &rt5650_if1_adc3_in_mux), 2082 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, 2083 0, 0, &rt5650_if1_adc_in_mux), 2084 2085 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2086 &rt5650_if1_dac0_tdm_sel_mux), 2087 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2088 &rt5650_if1_dac1_tdm_sel_mux), 2089 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2090 &rt5650_if1_dac2_tdm_sel_mux), 2091 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2092 &rt5650_if1_dac3_tdm_sel_mux), 2093 }; 2094 2095 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { 2096 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2097 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2098 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2099 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, 2100 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, 2101 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2102 2103 { "I2S1", NULL, "I2S1 ASRC" }, 2104 { "I2S2", NULL, "I2S2 ASRC" }, 2105 2106 { "IN1P", NULL, "LDO2" }, 2107 { "IN2P", NULL, "LDO2" }, 2108 2109 { "DMIC1", NULL, "DMIC L1" }, 2110 { "DMIC1", NULL, "DMIC R1" }, 2111 { "DMIC2", NULL, "DMIC L2" }, 2112 { "DMIC2", NULL, "DMIC R2" }, 2113 2114 { "BST1", NULL, "IN1P" }, 2115 { "BST1", NULL, "IN1N" }, 2116 { "BST1", NULL, "JD Power" }, 2117 { "BST1", NULL, "Mic Det Power" }, 2118 { "BST2", NULL, "IN2P" }, 2119 { "BST2", NULL, "IN2N" }, 2120 2121 { "INL VOL", NULL, "IN2P" }, 2122 { "INR VOL", NULL, "IN2N" }, 2123 2124 { "RECMIXL", "HPOL Switch", "HPOL" }, 2125 { "RECMIXL", "INL Switch", "INL VOL" }, 2126 { "RECMIXL", "BST2 Switch", "BST2" }, 2127 { "RECMIXL", "BST1 Switch", "BST1" }, 2128 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 2129 2130 { "RECMIXR", "HPOR Switch", "HPOR" }, 2131 { "RECMIXR", "INR Switch", "INR VOL" }, 2132 { "RECMIXR", "BST2 Switch", "BST2" }, 2133 { "RECMIXR", "BST1 Switch", "BST1" }, 2134 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 2135 2136 { "ADC L", NULL, "RECMIXL" }, 2137 { "ADC L", NULL, "ADC L power" }, 2138 { "ADC R", NULL, "RECMIXR" }, 2139 { "ADC R", NULL, "ADC R power" }, 2140 2141 {"DMIC L1", NULL, "DMIC CLK"}, 2142 {"DMIC L1", NULL, "DMIC1 Power"}, 2143 {"DMIC R1", NULL, "DMIC CLK"}, 2144 {"DMIC R1", NULL, "DMIC1 Power"}, 2145 {"DMIC L2", NULL, "DMIC CLK"}, 2146 {"DMIC L2", NULL, "DMIC2 Power"}, 2147 {"DMIC R2", NULL, "DMIC CLK"}, 2148 {"DMIC R2", NULL, "DMIC2 Power"}, 2149 2150 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2151 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2152 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, 2153 2154 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, 2155 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, 2156 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, 2157 2158 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, 2159 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, 2160 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, 2161 2162 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2163 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2164 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, 2165 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2166 2167 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, 2168 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2169 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2170 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2171 2172 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2173 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2174 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2175 { "Mono ADC L1 Mux", "ADC", "ADC L" }, 2176 2177 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2178 { "Mono ADC R1 Mux", "ADC", "ADC R" }, 2179 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2180 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2181 2182 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2183 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2184 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2185 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2186 2187 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2188 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2189 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2190 2191 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2192 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2193 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2194 2195 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2196 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2197 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2198 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2199 2200 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2201 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2202 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2203 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2204 2205 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, 2206 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, 2207 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, 2208 2209 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, 2210 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, 2211 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 2212 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2213 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2214 2215 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2216 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2217 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2218 2219 { "IF1 ADC", NULL, "I2S1" }, 2220 { "IF2 ADC", NULL, "I2S2" }, 2221 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2222 2223 { "AIF2TX", NULL, "IF2 ADC" }, 2224 2225 { "IF1 DAC0", NULL, "AIF1RX" }, 2226 { "IF1 DAC1", NULL, "AIF1RX" }, 2227 { "IF1 DAC2", NULL, "AIF1RX" }, 2228 { "IF1 DAC3", NULL, "AIF1RX" }, 2229 { "IF2 DAC", NULL, "AIF2RX" }, 2230 2231 { "IF1 DAC0", NULL, "I2S1" }, 2232 { "IF1 DAC1", NULL, "I2S1" }, 2233 { "IF1 DAC2", NULL, "I2S1" }, 2234 { "IF1 DAC3", NULL, "I2S1" }, 2235 { "IF2 DAC", NULL, "I2S2" }, 2236 2237 { "IF2 DAC L", NULL, "IF2 DAC" }, 2238 { "IF2 DAC R", NULL, "IF2 DAC" }, 2239 2240 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2241 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2242 2243 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2244 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, 2245 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 2246 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 2247 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2248 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2249 2250 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2251 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2252 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2253 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2254 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2255 2256 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2257 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2258 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2259 { "DAC R2 Volume", NULL, "DAC R2 Mux" }, 2260 { "DAC R2 Volume", NULL, "dac mono right filter" }, 2261 2262 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2263 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 2264 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2265 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 2266 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2267 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 2268 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2269 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 2270 2271 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2272 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2273 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2274 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 2275 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2276 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2277 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2278 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 2279 2280 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 2281 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2282 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2283 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 2284 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2285 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2286 2287 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, 2288 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, 2289 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, 2290 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, 2291 2292 { "SPK MIXL", "BST1 Switch", "BST1" }, 2293 { "SPK MIXL", "INL Switch", "INL VOL" }, 2294 { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, 2295 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 2296 { "SPK MIXR", "BST2 Switch", "BST2" }, 2297 { "SPK MIXR", "INR Switch", "INR VOL" }, 2298 { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, 2299 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 2300 2301 { "OUT MIXL", "BST1 Switch", "BST1" }, 2302 { "OUT MIXL", "INL Switch", "INL VOL" }, 2303 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 2304 { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, 2305 2306 { "OUT MIXR", "BST2 Switch", "BST2" }, 2307 { "OUT MIXR", "INR Switch", "INR VOL" }, 2308 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 2309 { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, 2310 2311 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, 2312 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, 2313 { "HPOVOL MIXL", "INL Switch", "INL VOL" }, 2314 { "HPOVOL MIXL", "BST1 Switch", "BST1" }, 2315 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, 2316 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, 2317 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, 2318 { "HPOVOL MIXR", "INR Switch", "INR VOL" }, 2319 { "HPOVOL MIXR", "BST2 Switch", "BST2" }, 2320 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, 2321 2322 { "DAC 2", NULL, "DAC L2" }, 2323 { "DAC 2", NULL, "DAC R2" }, 2324 { "DAC 1", NULL, "DAC L1" }, 2325 { "DAC 1", NULL, "DAC R1" }, 2326 { "HPOVOL L", "Switch", "HPOVOL MIXL" }, 2327 { "HPOVOL R", "Switch", "HPOVOL MIXR" }, 2328 { "HPOVOL", NULL, "HPOVOL L" }, 2329 { "HPOVOL", NULL, "HPOVOL R" }, 2330 { "HPO MIX", "DAC1 Switch", "DAC 1" }, 2331 { "HPO MIX", "HPVOL Switch", "HPOVOL" }, 2332 2333 { "SPKVOL L", "Switch", "SPK MIXL" }, 2334 { "SPKVOL R", "Switch", "SPK MIXR" }, 2335 2336 { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, 2337 { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, 2338 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, 2339 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, 2340 { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, 2341 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, 2342 2343 { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, 2344 { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, 2345 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, 2346 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, 2347 2348 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 2349 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, 2350 { "PDM1 L Mux", NULL, "PDM1 Power" }, 2351 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 2352 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, 2353 { "PDM1 R Mux", NULL, "PDM1 Power" }, 2354 2355 { "HP amp", NULL, "HPO MIX" }, 2356 { "HP amp", NULL, "JD Power" }, 2357 { "HP amp", NULL, "Mic Det Power" }, 2358 { "HP amp", NULL, "LDO2" }, 2359 { "HPOL", NULL, "HP amp" }, 2360 { "HPOR", NULL, "HP amp" }, 2361 2362 { "LOUT amp", NULL, "LOUT MIX" }, 2363 { "LOUTL", NULL, "LOUT amp" }, 2364 { "LOUTR", NULL, "LOUT amp" }, 2365 2366 { "PDM1 L", "Switch", "PDM1 L Mux" }, 2367 { "PDM1 R", "Switch", "PDM1 R Mux" }, 2368 2369 { "PDM1L", NULL, "PDM1 L" }, 2370 { "PDM1R", NULL, "PDM1 R" }, 2371 2372 { "SPK amp", NULL, "SPOL MIX" }, 2373 { "SPK amp", NULL, "SPOR MIX" }, 2374 { "SPOL", NULL, "SPK amp" }, 2375 { "SPOR", NULL, "SPK amp" }, 2376 }; 2377 2378 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { 2379 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, 2380 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2381 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, 2382 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2383 2384 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2385 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, 2386 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2387 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, 2388 2389 { "DAC L1", NULL, "A DAC1 L Mux" }, 2390 { "DAC R1", NULL, "A DAC1 R Mux" }, 2391 { "DAC L2", NULL, "A DAC2 L Mux" }, 2392 { "DAC R2", NULL, "A DAC2 R Mux" }, 2393 2394 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2395 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2396 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2397 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2398 2399 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2400 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2401 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2402 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2403 2404 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2405 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2406 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2407 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2408 2409 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, 2410 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, 2411 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, 2412 2413 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, 2414 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, 2415 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, 2416 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, 2417 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, 2418 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, 2419 2420 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, 2421 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, 2422 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, 2423 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, 2424 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, 2425 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, 2426 2427 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, 2428 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, 2429 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, 2430 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, 2431 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2432 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2433 2434 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, 2435 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, 2436 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, 2437 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, 2438 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2439 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2440 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, 2441 2442 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2443 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2444 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2445 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2446 2447 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2448 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2449 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2450 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2451 2452 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2453 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2454 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2455 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2456 2457 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2458 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2459 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2460 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2461 2462 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, 2463 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, 2464 2465 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, 2466 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, 2467 }; 2468 2469 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2470 { "DAC L1", NULL, "Stereo DAC MIXL" }, 2471 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2472 { "DAC L2", NULL, "Mono DAC MIXL" }, 2473 { "DAC R2", NULL, "Mono DAC MIXR" }, 2474 2475 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2476 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2477 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2478 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2479 2480 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2481 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2482 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2483 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2484 2485 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2486 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2487 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2488 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2489 2490 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, 2491 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, 2492 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, 2493 2494 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, 2495 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, 2496 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2497 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2498 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, 2499 2500 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2501 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2502 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2503 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2504 2505 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2506 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2507 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2508 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2509 2510 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2511 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2512 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2513 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2514 2515 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2516 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2517 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2518 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2519 2520 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, 2521 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, 2522 2523 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, 2524 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, 2525 }; 2526 2527 static int rt5645_hw_params(struct snd_pcm_substream *substream, 2528 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2529 { 2530 struct snd_soc_codec *codec = dai->codec; 2531 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2532 unsigned int val_len = 0, val_clk, mask_clk, dl_sft; 2533 int pre_div, bclk_ms, frame_size; 2534 2535 rt5645->lrck[dai->id] = params_rate(params); 2536 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 2537 if (pre_div < 0) { 2538 dev_err(codec->dev, "Unsupported clock setting\n"); 2539 return -EINVAL; 2540 } 2541 frame_size = snd_soc_params_to_frame_size(params); 2542 if (frame_size < 0) { 2543 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 2544 return -EINVAL; 2545 } 2546 2547 switch (rt5645->codec_type) { 2548 case CODEC_TYPE_RT5650: 2549 dl_sft = 4; 2550 break; 2551 default: 2552 dl_sft = 2; 2553 break; 2554 } 2555 2556 bclk_ms = frame_size > 32; 2557 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); 2558 2559 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 2560 rt5645->bclk[dai->id], rt5645->lrck[dai->id]); 2561 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 2562 bclk_ms, pre_div, dai->id); 2563 2564 switch (params_width(params)) { 2565 case 16: 2566 break; 2567 case 20: 2568 val_len = 0x1; 2569 break; 2570 case 24: 2571 val_len = 0x2; 2572 break; 2573 case 8: 2574 val_len = 0x3; 2575 break; 2576 default: 2577 return -EINVAL; 2578 } 2579 2580 switch (dai->id) { 2581 case RT5645_AIF1: 2582 mask_clk = RT5645_I2S_PD1_MASK; 2583 val_clk = pre_div << RT5645_I2S_PD1_SFT; 2584 snd_soc_update_bits(codec, RT5645_I2S1_SDP, 2585 (0x3 << dl_sft), (val_len << dl_sft)); 2586 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); 2587 break; 2588 case RT5645_AIF2: 2589 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; 2590 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | 2591 pre_div << RT5645_I2S_PD2_SFT; 2592 snd_soc_update_bits(codec, RT5645_I2S2_SDP, 2593 (0x3 << dl_sft), (val_len << dl_sft)); 2594 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); 2595 break; 2596 default: 2597 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 2598 return -EINVAL; 2599 } 2600 2601 return 0; 2602 } 2603 2604 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2605 { 2606 struct snd_soc_codec *codec = dai->codec; 2607 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2608 unsigned int reg_val = 0, pol_sft; 2609 2610 switch (rt5645->codec_type) { 2611 case CODEC_TYPE_RT5650: 2612 pol_sft = 8; 2613 break; 2614 default: 2615 pol_sft = 7; 2616 break; 2617 } 2618 2619 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2620 case SND_SOC_DAIFMT_CBM_CFM: 2621 rt5645->master[dai->id] = 1; 2622 break; 2623 case SND_SOC_DAIFMT_CBS_CFS: 2624 reg_val |= RT5645_I2S_MS_S; 2625 rt5645->master[dai->id] = 0; 2626 break; 2627 default: 2628 return -EINVAL; 2629 } 2630 2631 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2632 case SND_SOC_DAIFMT_NB_NF: 2633 break; 2634 case SND_SOC_DAIFMT_IB_NF: 2635 reg_val |= (1 << pol_sft); 2636 break; 2637 default: 2638 return -EINVAL; 2639 } 2640 2641 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2642 case SND_SOC_DAIFMT_I2S: 2643 break; 2644 case SND_SOC_DAIFMT_LEFT_J: 2645 reg_val |= RT5645_I2S_DF_LEFT; 2646 break; 2647 case SND_SOC_DAIFMT_DSP_A: 2648 reg_val |= RT5645_I2S_DF_PCM_A; 2649 break; 2650 case SND_SOC_DAIFMT_DSP_B: 2651 reg_val |= RT5645_I2S_DF_PCM_B; 2652 break; 2653 default: 2654 return -EINVAL; 2655 } 2656 switch (dai->id) { 2657 case RT5645_AIF1: 2658 snd_soc_update_bits(codec, RT5645_I2S1_SDP, 2659 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2660 RT5645_I2S_DF_MASK, reg_val); 2661 break; 2662 case RT5645_AIF2: 2663 snd_soc_update_bits(codec, RT5645_I2S2_SDP, 2664 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2665 RT5645_I2S_DF_MASK, reg_val); 2666 break; 2667 default: 2668 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 2669 return -EINVAL; 2670 } 2671 return 0; 2672 } 2673 2674 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, 2675 int clk_id, unsigned int freq, int dir) 2676 { 2677 struct snd_soc_codec *codec = dai->codec; 2678 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2679 unsigned int reg_val = 0; 2680 2681 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) 2682 return 0; 2683 2684 switch (clk_id) { 2685 case RT5645_SCLK_S_MCLK: 2686 reg_val |= RT5645_SCLK_SRC_MCLK; 2687 break; 2688 case RT5645_SCLK_S_PLL1: 2689 reg_val |= RT5645_SCLK_SRC_PLL1; 2690 break; 2691 case RT5645_SCLK_S_RCCLK: 2692 reg_val |= RT5645_SCLK_SRC_RCCLK; 2693 break; 2694 default: 2695 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 2696 return -EINVAL; 2697 } 2698 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2699 RT5645_SCLK_SRC_MASK, reg_val); 2700 rt5645->sysclk = freq; 2701 rt5645->sysclk_src = clk_id; 2702 2703 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 2704 2705 return 0; 2706 } 2707 2708 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2709 unsigned int freq_in, unsigned int freq_out) 2710 { 2711 struct snd_soc_codec *codec = dai->codec; 2712 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2713 struct rl6231_pll_code pll_code; 2714 int ret; 2715 2716 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 2717 freq_out == rt5645->pll_out) 2718 return 0; 2719 2720 if (!freq_in || !freq_out) { 2721 dev_dbg(codec->dev, "PLL disabled\n"); 2722 2723 rt5645->pll_in = 0; 2724 rt5645->pll_out = 0; 2725 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2726 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); 2727 return 0; 2728 } 2729 2730 switch (source) { 2731 case RT5645_PLL1_S_MCLK: 2732 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2733 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); 2734 break; 2735 case RT5645_PLL1_S_BCLK1: 2736 case RT5645_PLL1_S_BCLK2: 2737 switch (dai->id) { 2738 case RT5645_AIF1: 2739 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2740 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); 2741 break; 2742 case RT5645_AIF2: 2743 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2744 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); 2745 break; 2746 default: 2747 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 2748 return -EINVAL; 2749 } 2750 break; 2751 default: 2752 dev_err(codec->dev, "Unknown PLL source %d\n", source); 2753 return -EINVAL; 2754 } 2755 2756 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2757 if (ret < 0) { 2758 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 2759 return ret; 2760 } 2761 2762 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", 2763 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2764 pll_code.n_code, pll_code.k_code); 2765 2766 snd_soc_write(codec, RT5645_PLL_CTRL1, 2767 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); 2768 snd_soc_write(codec, RT5645_PLL_CTRL2, 2769 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT | 2770 pll_code.m_bp << RT5645_PLL_M_BP_SFT); 2771 2772 rt5645->pll_in = freq_in; 2773 rt5645->pll_out = freq_out; 2774 rt5645->pll_src = source; 2775 2776 return 0; 2777 } 2778 2779 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2780 unsigned int rx_mask, int slots, int slot_width) 2781 { 2782 struct snd_soc_codec *codec = dai->codec; 2783 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2784 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; 2785 unsigned int mask, val = 0; 2786 2787 switch (rt5645->codec_type) { 2788 case CODEC_TYPE_RT5650: 2789 en_sft = 15; 2790 i_slot_sft = 10; 2791 o_slot_sft = 8; 2792 i_width_sht = 6; 2793 o_width_sht = 4; 2794 mask = 0x8ff0; 2795 break; 2796 default: 2797 en_sft = 14; 2798 i_slot_sft = o_slot_sft = 12; 2799 i_width_sht = o_width_sht = 10; 2800 mask = 0x7c00; 2801 break; 2802 } 2803 if (rx_mask || tx_mask) { 2804 val |= (1 << en_sft); 2805 if (rt5645->codec_type == CODEC_TYPE_RT5645) 2806 snd_soc_update_bits(codec, RT5645_BASS_BACK, 2807 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); 2808 } 2809 2810 switch (slots) { 2811 case 4: 2812 val |= (1 << i_slot_sft) | (1 << o_slot_sft); 2813 break; 2814 case 6: 2815 val |= (2 << i_slot_sft) | (2 << o_slot_sft); 2816 break; 2817 case 8: 2818 val |= (3 << i_slot_sft) | (3 << o_slot_sft); 2819 break; 2820 case 2: 2821 default: 2822 break; 2823 } 2824 2825 switch (slot_width) { 2826 case 20: 2827 val |= (1 << i_width_sht) | (1 << o_width_sht); 2828 break; 2829 case 24: 2830 val |= (2 << i_width_sht) | (2 << o_width_sht); 2831 break; 2832 case 32: 2833 val |= (3 << i_width_sht) | (3 << o_width_sht); 2834 break; 2835 case 16: 2836 default: 2837 break; 2838 } 2839 2840 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val); 2841 2842 return 0; 2843 } 2844 2845 static int rt5645_set_bias_level(struct snd_soc_codec *codec, 2846 enum snd_soc_bias_level level) 2847 { 2848 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2849 2850 switch (level) { 2851 case SND_SOC_BIAS_PREPARE: 2852 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) { 2853 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2854 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2855 RT5645_PWR_BG | RT5645_PWR_VREF2, 2856 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2857 RT5645_PWR_BG | RT5645_PWR_VREF2); 2858 mdelay(10); 2859 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2860 RT5645_PWR_FV1 | RT5645_PWR_FV2, 2861 RT5645_PWR_FV1 | RT5645_PWR_FV2); 2862 snd_soc_update_bits(codec, RT5645_GEN_CTRL1, 2863 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 2864 } 2865 break; 2866 2867 case SND_SOC_BIAS_STANDBY: 2868 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2869 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2870 RT5645_PWR_BG | RT5645_PWR_VREF2, 2871 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2872 RT5645_PWR_BG | RT5645_PWR_VREF2); 2873 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2874 RT5645_PWR_FV1 | RT5645_PWR_FV2, 2875 RT5645_PWR_FV1 | RT5645_PWR_FV2); 2876 if (rt5645->en_button_func && 2877 snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) 2878 queue_delayed_work(system_power_efficient_wq, 2879 &rt5645->jack_detect_work, msecs_to_jiffies(0)); 2880 break; 2881 2882 case SND_SOC_BIAS_OFF: 2883 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100); 2884 if (!rt5645->en_button_func) 2885 snd_soc_update_bits(codec, RT5645_GEN_CTRL1, 2886 RT5645_DIG_GATE_CTRL, 0); 2887 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2888 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2889 RT5645_PWR_BG | RT5645_PWR_VREF2 | 2890 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); 2891 break; 2892 2893 default: 2894 break; 2895 } 2896 2897 return 0; 2898 } 2899 2900 static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec, 2901 bool enable) 2902 { 2903 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 2904 2905 if (enable) { 2906 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 2907 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 2908 snd_soc_dapm_sync(dapm); 2909 2910 snd_soc_update_bits(codec, 2911 RT5645_INT_IRQ_ST, 0x8, 0x8); 2912 snd_soc_update_bits(codec, 2913 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); 2914 snd_soc_read(codec, RT5650_4BTN_IL_CMD1); 2915 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 2916 snd_soc_read(codec, RT5650_4BTN_IL_CMD1)); 2917 } else { 2918 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 2919 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0); 2920 2921 snd_soc_dapm_disable_pin(dapm, "ADC L power"); 2922 snd_soc_dapm_disable_pin(dapm, "ADC R power"); 2923 snd_soc_dapm_sync(dapm); 2924 } 2925 } 2926 2927 static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert) 2928 { 2929 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 2930 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2931 unsigned int val; 2932 2933 if (jack_insert) { 2934 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006); 2935 2936 /* for jack type detect */ 2937 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 2938 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 2939 snd_soc_dapm_sync(dapm); 2940 if (!dapm->card->instantiated) { 2941 /* Power up necessary bits for JD if dapm is 2942 not ready yet */ 2943 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, 2944 RT5645_PWR_MB | RT5645_PWR_VREF2, 2945 RT5645_PWR_MB | RT5645_PWR_VREF2); 2946 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, 2947 RT5645_PWR_LDO2, RT5645_PWR_LDO2); 2948 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, 2949 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); 2950 } 2951 2952 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); 2953 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 2954 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 2955 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 2956 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 2957 msleep(100); 2958 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 2959 RT5645_CBJ_MN_JD, 0); 2960 2961 msleep(600); 2962 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); 2963 val &= 0x7; 2964 dev_dbg(codec->dev, "val = %d\n", val); 2965 2966 if (val == 1 || val == 2) { 2967 rt5645->jack_type = SND_JACK_HEADSET; 2968 if (rt5645->en_button_func) { 2969 rt5645_enable_push_button_irq(codec, true); 2970 } 2971 } else { 2972 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 2973 snd_soc_dapm_sync(dapm); 2974 rt5645->jack_type = SND_JACK_HEADPHONE; 2975 } 2976 if (rt5645->pdata.jd_invert) 2977 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 2978 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 2979 } else { /* jack out */ 2980 rt5645->jack_type = 0; 2981 2982 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, 2983 RT5645_L_MUTE | RT5645_R_MUTE, 2984 RT5645_L_MUTE | RT5645_R_MUTE); 2985 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 2986 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 2987 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 2988 RT5645_CBJ_BST1_EN, 0); 2989 2990 if (rt5645->en_button_func) 2991 rt5645_enable_push_button_irq(codec, false); 2992 2993 if (rt5645->pdata.jd_mode == 0) 2994 snd_soc_dapm_disable_pin(dapm, "LDO2"); 2995 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 2996 snd_soc_dapm_sync(dapm); 2997 if (rt5645->pdata.jd_invert) 2998 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 2999 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); 3000 } 3001 3002 return rt5645->jack_type; 3003 } 3004 3005 static int rt5645_button_detect(struct snd_soc_codec *codec) 3006 { 3007 int btn_type, val; 3008 3009 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1); 3010 pr_debug("val=0x%x\n", val); 3011 btn_type = val & 0xfff0; 3012 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val); 3013 3014 return btn_type; 3015 } 3016 3017 static irqreturn_t rt5645_irq(int irq, void *data); 3018 3019 int rt5645_set_jack_detect(struct snd_soc_codec *codec, 3020 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, 3021 struct snd_soc_jack *btn_jack) 3022 { 3023 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3024 3025 rt5645->hp_jack = hp_jack; 3026 rt5645->mic_jack = mic_jack; 3027 rt5645->btn_jack = btn_jack; 3028 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { 3029 rt5645->en_button_func = true; 3030 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3031 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3032 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, 3033 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3034 } 3035 rt5645_irq(0, rt5645); 3036 3037 return 0; 3038 } 3039 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); 3040 3041 static void rt5645_jack_detect_work(struct work_struct *work) 3042 { 3043 struct rt5645_priv *rt5645 = 3044 container_of(work, struct rt5645_priv, jack_detect_work.work); 3045 int val, btn_type, gpio_state = 0, report = 0; 3046 3047 if (!rt5645->codec) 3048 return; 3049 3050 switch (rt5645->pdata.jd_mode) { 3051 case 0: /* Not using rt5645 JD */ 3052 if (rt5645->gpiod_hp_det) { 3053 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); 3054 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n", 3055 gpio_state); 3056 report = rt5645_jack_detect(rt5645->codec, gpio_state); 3057 } 3058 snd_soc_jack_report(rt5645->hp_jack, 3059 report, SND_JACK_HEADPHONE); 3060 snd_soc_jack_report(rt5645->mic_jack, 3061 report, SND_JACK_MICROPHONE); 3062 return; 3063 case 1: /* 2 port */ 3064 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070; 3065 break; 3066 default: /* 1 port */ 3067 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020; 3068 break; 3069 3070 } 3071 3072 switch (val) { 3073 /* jack in */ 3074 case 0x30: /* 2 port */ 3075 case 0x0: /* 1 port or 2 port */ 3076 if (rt5645->jack_type == 0) { 3077 report = rt5645_jack_detect(rt5645->codec, 1); 3078 /* for push button and jack out */ 3079 break; 3080 } 3081 btn_type = 0; 3082 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) { 3083 /* button pressed */ 3084 report = SND_JACK_HEADSET; 3085 btn_type = rt5645_button_detect(rt5645->codec); 3086 /* rt5650 can report three kinds of button behavior, 3087 one click, double click and hold. However, 3088 currently we will report button pressed/released 3089 event. So all the three button behaviors are 3090 treated as button pressed. */ 3091 switch (btn_type) { 3092 case 0x8000: 3093 case 0x4000: 3094 case 0x2000: 3095 report |= SND_JACK_BTN_0; 3096 break; 3097 case 0x1000: 3098 case 0x0800: 3099 case 0x0400: 3100 report |= SND_JACK_BTN_1; 3101 break; 3102 case 0x0200: 3103 case 0x0100: 3104 case 0x0080: 3105 report |= SND_JACK_BTN_2; 3106 break; 3107 case 0x0040: 3108 case 0x0020: 3109 case 0x0010: 3110 report |= SND_JACK_BTN_3; 3111 break; 3112 case 0x0000: /* unpressed */ 3113 break; 3114 default: 3115 dev_err(rt5645->codec->dev, 3116 "Unexpected button code 0x%04x\n", 3117 btn_type); 3118 break; 3119 } 3120 } 3121 if (btn_type == 0)/* button release */ 3122 report = rt5645->jack_type; 3123 3124 break; 3125 /* jack out */ 3126 case 0x70: /* 2 port */ 3127 case 0x10: /* 2 port */ 3128 case 0x20: /* 1 port */ 3129 report = 0; 3130 snd_soc_update_bits(rt5645->codec, 3131 RT5645_INT_IRQ_ST, 0x1, 0x0); 3132 rt5645_jack_detect(rt5645->codec, 0); 3133 break; 3134 default: 3135 break; 3136 } 3137 3138 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); 3139 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); 3140 if (rt5645->en_button_func) 3141 snd_soc_jack_report(rt5645->btn_jack, 3142 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3143 SND_JACK_BTN_2 | SND_JACK_BTN_3); 3144 } 3145 3146 static void rt5645_rcclock_work(struct work_struct *work) 3147 { 3148 struct rt5645_priv *rt5645 = 3149 container_of(work, struct rt5645_priv, rcclock_work.work); 3150 3151 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3152 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); 3153 } 3154 3155 static irqreturn_t rt5645_irq(int irq, void *data) 3156 { 3157 struct rt5645_priv *rt5645 = data; 3158 3159 queue_delayed_work(system_power_efficient_wq, 3160 &rt5645->jack_detect_work, msecs_to_jiffies(250)); 3161 3162 return IRQ_HANDLED; 3163 } 3164 3165 static int rt5645_probe(struct snd_soc_codec *codec) 3166 { 3167 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3168 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3169 3170 rt5645->codec = codec; 3171 3172 switch (rt5645->codec_type) { 3173 case CODEC_TYPE_RT5645: 3174 snd_soc_dapm_new_controls(dapm, 3175 rt5645_specific_dapm_widgets, 3176 ARRAY_SIZE(rt5645_specific_dapm_widgets)); 3177 snd_soc_dapm_add_routes(dapm, 3178 rt5645_specific_dapm_routes, 3179 ARRAY_SIZE(rt5645_specific_dapm_routes)); 3180 break; 3181 case CODEC_TYPE_RT5650: 3182 snd_soc_dapm_new_controls(dapm, 3183 rt5650_specific_dapm_widgets, 3184 ARRAY_SIZE(rt5650_specific_dapm_widgets)); 3185 snd_soc_dapm_add_routes(dapm, 3186 rt5650_specific_dapm_routes, 3187 ARRAY_SIZE(rt5650_specific_dapm_routes)); 3188 break; 3189 } 3190 3191 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 3192 3193 /* for JD function */ 3194 if (rt5645->pdata.jd_mode) { 3195 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 3196 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3197 snd_soc_dapm_sync(dapm); 3198 } 3199 3200 rt5645->eq_param = devm_kzalloc(codec->dev, 3201 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s), GFP_KERNEL); 3202 3203 return 0; 3204 } 3205 3206 static int rt5645_remove(struct snd_soc_codec *codec) 3207 { 3208 rt5645_reset(codec); 3209 return 0; 3210 } 3211 3212 #ifdef CONFIG_PM 3213 static int rt5645_suspend(struct snd_soc_codec *codec) 3214 { 3215 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3216 3217 regcache_cache_only(rt5645->regmap, true); 3218 regcache_mark_dirty(rt5645->regmap); 3219 3220 return 0; 3221 } 3222 3223 static int rt5645_resume(struct snd_soc_codec *codec) 3224 { 3225 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3226 3227 regcache_cache_only(rt5645->regmap, false); 3228 regcache_sync(rt5645->regmap); 3229 3230 return 0; 3231 } 3232 #else 3233 #define rt5645_suspend NULL 3234 #define rt5645_resume NULL 3235 #endif 3236 3237 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 3238 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3239 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3240 3241 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { 3242 .hw_params = rt5645_hw_params, 3243 .set_fmt = rt5645_set_dai_fmt, 3244 .set_sysclk = rt5645_set_dai_sysclk, 3245 .set_tdm_slot = rt5645_set_tdm_slot, 3246 .set_pll = rt5645_set_dai_pll, 3247 }; 3248 3249 static struct snd_soc_dai_driver rt5645_dai[] = { 3250 { 3251 .name = "rt5645-aif1", 3252 .id = RT5645_AIF1, 3253 .playback = { 3254 .stream_name = "AIF1 Playback", 3255 .channels_min = 1, 3256 .channels_max = 2, 3257 .rates = RT5645_STEREO_RATES, 3258 .formats = RT5645_FORMATS, 3259 }, 3260 .capture = { 3261 .stream_name = "AIF1 Capture", 3262 .channels_min = 1, 3263 .channels_max = 4, 3264 .rates = RT5645_STEREO_RATES, 3265 .formats = RT5645_FORMATS, 3266 }, 3267 .ops = &rt5645_aif_dai_ops, 3268 }, 3269 { 3270 .name = "rt5645-aif2", 3271 .id = RT5645_AIF2, 3272 .playback = { 3273 .stream_name = "AIF2 Playback", 3274 .channels_min = 1, 3275 .channels_max = 2, 3276 .rates = RT5645_STEREO_RATES, 3277 .formats = RT5645_FORMATS, 3278 }, 3279 .capture = { 3280 .stream_name = "AIF2 Capture", 3281 .channels_min = 1, 3282 .channels_max = 2, 3283 .rates = RT5645_STEREO_RATES, 3284 .formats = RT5645_FORMATS, 3285 }, 3286 .ops = &rt5645_aif_dai_ops, 3287 }, 3288 }; 3289 3290 static struct snd_soc_codec_driver soc_codec_dev_rt5645 = { 3291 .probe = rt5645_probe, 3292 .remove = rt5645_remove, 3293 .suspend = rt5645_suspend, 3294 .resume = rt5645_resume, 3295 .set_bias_level = rt5645_set_bias_level, 3296 .idle_bias_off = true, 3297 .controls = rt5645_snd_controls, 3298 .num_controls = ARRAY_SIZE(rt5645_snd_controls), 3299 .dapm_widgets = rt5645_dapm_widgets, 3300 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), 3301 .dapm_routes = rt5645_dapm_routes, 3302 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), 3303 }; 3304 3305 static const struct regmap_config rt5645_regmap = { 3306 .reg_bits = 8, 3307 .val_bits = 16, 3308 .use_single_rw = true, 3309 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3310 RT5645_PR_SPACING), 3311 .volatile_reg = rt5645_volatile_register, 3312 .readable_reg = rt5645_readable_register, 3313 3314 .cache_type = REGCACHE_RBTREE, 3315 .reg_defaults = rt5645_reg, 3316 .num_reg_defaults = ARRAY_SIZE(rt5645_reg), 3317 .ranges = rt5645_ranges, 3318 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3319 }; 3320 3321 static const struct i2c_device_id rt5645_i2c_id[] = { 3322 { "rt5645", 0 }, 3323 { "rt5650", 0 }, 3324 { } 3325 }; 3326 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); 3327 3328 #ifdef CONFIG_ACPI 3329 static struct acpi_device_id rt5645_acpi_match[] = { 3330 { "10EC5645", 0 }, 3331 { "10EC5650", 0 }, 3332 {}, 3333 }; 3334 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3335 #endif 3336 3337 static struct rt5645_platform_data *rt5645_pdata; 3338 3339 static struct rt5645_platform_data strago_platform_data = { 3340 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3341 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3342 .jd_mode = 3, 3343 }; 3344 3345 static int strago_quirk_cb(const struct dmi_system_id *id) 3346 { 3347 rt5645_pdata = &strago_platform_data; 3348 3349 return 1; 3350 } 3351 3352 static const struct dmi_system_id dmi_platform_intel_braswell[] = { 3353 { 3354 .ident = "Intel Strago", 3355 .callback = strago_quirk_cb, 3356 .matches = { 3357 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), 3358 }, 3359 }, 3360 { 3361 .ident = "Google Celes", 3362 .callback = strago_quirk_cb, 3363 .matches = { 3364 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 3365 }, 3366 }, 3367 { 3368 .ident = "Google Ultima", 3369 .callback = strago_quirk_cb, 3370 .matches = { 3371 DMI_MATCH(DMI_PRODUCT_NAME, "Ultima"), 3372 }, 3373 }, 3374 { 3375 .ident = "Google Reks", 3376 .callback = strago_quirk_cb, 3377 .matches = { 3378 DMI_MATCH(DMI_PRODUCT_NAME, "Reks"), 3379 }, 3380 }, 3381 { 3382 .ident = "Google Edgar", 3383 .callback = strago_quirk_cb, 3384 .matches = { 3385 DMI_MATCH(DMI_PRODUCT_NAME, "Edgar"), 3386 }, 3387 }, 3388 { 3389 .ident = "Google Wizpig", 3390 .callback = strago_quirk_cb, 3391 .matches = { 3392 DMI_MATCH(DMI_PRODUCT_NAME, "Wizpig"), 3393 }, 3394 }, 3395 { 3396 .ident = "Google Terra", 3397 .callback = strago_quirk_cb, 3398 .matches = { 3399 DMI_MATCH(DMI_PRODUCT_NAME, "Terra"), 3400 }, 3401 }, 3402 { } 3403 }; 3404 3405 static struct rt5645_platform_data buddy_platform_data = { 3406 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3407 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3408 .jd_mode = 3, 3409 .jd_invert = true, 3410 }; 3411 3412 static int buddy_quirk_cb(const struct dmi_system_id *id) 3413 { 3414 rt5645_pdata = &buddy_platform_data; 3415 3416 return 1; 3417 } 3418 3419 static struct dmi_system_id dmi_platform_intel_broadwell[] = { 3420 { 3421 .ident = "Chrome Buddy", 3422 .callback = buddy_quirk_cb, 3423 .matches = { 3424 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), 3425 }, 3426 }, 3427 { } 3428 }; 3429 3430 3431 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev) 3432 { 3433 rt5645->pdata.in2_diff = device_property_read_bool(dev, 3434 "realtek,in2-differential"); 3435 device_property_read_u32(dev, 3436 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin); 3437 device_property_read_u32(dev, 3438 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin); 3439 device_property_read_u32(dev, 3440 "realtek,jd-mode", &rt5645->pdata.jd_mode); 3441 3442 return 0; 3443 } 3444 3445 static int rt5645_i2c_probe(struct i2c_client *i2c, 3446 const struct i2c_device_id *id) 3447 { 3448 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev); 3449 struct rt5645_priv *rt5645; 3450 int ret, i; 3451 unsigned int val; 3452 3453 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 3454 GFP_KERNEL); 3455 if (rt5645 == NULL) 3456 return -ENOMEM; 3457 3458 rt5645->i2c = i2c; 3459 i2c_set_clientdata(i2c, rt5645); 3460 3461 if (pdata) 3462 rt5645->pdata = *pdata; 3463 else if (dmi_check_system(dmi_platform_intel_braswell) || 3464 dmi_check_system(dmi_platform_intel_broadwell)) 3465 rt5645->pdata = *rt5645_pdata; 3466 else 3467 rt5645_parse_dt(rt5645, &i2c->dev); 3468 3469 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", 3470 GPIOD_IN); 3471 3472 if (IS_ERR(rt5645->gpiod_hp_det)) { 3473 dev_err(&i2c->dev, "failed to initialize gpiod\n"); 3474 return PTR_ERR(rt5645->gpiod_hp_det); 3475 } 3476 3477 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 3478 if (IS_ERR(rt5645->regmap)) { 3479 ret = PTR_ERR(rt5645->regmap); 3480 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3481 ret); 3482 return ret; 3483 } 3484 3485 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) 3486 rt5645->supplies[i].supply = rt5645_supply_names[i]; 3487 3488 ret = devm_regulator_bulk_get(&i2c->dev, 3489 ARRAY_SIZE(rt5645->supplies), 3490 rt5645->supplies); 3491 if (ret) { 3492 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3493 return ret; 3494 } 3495 3496 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), 3497 rt5645->supplies); 3498 if (ret) { 3499 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3500 return ret; 3501 } 3502 3503 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val); 3504 3505 switch (val) { 3506 case RT5645_DEVICE_ID: 3507 rt5645->codec_type = CODEC_TYPE_RT5645; 3508 break; 3509 case RT5650_DEVICE_ID: 3510 rt5645->codec_type = CODEC_TYPE_RT5650; 3511 break; 3512 default: 3513 dev_err(&i2c->dev, 3514 "Device with ID register %#x is not rt5645 or rt5650\n", 3515 val); 3516 ret = -ENODEV; 3517 goto err_enable; 3518 } 3519 3520 regmap_write(rt5645->regmap, RT5645_RESET, 0); 3521 3522 ret = regmap_register_patch(rt5645->regmap, init_list, 3523 ARRAY_SIZE(init_list)); 3524 if (ret != 0) 3525 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 3526 3527 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 3528 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list, 3529 ARRAY_SIZE(rt5650_init_list)); 3530 if (ret != 0) 3531 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", 3532 ret); 3533 } 3534 3535 if (rt5645->pdata.in2_diff) 3536 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 3537 RT5645_IN_DF2, RT5645_IN_DF2); 3538 3539 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { 3540 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3541 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 3542 } 3543 switch (rt5645->pdata.dmic1_data_pin) { 3544 case RT5645_DMIC_DATA_IN2N: 3545 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3546 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 3547 break; 3548 3549 case RT5645_DMIC_DATA_GPIO5: 3550 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3551 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); 3552 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3553 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); 3554 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3555 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); 3556 break; 3557 3558 case RT5645_DMIC_DATA_GPIO11: 3559 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3560 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); 3561 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3562 RT5645_GP11_PIN_MASK, 3563 RT5645_GP11_PIN_DMIC1_SDA); 3564 break; 3565 3566 default: 3567 break; 3568 } 3569 3570 switch (rt5645->pdata.dmic2_data_pin) { 3571 case RT5645_DMIC_DATA_IN2P: 3572 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3573 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); 3574 break; 3575 3576 case RT5645_DMIC_DATA_GPIO6: 3577 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3578 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 3579 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3580 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 3581 break; 3582 3583 case RT5645_DMIC_DATA_GPIO10: 3584 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3585 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 3586 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3587 RT5645_GP10_PIN_MASK, 3588 RT5645_GP10_PIN_DMIC2_SDA); 3589 break; 3590 3591 case RT5645_DMIC_DATA_GPIO12: 3592 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3593 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 3594 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3595 RT5645_GP12_PIN_MASK, 3596 RT5645_GP12_PIN_DMIC2_SDA); 3597 break; 3598 3599 default: 3600 break; 3601 } 3602 3603 if (rt5645->pdata.jd_mode) { 3604 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3605 RT5645_IRQ_CLK_GATE_CTRL, 3606 RT5645_IRQ_CLK_GATE_CTRL); 3607 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3608 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 3609 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3610 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 3611 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3612 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); 3613 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, 3614 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); 3615 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3616 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); 3617 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3618 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3619 switch (rt5645->pdata.jd_mode) { 3620 case 1: 3621 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 3622 RT5645_JD1_MODE_MASK, 3623 RT5645_JD1_MODE_0); 3624 break; 3625 case 2: 3626 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 3627 RT5645_JD1_MODE_MASK, 3628 RT5645_JD1_MODE_1); 3629 break; 3630 case 3: 3631 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 3632 RT5645_JD1_MODE_MASK, 3633 RT5645_JD1_MODE_2); 3634 break; 3635 default: 3636 break; 3637 } 3638 } 3639 3640 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); 3641 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); 3642 3643 if (rt5645->i2c->irq) { 3644 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, 3645 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 3646 | IRQF_ONESHOT, "rt5645", rt5645); 3647 if (ret) { 3648 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 3649 goto err_enable; 3650 } 3651 } 3652 3653 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645, 3654 rt5645_dai, ARRAY_SIZE(rt5645_dai)); 3655 if (ret) 3656 goto err_irq; 3657 3658 return 0; 3659 3660 err_irq: 3661 if (rt5645->i2c->irq) 3662 free_irq(rt5645->i2c->irq, rt5645); 3663 err_enable: 3664 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 3665 return ret; 3666 } 3667 3668 static int rt5645_i2c_remove(struct i2c_client *i2c) 3669 { 3670 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 3671 3672 if (i2c->irq) 3673 free_irq(i2c->irq, rt5645); 3674 3675 cancel_delayed_work_sync(&rt5645->jack_detect_work); 3676 cancel_delayed_work_sync(&rt5645->rcclock_work); 3677 3678 snd_soc_unregister_codec(&i2c->dev); 3679 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 3680 3681 return 0; 3682 } 3683 3684 static void rt5645_i2c_shutdown(struct i2c_client *i2c) 3685 { 3686 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 3687 3688 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3689 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); 3690 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, 3691 RT5645_CBJ_MN_JD); 3692 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, 3693 0); 3694 msleep(20); 3695 regmap_write(rt5645->regmap, RT5645_RESET, 0); 3696 } 3697 3698 static struct i2c_driver rt5645_i2c_driver = { 3699 .driver = { 3700 .name = "rt5645", 3701 .acpi_match_table = ACPI_PTR(rt5645_acpi_match), 3702 }, 3703 .probe = rt5645_i2c_probe, 3704 .remove = rt5645_i2c_remove, 3705 .shutdown = rt5645_i2c_shutdown, 3706 .id_table = rt5645_i2c_id, 3707 }; 3708 module_i2c_driver(rt5645_i2c_driver); 3709 3710 MODULE_DESCRIPTION("ASoC RT5645 driver"); 3711 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3712 MODULE_LICENSE("GPL v2"); 3713