1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 26eebf35bSOder Chiou /* 36eebf35bSOder Chiou * rt5514-spi.h -- RT5514 driver 46eebf35bSOder Chiou * 56eebf35bSOder Chiou * Copyright 2015 Realtek Semiconductor Corp. 66eebf35bSOder Chiou * Author: Oder Chiou <oder_chiou@realtek.com> 76eebf35bSOder Chiou */ 86eebf35bSOder Chiou 96eebf35bSOder Chiou #ifndef __RT5514_SPI_H__ 106eebf35bSOder Chiou #define __RT5514_SPI_H__ 116eebf35bSOder Chiou 126eebf35bSOder Chiou /** 136eebf35bSOder Chiou * RT5514_SPI_BUF_LEN is the buffer size of SPI master controller. 146eebf35bSOder Chiou */ 156eebf35bSOder Chiou #define RT5514_SPI_BUF_LEN 240 166eebf35bSOder Chiou 17173f4612Soder_chiou@realtek.com #define RT5514_BUFFER_VOICE_BASE 0x18000200 18173f4612Soder_chiou@realtek.com #define RT5514_BUFFER_VOICE_LIMIT 0x18000204 19173f4612Soder_chiou@realtek.com #define RT5514_BUFFER_VOICE_WP 0x1800020c 20659178f5SHsin-Yu Chao #define RT5514_IRQ_CTRL 0x18002094 21659178f5SHsin-Yu Chao 22659178f5SHsin-Yu Chao #define RT5514_IRQ_STATUS_BIT (0x1 << 5) 236eebf35bSOder Chiou 246eebf35bSOder Chiou /* SPI Command */ 256eebf35bSOder Chiou enum { 266eebf35bSOder Chiou RT5514_SPI_CMD_16_READ = 0, 276eebf35bSOder Chiou RT5514_SPI_CMD_16_WRITE, 286eebf35bSOder Chiou RT5514_SPI_CMD_32_READ, 296eebf35bSOder Chiou RT5514_SPI_CMD_32_WRITE, 306eebf35bSOder Chiou RT5514_SPI_CMD_BURST_READ, 316eebf35bSOder Chiou RT5514_SPI_CMD_BURST_WRITE, 326eebf35bSOder Chiou }; 336eebf35bSOder Chiou 346eebf35bSOder Chiou int rt5514_spi_burst_read(unsigned int addr, u8 *rxbuf, size_t len); 356eebf35bSOder Chiou int rt5514_spi_burst_write(u32 addr, const u8 *txbuf, size_t len); 366eebf35bSOder Chiou 376eebf35bSOder Chiou #endif /* __RT5514_SPI_H__ */ 38