1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt1320-sdw.h -- RT1320 SDCA ALSA SoC audio driver header 4 * 5 * Copyright(c) 2024 Realtek Semiconductor Corp. 6 */ 7 8 #ifndef __RT1320_SDW_H__ 9 #define __RT1320_SDW_H__ 10 11 #include <linux/regmap.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <linux/soundwire/sdw_registers.h> 15 #include <sound/soc.h> 16 #include "../../../drivers/soundwire/bus.h" 17 18 #define RT1320_DEV_ID 0x6981 19 #define RT1321_DEV_ID 0x7045 20 21 /* imp-defined registers */ 22 #define RT1320_DEV_VERSION_ID_1 0xc404 23 #define RT1320_DEV_ID_1 0xc405 24 #define RT1320_DEV_ID_0 0xc406 25 26 #define RT1320_POWER_STATE 0xc560 27 28 #define RT1321_PATCH_MAIN_VER 0x1000cffe 29 #define RT1321_PATCH_BETA_VER 0x1000cfff 30 31 #define RT1320_KR0_STATUS_CNT 0x1000f008 32 #define RT1320_KR0_INT_READY 0x1000f021 33 #define RT1320_HIFI_VER_0 0x3fe2e000 34 #define RT1320_HIFI_VER_1 0x3fe2e001 35 #define RT1320_HIFI_VER_2 0x3fe2e002 36 #define RT1320_HIFI_VER_3 0x3fe2e003 37 38 /* RT1320 SDCA Control - function number */ 39 #define FUNC_NUM_AMP 0x04 40 #define FUNC_NUM_MIC 0x02 41 42 /* RT1320 SDCA entity */ 43 #define RT1320_SDCA_ENT0 0x00 44 #define RT1320_SDCA_ENT_PDE11 0x2a 45 #define RT1320_SDCA_ENT_PDE23 0x33 46 #define RT1320_SDCA_ENT_PDE27 0x27 47 #define RT1320_SDCA_ENT_FU14 0x32 48 #define RT1320_SDCA_ENT_FU21 0x03 49 #define RT1320_SDCA_ENT_FU113 0x30 50 #define RT1320_SDCA_ENT_CS14 0x13 51 #define RT1320_SDCA_ENT_CS21 0x21 52 #define RT1320_SDCA_ENT_CS113 0x12 53 #define RT1320_SDCA_ENT_SAPU 0x29 54 #define RT1320_SDCA_ENT_PPU21 0x04 55 56 /* RT1320 SDCA control */ 57 #define RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10 58 #define RT1320_SDCA_CTL_REQ_POWER_STATE 0x01 59 #define RT1320_SDCA_CTL_ACTUAL_POWER_STATE 0x10 60 #define RT1320_SDCA_CTL_FU_MUTE 0x01 61 #define RT1320_SDCA_CTL_FU_VOLUME 0x02 62 #define RT1320_SDCA_CTL_SAPU_PROTECTION_MODE 0x10 63 #define RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11 64 #define RT1320_SDCA_CTL_POSTURE_NUMBER 0x10 65 #define RT1320_SDCA_CTL_FUNC_STATUS 0x10 66 67 /* RT1320 SDCA channel */ 68 #define CH_01 0x01 69 #define CH_02 0x02 70 71 /* Function_Status */ 72 #define FUNCTION_NEEDS_INITIALIZATION BIT(5) 73 74 /* Sample Frequency Index */ 75 #define RT1320_SDCA_RATE_16000HZ 0x04 76 #define RT1320_SDCA_RATE_32000HZ 0x07 77 #define RT1320_SDCA_RATE_44100HZ 0x08 78 #define RT1320_SDCA_RATE_48000HZ 0x09 79 #define RT1320_SDCA_RATE_96000HZ 0x0b 80 #define RT1320_SDCA_RATE_192000HZ 0x0d 81 82 enum { 83 RT1320_AIF1, 84 RT1320_AIF2, 85 }; 86 87 /* 88 * The version id will be useful to distinguish the capability between the different IC versions. 89 * Currently, VA and VB have different DSP FW versions. 90 */ 91 enum rt1320_version_id { 92 RT1320_VA, 93 RT1320_VB, 94 RT1320_VC, 95 }; 96 97 #define RT1320_VER_B_ID 0x07392238 98 #define RT1320_VAB_MCU_PATCH "realtek/rt1320/rt1320-patch-code-vab.bin" 99 #define RT1320_VC_MCU_PATCH "realtek/rt1320/rt1320-patch-code-vc.bin" 100 #define RT1321_VA_MCU_PATCH "realtek/rt1320/rt1321-patch-code-va.bin" 101 102 #define RT1320_FW_PARAM_ADDR 0x3fc2ab80 103 #define RT1320_CMD_ID 0x3fc2ab81 104 #define RT1320_CMD_PARAM_ADDR 0x3fc2ab90 105 #define RT1320_DSPFW_STATUS_ADDR 0x3fc2bfc4 106 107 #define RT1321_FW_PARAM_ADDR 0x3fc2d300 108 #define RT1321_CMD_ID 0x3fc2d301 109 #define RT1321_CMD_PARAM_ADDR 0x3fc2d310 110 #define RT1321_DSPFW_STATUS_ADDR 0x3fc2dfc4 111 112 /* FW parameter id 6, 7 */ 113 struct rt1320_datafixpoint { 114 int silencedetect; 115 int r0; 116 int meanr0; 117 int advancegain; 118 int ts; 119 int re; 120 int t; 121 int invrs; 122 }; 123 124 struct rt1320_paramcmd { 125 unsigned char moudleid; 126 unsigned char commandtype; 127 unsigned short reserved1; 128 unsigned int commandlength; 129 long long reserved2; 130 unsigned int paramid; 131 unsigned int paramlength; 132 }; 133 134 enum rt1320_fw_cmdid { 135 RT1320_FW_READY, 136 RT1320_SET_PARAM, 137 RT1320_GET_PARAM, 138 RT1320_GET_POOLSIZE, 139 }; 140 141 enum rt1320_power_state { 142 RT1320_NORMAL_STATE = 0x18, 143 RT1320_K_R0_STATE = 0x1b, 144 }; 145 146 enum rt1320_rw_type { 147 RT1320_BRA_WRITE = 0, 148 RT1320_BRA_READ = 1, 149 RT1320_PARAM_WRITE = 2, 150 RT1320_PARAM_READ = 3, 151 }; 152 153 struct rt1320_sdw_priv { 154 struct snd_soc_component *component; 155 struct regmap *regmap; 156 struct regmap *mbq_regmap; 157 struct sdw_slave *sdw_slave; 158 struct sdw_bus_params params; 159 bool hw_init; 160 bool first_hw_init; 161 int version_id; 162 unsigned int dev_id; 163 bool fu_dapm_mute; 164 bool fu_mixer_mute[4]; 165 unsigned long long r0_l_reg; 166 unsigned long long r0_r_reg; 167 unsigned int r0_l_calib; 168 unsigned int r0_r_calib; 169 unsigned int temp_l_calib; 170 unsigned int temp_r_calib; 171 const char *dspfw_name; 172 bool cali_done; 173 bool fw_load_done; 174 bool rae_update_done; 175 struct work_struct load_dspfw_work; 176 struct sdw_bpt_msg bra_msg; 177 }; 178 179 #endif /* __RT1320_SDW_H__ */ 180