1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 #include "rt-sdw-common.h" 25 26 /* 27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 28 * It might include vendor-specific or SDCA control registers. 29 */ 30 static const struct reg_sequence rt1320_blind_write[] = { 31 { 0xc003, 0xe0 }, 32 { 0xc01b, 0xfc }, 33 { 0xc5c3, 0xf2 }, 34 { 0xc5c2, 0x00 }, 35 { 0xc5c6, 0x10 }, 36 { 0xc5c4, 0x12 }, 37 { 0xc5c8, 0x03 }, 38 { 0xc5d8, 0x0a }, 39 { 0xc5f7, 0x22 }, 40 { 0xc5f6, 0x22 }, 41 { 0xc5d0, 0x0f }, 42 { 0xc5d1, 0x89 }, 43 { 0xc057, 0x51 }, 44 { 0xc054, 0x35 }, 45 { 0xc053, 0x55 }, 46 { 0xc052, 0x55 }, 47 { 0xc051, 0x13 }, 48 { 0xc050, 0x15 }, 49 { 0xc060, 0x77 }, 50 { 0xc061, 0x55 }, 51 { 0xc063, 0x55 }, 52 { 0xc065, 0xa5 }, 53 { 0xc06b, 0x0a }, 54 { 0xca05, 0xd6 }, 55 { 0xca25, 0xd6 }, 56 { 0xcd00, 0x05 }, 57 { 0xc604, 0x40 }, 58 { 0xc609, 0x40 }, 59 { 0xc046, 0xff }, 60 { 0xc045, 0xff }, 61 { 0xc044, 0xff }, 62 { 0xc043, 0xff }, 63 { 0xc042, 0xff }, 64 { 0xc041, 0xff }, 65 { 0xc040, 0xff }, 66 { 0xcc10, 0x01 }, 67 { 0xc700, 0xf0 }, 68 { 0xc701, 0x13 }, 69 { 0xc901, 0x04 }, 70 { 0xc900, 0x73 }, 71 { 0xde03, 0x05 }, 72 { 0xdd0b, 0x0d }, 73 { 0xdd0a, 0xff }, 74 { 0xdd09, 0x0d }, 75 { 0xdd08, 0xff }, 76 { 0xc570, 0x08 }, 77 { 0xe803, 0xbe }, 78 { 0xc003, 0xc0 }, 79 { 0xc081, 0xfe }, 80 { 0xce31, 0x0d }, 81 { 0xce30, 0xae }, 82 { 0xce37, 0x0b }, 83 { 0xce36, 0xd2 }, 84 { 0xce39, 0x04 }, 85 { 0xce38, 0x80 }, 86 { 0xce3f, 0x00 }, 87 { 0xce3e, 0x00 }, 88 { 0xd470, 0x8b }, 89 { 0xd471, 0x18 }, 90 { 0xc019, 0x10 }, 91 { 0xd487, 0x3f }, 92 { 0xd486, 0xc3 }, 93 { 0x3fc2bfc7, 0x00 }, 94 { 0x3fc2bfc6, 0x00 }, 95 { 0x3fc2bfc5, 0x00 }, 96 { 0x3fc2bfc4, 0x01 }, 97 { 0x0000d486, 0x43 }, 98 { 0x1000db00, 0x02 }, 99 { 0x1000db01, 0x00 }, 100 { 0x1000db02, 0x11 }, 101 { 0x1000db03, 0x00 }, 102 { 0x1000db04, 0x00 }, 103 { 0x1000db05, 0x82 }, 104 { 0x1000db06, 0x04 }, 105 { 0x1000db07, 0xf1 }, 106 { 0x1000db08, 0x00 }, 107 { 0x1000db09, 0x00 }, 108 { 0x1000db0a, 0x40 }, 109 { 0x0000d540, 0x01 }, 110 { 0xd172, 0x2a }, 111 { 0xc5d6, 0x01 }, 112 { 0xd478, 0xff }, 113 }; 114 115 static const struct reg_sequence rt1320_vc_blind_write[] = { 116 { 0xc003, 0xe0 }, 117 { 0xe80a, 0x01 }, 118 { 0xc5c3, 0xf3 }, 119 { 0xc057, 0x51 }, 120 { 0xc054, 0x35 }, 121 { 0xca05, 0xd6 }, 122 { 0xca07, 0x07 }, 123 { 0xca25, 0xd6 }, 124 { 0xca27, 0x07 }, 125 { 0xc604, 0x40 }, 126 { 0xc609, 0x40 }, 127 { 0xc046, 0xff }, 128 { 0xc045, 0xff }, 129 { 0xda81, 0x14 }, 130 { 0xda8d, 0x14 }, 131 { 0xc044, 0xff }, 132 { 0xc043, 0xff }, 133 { 0xc042, 0xff }, 134 { 0xc041, 0x7f }, 135 { 0xc040, 0xff }, 136 { 0xcc10, 0x01 }, 137 { 0xc700, 0xf0 }, 138 { 0xc701, 0x13 }, 139 { 0xc901, 0x09 }, 140 { 0xc900, 0xd0 }, 141 { 0xde03, 0x05 }, 142 { 0xdd0b, 0x0d }, 143 { 0xdd0a, 0xff }, 144 { 0xdd09, 0x0d }, 145 { 0xdd08, 0xff }, 146 { 0xc570, 0x08 }, 147 { 0xc086, 0x02 }, 148 { 0xc085, 0x7f }, 149 { 0xc084, 0x00 }, 150 { 0xc081, 0xfe }, 151 { 0xf084, 0x0f }, 152 { 0xf083, 0xff }, 153 { 0xf082, 0xff }, 154 { 0xf081, 0xff }, 155 { 0xf080, 0xff }, 156 { 0xe802, 0xf8 }, 157 { 0xe803, 0xbe }, 158 { 0xc003, 0xc0 }, 159 { 0xd470, 0xec }, 160 { 0xd471, 0x3a }, 161 { 0xd474, 0x11 }, 162 { 0xd475, 0x32 }, 163 { 0xd478, 0xff }, 164 { 0xd479, 0x20 }, 165 { 0xd47a, 0x10 }, 166 { 0xd47c, 0xff }, 167 { 0xc019, 0x10 }, 168 { 0xd487, 0x0b }, 169 { 0xd487, 0x3b }, 170 { 0xd486, 0xc3 }, 171 { 0xc598, 0x04 }, 172 { 0xdb03, 0xf0 }, 173 { 0xdb09, 0x00 }, 174 { 0xdb08, 0x7a }, 175 { 0xdb19, 0x02 }, 176 { 0xdb07, 0x5a }, 177 { 0xdb05, 0x45 }, 178 { 0xd500, 0x00 }, 179 { 0xd500, 0x17 }, 180 { 0xd600, 0x01 }, 181 { 0xd601, 0x02 }, 182 { 0xd602, 0x03 }, 183 { 0xd603, 0x04 }, 184 { 0xd64c, 0x03 }, 185 { 0xd64d, 0x03 }, 186 { 0xd64e, 0x03 }, 187 { 0xd64f, 0x03 }, 188 { 0xd650, 0x03 }, 189 { 0xd651, 0x03 }, 190 { 0xd652, 0x03 }, 191 { 0xd610, 0x01 }, 192 { 0xd608, 0x03 }, 193 { 0xd609, 0x00 }, 194 { 0x3fc2bf83, 0x00 }, 195 { 0x3fc2bf82, 0x00 }, 196 { 0x3fc2bf81, 0x00 }, 197 { 0x3fc2bf80, 0x00 }, 198 { 0x3fc2bfc7, 0x00 }, 199 { 0x3fc2bfc6, 0x00 }, 200 { 0x3fc2bfc5, 0x00 }, 201 { 0x3fc2bfc4, 0x00 }, 202 { 0x3fc2bfc3, 0x00 }, 203 { 0x3fc2bfc2, 0x00 }, 204 { 0x3fc2bfc1, 0x00 }, 205 { 0x3fc2bfc0, 0x03 }, 206 { 0x0000d486, 0x43 }, 207 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 208 { 0x1000db00, 0x07 }, 209 { 0x1000db01, 0x00 }, 210 { 0x1000db02, 0x11 }, 211 { 0x1000db03, 0x00 }, 212 { 0x1000db04, 0x00 }, 213 { 0x1000db05, 0x82 }, 214 { 0x1000db06, 0x04 }, 215 { 0x1000db07, 0xf1 }, 216 { 0x1000db08, 0x00 }, 217 { 0x1000db09, 0x00 }, 218 { 0x1000db0a, 0x40 }, 219 { 0x1000db0b, 0x02 }, 220 { 0x1000db0c, 0xf2 }, 221 { 0x1000db0d, 0x00 }, 222 { 0x1000db0e, 0x00 }, 223 { 0x1000db0f, 0xe0 }, 224 { 0x1000db10, 0x00 }, 225 { 0x1000db11, 0x10 }, 226 { 0x1000db12, 0x00 }, 227 { 0x1000db13, 0x00 }, 228 { 0x1000db14, 0x45 }, 229 { 0x1000db15, 0x0d }, 230 { 0x1000db16, 0x01 }, 231 { 0x1000db17, 0x00 }, 232 { 0x1000db18, 0x00 }, 233 { 0x1000db19, 0xbf }, 234 { 0x1000db1a, 0x13 }, 235 { 0x1000db1b, 0x09 }, 236 { 0x1000db1c, 0x00 }, 237 { 0x1000db1d, 0x00 }, 238 { 0x1000db1e, 0x00 }, 239 { 0x1000db1f, 0x12 }, 240 { 0x1000db20, 0x09 }, 241 { 0x1000db21, 0x00 }, 242 { 0x1000db22, 0x00 }, 243 { 0x1000db23, 0x00 }, 244 { 0x0000d540, 0x01 }, 245 { 0x0000c081, 0xfc }, 246 { 0x0000f01e, 0x80 }, 247 { 0xc01b, 0xfc }, 248 { 0xc5d1, 0x89 }, 249 { 0xc5d8, 0x0a }, 250 { 0xc5f7, 0x22 }, 251 { 0xc5f6, 0x22 }, 252 { 0xc065, 0xa5 }, 253 { 0xc06b, 0x0a }, 254 { 0xd172, 0x2a }, 255 { 0xc5d6, 0x01 }, 256 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 257 }; 258 259 static const struct reg_sequence rt1321_blind_write[] = { 260 { 0x0000c003, 0xf0 }, 261 { 0x0000c01b, 0xfc }, 262 { 0x0000c5c3, 0xf2 }, 263 { 0x0000c5c2, 0x00 }, 264 { 0x0000c5c1, 0x10 }, 265 { 0x0000c5c0, 0x04 }, 266 { 0x0000c5c7, 0x03 }, 267 { 0x0000c5c6, 0x10 }, 268 { 0x0000c526, 0x47 }, 269 { 0x0000c5c4, 0x12 }, 270 { 0x0000c5c5, 0x60 }, 271 { 0x0000c520, 0x10 }, 272 { 0x0000c521, 0x32 }, 273 { 0x0000c5c7, 0x00 }, 274 { 0x0000c5c8, 0x03 }, 275 { 0x0000c5d3, 0x08 }, 276 { 0x0000c5d2, 0x0a }, 277 { 0x0000c5d1, 0x49 }, 278 { 0x0000c5d0, 0x0f }, 279 { 0x0000c580, 0x10 }, 280 { 0x0000c581, 0x32 }, 281 { 0x0000c582, 0x01 }, 282 { 0x0000cb00, 0x03 }, 283 { 0x0000cb02, 0x52 }, 284 { 0x0000cb04, 0x80 }, 285 { 0x0000cb0b, 0x01 }, 286 { 0x0000c682, 0x60 }, 287 { 0x0000c019, 0x10 }, 288 { 0x0000c5f0, 0x01 }, 289 { 0x0000c5f7, 0x22 }, 290 { 0x0000c5f6, 0x22 }, 291 { 0x0000c057, 0x51 }, 292 { 0x0000c054, 0x55 }, 293 { 0x0000c053, 0x55 }, 294 { 0x0000c052, 0x55 }, 295 { 0x0000c051, 0x01 }, 296 { 0x0000c050, 0x15 }, 297 { 0x0000c060, 0x99 }, 298 { 0x0000c030, 0x55 }, 299 { 0x0000c061, 0x55 }, 300 { 0x0000c063, 0x55 }, 301 { 0x0000c065, 0xa5 }, 302 { 0x0000c06b, 0x0a }, 303 { 0x0000ca05, 0xd6 }, 304 { 0x0000ca07, 0x07 }, 305 { 0x0000ca25, 0xd6 }, 306 { 0x0000ca27, 0x07 }, 307 { 0x0000cd00, 0x05 }, 308 { 0x0000c604, 0x40 }, 309 { 0x0000c609, 0x40 }, 310 { 0x0000c046, 0xf7 }, 311 { 0x0000c045, 0xff }, 312 { 0x0000c044, 0xff }, 313 { 0x0000c043, 0xff }, 314 { 0x0000c042, 0xff }, 315 { 0x0000c041, 0xff }, 316 { 0x0000c040, 0xff }, 317 { 0x0000c049, 0xff }, 318 { 0x0000c028, 0x3f }, 319 { 0x0000c020, 0x3f }, 320 { 0x0000c032, 0x13 }, 321 { 0x0000c033, 0x01 }, 322 { 0x0000cc10, 0x01 }, 323 { 0x0000dc20, 0x03 }, 324 { 0x0000de03, 0x05 }, 325 { 0x0000dc00, 0x00 }, 326 { 0x0000c700, 0xf0 }, 327 { 0x0000c701, 0x13 }, 328 { 0x0000c900, 0xc3 }, 329 { 0x0000c570, 0x08 }, 330 { 0x0000c086, 0x02 }, 331 { 0x0000c085, 0x7f }, 332 { 0x0000c084, 0x00 }, 333 { 0x0000c081, 0xff }, 334 { 0x0000f084, 0x0f }, 335 { 0x0000f083, 0xff }, 336 { 0x0000f082, 0xff }, 337 { 0x0000f081, 0xff }, 338 { 0x0000f080, 0xff }, 339 { 0x20003003, 0x3f }, 340 { 0x20005818, 0x81 }, 341 { 0x20009018, 0x81 }, 342 { 0x2000301c, 0x81 }, 343 { 0x0000c003, 0xc0 }, 344 { 0x0000c047, 0x80 }, 345 { 0x0000d541, 0x80 }, 346 { 0x0000d487, 0x0b }, 347 { 0x0000d487, 0x3b }, 348 { 0x0000d486, 0xc3 }, 349 { 0x0000d470, 0x89 }, 350 { 0x0000d471, 0x3a }, 351 { 0x0000d472, 0x1d }, 352 { 0x0000d478, 0xff }, 353 { 0x0000d479, 0x20 }, 354 { 0x0000d47a, 0x10 }, 355 { 0x0000d73c, 0xb7 }, 356 { 0x0000d73d, 0xd7 }, 357 { 0x0000d73e, 0x00 }, 358 { 0x0000d73f, 0x10 }, 359 { 0x3fc2dfc3, 0x00 }, 360 { 0x3fc2dfc2, 0x00 }, 361 { 0x3fc2dfc1, 0x00 }, 362 { 0x3fc2dfc0, 0x07 }, 363 { 0x3fc2dfc7, 0x00 }, 364 { 0x3fc2dfc6, 0x00 }, 365 { 0x3fc2dfc5, 0x00 }, 366 { 0x3fc2dfc4, 0x01 }, 367 { 0x3fc2df83, 0x00 }, 368 { 0x3fc2df82, 0x00 }, 369 { 0x3fc2df81, 0x00 }, 370 { 0x3fc2df80, 0x00 }, 371 { 0x0000d541, 0x40 }, 372 { 0x0000d486, 0x43 }, 373 { 0x1000db00, 0x03 }, 374 { 0x1000db01, 0x00 }, 375 { 0x1000db02, 0x10 }, 376 { 0x1000db03, 0x00 }, 377 { 0x1000db04, 0x00 }, 378 { 0x1000db05, 0x45 }, 379 { 0x1000db06, 0x12 }, 380 { 0x1000db07, 0x09 }, 381 { 0x1000db08, 0x00 }, 382 { 0x1000db09, 0x00 }, 383 { 0x1000db0a, 0x00 }, 384 { 0x1000db0b, 0x13 }, 385 { 0x1000db0c, 0x09 }, 386 { 0x1000db0d, 0x00 }, 387 { 0x1000db0e, 0x00 }, 388 { 0x1000db0f, 0x00 }, 389 { 0x0000d540, 0x21 }, 390 { 0x41000189, 0x00 }, 391 { 0x4100018a, 0x00 }, 392 { 0x41001988, 0x00 }, 393 { 0x41081400, 0x09 }, 394 { 0x40801508, 0x03 }, 395 { 0x40801588, 0x03 }, 396 { 0x40801809, 0x00 }, 397 { 0x4080180a, 0x00 }, 398 { 0x4080180b, 0x00 }, 399 { 0x4080180c, 0x00 }, 400 { 0x40801b09, 0x00 }, 401 { 0x40801b0a, 0x00 }, 402 { 0x40801b0b, 0x00 }, 403 { 0x40801b0c, 0x00 }, 404 { 0x0000d714, 0x17 }, 405 { 0x20009012, 0x00 }, 406 { 0x0000dd0b, 0x0d }, 407 { 0x0000dd0a, 0xff }, 408 { 0x0000dd09, 0x0d }, 409 { 0x0000dd08, 0xff }, 410 { 0x0000d172, 0x2a }, 411 { 0x41001988, 0x03 }, 412 }; 413 414 static const struct reg_default rt1320_reg_defaults[] = { 415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 416 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 417 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 418 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 419 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 420 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 421 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 422 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 423 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 424 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 425 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 426 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 427 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 428 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 429 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 430 }; 431 432 static const struct reg_default rt1320_mbq_defaults[] = { 433 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 434 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 435 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 436 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 437 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 438 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 439 }; 440 441 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 442 { 443 switch (reg) { 444 case 0xc000 ... 0xc086: 445 case 0xc400 ... 0xc409: 446 case 0xc480 ... 0xc48f: 447 case 0xc4c0 ... 0xc4c4: 448 case 0xc4e0 ... 0xc4e7: 449 case 0xc500: 450 case 0xc560 ... 0xc56b: 451 case 0xc570: 452 case 0xc580 ... 0xc59a: 453 case 0xc5b0 ... 0xc60f: 454 case 0xc640 ... 0xc64f: 455 case 0xc670: 456 case 0xc680 ... 0xc683: 457 case 0xc700 ... 0xc76f: 458 case 0xc800 ... 0xc801: 459 case 0xc820: 460 case 0xc900 ... 0xc901: 461 case 0xc920 ... 0xc921: 462 case 0xca00 ... 0xca07: 463 case 0xca20 ... 0xca27: 464 case 0xca40 ... 0xca4b: 465 case 0xca60 ... 0xca68: 466 case 0xca80 ... 0xca88: 467 case 0xcb00 ... 0xcb0c: 468 case 0xcc00 ... 0xcc12: 469 case 0xcc80 ... 0xcc81: 470 case 0xcd00: 471 case 0xcd80 ... 0xcd82: 472 case 0xce00 ... 0xce4d: 473 case 0xcf00 ... 0xcf25: 474 case 0xd000 ... 0xd0ff: 475 case 0xd100 ... 0xd1ff: 476 case 0xd200 ... 0xd2ff: 477 case 0xd300 ... 0xd3ff: 478 case 0xd400 ... 0xd403: 479 case 0xd410 ... 0xd417: 480 case 0xd470 ... 0xd497: 481 case 0xd4dc ... 0xd50f: 482 case 0xd520 ... 0xd543: 483 case 0xd560 ... 0xd5ef: 484 case 0xd600 ... 0xd663: 485 case 0xda00 ... 0xda6e: 486 case 0xda80 ... 0xda9e: 487 case 0xdb00 ... 0xdb7f: 488 case 0xdc00: 489 case 0xdc20 ... 0xdc21: 490 case 0xdd00 ... 0xdd17: 491 case 0xde00 ... 0xde09: 492 case 0xdf00 ... 0xdf1b: 493 case 0xe000 ... 0xe847: 494 case 0xf01e: 495 case 0xf717 ... 0xf719: 496 case 0xf720 ... 0xf723: 497 case 0x1000cd91 ... 0x1000cd96: 498 case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER: 499 case 0x1000f008: 500 case 0x1000f021: 501 case 0x2000300f: 502 case 0x2000301c: 503 case 0x2000900f: 504 case 0x20009018: 505 case 0x3fc000c0 ... 0x3fc2dfc8: 506 case 0x3fe00000 ... 0x3fe36fff: 507 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 508 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 509 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 510 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 511 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 512 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 513 /* 0x40880900/0x40880980 */ 514 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 515 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 516 /* 0x40881500 */ 517 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 518 /* 0x41000189/0x4100018a */ 519 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 520 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 521 /* 0x41001388 */ 522 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 523 /* 0x41001988 */ 524 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 525 /* 0x41080000 */ 526 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 527 /* 0x41080200 */ 528 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 529 /* 0x41080900 */ 530 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 531 /* 0x41080980 */ 532 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 533 /* 0x41081080 */ 534 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 535 /* 0x41081480/0x41081488 */ 536 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 537 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 538 /* 0x41081980 */ 539 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 540 return true; 541 default: 542 return false; 543 } 544 } 545 546 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 547 { 548 switch (reg) { 549 case 0xc000: 550 case 0xc003: 551 case 0xc081: 552 case 0xc402 ... 0xc406: 553 case 0xc48c ... 0xc48f: 554 case 0xc560: 555 case 0xc5b5 ... 0xc5b7: 556 case 0xc5c3: 557 case 0xc5c8: 558 case 0xc5fc ... 0xc5ff: 559 case 0xc680 ... 0xc683: 560 case 0xc820: 561 case 0xc900: 562 case 0xc920: 563 case 0xca42: 564 case 0xca62: 565 case 0xca82: 566 case 0xcd00: 567 case 0xce03: 568 case 0xce10: 569 case 0xce14 ... 0xce17: 570 case 0xce44 ... 0xce49: 571 case 0xce4c ... 0xce4d: 572 case 0xcf0c: 573 case 0xcf10 ... 0xcf25: 574 case 0xd486 ... 0xd487: 575 case 0xd4e5 ... 0xd4e6: 576 case 0xd4e8 ... 0xd4ff: 577 case 0xd530: 578 case 0xd540 ... 0xd541: 579 case 0xd543: 580 case 0xdb58 ... 0xdb5f: 581 case 0xdb60 ... 0xdb63: 582 case 0xdb68 ... 0xdb69: 583 case 0xdb6d: 584 case 0xdb70 ... 0xdb71: 585 case 0xdb76: 586 case 0xdb7a: 587 case 0xdb7c ... 0xdb7f: 588 case 0xdd0c ... 0xdd13: 589 case 0xde02: 590 case 0xdf14 ... 0xdf1b: 591 case 0xe80b: 592 case 0xe83c ... 0xe847: 593 case 0xf01e: 594 case 0xf717 ... 0xf719: 595 case 0xf720 ... 0xf723: 596 case 0x10000000 ... 0x10008fff: 597 case 0x1000c000 ... 0x1000dfff: 598 case 0x1000f008: 599 case 0x1000f021: 600 case 0x2000300f: 601 case 0x2000301c: 602 case 0x2000900f: 603 case 0x20009018: 604 case 0x3fc2ab80 ... 0x3fc2ac4c: 605 case 0x3fc2b780: 606 case 0x3fc2bf80 ... 0x3fc2bf83: 607 case 0x3fc2bfc0 ... 0x3fc2bfc8: 608 case 0x3fc2d300 ... 0x3fc2d354: 609 case 0x3fc2dfc0 ... 0x3fc2dfc8: 610 case 0x3fe2e000 ... 0x3fe2e003: 611 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 612 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 613 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 614 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 615 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 616 return true; 617 default: 618 return false; 619 } 620 } 621 622 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 623 { 624 switch (reg) { 625 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 626 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 627 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 628 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 629 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 630 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 631 return true; 632 default: 633 return false; 634 } 635 } 636 637 static const struct regmap_config rt1320_sdw_regmap = { 638 .reg_bits = 32, 639 .val_bits = 8, 640 .readable_reg = rt1320_readable_register, 641 .volatile_reg = rt1320_volatile_register, 642 .max_register = 0x41081980, 643 .reg_defaults = rt1320_reg_defaults, 644 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 645 .cache_type = REGCACHE_MAPLE, 646 .use_single_read = true, 647 .use_single_write = true, 648 }; 649 650 static const struct regmap_config rt1320_mbq_regmap = { 651 .name = "sdw-mbq", 652 .reg_bits = 32, 653 .val_bits = 16, 654 .readable_reg = rt1320_mbq_readable_register, 655 .max_register = 0x41000192, 656 .reg_defaults = rt1320_mbq_defaults, 657 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 658 .cache_type = REGCACHE_MAPLE, 659 .use_single_read = true, 660 .use_single_write = true, 661 }; 662 663 static int rt1320_read_prop(struct sdw_slave *slave) 664 { 665 struct sdw_slave_prop *prop = &slave->prop; 666 int nval; 667 int i, j; 668 u32 bit; 669 unsigned long addr; 670 struct sdw_dpn_prop *dpn; 671 672 /* 673 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 674 */ 675 sdw_slave_read_prop(slave); 676 677 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 678 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 679 680 prop->paging_support = true; 681 prop->lane_control_support = true; 682 683 /* first we need to allocate memory for set bits in port lists */ 684 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 685 prop->sink_ports = BIT(1); 686 687 nval = hweight32(prop->source_ports); 688 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 689 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 690 if (!prop->src_dpn_prop) 691 return -ENOMEM; 692 693 i = 0; 694 dpn = prop->src_dpn_prop; 695 addr = prop->source_ports; 696 for_each_set_bit(bit, &addr, 32) { 697 dpn[i].num = bit; 698 dpn[i].type = SDW_DPN_FULL; 699 dpn[i].simple_ch_prep_sm = true; 700 dpn[i].ch_prep_timeout = 10; 701 i++; 702 } 703 704 /* do this again for sink now */ 705 nval = hweight32(prop->sink_ports); 706 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 707 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 708 if (!prop->sink_dpn_prop) 709 return -ENOMEM; 710 711 j = 0; 712 dpn = prop->sink_dpn_prop; 713 addr = prop->sink_ports; 714 for_each_set_bit(bit, &addr, 32) { 715 dpn[j].num = bit; 716 dpn[j].type = SDW_DPN_FULL; 717 dpn[j].simple_ch_prep_sm = true; 718 dpn[j].ch_prep_timeout = 10; 719 j++; 720 } 721 722 prop->dp0_prop = devm_kzalloc(&slave->dev, sizeof(*prop->dp0_prop), GFP_KERNEL); 723 if (!prop->dp0_prop) 724 return -ENOMEM; 725 726 prop->dp0_prop->simple_ch_prep_sm = true; 727 prop->dp0_prop->ch_prep_timeout = 10; 728 729 /* set the timeout values */ 730 prop->clk_stop_timeout = 64; 731 732 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */ 733 prop->wake_capable = 0; 734 735 return 0; 736 } 737 738 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 739 unsigned char entity, unsigned char ps) 740 { 741 unsigned int delay = 2000, val; 742 743 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 744 745 /* waiting for Actual PDE becomes to PS0/PS3 */ 746 while (delay) { 747 regmap_read(rt1320->regmap, 748 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 749 if (val == ps) 750 break; 751 752 usleep_range(1000, 1500); 753 delay--; 754 } 755 if (!delay) { 756 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 757 return -ETIMEDOUT; 758 } 759 760 return 0; 761 } 762 763 static void rt1320_data_rw(struct rt1320_sdw_priv *rt1320, unsigned int start, 764 unsigned char *data, unsigned int size, enum rt1320_rw_type rw) 765 { 766 struct device *dev = &rt1320->sdw_slave->dev; 767 unsigned int tmp; 768 int ret = -1; 769 int i, j; 770 771 pm_runtime_set_autosuspend_delay(dev, 20000); 772 pm_runtime_mark_last_busy(dev); 773 774 switch (rw) { 775 case RT1320_BRA_WRITE: 776 case RT1320_BRA_READ: 777 ret = sdw_bpt_send_sync(rt1320->sdw_slave->bus, rt1320->sdw_slave, &rt1320->bra_msg); 778 if (ret < 0) 779 dev_err(dev, "%s: Failed to send BRA message: %d\n", __func__, ret); 780 fallthrough; 781 case RT1320_PARAM_WRITE: 782 case RT1320_PARAM_READ: 783 if (ret < 0) { 784 /* if BRA fails, we try to access by the control word */ 785 if (rw == RT1320_BRA_WRITE || rw == RT1320_BRA_READ) { 786 for (i = 0; i < rt1320->bra_msg.sections; i++) { 787 pm_runtime_mark_last_busy(dev); 788 for (j = 0; j < rt1320->bra_msg.sec[i].len; j++) { 789 if (rw == RT1320_BRA_WRITE) { 790 regmap_write(rt1320->regmap, 791 rt1320->bra_msg.sec[i].addr + j, rt1320->bra_msg.sec[i].buf[j]); 792 } else { 793 regmap_read(rt1320->regmap, rt1320->bra_msg.sec[i].addr + j, &tmp); 794 rt1320->bra_msg.sec[i].buf[j] = tmp; 795 } 796 } 797 } 798 } else { 799 for (i = 0; i < size; i++) { 800 if (rw == RT1320_PARAM_WRITE) 801 regmap_write(rt1320->regmap, start + i, data[i]); 802 else { 803 regmap_read(rt1320->regmap, start + i, &tmp); 804 data[i] = tmp; 805 } 806 } 807 } 808 } 809 break; 810 } 811 812 pm_runtime_set_autosuspend_delay(dev, 3000); 813 pm_runtime_mark_last_busy(dev); 814 } 815 816 static unsigned long long rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv *rt1320, unsigned int rsgain) 817 { 818 unsigned long long base = 1000000000U; 819 unsigned long long step = 1960784U; 820 unsigned long long tmp, result; 821 822 if (rsgain == 0 || rsgain == 0x1ff) 823 result = 1000000000; 824 else if (rsgain & 0x100) { 825 tmp = 0xff - (rsgain & 0xff); 826 tmp = tmp * step; 827 result = base + tmp; 828 } else { 829 tmp = (rsgain & 0xff); 830 tmp = tmp * step; 831 result = base - tmp; 832 } 833 834 return result; 835 } 836 837 static void rt1320_pr_read(struct rt1320_sdw_priv *rt1320, unsigned int reg, unsigned int *val) 838 { 839 unsigned int byte3, byte2, byte1, byte0; 840 841 regmap_write(rt1320->regmap, 0xc483, 0x80); 842 regmap_write(rt1320->regmap, 0xc482, 0x40); 843 regmap_write(rt1320->regmap, 0xc481, 0x0c); 844 regmap_write(rt1320->regmap, 0xc480, 0x10); 845 846 regmap_write(rt1320->regmap, 0xc487, ((reg & 0xff000000) >> 24)); 847 regmap_write(rt1320->regmap, 0xc486, ((reg & 0x00ff0000) >> 16)); 848 regmap_write(rt1320->regmap, 0xc485, ((reg & 0x0000ff00) >> 8)); 849 regmap_write(rt1320->regmap, 0xc484, (reg & 0x000000ff)); 850 851 regmap_write(rt1320->regmap, 0xc482, 0xc0); 852 853 regmap_read(rt1320->regmap, 0xc48f, &byte3); 854 regmap_read(rt1320->regmap, 0xc48e, &byte2); 855 regmap_read(rt1320->regmap, 0xc48d, &byte1); 856 regmap_read(rt1320->regmap, 0xc48c, &byte0); 857 858 *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; 859 } 860 861 static int rt1320_check_fw_ready(struct rt1320_sdw_priv *rt1320) 862 { 863 struct device *dev = &rt1320->sdw_slave->dev; 864 unsigned int tmp, retry = 0; 865 unsigned int cmd_addr; 866 867 switch (rt1320->dev_id) { 868 case RT1320_DEV_ID: 869 cmd_addr = RT1320_CMD_ID; 870 break; 871 case RT1321_DEV_ID: 872 cmd_addr = RT1321_CMD_ID; 873 break; 874 default: 875 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 876 return -EINVAL; 877 } 878 879 pm_runtime_mark_last_busy(dev); 880 /* check the value of cmd_addr becomes to zero */ 881 while (retry < 500) { 882 regmap_read(rt1320->regmap, cmd_addr, &tmp); 883 if (tmp == 0) 884 break; 885 usleep_range(1000, 1100); 886 retry++; 887 } 888 if (retry == 500) { 889 dev_warn(dev, "%s FW is NOT ready!", __func__); 890 return -ETIMEDOUT; 891 } 892 893 return 0; 894 } 895 896 static int rt1320_check_power_state_ready(struct rt1320_sdw_priv *rt1320, enum rt1320_power_state ps) 897 { 898 struct device *dev = &rt1320->sdw_slave->dev; 899 unsigned int retry = 0, tmp; 900 901 pm_runtime_mark_last_busy(dev); 902 while (retry < 200) { 903 regmap_read(rt1320->regmap, RT1320_POWER_STATE, &tmp); 904 dev_dbg(dev, "%s, RT1320_POWER_STATE=0x%x\n", __func__, tmp); 905 if (tmp >= ps) 906 break; 907 usleep_range(1000, 1500); 908 retry++; 909 } 910 if (retry == 200) { 911 dev_warn(dev, "%s FW Power State is NOT ready!", __func__); 912 return -ETIMEDOUT; 913 } 914 915 return 0; 916 } 917 918 static int rt1320_process_fw_param(struct rt1320_sdw_priv *rt1320, unsigned char *buf, unsigned int buf_size) 919 { 920 struct device *dev = &rt1320->sdw_slave->dev; 921 struct rt1320_paramcmd *paramhr = (struct rt1320_paramcmd *)buf; 922 unsigned char moudleid = paramhr->moudleid; 923 unsigned char cmdtype = paramhr->commandtype; 924 unsigned int fw_param_addr; 925 unsigned int start_addr; 926 int ret = 0; 927 928 switch (rt1320->dev_id) { 929 case RT1320_DEV_ID: 930 fw_param_addr = RT1320_FW_PARAM_ADDR; 931 start_addr = RT1320_CMD_PARAM_ADDR; 932 break; 933 case RT1321_DEV_ID: 934 fw_param_addr = RT1321_FW_PARAM_ADDR; 935 start_addr = RT1321_CMD_PARAM_ADDR; 936 break; 937 default: 938 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 939 return -EINVAL; 940 } 941 942 ret = rt1320_check_fw_ready(rt1320); 943 if (ret < 0) 944 goto _timeout_; 945 946 /* don't set offset 0x0/0x1, it will be set later*/ 947 paramhr->moudleid = 0; 948 paramhr->commandtype = 0; 949 rt1320_data_rw(rt1320, fw_param_addr, buf, buf_size, RT1320_PARAM_WRITE); 950 951 dev_dbg(dev, "%s, moudleid=%d, cmdtype=%d, paramid=%d, paramlength=%d\n", __func__, 952 moudleid, cmdtype, paramhr->paramid, paramhr->paramlength); 953 954 if (cmdtype == RT1320_SET_PARAM) { 955 regmap_write(rt1320->regmap, fw_param_addr, moudleid); 956 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x01); 957 } 958 if (cmdtype == RT1320_GET_PARAM) { 959 regmap_write(rt1320->regmap, fw_param_addr, moudleid); 960 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x02); 961 ret = rt1320_check_fw_ready(rt1320); 962 if (ret < 0) 963 goto _timeout_; 964 965 rt1320_data_rw(rt1320, start_addr, buf + 0x10, paramhr->commandlength, RT1320_PARAM_READ); 966 } 967 return 0; 968 969 _timeout_: 970 dev_err(&rt1320->sdw_slave->dev, "%s: FW is NOT ready for SET/GET_PARAM\n", __func__); 971 return ret; 972 } 973 974 static int rt1320_fw_param_protocol(struct rt1320_sdw_priv *rt1320, enum rt1320_fw_cmdid cmdid, 975 unsigned int paramid, void *parambuf, unsigned int paramsize) 976 { 977 struct device *dev = &rt1320->sdw_slave->dev; 978 unsigned char *tempbuf = NULL; 979 struct rt1320_paramcmd paramhr; 980 int ret = 0; 981 982 tempbuf = kzalloc(sizeof(paramhr) + paramsize, GFP_KERNEL); 983 if (!tempbuf) 984 return -ENOMEM; 985 986 paramhr.moudleid = 1; 987 paramhr.commandtype = cmdid; 988 /* 8 is "sizeof(paramid) + sizeof(paramlength)" */ 989 paramhr.commandlength = 8 + paramsize; 990 paramhr.paramid = paramid; 991 paramhr.paramlength = paramsize; 992 993 memcpy(tempbuf, ¶mhr, sizeof(paramhr)); 994 if (cmdid == RT1320_SET_PARAM) 995 memcpy(tempbuf + sizeof(paramhr), parambuf, paramsize); 996 997 ret = rt1320_process_fw_param(rt1320, tempbuf, sizeof(paramhr) + paramsize); 998 if (ret < 0) { 999 dev_err(dev, "%s: process_fw_param failed\n", __func__); 1000 goto _finish_; 1001 } 1002 1003 if (cmdid == RT1320_GET_PARAM) 1004 memcpy(parambuf, tempbuf + sizeof(paramhr), paramsize); 1005 1006 _finish_: 1007 kfree(tempbuf); 1008 return ret; 1009 } 1010 1011 static void rt1320_set_advancemode(struct rt1320_sdw_priv *rt1320) 1012 { 1013 struct device *dev = &rt1320->sdw_slave->dev; 1014 struct rt1320_datafixpoint r0_data[2]; 1015 unsigned short l_advancegain, r_advancegain; 1016 int ret; 1017 1018 /* Get advance gain/r0 */ 1019 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1020 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1021 l_advancegain = r0_data[0].advancegain; 1022 r_advancegain = r0_data[1].advancegain; 1023 dev_dbg(dev, "%s, LR advanceGain=0x%x 0x%x\n", __func__, l_advancegain, r_advancegain); 1024 1025 /* set R0 and enable protection by SetParameter id 6, 7 */ 1026 r0_data[0].silencedetect = 0; 1027 r0_data[0].r0 = rt1320->r0_l_reg; 1028 r0_data[1].silencedetect = 0; 1029 r0_data[1].r0 = rt1320->r0_r_reg; 1030 dev_dbg(dev, "%s, write LR r0=%d, %d\n", __func__, r0_data[0].r0, r0_data[1].r0); 1031 1032 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1033 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1034 ret = rt1320_check_fw_ready(rt1320); 1035 if (ret < 0) 1036 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__); 1037 1038 if (l_advancegain != 0 && r_advancegain != 0) { 1039 regmap_write(rt1320->regmap, 0xdd0b, (l_advancegain & 0xff00) >> 8); 1040 regmap_write(rt1320->regmap, 0xdd0a, (l_advancegain & 0xff)); 1041 regmap_write(rt1320->regmap, 0xdd09, (r_advancegain & 0xff00) >> 8); 1042 regmap_write(rt1320->regmap, 0xdd08, (r_advancegain & 0xff)); 1043 dev_dbg(dev, "%s, set Advance mode gain\n", __func__); 1044 } 1045 } 1046 1047 static int rt1320_invrs_load(struct rt1320_sdw_priv *rt1320) 1048 { 1049 struct device *dev = &rt1320->sdw_slave->dev; 1050 unsigned long long l_rsratio, r_rsratio; 1051 unsigned int pr_1058, pr_1059, pr_105a; 1052 unsigned long long l_invrs, r_invrs; 1053 unsigned long long factor = (1 << 28); 1054 unsigned int l_rsgain, r_rsgain; 1055 struct rt1320_datafixpoint r0_data[2]; 1056 int ret; 1057 1058 /* read L/Rch Rs Gain - it uses for compensating the R0 value */ 1059 rt1320_pr_read(rt1320, 0x1058, &pr_1058); 1060 rt1320_pr_read(rt1320, 0x1059, &pr_1059); 1061 rt1320_pr_read(rt1320, 0x105a, &pr_105a); 1062 l_rsgain = ((pr_1059 & 0x7f) << 2) | ((pr_105a & 0xc0) >> 6); 1063 r_rsgain = ((pr_1058 & 0xff) << 1) | ((pr_1059 & 0x80) >> 7); 1064 dev_dbg(dev, "%s, LR rsgain=0x%x, 0x%x\n", __func__, l_rsgain, r_rsgain); 1065 1066 l_rsratio = rt1320_rsgain_to_rsratio(rt1320, l_rsgain); 1067 r_rsratio = rt1320_rsgain_to_rsratio(rt1320, r_rsgain); 1068 dev_dbg(dev, "%s, LR rsratio=%lld, %lld\n", __func__, l_rsratio, r_rsratio); 1069 1070 l_invrs = (l_rsratio * factor) / 1000000000U; 1071 r_invrs = (r_rsratio * factor) / 1000000000U; 1072 1073 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1074 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1075 1076 r0_data[0].invrs = l_invrs; 1077 r0_data[1].invrs = r_invrs; 1078 dev_dbg(dev, "%s, write DSP LR invrs=0x%x, 0x%x\n", __func__, r0_data[0].invrs, r0_data[1].invrs); 1079 1080 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1081 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1082 ret = rt1320_check_fw_ready(rt1320); 1083 if (ret < 0) 1084 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__); 1085 1086 return ret; 1087 } 1088 1089 static void rt1320_calc_r0(struct rt1320_sdw_priv *rt1320) 1090 { 1091 struct device *dev = &rt1320->sdw_slave->dev; 1092 unsigned long long l_calir0, r_calir0; 1093 const unsigned int factor = (1 << 27); 1094 1095 l_calir0 = (rt1320->r0_l_reg * 1000) / factor; 1096 r_calir0 = (rt1320->r0_r_reg * 1000) / factor; 1097 1098 dev_dbg(dev, "%s, l_calir0=%lld.%03lld ohm, r_calir0=%lld.%03lld ohm\n", __func__, 1099 l_calir0 / 1000, l_calir0 % 1000, 1100 r_calir0 / 1000, r_calir0 % 1000); 1101 } 1102 1103 static void rt1320_calibrate(struct rt1320_sdw_priv *rt1320) 1104 { 1105 struct device *dev = &rt1320->sdw_slave->dev; 1106 struct rt1320_datafixpoint audfixpoint[2]; 1107 unsigned int reg_c5fb, reg_c570, reg_cd00; 1108 unsigned int vol_reg[4], fw_ready; 1109 unsigned long long l_meanr0, r_meanr0; 1110 unsigned int fw_status_addr; 1111 int l_re[5], r_re[5]; 1112 int ret, tmp; 1113 unsigned long long factor = (1 << 27); 1114 unsigned short l_advancegain, r_advancegain; 1115 unsigned int delay_s = 7; /* delay seconds for the calibration */ 1116 1117 if (!rt1320->component) 1118 return; 1119 1120 switch (rt1320->dev_id) { 1121 case RT1320_DEV_ID: 1122 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 1123 break; 1124 case RT1321_DEV_ID: 1125 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 1126 break; 1127 default: 1128 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1129 return; 1130 } 1131 1132 /* set volume 0dB */ 1133 regmap_read(rt1320->regmap, 0xdd0b, &vol_reg[3]); 1134 regmap_read(rt1320->regmap, 0xdd0a, &vol_reg[2]); 1135 regmap_read(rt1320->regmap, 0xdd09, &vol_reg[1]); 1136 regmap_read(rt1320->regmap, 0xdd08, &vol_reg[0]); 1137 regmap_write(rt1320->regmap, 0xdd0b, 0x0f); 1138 regmap_write(rt1320->regmap, 0xdd0a, 0xff); 1139 regmap_write(rt1320->regmap, 0xdd09, 0x0f); 1140 regmap_write(rt1320->regmap, 0xdd08, 0xff); 1141 1142 regmap_read(rt1320->regmap, 0xc5fb, ®_c5fb); 1143 regmap_read(rt1320->regmap, 0xc570, ®_c570); 1144 regmap_read(rt1320->regmap, 0xcd00, ®_cd00); 1145 1146 regmap_write(rt1320->regmap, 1147 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1148 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1149 if (ret < 0) { 1150 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__); 1151 goto _finish_; 1152 } 1153 1154 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 1155 fw_ready &= 0x1; 1156 if (!fw_ready) { 1157 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__); 1158 goto _finish_; 1159 } 1160 1161 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE); 1162 if (ret < 0) { 1163 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__); 1164 goto _finish_; 1165 } 1166 1167 if (rt1320->dev_id == RT1320_DEV_ID) 1168 regmap_write(rt1320->regmap, 0xc5fb, 0x00); 1169 regmap_write(rt1320->regmap, 0xc570, 0x0b); 1170 regmap_write(rt1320->regmap, 0xcd00, 0xc5); 1171 1172 /* disable silence detection */ 1173 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0x00); 1174 dev_dbg(dev, "%s, disable silence detection\n", __func__); 1175 1176 ret = rt1320_check_power_state_ready(rt1320, RT1320_K_R0_STATE); 1177 if (ret < 0) { 1178 dev_dbg(dev, "%s, check class D status before k r0\n", __func__); 1179 goto _finish_; 1180 } 1181 1182 for (tmp = 0; tmp < delay_s; tmp++) { 1183 msleep(1000); 1184 pm_runtime_mark_last_busy(dev); 1185 1186 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re)); 1187 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re)); 1188 1189 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]); 1190 dev_dbg(dev, "%s, waiting for calibration R0...%d seconds\n", __func__, tmp + 1); 1191 } 1192 1193 /* Get Calibration data */ 1194 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re)); 1195 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re)); 1196 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]); 1197 1198 /* Get advance gain/mean r0 */ 1199 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &audfixpoint[0], sizeof(struct rt1320_datafixpoint)); 1200 l_meanr0 = audfixpoint[0].meanr0; 1201 l_advancegain = audfixpoint[0].advancegain; 1202 l_meanr0 = ((l_meanr0 * 1000U) / factor); 1203 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &audfixpoint[1], sizeof(struct rt1320_datafixpoint)); 1204 r_meanr0 = audfixpoint[1].meanr0; 1205 r_advancegain = audfixpoint[1].advancegain; 1206 r_meanr0 = ((r_meanr0 * 1000U) / factor); 1207 dev_dbg(dev, "%s, LR meanr0=%lld, %lld\n", __func__, l_meanr0, r_meanr0); 1208 dev_dbg(dev, "%s, LR advanceGain=0x%x, 0x%x\n", __func__, l_advancegain, r_advancegain); 1209 dev_dbg(dev, "%s, LR invrs=0x%x, 0x%x\n", __func__, audfixpoint[0].invrs, audfixpoint[1].invrs); 1210 1211 /* enable silence detection */ 1212 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0xe0); 1213 dev_dbg(dev, "%s, enable silence detection\n", __func__); 1214 1215 regmap_write(rt1320->regmap, 0xc5fb, reg_c5fb); 1216 regmap_write(rt1320->regmap, 0xc570, reg_c570); 1217 regmap_write(rt1320->regmap, 0xcd00, reg_cd00); 1218 1219 rt1320->r0_l_reg = l_re[4]; 1220 rt1320->r0_r_reg = r_re[4]; 1221 rt1320->cali_done = true; 1222 rt1320_calc_r0(rt1320); 1223 1224 _finish_: 1225 regmap_write(rt1320->regmap, 1226 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1227 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1228 1229 /* advance gain will be set when R0 load, not here */ 1230 regmap_write(rt1320->regmap, 0xdd0b, vol_reg[3]); 1231 regmap_write(rt1320->regmap, 0xdd0a, vol_reg[2]); 1232 regmap_write(rt1320->regmap, 0xdd09, vol_reg[1]); 1233 regmap_write(rt1320->regmap, 0xdd08, vol_reg[0]); 1234 } 1235 1236 static int rt1320_r0_cali_get(struct snd_kcontrol *kcontrol, 1237 struct snd_ctl_elem_value *ucontrol) 1238 { 1239 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1240 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1241 1242 ucontrol->value.integer.value[0] = rt1320->cali_done; 1243 return 0; 1244 } 1245 1246 static int rt1320_r0_cali_put(struct snd_kcontrol *kcontrol, 1247 struct snd_ctl_elem_value *ucontrol) 1248 { 1249 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1250 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1251 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(rt1320->component); 1252 int ret; 1253 1254 if (!rt1320->hw_init) 1255 return 0; 1256 1257 ret = pm_runtime_resume(component->dev); 1258 if (ret < 0 && ret != -EACCES) 1259 return ret; 1260 1261 rt1320->cali_done = false; 1262 snd_soc_dapm_mutex_lock(dapm); 1263 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF && 1264 ucontrol->value.integer.value[0]) { 1265 rt1320_calibrate(rt1320); 1266 } 1267 snd_soc_dapm_mutex_unlock(dapm); 1268 1269 return 0; 1270 } 1271 1272 /* 1273 * The 'patch code' is written to the patch code area. 1274 * The patch code area is used for SDCA register expansion flexibility. 1275 */ 1276 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 1277 { 1278 struct sdw_slave *slave = rt1320->sdw_slave; 1279 const struct firmware *patch; 1280 const char *filename; 1281 unsigned int addr, val, min_addr, max_addr; 1282 const unsigned char *ptr; 1283 int ret, i; 1284 1285 switch (rt1320->dev_id) { 1286 case RT1320_DEV_ID: 1287 if (rt1320->version_id <= RT1320_VB) 1288 filename = RT1320_VAB_MCU_PATCH; 1289 else 1290 filename = RT1320_VC_MCU_PATCH; 1291 min_addr = 0x10007000; 1292 max_addr = 0x10007fff; 1293 break; 1294 case RT1321_DEV_ID: 1295 filename = RT1321_VA_MCU_PATCH; 1296 min_addr = 0x10008000; 1297 max_addr = 0x10008fff; 1298 break; 1299 default: 1300 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1301 return; 1302 } 1303 1304 /* load the patch code here */ 1305 ret = request_firmware(&patch, filename, &slave->dev); 1306 if (ret) { 1307 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 1308 regmap_write(rt1320->regmap, 0xc598, 0x00); 1309 regmap_write(rt1320->regmap, min_addr, 0x67); 1310 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80); 1311 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00); 1312 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00); 1313 if (rt1320->dev_id == RT1321_DEV_ID) { 1314 regmap_write(rt1320->regmap, 0xd73c, 0x67); 1315 regmap_write(rt1320->regmap, 0xd73d, 0x80); 1316 regmap_write(rt1320->regmap, 0xd73e, 0x00); 1317 regmap_write(rt1320->regmap, 0xd73f, 0x00); 1318 } 1319 } else { 1320 ptr = (const unsigned char *)patch->data; 1321 if ((patch->size % 8) == 0) { 1322 for (i = 0; i < patch->size; i += 8) { 1323 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 1324 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 1325 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 1326 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 1327 1328 if (addr > max_addr || addr < min_addr) { 1329 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 1330 goto _exit_; 1331 } 1332 if (val > 0xff) { 1333 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 1334 goto _exit_; 1335 } 1336 regmap_write(rt1320->regmap, addr, val); 1337 } 1338 } 1339 _exit_: 1340 release_firmware(patch); 1341 } 1342 } 1343 1344 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 1345 { 1346 unsigned int i, reg, val, delay; 1347 1348 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 1349 reg = rt1320_blind_write[i].reg; 1350 val = rt1320_blind_write[i].def; 1351 delay = rt1320_blind_write[i].delay_us; 1352 1353 if (reg == 0x3fc2bfc7) 1354 rt1320_load_mcu_patch(rt1320); 1355 1356 regmap_write(rt1320->regmap, reg, val); 1357 if (delay) 1358 usleep_range(delay, delay + 1000); 1359 } 1360 } 1361 1362 static void rt1320_t0_load(struct rt1320_sdw_priv *rt1320, unsigned int l_t0, unsigned int r_t0) 1363 { 1364 struct device *dev = &rt1320->sdw_slave->dev; 1365 unsigned int factor = (1 << 22), fw_ready; 1366 int l_t0_data[38], r_t0_data[38]; 1367 unsigned int fw_status_addr; 1368 1369 switch (rt1320->dev_id) { 1370 case RT1320_DEV_ID: 1371 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 1372 break; 1373 case RT1321_DEV_ID: 1374 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 1375 break; 1376 default: 1377 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1378 return; 1379 } 1380 1381 regmap_write(rt1320->regmap, 1382 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1383 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1384 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1385 1386 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 1387 fw_ready &= 0x1; 1388 if (!fw_ready) { 1389 dev_warn(dev, "%s, DSP FW is NOT ready\n", __func__); 1390 goto _exit_; 1391 } 1392 1393 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1394 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1395 1396 l_t0_data[37] = l_t0 * factor; 1397 r_t0_data[37] = r_t0 * factor; 1398 1399 dev_dbg(dev, "%s, write LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]); 1400 1401 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1402 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1403 if (rt1320_check_fw_ready(rt1320) < 0) 1404 dev_err(dev, "%s: Failed to set FW param 3,4!\n", __func__); 1405 1406 rt1320->temp_l_calib = l_t0; 1407 rt1320->temp_r_calib = r_t0; 1408 1409 memset(&l_t0_data[0], 0x00, sizeof(l_t0_data)); 1410 memset(&r_t0_data[0], 0x00, sizeof(r_t0_data)); 1411 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1412 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1413 dev_dbg(dev, "%s, read after writing LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]); 1414 1415 _exit_: 1416 regmap_write(rt1320->regmap, 1417 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1418 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1419 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1420 } 1421 1422 static int rt1320_rae_load(struct rt1320_sdw_priv *rt1320) 1423 { 1424 struct device *dev = &rt1320->sdw_slave->dev; 1425 static const char func_tag[] = "FUNC"; 1426 static const char xu_tag[] = "XU"; 1427 const struct firmware *rae_fw = NULL; 1428 unsigned int fw_offset; 1429 unsigned char *fw_data; 1430 unsigned char *param_data; 1431 unsigned int addr, size; 1432 unsigned int func, value; 1433 const char *dmi_vendor, *dmi_product, *dmi_sku; 1434 char vendor[128], product[128], sku[128]; 1435 char *ptr_vendor, *ptr_product, *ptr_sku; 1436 char rae_filename[512]; 1437 char tag[5]; 1438 int ret = 0; 1439 int retry = 200; 1440 1441 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1442 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 1443 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 1444 1445 if (dmi_vendor && dmi_product && dmi_sku) { 1446 strscpy(vendor, dmi_vendor); 1447 strscpy(product, dmi_product); 1448 strscpy(sku, dmi_sku); 1449 ptr_vendor = &vendor[0]; 1450 ptr_product = &product[0]; 1451 ptr_sku = &sku[0]; 1452 ptr_vendor = strsep(&ptr_vendor, " "); 1453 ptr_product = strsep(&ptr_product, " "); 1454 ptr_sku = strsep(&ptr_sku, " "); 1455 1456 dev_dbg(dev, "%s: DMI vendor=%s, product=%s, sku=%s\n", __func__, 1457 vendor, product, sku); 1458 1459 snprintf(rae_filename, sizeof(rae_filename), 1460 "realtek/rt1320/rt1320_RAE_%s_%s_%s.dat", vendor, product, sku); 1461 dev_dbg(dev, "%s: try to load RAE file %s\n", __func__, rae_filename); 1462 } else { 1463 dev_warn(dev, "%s: Can't find proper RAE file name\n", __func__); 1464 return -EINVAL; 1465 } 1466 1467 regmap_write(rt1320->regmap, 1468 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1469 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1470 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1471 1472 request_firmware(&rae_fw, rae_filename, dev); 1473 if (rae_fw) { 1474 1475 /* RAE CRC clear */ 1476 regmap_write(rt1320->regmap, 0xe80b, 0x0f); 1477 1478 /* RAE stop & CRC disable */ 1479 regmap_update_bits(rt1320->regmap, 0xe803, 0xbc, 0x00); 1480 1481 while (--retry) { 1482 regmap_read(rt1320->regmap, 0xe83f, &value); 1483 if (value & 0x40) 1484 break; 1485 usleep_range(1000, 1100); 1486 } 1487 if (!retry && !(value & 0x40)) { 1488 dev_err(dev, "%s: RAE is not ready to load\n", __func__); 1489 return -ETIMEDOUT; 1490 } 1491 1492 dev_dbg(dev, "%s, rae_fw size=0x%lx\n", __func__, rae_fw->size); 1493 regcache_cache_bypass(rt1320->regmap, true); 1494 for (fw_offset = 0; fw_offset < rae_fw->size;) { 1495 1496 dev_dbg(dev, "%s, fw_offset=0x%x\n", __func__, fw_offset); 1497 1498 fw_data = (unsigned char *)&rae_fw->data[fw_offset]; 1499 1500 memcpy(tag, fw_data, 4); 1501 tag[4] = '\0'; 1502 dev_dbg(dev, "%s, tag=%s\n", __func__, tag); 1503 if (strcmp(tag, xu_tag) == 0) { 1504 dev_dbg(dev, "%s: This is a XU tag", __func__); 1505 memcpy(&addr, (fw_data + 4), 4); 1506 memcpy(&size, (fw_data + 8), 4); 1507 param_data = (unsigned char *)(fw_data + 12); 1508 1509 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size); 1510 1511 /* 1512 * UI register ranges from 0x1000d000 to 0x1000d7ff 1513 * UI registers should be accessed by tuning tool. 1514 * So, there registers should be cached. 1515 */ 1516 if (addr <= 0x1000d7ff && addr >= 0x1000d000) 1517 regcache_cache_bypass(rt1320->regmap, false); 1518 1519 rt1320_data_rw(rt1320, addr, param_data, size, RT1320_PARAM_WRITE); 1520 1521 regcache_cache_bypass(rt1320->regmap, true); 1522 1523 fw_offset += (size + 12); 1524 } else if (strcmp(tag, func_tag) == 0) { 1525 dev_err(dev, "%s: This is a FUNC tag", __func__); 1526 1527 memcpy(&func, (fw_data + 4), 4); 1528 memcpy(&value, (fw_data + 8), 4); 1529 1530 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", __func__, func, value); 1531 if (func == 1) //DelayMs 1532 msleep(value); 1533 1534 fw_offset += 12; 1535 } else { 1536 dev_err(dev, "%s: This is NOT a XU file (wrong tag)", __func__); 1537 break; 1538 } 1539 } 1540 1541 regcache_cache_bypass(rt1320->regmap, false); 1542 release_firmware(rae_fw); 1543 1544 } else { 1545 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, rae_filename); 1546 ret = -EINVAL; 1547 goto _exit_; 1548 } 1549 1550 /* RAE CRC enable */ 1551 regmap_update_bits(rt1320->regmap, 0xe803, 0x0c, 0x0c); 1552 1553 /* RAE update */ 1554 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x00); 1555 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x80); 1556 1557 /* RAE run */ 1558 regmap_update_bits(rt1320->regmap, 0xe803, 0x80, 0x80); 1559 1560 regmap_read(rt1320->regmap, 0xe80b, &value); 1561 dev_dbg(dev, "%s: CAE run => 0xe80b reg = 0x%x\n", __func__, value); 1562 1563 rt1320->rae_update_done = true; 1564 1565 _exit_: 1566 regmap_write(rt1320->regmap, 1567 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1568 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1569 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1570 1571 return ret; 1572 } 1573 1574 static void rt1320_dspfw_load_code(struct rt1320_sdw_priv *rt1320) 1575 { 1576 struct rt1320_imageinfo { 1577 unsigned int addr; 1578 unsigned int size; 1579 }; 1580 1581 struct rt1320_dspfwheader { 1582 unsigned int sync; 1583 short num; 1584 short crc; 1585 }; 1586 1587 struct snd_soc_dapm_context *dapm = 1588 snd_soc_component_get_dapm(rt1320->component); 1589 struct device *dev = &rt1320->sdw_slave->dev; 1590 unsigned int val, i, fw_offset, fw_ready; 1591 unsigned int fw_status_addr; 1592 struct rt1320_dspfwheader *fwheader; 1593 struct rt1320_imageinfo *ptr_img; 1594 struct sdw_bpt_section sec[10]; 1595 const struct firmware *fw = NULL; 1596 unsigned char *fw_data; 1597 bool dev_fw_match = false; 1598 static const char hdr_sig[] = "AFX"; 1599 unsigned int hdr_size = 0; 1600 const char *dmi_vendor, *dmi_product, *dmi_sku; 1601 char vendor[128], product[128], sku[128]; 1602 char *ptr_vendor, *ptr_product, *ptr_sku; 1603 char filename[512]; 1604 1605 switch (rt1320->dev_id) { 1606 case RT1320_DEV_ID: 1607 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 1608 break; 1609 case RT1321_DEV_ID: 1610 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 1611 break; 1612 default: 1613 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1614 return; 1615 } 1616 1617 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1618 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 1619 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 1620 1621 if (dmi_vendor && dmi_product && dmi_sku) { 1622 strscpy(vendor, dmi_vendor); 1623 strscpy(product, dmi_product); 1624 strscpy(sku, dmi_sku); 1625 ptr_vendor = &vendor[0]; 1626 ptr_product = &product[0]; 1627 ptr_sku = &sku[0]; 1628 ptr_vendor = strsep(&ptr_vendor, " "); 1629 ptr_product = strsep(&ptr_product, " "); 1630 ptr_sku = strsep(&ptr_sku, " "); 1631 1632 dev_dbg(dev, "%s: DMI vendor=%s, product=%s, sku=%s\n", __func__, 1633 vendor, product, sku); 1634 1635 snprintf(filename, sizeof(filename), 1636 "realtek/rt1320/rt1320_%s_%s_%s.dat", vendor, product, sku); 1637 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename); 1638 } else if (rt1320->dspfw_name) { 1639 snprintf(filename, sizeof(filename), "rt1320_%s.dat", 1640 rt1320->dspfw_name); 1641 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename); 1642 } else { 1643 dev_warn(dev, "%s: Can't find proper FW file name\n", __func__); 1644 return; 1645 } 1646 1647 snd_soc_dapm_mutex_lock(dapm); 1648 regmap_write(rt1320->regmap, 1649 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1650 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1651 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1652 1653 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 1654 fw_ready &= 0x1; 1655 if (fw_ready) { 1656 dev_dbg(dev, "%s, DSP FW was already\n", __func__); 1657 rt1320->fw_load_done = true; 1658 goto _exit_; 1659 } 1660 1661 /* change to IRAM */ 1662 regmap_update_bits(rt1320->regmap, 0xf01e, 0x80, 0x00); 1663 1664 request_firmware(&fw, filename, dev); 1665 if (fw) { 1666 fwheader = (struct rt1320_dspfwheader *)fw->data; 1667 dev_dbg(dev, "%s, fw sync = 0x%x, num=%d, crc=0x%x\n", __func__, 1668 fwheader->sync, fwheader->num, fwheader->crc); 1669 1670 if (fwheader->sync != 0x0a1c5679) { 1671 dev_err(dev, "%s: FW sync error\n", __func__); 1672 release_firmware(fw); 1673 goto _exit_; 1674 } 1675 1676 fw_offset = sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * fwheader->num); 1677 dev_dbg(dev, "%s, fw_offset = 0x%x\n", __func__, fw_offset); 1678 1679 regcache_cache_bypass(rt1320->regmap, true); 1680 1681 for (i = 0; i < fwheader->num; i++) { 1682 ptr_img = (struct rt1320_imageinfo *)&fw->data[sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * i)]; 1683 1684 dev_dbg(dev, "%s, fw_offset=0x%x, load fw addr=0x%x, size=%d\n", __func__, 1685 fw_offset, ptr_img->addr, ptr_img->size); 1686 1687 fw_data = (unsigned char *)&fw->data[fw_offset]; 1688 1689 /* The binary file has a header of 64 bytes */ 1690 if (memcmp(fw_data, hdr_sig, sizeof(hdr_sig)) == 0) 1691 hdr_size = 64; 1692 else 1693 hdr_size = 0; 1694 1695 sec[i].addr = ptr_img->addr; 1696 sec[i].len = ptr_img->size - hdr_size; 1697 sec[i].buf = fw_data + hdr_size; 1698 1699 dev_dbg(dev, "%s, hdr_size=%d, sec[%d].buf[0]=0x%x\n", 1700 __func__, hdr_size, i, sec[i].buf[0]); 1701 1702 switch (rt1320->dev_id) { 1703 case RT1320_DEV_ID: 1704 if (ptr_img->addr == 0x3fc29d80) 1705 if (fw_data[9] == '0') 1706 dev_fw_match = true; 1707 break; 1708 case RT1321_DEV_ID: 1709 if (ptr_img->addr == 0x3fc00000) 1710 if (fw_data[9] == '1') 1711 dev_fw_match = true; 1712 break; 1713 default: 1714 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1715 goto _exit_; 1716 } 1717 1718 fw_offset += ptr_img->size; 1719 } 1720 1721 if (dev_fw_match) { 1722 dev_dbg(dev, "%s, starting BRA downloading FW..\n", __func__); 1723 rt1320->bra_msg.dev_num = rt1320->sdw_slave->dev_num; 1724 rt1320->bra_msg.flags = SDW_MSG_FLAG_WRITE; 1725 rt1320->bra_msg.sections = fwheader->num; 1726 rt1320->bra_msg.sec = &sec[0]; 1727 rt1320_data_rw(rt1320, 0, NULL, 0, RT1320_BRA_WRITE); 1728 dev_dbg(dev, "%s, BRA downloading FW done..\n", __func__); 1729 } 1730 1731 regcache_cache_bypass(rt1320->regmap, false); 1732 release_firmware(fw); 1733 1734 if (!dev_fw_match) { 1735 dev_err(dev, "%s: FW file doesn't match to device\n", __func__); 1736 goto _exit_; 1737 } 1738 } else { 1739 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, filename); 1740 goto _exit_; 1741 } 1742 1743 /* run RAM code */ 1744 regmap_read(rt1320->regmap, 0x3fc2bfc0, &val); 1745 val |= 0x8; 1746 regmap_write(rt1320->regmap, 0x3fc2bfc0, val); 1747 1748 /* clear frame counter */ 1749 switch (rt1320->dev_id) { 1750 case RT1320_DEV_ID: 1751 regmap_write(rt1320->regmap, 0x3fc2bfcb, 0x00); 1752 regmap_write(rt1320->regmap, 0x3fc2bfca, 0x00); 1753 regmap_write(rt1320->regmap, 0x3fc2bfc9, 0x00); 1754 regmap_write(rt1320->regmap, 0x3fc2bfc8, 0x00); 1755 break; 1756 case RT1321_DEV_ID: 1757 regmap_write(rt1320->regmap, 0x3fc2dfcb, 0x00); 1758 regmap_write(rt1320->regmap, 0x3fc2dfca, 0x00); 1759 regmap_write(rt1320->regmap, 0x3fc2dfc9, 0x00); 1760 regmap_write(rt1320->regmap, 0x3fc2dfc8, 0x00); 1761 break; 1762 } 1763 1764 /* enable DSP FW */ 1765 regmap_write(rt1320->regmap, 0xc081, 0xfc); 1766 regmap_update_bits(rt1320->regmap, 0xf01e, 0x1, 0x0); 1767 1768 /* RsRatio should restore into DSP FW when FW was ready */ 1769 rt1320_invrs_load(rt1320); 1770 1771 /* DSP clock switches to PLL */ 1772 regmap_write(rt1320->regmap, 0xc081, 0xfc); 1773 /* pass DSP settings */ 1774 regmap_write(rt1320->regmap, 0xc5c3, 0xf3); 1775 regmap_write(rt1320->regmap, 0xc5c8, 0x05); 1776 1777 rt1320->fw_load_done = true; 1778 1779 pm_runtime_set_autosuspend_delay(dev, 3000); 1780 pm_runtime_mark_last_busy(dev); 1781 1782 _exit_: 1783 regmap_write(rt1320->regmap, 1784 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1785 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1786 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1787 1788 snd_soc_dapm_mutex_unlock(dapm); 1789 } 1790 1791 static void rt1320_load_dspfw_work(struct work_struct *work) 1792 { 1793 struct rt1320_sdw_priv *rt1320 = 1794 container_of(work, struct rt1320_sdw_priv, load_dspfw_work); 1795 int ret; 1796 1797 ret = pm_runtime_resume(rt1320->component->dev); 1798 if (ret < 0 && ret != -EACCES) 1799 return; 1800 1801 dev_dbg(&rt1320->sdw_slave->dev, "%s, Starting to reload DSP FW", __func__); 1802 rt1320_dspfw_load_code(rt1320); 1803 } 1804 1805 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 1806 { 1807 struct sdw_slave *slave = rt1320->sdw_slave; 1808 unsigned int i, reg, val, delay, retry, tmp; 1809 1810 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 1811 reg = rt1320_vc_blind_write[i].reg; 1812 val = rt1320_vc_blind_write[i].def; 1813 delay = rt1320_vc_blind_write[i].delay_us; 1814 1815 if (reg == 0x3fc2bf83) 1816 rt1320_load_mcu_patch(rt1320); 1817 1818 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 1819 (val == 0x00)) { 1820 retry = 200; 1821 while (retry) { 1822 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 1823 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 1824 if (tmp == 0x1f) 1825 break; 1826 usleep_range(1000, 1500); 1827 retry--; 1828 } 1829 if (!retry) 1830 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 1831 } 1832 regmap_write(rt1320->regmap, reg, val); 1833 if (delay) 1834 usleep_range(delay, delay + 1000); 1835 1836 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 1837 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 1838 } 1839 } 1840 1841 static void rt1321_preset(struct rt1320_sdw_priv *rt1320) 1842 { 1843 unsigned int i, reg, val, delay; 1844 1845 for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) { 1846 reg = rt1321_blind_write[i].reg; 1847 val = rt1321_blind_write[i].def; 1848 delay = rt1321_blind_write[i].delay_us; 1849 1850 if (reg == 0x3fc2dfc3) 1851 rt1320_load_mcu_patch(rt1320); 1852 1853 regmap_write(rt1320->regmap, reg, val); 1854 1855 if (delay) 1856 usleep_range(delay, delay + 1000); 1857 1858 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 1859 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 1860 } 1861 } 1862 1863 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 1864 { 1865 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1866 unsigned int amp_func_status, val, tmp; 1867 1868 if (rt1320->hw_init) 1869 return 0; 1870 1871 regcache_cache_only(rt1320->regmap, false); 1872 regcache_cache_only(rt1320->mbq_regmap, false); 1873 if (rt1320->first_hw_init) { 1874 regcache_cache_bypass(rt1320->regmap, true); 1875 regcache_cache_bypass(rt1320->mbq_regmap, true); 1876 } else { 1877 /* 1878 * PM runtime status is marked as 'active' only when a Slave reports as Attached 1879 */ 1880 /* update count of parent 'active' children */ 1881 pm_runtime_set_active(&slave->dev); 1882 } 1883 1884 pm_runtime_get_noresume(&slave->dev); 1885 1886 if (rt1320->version_id < 0) { 1887 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 1888 rt1320->version_id = val; 1889 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val); 1890 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp); 1891 rt1320->dev_id = (val << 8) | tmp; 1892 } 1893 1894 regmap_read(rt1320->regmap, 1895 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 1896 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 1897 1898 /* initialization write */ 1899 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 1900 switch (rt1320->dev_id) { 1901 case RT1320_DEV_ID: 1902 if (rt1320->version_id < RT1320_VC) 1903 rt1320_vab_preset(rt1320); 1904 else 1905 rt1320_vc_preset(rt1320); 1906 break; 1907 case RT1321_DEV_ID: 1908 rt1321_preset(rt1320); 1909 break; 1910 default: 1911 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1912 } 1913 1914 regmap_write(rt1320->regmap, 1915 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 1916 FUNCTION_NEEDS_INITIALIZATION); 1917 1918 /* reload DSP FW */ 1919 if (rt1320->fw_load_done) 1920 schedule_work(&rt1320->load_dspfw_work); 1921 } 1922 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) { 1923 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1924 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 1925 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 1926 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 1927 val = (tmp << 8) | val; 1928 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 1929 val = (tmp << 16) | val; 1930 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 1931 val = (tmp << 24) | val; 1932 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 1933 /* 1934 * We call the version b which has the new DSP ROM code against version a. 1935 * Therefore, we read the DSP address to check the ID. 1936 */ 1937 if (val == RT1320_VER_B_ID) 1938 rt1320->version_id = RT1320_VB; 1939 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1940 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 1941 } 1942 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id); 1943 1944 if (rt1320->first_hw_init) { 1945 regcache_cache_bypass(rt1320->regmap, false); 1946 regcache_cache_bypass(rt1320->mbq_regmap, false); 1947 regcache_mark_dirty(rt1320->regmap); 1948 regcache_mark_dirty(rt1320->mbq_regmap); 1949 } 1950 1951 /* Mark Slave initialization complete */ 1952 rt1320->first_hw_init = true; 1953 rt1320->hw_init = true; 1954 1955 pm_runtime_put_autosuspend(&slave->dev); 1956 1957 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1958 return 0; 1959 } 1960 1961 static int rt1320_update_status(struct sdw_slave *slave, 1962 enum sdw_slave_status status) 1963 { 1964 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 1965 1966 if (status == SDW_SLAVE_UNATTACHED) 1967 rt1320->hw_init = false; 1968 1969 /* 1970 * Perform initialization only if slave status is present and 1971 * hw_init flag is false 1972 */ 1973 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 1974 return 0; 1975 1976 /* perform I/O transfers required for Slave initialization */ 1977 return rt1320_io_init(&slave->dev, slave); 1978 } 1979 1980 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 1981 struct snd_kcontrol *kcontrol, int event) 1982 { 1983 struct snd_soc_component *component = 1984 snd_soc_dapm_to_component(w->dapm); 1985 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1986 unsigned char ps0 = 0x0, ps3 = 0x3; 1987 1988 switch (event) { 1989 case SND_SOC_DAPM_POST_PMU: 1990 regmap_write(rt1320->regmap, 1991 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 1992 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1993 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 1994 break; 1995 case SND_SOC_DAPM_PRE_PMD: 1996 regmap_write(rt1320->regmap, 1997 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 1998 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1999 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 2000 break; 2001 default: 2002 break; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 2009 struct snd_kcontrol *kcontrol, int event) 2010 { 2011 struct snd_soc_component *component = 2012 snd_soc_dapm_to_component(w->dapm); 2013 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2014 unsigned char ps0 = 0x0, ps3 = 0x3; 2015 2016 switch (event) { 2017 case SND_SOC_DAPM_POST_PMU: 2018 regmap_write(rt1320->regmap, 2019 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2020 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 2021 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 2022 break; 2023 case SND_SOC_DAPM_PRE_PMD: 2024 regmap_write(rt1320->regmap, 2025 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2026 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 2027 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 2028 break; 2029 default: 2030 break; 2031 } 2032 2033 return 0; 2034 } 2035 2036 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 2037 struct snd_ctl_elem_value *ucontrol) 2038 { 2039 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2040 struct soc_mixer_control *mc = 2041 (struct soc_mixer_control *)kcontrol->private_value; 2042 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2043 unsigned int gain_l_val, gain_r_val; 2044 unsigned int lvalue, rvalue; 2045 const unsigned int interval_offset = 0xc0; 2046 unsigned int changed = 0, reg_base; 2047 struct rt_sdca_dmic_kctrl_priv *p; 2048 unsigned int regvalue[4], gain_val[4], i; 2049 int err; 2050 2051 if (strstr(ucontrol->id.name, "FU Capture Volume")) 2052 goto _dmic_vol_; 2053 2054 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 2055 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 2056 2057 /* L Channel */ 2058 gain_l_val = ucontrol->value.integer.value[0]; 2059 if (gain_l_val > mc->max) 2060 gain_l_val = mc->max; 2061 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 2062 gain_l_val &= 0xffff; 2063 2064 /* R Channel */ 2065 gain_r_val = ucontrol->value.integer.value[1]; 2066 if (gain_r_val > mc->max) 2067 gain_r_val = mc->max; 2068 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 2069 gain_r_val &= 0xffff; 2070 2071 if (lvalue == gain_l_val && rvalue == gain_r_val) 2072 return 0; 2073 2074 /* Lch*/ 2075 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 2076 /* Rch */ 2077 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 2078 goto _done_; 2079 2080 _dmic_vol_: 2081 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2082 2083 /* check all channels */ 2084 for (i = 0; i < p->count; i++) { 2085 switch (rt1320->dev_id) { 2086 case RT1320_DEV_ID: 2087 if (i < 2) { 2088 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2089 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 2090 } else { 2091 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2092 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 2093 } 2094 break; 2095 case RT1321_DEV_ID: 2096 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2097 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 2098 break; 2099 } 2100 2101 gain_val[i] = ucontrol->value.integer.value[i]; 2102 if (gain_val[i] > p->max) 2103 gain_val[i] = p->max; 2104 2105 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 2106 gain_val[i] &= 0xffff; 2107 if (regvalue[i] != gain_val[i]) 2108 changed = 1; 2109 } 2110 2111 if (!changed) 2112 return 0; 2113 2114 for (i = 0; i < p->count; i++) { 2115 switch (rt1320->dev_id) { 2116 case RT1320_DEV_ID: 2117 if (i < 2) { 2118 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2119 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 2120 } else { 2121 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2122 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 2123 } 2124 break; 2125 case RT1321_DEV_ID: 2126 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2127 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 2128 break; 2129 } 2130 2131 if (err < 0) 2132 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 2133 } 2134 2135 _done_: 2136 return 1; 2137 } 2138 2139 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 2140 struct snd_ctl_elem_value *ucontrol) 2141 { 2142 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2143 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2144 struct soc_mixer_control *mc = 2145 (struct soc_mixer_control *)kcontrol->private_value; 2146 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 2147 const unsigned int interval_offset = 0xc0; 2148 unsigned int reg_base, regvalue, ctl, i; 2149 struct rt_sdca_dmic_kctrl_priv *p; 2150 2151 if (strstr(ucontrol->id.name, "FU Capture Volume")) 2152 goto _dmic_vol_; 2153 2154 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 2155 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 2156 2157 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 2158 2159 if (read_l != read_r) 2160 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 2161 else 2162 ctl_r = ctl_l; 2163 2164 ucontrol->value.integer.value[0] = ctl_l; 2165 ucontrol->value.integer.value[1] = ctl_r; 2166 goto _done_; 2167 2168 _dmic_vol_: 2169 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2170 2171 /* check all channels */ 2172 for (i = 0; i < p->count; i++) { 2173 switch (rt1320->dev_id) { 2174 case RT1320_DEV_ID: 2175 if (i < 2) { 2176 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2177 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 2178 } else { 2179 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2180 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 2181 } 2182 break; 2183 case RT1321_DEV_ID: 2184 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2185 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 2186 break; 2187 } 2188 2189 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 2190 ucontrol->value.integer.value[i] = ctl; 2191 } 2192 _done_: 2193 return 0; 2194 } 2195 2196 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 2197 { 2198 int err, i; 2199 unsigned int ch_mute; 2200 2201 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 2202 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 2203 2204 switch (rt1320->dev_id) { 2205 case RT1320_DEV_ID: 2206 if (i < 2) 2207 err = regmap_write(rt1320->regmap, 2208 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 2209 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 2210 else 2211 err = regmap_write(rt1320->regmap, 2212 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 2213 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 2214 break; 2215 case RT1321_DEV_ID: 2216 err = regmap_write(rt1320->regmap, 2217 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 2218 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 2219 break; 2220 default: 2221 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2222 return -EINVAL; 2223 } 2224 if (err < 0) 2225 return err; 2226 } 2227 2228 return 0; 2229 } 2230 2231 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 2232 struct snd_ctl_elem_value *ucontrol) 2233 { 2234 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2235 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2236 struct rt_sdca_dmic_kctrl_priv *p = 2237 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2238 unsigned int i; 2239 2240 for (i = 0; i < p->count; i++) 2241 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 2242 2243 return 0; 2244 } 2245 2246 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 2247 struct snd_ctl_elem_value *ucontrol) 2248 { 2249 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2250 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2251 struct rt_sdca_dmic_kctrl_priv *p = 2252 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2253 int err, changed = 0, i; 2254 2255 for (i = 0; i < p->count; i++) { 2256 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 2257 changed = 1; 2258 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 2259 } 2260 2261 err = rt1320_set_fu_capture_ctl(rt1320); 2262 if (err < 0) 2263 return err; 2264 2265 return changed; 2266 } 2267 2268 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 2269 struct snd_ctl_elem_info *uinfo) 2270 { 2271 struct rt_sdca_dmic_kctrl_priv *p = 2272 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2273 2274 if (p->max == 1) 2275 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2276 else 2277 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2278 uinfo->count = p->count; 2279 uinfo->value.integer.min = 0; 2280 uinfo->value.integer.max = p->max; 2281 return 0; 2282 } 2283 2284 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 2285 struct snd_kcontrol *kcontrol, int event) 2286 { 2287 struct snd_soc_component *component = 2288 snd_soc_dapm_to_component(w->dapm); 2289 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2290 2291 switch (event) { 2292 case SND_SOC_DAPM_POST_PMU: 2293 rt1320->fu_dapm_mute = false; 2294 rt1320_set_fu_capture_ctl(rt1320); 2295 break; 2296 case SND_SOC_DAPM_PRE_PMD: 2297 rt1320->fu_dapm_mute = true; 2298 rt1320_set_fu_capture_ctl(rt1320); 2299 break; 2300 } 2301 return 0; 2302 } 2303 2304 static const char * const rt1320_rx_data_ch_select[] = { 2305 "L,R", 2306 "R,L", 2307 "L,L", 2308 "R,R", 2309 "L,L+R", 2310 "R,L+R", 2311 "L+R,L", 2312 "L+R,R", 2313 "L+R,L+R", 2314 }; 2315 2316 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 2317 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 2318 rt1320_rx_data_ch_select); 2319 2320 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 2321 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 2322 2323 static int rt1320_r0_load(struct rt1320_sdw_priv *rt1320) 2324 { 2325 struct device *dev = regmap_get_device(rt1320->regmap); 2326 unsigned int fw_status_addr; 2327 unsigned int fw_ready; 2328 int ret = 0; 2329 2330 if (!rt1320->r0_l_reg || !rt1320->r0_r_reg) 2331 return -EINVAL; 2332 2333 switch (rt1320->dev_id) { 2334 case RT1320_DEV_ID: 2335 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 2336 break; 2337 case RT1321_DEV_ID: 2338 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 2339 break; 2340 default: 2341 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2342 return -EINVAL; 2343 } 2344 2345 regmap_write(rt1320->regmap, 2346 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 2347 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 2348 if (ret < 0) { 2349 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__); 2350 goto _timeout_; 2351 } 2352 2353 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 2354 fw_ready &= 0x1; 2355 if (!fw_ready) { 2356 dev_dbg(dev, "%s, DSP FW is NOT ready\n", __func__); 2357 goto _timeout_; 2358 } 2359 2360 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE); 2361 if (ret < 0) { 2362 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__); 2363 goto _timeout_; 2364 } 2365 2366 rt1320_set_advancemode(rt1320); 2367 2368 _timeout_: 2369 regmap_write(rt1320->regmap, 2370 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 2371 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 2372 2373 return ret; 2374 } 2375 2376 static int rt1320_r0_load_mode_get(struct snd_kcontrol *kcontrol, 2377 struct snd_ctl_elem_value *ucontrol) 2378 { 2379 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2380 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2381 2382 ucontrol->value.integer.value[0] = rt1320->r0_l_reg; 2383 ucontrol->value.integer.value[1] = rt1320->r0_r_reg; 2384 2385 return 0; 2386 } 2387 2388 static int rt1320_r0_load_mode_put(struct snd_kcontrol *kcontrol, 2389 struct snd_ctl_elem_value *ucontrol) 2390 { 2391 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2392 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2393 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(rt1320->component); 2394 int ret; 2395 2396 if (!rt1320->hw_init) 2397 return 0; 2398 2399 if (ucontrol->value.integer.value[0] == 0 || 2400 ucontrol->value.integer.value[1] == 0) 2401 return -EINVAL; 2402 2403 ret = pm_runtime_resume(component->dev); 2404 if (ret < 0 && ret != -EACCES) 2405 return ret; 2406 2407 snd_soc_dapm_mutex_lock(dapm); 2408 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 2409 rt1320->r0_l_reg = ucontrol->value.integer.value[0]; 2410 rt1320->r0_r_reg = ucontrol->value.integer.value[1]; 2411 rt1320_calc_r0(rt1320); 2412 rt1320_r0_load(rt1320); 2413 } 2414 snd_soc_dapm_mutex_unlock(dapm); 2415 2416 return 0; 2417 } 2418 2419 static int rt1320_t0_r0_load_info(struct snd_kcontrol *kcontrol, 2420 struct snd_ctl_elem_info *uinfo) 2421 { 2422 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2423 uinfo->count = 2; 2424 uinfo->value.integer.max = kcontrol->private_value; 2425 2426 return 0; 2427 } 2428 2429 #define RT1320_T0_R0_LOAD(xname, xmax, xhandler_get, xhandler_put) \ 2430 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2431 .info = rt1320_t0_r0_load_info, \ 2432 .get = xhandler_get, \ 2433 .put = xhandler_put, \ 2434 .private_value = xmax, \ 2435 } 2436 2437 static int rt1320_dspfw_load_get(struct snd_kcontrol *kcontrol, 2438 struct snd_ctl_elem_value *ucontrol) 2439 { 2440 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2441 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2442 2443 ucontrol->value.integer.value[0] = rt1320->fw_load_done; 2444 return 0; 2445 } 2446 2447 static int rt1320_dspfw_load_put(struct snd_kcontrol *kcontrol, 2448 struct snd_ctl_elem_value *ucontrol) 2449 { 2450 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2451 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2452 int ret; 2453 2454 if (!rt1320->hw_init) 2455 return 0; 2456 2457 ret = pm_runtime_resume(component->dev); 2458 if (ret < 0 && ret != -EACCES) 2459 return ret; 2460 2461 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF && 2462 ucontrol->value.integer.value[0]) 2463 rt1320_dspfw_load_code(rt1320); 2464 2465 if (!ucontrol->value.integer.value[0]) 2466 rt1320->fw_load_done = false; 2467 2468 return 0; 2469 } 2470 2471 static int rt1320_rae_update_get(struct snd_kcontrol *kcontrol, 2472 struct snd_ctl_elem_value *ucontrol) 2473 { 2474 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2475 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2476 2477 ucontrol->value.integer.value[0] = rt1320->rae_update_done; 2478 return 0; 2479 } 2480 2481 static int rt1320_rae_update_put(struct snd_kcontrol *kcontrol, 2482 struct snd_ctl_elem_value *ucontrol) 2483 { 2484 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2485 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2486 int ret; 2487 2488 if (!rt1320->hw_init) 2489 return 0; 2490 2491 ret = pm_runtime_resume(component->dev); 2492 if (ret < 0 && ret != -EACCES) 2493 return ret; 2494 2495 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF && 2496 ucontrol->value.integer.value[0] && rt1320->fw_load_done) 2497 rt1320_rae_load(rt1320); 2498 2499 if (!ucontrol->value.integer.value[0]) 2500 rt1320->rae_update_done = false; 2501 2502 return 0; 2503 } 2504 2505 static int rt1320_r0_temperature_get(struct snd_kcontrol *kcontrol, 2506 struct snd_ctl_elem_value *ucontrol) 2507 { 2508 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2509 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2510 2511 ucontrol->value.integer.value[0] = rt1320->temp_l_calib; 2512 ucontrol->value.integer.value[1] = rt1320->temp_r_calib; 2513 return 0; 2514 } 2515 2516 static int rt1320_r0_temperature_put(struct snd_kcontrol *kcontrol, 2517 struct snd_ctl_elem_value *ucontrol) 2518 { 2519 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2520 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2521 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(rt1320->component); 2522 int ret; 2523 2524 if (!rt1320->hw_init) 2525 return 0; 2526 2527 ret = pm_runtime_resume(component->dev); 2528 if (ret < 0 && ret != -EACCES) 2529 return ret; 2530 2531 snd_soc_dapm_mutex_lock(dapm); 2532 if ((snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) && 2533 ucontrol->value.integer.value[0] && ucontrol->value.integer.value[1]) 2534 rt1320_t0_load(rt1320, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1]); 2535 snd_soc_dapm_mutex_unlock(dapm); 2536 2537 return 0; 2538 } 2539 2540 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 2541 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 2542 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 2543 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 2544 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 2545 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 2546 2547 RT_SDCA_FU_CTRL("FU Capture Switch", 2548 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 2549 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 2550 RT_SDCA_EXT_TLV("FU Capture Volume", 2551 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 2552 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 2553 2554 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0, 2555 rt1320_r0_cali_get, rt1320_r0_cali_put), 2556 SOC_SINGLE_EXT("DSP FW Update", SND_SOC_NOPM, 0, 1, 0, 2557 rt1320_dspfw_load_get, rt1320_dspfw_load_put), 2558 RT1320_T0_R0_LOAD("R0 Load Mode", 0xffffffff, 2559 rt1320_r0_load_mode_get, rt1320_r0_load_mode_put), 2560 RT1320_T0_R0_LOAD("R0 Temperature", 0xff, 2561 rt1320_r0_temperature_get, rt1320_r0_temperature_put), 2562 SOC_SINGLE_EXT("RAE Update", SND_SOC_NOPM, 0, 1, 0, 2563 rt1320_rae_update_get, rt1320_rae_update_put), 2564 }; 2565 2566 static const struct snd_kcontrol_new rt1320_spk_l_dac = 2567 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 2568 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 2569 0, 1, 1); 2570 static const struct snd_kcontrol_new rt1320_spk_r_dac = 2571 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 2572 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 2573 0, 1, 1); 2574 2575 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 2576 /* Audio Interface */ 2577 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 2578 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 2579 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 2580 2581 /* Digital Interface */ 2582 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 2583 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 2584 rt1320_pde23_event, 2585 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2586 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 2587 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2588 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 2589 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 2590 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 2591 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2592 2593 /* Output */ 2594 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 2595 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 2596 SND_SOC_DAPM_OUTPUT("SPOL"), 2597 SND_SOC_DAPM_OUTPUT("SPOR"), 2598 2599 /* Input */ 2600 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 2601 SND_SOC_DAPM_SIGGEN("AEC Gen"), 2602 SND_SOC_DAPM_INPUT("DMIC1"), 2603 SND_SOC_DAPM_INPUT("DMIC2"), 2604 }; 2605 2606 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 2607 { "FU21", NULL, "DP1RX" }, 2608 { "FU21", NULL, "PDE 23" }, 2609 { "OT23 L", "Switch", "FU21" }, 2610 { "OT23 R", "Switch", "FU21" }, 2611 { "SPOL", NULL, "OT23 L" }, 2612 { "SPOR", NULL, "OT23 R" }, 2613 2614 { "AEC Data", NULL, "AEC Gen" }, 2615 { "DP4TX", NULL, "AEC Data" }, 2616 2617 {"DP8-10TX", NULL, "FU"}, 2618 {"FU", NULL, "PDE 11"}, 2619 {"FU", NULL, "FU 113"}, 2620 {"FU", NULL, "FU 14"}, 2621 {"FU 113", NULL, "DMIC1"}, 2622 {"FU 14", NULL, "DMIC2"}, 2623 }; 2624 2625 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 2626 int direction) 2627 { 2628 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 2629 return 0; 2630 } 2631 2632 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 2633 struct snd_soc_dai *dai) 2634 { 2635 snd_soc_dai_set_dma_data(dai, substream, NULL); 2636 } 2637 2638 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 2639 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2640 { 2641 struct snd_soc_component *component = dai->component; 2642 struct rt1320_sdw_priv *rt1320 = 2643 snd_soc_component_get_drvdata(component); 2644 struct sdw_stream_config stream_config; 2645 struct sdw_port_config port_config; 2646 struct sdw_port_config dmic_port_config[2]; 2647 struct sdw_stream_runtime *sdw_stream; 2648 int retval; 2649 unsigned int sampling_rate; 2650 2651 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 2652 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 2653 2654 if (!sdw_stream) 2655 return -EINVAL; 2656 2657 if (!rt1320->sdw_slave) 2658 return -EINVAL; 2659 2660 /* SoundWire specific configuration */ 2661 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 2662 2663 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2664 if (dai->id == RT1320_AIF1) 2665 port_config.num = 1; 2666 else 2667 return -EINVAL; 2668 } else { 2669 if (dai->id == RT1320_AIF1) 2670 port_config.num = 4; 2671 else if (dai->id == RT1320_AIF2) { 2672 switch (rt1320->dev_id) { 2673 case RT1320_DEV_ID: 2674 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 2675 dmic_port_config[0].num = 8; 2676 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 2677 dmic_port_config[1].num = 10; 2678 break; 2679 case RT1321_DEV_ID: 2680 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 2681 dmic_port_config[0].num = 8; 2682 break; 2683 default: 2684 return -EINVAL; 2685 } 2686 } else 2687 return -EINVAL; 2688 } 2689 2690 if (dai->id == RT1320_AIF1) 2691 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 2692 &port_config, 1, sdw_stream); 2693 else if (dai->id == RT1320_AIF2) { 2694 switch (rt1320->dev_id) { 2695 case RT1320_DEV_ID: 2696 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 2697 dmic_port_config, 2, sdw_stream); 2698 break; 2699 case RT1321_DEV_ID: 2700 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 2701 dmic_port_config, 1, sdw_stream); 2702 break; 2703 default: 2704 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2705 return -EINVAL; 2706 } 2707 } else 2708 return -EINVAL; 2709 if (retval) { 2710 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 2711 return retval; 2712 } 2713 2714 /* sampling rate configuration */ 2715 switch (params_rate(params)) { 2716 case 16000: 2717 sampling_rate = RT1320_SDCA_RATE_16000HZ; 2718 break; 2719 case 32000: 2720 sampling_rate = RT1320_SDCA_RATE_32000HZ; 2721 break; 2722 case 44100: 2723 sampling_rate = RT1320_SDCA_RATE_44100HZ; 2724 break; 2725 case 48000: 2726 sampling_rate = RT1320_SDCA_RATE_48000HZ; 2727 break; 2728 case 96000: 2729 sampling_rate = RT1320_SDCA_RATE_96000HZ; 2730 break; 2731 case 192000: 2732 sampling_rate = RT1320_SDCA_RATE_192000HZ; 2733 break; 2734 default: 2735 dev_err(component->dev, "%s: Rate %d is not supported\n", 2736 __func__, params_rate(params)); 2737 return -EINVAL; 2738 } 2739 2740 /* set sampling frequency */ 2741 if (dai->id == RT1320_AIF1) 2742 regmap_write(rt1320->regmap, 2743 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 2744 sampling_rate); 2745 else { 2746 regmap_write(rt1320->regmap, 2747 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 2748 sampling_rate); 2749 2750 if (rt1320->dev_id == RT1320_DEV_ID) 2751 regmap_write(rt1320->regmap, 2752 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 2753 sampling_rate); 2754 } 2755 2756 return 0; 2757 } 2758 2759 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 2760 struct snd_soc_dai *dai) 2761 { 2762 struct snd_soc_component *component = dai->component; 2763 struct rt1320_sdw_priv *rt1320 = 2764 snd_soc_component_get_drvdata(component); 2765 struct sdw_stream_runtime *sdw_stream = 2766 snd_soc_dai_get_dma_data(dai, substream); 2767 2768 if (!rt1320->sdw_slave) 2769 return -EINVAL; 2770 2771 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 2772 return 0; 2773 } 2774 2775 /* 2776 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 2777 * port_prep are not defined for now 2778 */ 2779 static const struct sdw_slave_ops rt1320_slave_ops = { 2780 .read_prop = rt1320_read_prop, 2781 .update_status = rt1320_update_status, 2782 }; 2783 2784 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 2785 { 2786 int ret; 2787 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2788 2789 rt1320->component = component; 2790 2791 if (!rt1320->first_hw_init) 2792 return 0; 2793 2794 ret = pm_runtime_resume(component->dev); 2795 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 2796 if (ret < 0 && ret != -EACCES) 2797 return ret; 2798 2799 /* Apply temperature and calibration data from device property */ 2800 if ((rt1320->temp_l_calib <= 0xff) && (rt1320->temp_l_calib > 0) && 2801 (rt1320->temp_r_calib <= 0xff) && (rt1320->temp_r_calib > 0)) 2802 rt1320_t0_load(rt1320, rt1320->temp_l_calib, rt1320->temp_r_calib); 2803 2804 if (rt1320->r0_l_calib && rt1320->r0_r_calib) { 2805 rt1320->r0_l_reg = rt1320->r0_l_calib; 2806 rt1320->r0_r_reg = rt1320->r0_r_calib; 2807 rt1320_calc_r0(rt1320); 2808 rt1320_r0_load(rt1320); 2809 } 2810 2811 return 0; 2812 } 2813 2814 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 2815 .probe = rt1320_sdw_component_probe, 2816 .controls = rt1320_snd_controls, 2817 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 2818 .dapm_widgets = rt1320_dapm_widgets, 2819 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 2820 .dapm_routes = rt1320_dapm_routes, 2821 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 2822 .endianness = 1, 2823 }; 2824 2825 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 2826 .hw_params = rt1320_sdw_hw_params, 2827 .hw_free = rt1320_sdw_pcm_hw_free, 2828 .set_stream = rt1320_set_sdw_stream, 2829 .shutdown = rt1320_sdw_shutdown, 2830 }; 2831 2832 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 2833 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 2834 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 2835 SNDRV_PCM_FMTBIT_S32_LE) 2836 2837 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 2838 { 2839 .name = "rt1320-aif1", 2840 .id = RT1320_AIF1, 2841 .playback = { 2842 .stream_name = "DP1 Playback", 2843 .channels_min = 1, 2844 .channels_max = 2, 2845 .rates = RT1320_STEREO_RATES, 2846 .formats = RT1320_FORMATS, 2847 }, 2848 .capture = { 2849 .stream_name = "DP4 Capture", 2850 .channels_min = 1, 2851 .channels_max = 2, 2852 .rates = RT1320_STEREO_RATES, 2853 .formats = RT1320_FORMATS, 2854 }, 2855 .ops = &rt1320_aif_dai_ops, 2856 }, 2857 /* DMIC: DP8 2ch + DP10 2ch */ 2858 { 2859 .name = "rt1320-aif2", 2860 .id = RT1320_AIF2, 2861 .capture = { 2862 .stream_name = "DP8-10 Capture", 2863 .channels_min = 1, 2864 .channels_max = 4, 2865 .rates = RT1320_STEREO_RATES, 2866 .formats = RT1320_FORMATS, 2867 }, 2868 .ops = &rt1320_aif_dai_ops, 2869 }, 2870 }; 2871 2872 static int rt1320_parse_dp(struct rt1320_sdw_priv *rt1320, struct device *dev) 2873 { 2874 device_property_read_u32(dev, "realtek,temperature_l_calib", 2875 &rt1320->temp_l_calib); 2876 device_property_read_u32(dev, "realtek,temperature_r_calib", 2877 &rt1320->temp_r_calib); 2878 device_property_read_u32(dev, "realtek,r0_l_calib", 2879 &rt1320->r0_l_calib); 2880 device_property_read_u32(dev, "realtek,r0_r_calib", 2881 &rt1320->r0_r_calib); 2882 device_property_read_string(dev, "realtek,dspfw-name", 2883 &rt1320->dspfw_name); 2884 2885 dev_dbg(dev, "%s: temp_l_calib: %d temp_r_calib: %d r0_l_calib: %d, r0_r_calib: %d", 2886 __func__, rt1320->temp_l_calib, rt1320->temp_r_calib, rt1320->r0_l_calib, rt1320->r0_r_calib); 2887 dev_dbg(dev, "%s: dspfw_name: %s", __func__, rt1320->dspfw_name); 2888 2889 return 0; 2890 } 2891 2892 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 2893 struct regmap *mbq_regmap, struct sdw_slave *slave) 2894 { 2895 struct rt1320_sdw_priv *rt1320; 2896 int ret; 2897 2898 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 2899 if (!rt1320) 2900 return -ENOMEM; 2901 2902 dev_set_drvdata(dev, rt1320); 2903 rt1320->sdw_slave = slave; 2904 rt1320->mbq_regmap = mbq_regmap; 2905 rt1320->regmap = regmap; 2906 2907 regcache_cache_only(rt1320->regmap, true); 2908 regcache_cache_only(rt1320->mbq_regmap, true); 2909 2910 rt1320_parse_dp(rt1320, dev); 2911 2912 /* 2913 * Mark hw_init to false 2914 * HW init will be performed when device reports present 2915 */ 2916 rt1320->hw_init = false; 2917 rt1320->first_hw_init = false; 2918 rt1320->version_id = -1; 2919 rt1320->fu_dapm_mute = true; 2920 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 2921 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 2922 2923 INIT_WORK(&rt1320->load_dspfw_work, rt1320_load_dspfw_work); 2924 2925 ret = devm_snd_soc_register_component(dev, 2926 &soc_component_sdw_rt1320, 2927 rt1320_sdw_dai, 2928 ARRAY_SIZE(rt1320_sdw_dai)); 2929 if (ret < 0) 2930 return ret; 2931 2932 /* set autosuspend parameters */ 2933 pm_runtime_set_autosuspend_delay(dev, 3000); 2934 pm_runtime_use_autosuspend(dev); 2935 2936 /* make sure the device does not suspend immediately */ 2937 pm_runtime_mark_last_busy(dev); 2938 2939 pm_runtime_enable(dev); 2940 2941 /* important note: the device is NOT tagged as 'active' and will remain 2942 * 'suspended' until the hardware is enumerated/initialized. This is required 2943 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 2944 * fail with -EACCESS because of race conditions between card creation and enumeration 2945 */ 2946 2947 dev_dbg(dev, "%s\n", __func__); 2948 2949 return ret; 2950 } 2951 2952 static int rt1320_sdw_probe(struct sdw_slave *slave, 2953 const struct sdw_device_id *id) 2954 { 2955 struct regmap *regmap, *mbq_regmap; 2956 2957 /* Regmap Initialization */ 2958 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 2959 if (IS_ERR(mbq_regmap)) 2960 return PTR_ERR(mbq_regmap); 2961 2962 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 2963 if (IS_ERR(regmap)) 2964 return PTR_ERR(regmap); 2965 2966 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 2967 } 2968 2969 static int rt1320_sdw_remove(struct sdw_slave *slave) 2970 { 2971 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 2972 2973 cancel_work_sync(&rt1320->load_dspfw_work); 2974 pm_runtime_disable(&slave->dev); 2975 2976 return 0; 2977 } 2978 2979 /* 2980 * Version A/B will use the class id 0 2981 * The newer version than A/B will use the class id 1, so add it in advance 2982 */ 2983 static const struct sdw_device_id rt1320_id[] = { 2984 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 2985 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 2986 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0), 2987 {}, 2988 }; 2989 MODULE_DEVICE_TABLE(sdw, rt1320_id); 2990 2991 static int rt1320_dev_suspend(struct device *dev) 2992 { 2993 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 2994 2995 if (!rt1320->hw_init) 2996 return 0; 2997 2998 regcache_cache_only(rt1320->regmap, true); 2999 regcache_cache_only(rt1320->mbq_regmap, true); 3000 return 0; 3001 } 3002 3003 #define RT1320_PROBE_TIMEOUT 5000 3004 3005 static int rt1320_dev_resume(struct device *dev) 3006 { 3007 struct sdw_slave *slave = dev_to_sdw_dev(dev); 3008 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 3009 unsigned long time; 3010 3011 if (!rt1320->first_hw_init) 3012 return 0; 3013 3014 if (!slave->unattach_request) 3015 goto regmap_sync; 3016 3017 time = wait_for_completion_timeout(&slave->initialization_complete, 3018 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 3019 if (!time) { 3020 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 3021 return -ETIMEDOUT; 3022 } 3023 3024 regmap_sync: 3025 slave->unattach_request = 0; 3026 regcache_cache_only(rt1320->regmap, false); 3027 regcache_sync(rt1320->regmap); 3028 regcache_cache_only(rt1320->mbq_regmap, false); 3029 regcache_sync(rt1320->mbq_regmap); 3030 return 0; 3031 } 3032 3033 static const struct dev_pm_ops rt1320_pm = { 3034 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 3035 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 3036 }; 3037 3038 static struct sdw_driver rt1320_sdw_driver = { 3039 .driver = { 3040 .name = "rt1320-sdca", 3041 .pm = pm_ptr(&rt1320_pm), 3042 }, 3043 .probe = rt1320_sdw_probe, 3044 .remove = rt1320_sdw_remove, 3045 .ops = &rt1320_slave_ops, 3046 .id_table = rt1320_id, 3047 }; 3048 module_sdw_driver(rt1320_sdw_driver); 3049 3050 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 3051 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 3052 MODULE_LICENSE("GPL"); 3053