1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 25 /* 26 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 27 * It might include vendor-specific or SDCA control registers. 28 */ 29 static const struct reg_sequence rt1320_blind_write[] = { 30 { 0xc003, 0xe0 }, 31 { 0xc01b, 0xfc }, 32 { 0xc5c3, 0xf2 }, 33 { 0xc5c2, 0x00 }, 34 { 0xc5c6, 0x10 }, 35 { 0xc5c4, 0x12 }, 36 { 0xc5c8, 0x03 }, 37 { 0xc5d8, 0x0a }, 38 { 0xc5f7, 0x22 }, 39 { 0xc5f6, 0x22 }, 40 { 0xc5d0, 0x0f }, 41 { 0xc5d1, 0x89 }, 42 { 0xc057, 0x51 }, 43 { 0xc054, 0x35 }, 44 { 0xc053, 0x55 }, 45 { 0xc052, 0x55 }, 46 { 0xc051, 0x13 }, 47 { 0xc050, 0x15 }, 48 { 0xc060, 0x77 }, 49 { 0xc061, 0x55 }, 50 { 0xc063, 0x55 }, 51 { 0xc065, 0xa5 }, 52 { 0xc06b, 0x0a }, 53 { 0xca05, 0xd6 }, 54 { 0xca25, 0xd6 }, 55 { 0xcd00, 0x05 }, 56 { 0xc604, 0x40 }, 57 { 0xc609, 0x40 }, 58 { 0xc046, 0xff }, 59 { 0xc045, 0xff }, 60 { 0xc044, 0xff }, 61 { 0xc043, 0xff }, 62 { 0xc042, 0xff }, 63 { 0xc041, 0xff }, 64 { 0xc040, 0xff }, 65 { 0xcc10, 0x01 }, 66 { 0xc700, 0xf0 }, 67 { 0xc701, 0x13 }, 68 { 0xc901, 0x04 }, 69 { 0xc900, 0x73 }, 70 { 0xde03, 0x05 }, 71 { 0xdd0b, 0x0d }, 72 { 0xdd0a, 0xff }, 73 { 0xdd09, 0x0d }, 74 { 0xdd08, 0xff }, 75 { 0xc570, 0x08 }, 76 { 0xe803, 0xbe }, 77 { 0xc003, 0xc0 }, 78 { 0xc081, 0xfe }, 79 { 0xce31, 0x0d }, 80 { 0xce30, 0xae }, 81 { 0xce37, 0x0b }, 82 { 0xce36, 0xd2 }, 83 { 0xce39, 0x04 }, 84 { 0xce38, 0x80 }, 85 { 0xce3f, 0x00 }, 86 { 0xce3e, 0x00 }, 87 { 0xd470, 0x8b }, 88 { 0xd471, 0x18 }, 89 { 0xc019, 0x10 }, 90 { 0xd487, 0x3f }, 91 { 0xd486, 0xc3 }, 92 { 0x3fc2bfc7, 0x00 }, 93 { 0x3fc2bfc6, 0x00 }, 94 { 0x3fc2bfc5, 0x00 }, 95 { 0x3fc2bfc4, 0x01 }, 96 { 0x0000d486, 0x43 }, 97 { 0x1000db00, 0x02 }, 98 { 0x1000db01, 0x00 }, 99 { 0x1000db02, 0x11 }, 100 { 0x1000db03, 0x00 }, 101 { 0x1000db04, 0x00 }, 102 { 0x1000db05, 0x82 }, 103 { 0x1000db06, 0x04 }, 104 { 0x1000db07, 0xf1 }, 105 { 0x1000db08, 0x00 }, 106 { 0x1000db09, 0x00 }, 107 { 0x1000db0a, 0x40 }, 108 { 0x0000d540, 0x01 }, 109 }; 110 111 static const struct reg_sequence rt1320_vc_blind_write[] = { 112 { 0xc003, 0xe0 }, 113 { 0xe80a, 0x01 }, 114 { 0xc5c3, 0xf3 }, 115 { 0xc057, 0x51 }, 116 { 0xc054, 0x35 }, 117 { 0xca05, 0xd6 }, 118 { 0xca07, 0x07 }, 119 { 0xca25, 0xd6 }, 120 { 0xca27, 0x07 }, 121 { 0xc604, 0x40 }, 122 { 0xc609, 0x40 }, 123 { 0xc046, 0xff }, 124 { 0xc045, 0xff }, 125 { 0xda81, 0x14 }, 126 { 0xda8d, 0x14 }, 127 { 0xc044, 0xff }, 128 { 0xc043, 0xff }, 129 { 0xc042, 0xff }, 130 { 0xc041, 0x7f }, 131 { 0xc040, 0xff }, 132 { 0xcc10, 0x01 }, 133 { 0xc700, 0xf0 }, 134 { 0xc701, 0x13 }, 135 { 0xc901, 0x09 }, 136 { 0xc900, 0xd0 }, 137 { 0xde03, 0x05 }, 138 { 0xdd0b, 0x0d }, 139 { 0xdd0a, 0xff }, 140 { 0xdd09, 0x0d }, 141 { 0xdd08, 0xff }, 142 { 0xc570, 0x08 }, 143 { 0xc086, 0x02 }, 144 { 0xc085, 0x7f }, 145 { 0xc084, 0x00 }, 146 { 0xc081, 0xfe }, 147 { 0xf084, 0x0f }, 148 { 0xf083, 0xff }, 149 { 0xf082, 0xff }, 150 { 0xf081, 0xff }, 151 { 0xf080, 0xff }, 152 { 0xe802, 0xf8 }, 153 { 0xe803, 0xbe }, 154 { 0xc003, 0xc0 }, 155 { 0xd470, 0xec }, 156 { 0xd471, 0x3a }, 157 { 0xd474, 0x11 }, 158 { 0xd475, 0x32 }, 159 { 0xd478, 0x64 }, 160 { 0xd479, 0x20 }, 161 { 0xd47a, 0x10 }, 162 { 0xd47c, 0xff }, 163 { 0xc019, 0x10 }, 164 { 0xd487, 0x0b }, 165 { 0xd487, 0x3b }, 166 { 0xd486, 0xc3 }, 167 { 0xc598, 0x04 }, 168 { 0xdb03, 0xf0 }, 169 { 0xdb09, 0x00 }, 170 { 0xdb08, 0x7a }, 171 { 0xdb19, 0x02 }, 172 { 0xdb07, 0x5a }, 173 { 0xdb05, 0x45 }, 174 { 0xd500, 0x00 }, 175 { 0xd500, 0x17 }, 176 { 0xd600, 0x01 }, 177 { 0xd601, 0x02 }, 178 { 0xd602, 0x03 }, 179 { 0xd603, 0x04 }, 180 { 0xd64c, 0x03 }, 181 { 0xd64d, 0x03 }, 182 { 0xd64e, 0x03 }, 183 { 0xd64f, 0x03 }, 184 { 0xd650, 0x03 }, 185 { 0xd651, 0x03 }, 186 { 0xd652, 0x03 }, 187 { 0xd610, 0x01 }, 188 { 0xd608, 0x03 }, 189 { 0xd609, 0x00 }, 190 { 0x3fc2bf83, 0x00 }, 191 { 0x3fc2bf82, 0x00 }, 192 { 0x3fc2bf81, 0x00 }, 193 { 0x3fc2bf80, 0x00 }, 194 { 0x3fc2bfc7, 0x00 }, 195 { 0x3fc2bfc6, 0x00 }, 196 { 0x3fc2bfc5, 0x00 }, 197 { 0x3fc2bfc4, 0x00 }, 198 { 0x3fc2bfc3, 0x00 }, 199 { 0x3fc2bfc2, 0x00 }, 200 { 0x3fc2bfc1, 0x00 }, 201 { 0x3fc2bfc0, 0x03 }, 202 { 0x0000d486, 0x43 }, 203 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 204 { 0x1000db00, 0x04 }, 205 { 0x1000db01, 0x00 }, 206 { 0x1000db02, 0x11 }, 207 { 0x1000db03, 0x00 }, 208 { 0x1000db04, 0x00 }, 209 { 0x1000db05, 0x82 }, 210 { 0x1000db06, 0x04 }, 211 { 0x1000db07, 0xf1 }, 212 { 0x1000db08, 0x00 }, 213 { 0x1000db09, 0x00 }, 214 { 0x1000db0a, 0x40 }, 215 { 0x1000db0b, 0x02 }, 216 { 0x1000db0c, 0xf2 }, 217 { 0x1000db0d, 0x00 }, 218 { 0x1000db0e, 0x00 }, 219 { 0x1000db0f, 0xe0 }, 220 { 0x1000db10, 0x00 }, 221 { 0x1000db11, 0x10 }, 222 { 0x1000db12, 0x00 }, 223 { 0x1000db13, 0x00 }, 224 { 0x1000db14, 0x45 }, 225 { 0x0000d540, 0x01 }, 226 { 0x0000c081, 0xfc }, 227 { 0x0000f01e, 0x80 }, 228 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 229 }; 230 231 static const struct reg_default rt1320_reg_defaults[] = { 232 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 233 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 234 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 235 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 236 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 237 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 238 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 239 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 240 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 241 }; 242 243 static const struct reg_default rt1320_mbq_defaults[] = { 244 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 245 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 246 }; 247 248 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 249 { 250 switch (reg) { 251 case 0xc000 ... 0xc086: 252 case 0xc400 ... 0xc409: 253 case 0xc480 ... 0xc48f: 254 case 0xc4c0 ... 0xc4c4: 255 case 0xc4e0 ... 0xc4e7: 256 case 0xc500: 257 case 0xc560 ... 0xc56b: 258 case 0xc570: 259 case 0xc580 ... 0xc59a: 260 case 0xc5b0 ... 0xc60f: 261 case 0xc640 ... 0xc64f: 262 case 0xc670: 263 case 0xc680 ... 0xc683: 264 case 0xc700 ... 0xc76f: 265 case 0xc800 ... 0xc801: 266 case 0xc820: 267 case 0xc900 ... 0xc901: 268 case 0xc920 ... 0xc921: 269 case 0xca00 ... 0xca07: 270 case 0xca20 ... 0xca27: 271 case 0xca40 ... 0xca4b: 272 case 0xca60 ... 0xca68: 273 case 0xca80 ... 0xca88: 274 case 0xcb00 ... 0xcb0c: 275 case 0xcc00 ... 0xcc12: 276 case 0xcc80 ... 0xcc81: 277 case 0xcd00: 278 case 0xcd80 ... 0xcd82: 279 case 0xce00 ... 0xce4d: 280 case 0xcf00 ... 0xcf25: 281 case 0xd000 ... 0xd0ff: 282 case 0xd100 ... 0xd1ff: 283 case 0xd200 ... 0xd2ff: 284 case 0xd300 ... 0xd3ff: 285 case 0xd400 ... 0xd403: 286 case 0xd410 ... 0xd417: 287 case 0xd470 ... 0xd497: 288 case 0xd4dc ... 0xd50f: 289 case 0xd520 ... 0xd543: 290 case 0xd560 ... 0xd5ef: 291 case 0xd600 ... 0xd663: 292 case 0xda00 ... 0xda6e: 293 case 0xda80 ... 0xda9e: 294 case 0xdb00 ... 0xdb7f: 295 case 0xdc00: 296 case 0xdc20 ... 0xdc21: 297 case 0xdd00 ... 0xdd17: 298 case 0xde00 ... 0xde09: 299 case 0xdf00 ... 0xdf1b: 300 case 0xe000 ... 0xe847: 301 case 0xf01e: 302 case 0xf717 ... 0xf719: 303 case 0xf720 ... 0xf723: 304 case 0x1000cd91 ... 0x1000cd96: 305 case 0x1000f008: 306 case 0x1000f021: 307 case 0x3fe2e000 ... 0x3fe2e003: 308 case 0x3fc2ab80 ... 0x3fc2abd4: 309 /* 0x41000189/0x4100018a */ 310 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 311 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 312 /* 0x41001388 */ 313 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 314 /* 0x41001988 */ 315 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 316 /* 0x41080000 */ 317 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 318 /* 0x41080200 */ 319 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 320 /* 0x41080900 */ 321 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 322 /* 0x41080980 */ 323 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 324 /* 0x41081080 */ 325 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 326 /* 0x41081480/0x41081488 */ 327 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 328 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 329 /* 0x41081980 */ 330 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 331 return true; 332 default: 333 return false; 334 } 335 } 336 337 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 338 { 339 switch (reg) { 340 case 0xc000: 341 case 0xc003: 342 case 0xc081: 343 case 0xc402 ... 0xc406: 344 case 0xc48c ... 0xc48f: 345 case 0xc560: 346 case 0xc5b5 ... 0xc5b7: 347 case 0xc5fc ... 0xc5ff: 348 case 0xc820: 349 case 0xc900: 350 case 0xc920: 351 case 0xca42: 352 case 0xca62: 353 case 0xca82: 354 case 0xcd00: 355 case 0xce03: 356 case 0xce10: 357 case 0xce14 ... 0xce17: 358 case 0xce44 ... 0xce49: 359 case 0xce4c ... 0xce4d: 360 case 0xcf0c: 361 case 0xcf10 ... 0xcf25: 362 case 0xd486 ... 0xd487: 363 case 0xd4e5 ... 0xd4e6: 364 case 0xd4e8 ... 0xd4ff: 365 case 0xd530: 366 case 0xd540: 367 case 0xd543: 368 case 0xdb58 ... 0xdb5f: 369 case 0xdb60 ... 0xdb63: 370 case 0xdb68 ... 0xdb69: 371 case 0xdb6d: 372 case 0xdb70 ... 0xdb71: 373 case 0xdb76: 374 case 0xdb7a: 375 case 0xdb7c ... 0xdb7f: 376 case 0xdd0c ... 0xdd13: 377 case 0xde02: 378 case 0xdf14 ... 0xdf1b: 379 case 0xe83c ... 0xe847: 380 case 0xf01e: 381 case 0xf717 ... 0xf719: 382 case 0xf720 ... 0xf723: 383 case 0x10000000 ... 0x10007fff: 384 case 0x1000c000 ... 0x1000dfff: 385 case 0x1000f008: 386 case 0x1000f021: 387 case 0x3fc2ab80 ... 0x3fc2abd4: 388 case 0x3fc2bf80 ... 0x3fc2bf83: 389 case 0x3fc2bfc0 ... 0x3fc2bfc7: 390 case 0x3fe2e000 ... 0x3fe2e003: 391 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 392 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 393 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 394 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 395 return true; 396 default: 397 return false; 398 } 399 } 400 401 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 402 { 403 switch (reg) { 404 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 405 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 406 return true; 407 default: 408 return false; 409 } 410 } 411 412 static const struct regmap_config rt1320_sdw_regmap = { 413 .reg_bits = 32, 414 .val_bits = 8, 415 .readable_reg = rt1320_readable_register, 416 .volatile_reg = rt1320_volatile_register, 417 .max_register = 0x41081980, 418 .reg_defaults = rt1320_reg_defaults, 419 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 420 .cache_type = REGCACHE_MAPLE, 421 .use_single_read = true, 422 .use_single_write = true, 423 }; 424 425 static const struct regmap_config rt1320_mbq_regmap = { 426 .name = "sdw-mbq", 427 .reg_bits = 32, 428 .val_bits = 16, 429 .readable_reg = rt1320_mbq_readable_register, 430 .max_register = 0x41000192, 431 .reg_defaults = rt1320_mbq_defaults, 432 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 433 .cache_type = REGCACHE_MAPLE, 434 .use_single_read = true, 435 .use_single_write = true, 436 }; 437 438 static int rt1320_read_prop(struct sdw_slave *slave) 439 { 440 struct sdw_slave_prop *prop = &slave->prop; 441 int nval; 442 int i, j; 443 u32 bit; 444 unsigned long addr; 445 struct sdw_dpn_prop *dpn; 446 447 /* 448 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 449 */ 450 sdw_slave_read_prop(slave); 451 452 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 453 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 454 455 prop->paging_support = true; 456 prop->lane_control_support = true; 457 458 /* first we need to allocate memory for set bits in port lists */ 459 prop->source_ports = BIT(4); 460 prop->sink_ports = BIT(1); 461 462 nval = hweight32(prop->source_ports); 463 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 464 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 465 if (!prop->src_dpn_prop) 466 return -ENOMEM; 467 468 i = 0; 469 dpn = prop->src_dpn_prop; 470 addr = prop->source_ports; 471 for_each_set_bit(bit, &addr, 32) { 472 dpn[i].num = bit; 473 dpn[i].type = SDW_DPN_FULL; 474 dpn[i].simple_ch_prep_sm = true; 475 dpn[i].ch_prep_timeout = 10; 476 i++; 477 } 478 479 /* do this again for sink now */ 480 nval = hweight32(prop->sink_ports); 481 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 482 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 483 if (!prop->sink_dpn_prop) 484 return -ENOMEM; 485 486 j = 0; 487 dpn = prop->sink_dpn_prop; 488 addr = prop->sink_ports; 489 for_each_set_bit(bit, &addr, 32) { 490 dpn[j].num = bit; 491 dpn[j].type = SDW_DPN_FULL; 492 dpn[j].simple_ch_prep_sm = true; 493 dpn[j].ch_prep_timeout = 10; 494 j++; 495 } 496 497 /* set the timeout values */ 498 prop->clk_stop_timeout = 64; 499 500 return 0; 501 } 502 503 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char ps) 504 { 505 unsigned int delay = 1000, val; 506 507 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 508 509 /* waiting for Actual PDE becomes to PS0/PS3 */ 510 while (delay) { 511 regmap_read(rt1320->regmap, 512 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 513 RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 514 if (val == ps) 515 break; 516 517 usleep_range(1000, 1500); 518 delay--; 519 } 520 if (!delay) { 521 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 522 return -ETIMEDOUT; 523 } 524 525 return 0; 526 } 527 528 /* 529 * The 'patch code' is written to the patch code area. 530 * The patch code area is used for SDCA register expansion flexibility. 531 */ 532 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 533 { 534 struct sdw_slave *slave = rt1320->sdw_slave; 535 const struct firmware *patch; 536 const char *filename; 537 unsigned int addr, val; 538 const unsigned char *ptr; 539 int ret, i; 540 541 if (rt1320->version_id <= RT1320_VB) 542 filename = RT1320_VAB_MCU_PATCH; 543 else 544 filename = RT1320_VC_MCU_PATCH; 545 546 /* load the patch code here */ 547 ret = request_firmware(&patch, filename, &slave->dev); 548 if (ret) { 549 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 550 regmap_write(rt1320->regmap, 0xc598, 0x00); 551 regmap_write(rt1320->regmap, 0x10007000, 0x67); 552 regmap_write(rt1320->regmap, 0x10007001, 0x80); 553 regmap_write(rt1320->regmap, 0x10007002, 0x00); 554 regmap_write(rt1320->regmap, 0x10007003, 0x00); 555 } else { 556 ptr = (const unsigned char *)patch->data; 557 if ((patch->size % 8) == 0) { 558 for (i = 0; i < patch->size; i += 8) { 559 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 560 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 561 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 562 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 563 564 if (addr > 0x10007fff || addr < 0x10007000) { 565 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 566 goto _exit_; 567 } 568 if (val > 0xff) { 569 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 570 goto _exit_; 571 } 572 regmap_write(rt1320->regmap, addr, val); 573 } 574 } 575 _exit_: 576 release_firmware(patch); 577 } 578 } 579 580 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 581 { 582 unsigned int i, reg, val, delay; 583 584 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 585 reg = rt1320_blind_write[i].reg; 586 val = rt1320_blind_write[i].def; 587 delay = rt1320_blind_write[i].delay_us; 588 589 if (reg == 0x3fc2bfc7) 590 rt1320_load_mcu_patch(rt1320); 591 592 regmap_write(rt1320->regmap, reg, val); 593 if (delay) 594 usleep_range(delay, delay + 1000); 595 } 596 } 597 598 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 599 { 600 struct sdw_slave *slave = rt1320->sdw_slave; 601 unsigned int i, reg, val, delay, retry, tmp; 602 603 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 604 reg = rt1320_vc_blind_write[i].reg; 605 val = rt1320_vc_blind_write[i].def; 606 delay = rt1320_vc_blind_write[i].delay_us; 607 608 if (reg == 0x3fc2bf83) 609 rt1320_load_mcu_patch(rt1320); 610 611 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 612 (val == 0x00)) { 613 retry = 200; 614 while (retry) { 615 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 616 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 617 if (tmp == 0x1f) 618 break; 619 usleep_range(1000, 1500); 620 retry--; 621 } 622 if (!retry) 623 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 624 } 625 regmap_write(rt1320->regmap, reg, val); 626 if (delay) 627 usleep_range(delay, delay + 1000); 628 629 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 630 rt1320_pde_transition_delay(rt1320, val); 631 } 632 } 633 634 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 635 { 636 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 637 unsigned int amp_func_status, val, tmp; 638 639 if (rt1320->hw_init) 640 return 0; 641 642 regcache_cache_only(rt1320->regmap, false); 643 regcache_cache_only(rt1320->mbq_regmap, false); 644 if (rt1320->first_hw_init) { 645 regcache_cache_bypass(rt1320->regmap, true); 646 regcache_cache_bypass(rt1320->mbq_regmap, true); 647 } else { 648 /* 649 * PM runtime status is marked as 'active' only when a Slave reports as Attached 650 */ 651 /* update count of parent 'active' children */ 652 pm_runtime_set_active(&slave->dev); 653 } 654 655 pm_runtime_get_noresume(&slave->dev); 656 657 if (rt1320->version_id < 0) { 658 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 659 rt1320->version_id = val; 660 } 661 662 regmap_read(rt1320->regmap, 663 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 664 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 665 666 /* initialization write */ 667 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 668 if (rt1320->version_id < RT1320_VC) 669 rt1320_vab_preset(rt1320); 670 else 671 rt1320_vc_preset(rt1320); 672 673 regmap_write(rt1320->regmap, 674 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 675 FUNCTION_NEEDS_INITIALIZATION); 676 } 677 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA) { 678 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 679 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 680 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 681 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 682 val = (tmp << 8) | val; 683 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 684 val = (tmp << 16) | val; 685 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 686 val = (tmp << 24) | val; 687 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 688 /* 689 * We call the version b which has the new DSP ROM code against version a. 690 * Therefore, we read the DSP address to check the ID. 691 */ 692 if (val == RT1320_VER_B_ID) 693 rt1320->version_id = RT1320_VB; 694 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 695 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 696 } 697 dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); 698 699 if (rt1320->first_hw_init) { 700 regcache_cache_bypass(rt1320->regmap, false); 701 regcache_cache_bypass(rt1320->mbq_regmap, false); 702 regcache_mark_dirty(rt1320->regmap); 703 regcache_mark_dirty(rt1320->mbq_regmap); 704 } 705 706 /* Mark Slave initialization complete */ 707 rt1320->first_hw_init = true; 708 rt1320->hw_init = true; 709 710 pm_runtime_mark_last_busy(&slave->dev); 711 pm_runtime_put_autosuspend(&slave->dev); 712 713 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 714 return 0; 715 } 716 717 static int rt1320_update_status(struct sdw_slave *slave, 718 enum sdw_slave_status status) 719 { 720 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 721 722 if (status == SDW_SLAVE_UNATTACHED) 723 rt1320->hw_init = false; 724 725 /* 726 * Perform initialization only if slave status is present and 727 * hw_init flag is false 728 */ 729 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 730 return 0; 731 732 /* perform I/O transfers required for Slave initialization */ 733 return rt1320_io_init(&slave->dev, slave); 734 } 735 736 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 737 struct snd_kcontrol *kcontrol, int event) 738 { 739 struct snd_soc_component *component = 740 snd_soc_dapm_to_component(w->dapm); 741 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 742 unsigned char ps0 = 0x0, ps3 = 0x3; 743 744 switch (event) { 745 case SND_SOC_DAPM_POST_PMU: 746 regmap_write(rt1320->regmap, 747 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 748 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 749 rt1320_pde_transition_delay(rt1320, ps0); 750 break; 751 case SND_SOC_DAPM_PRE_PMD: 752 regmap_write(rt1320->regmap, 753 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 754 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 755 rt1320_pde_transition_delay(rt1320, ps3); 756 break; 757 default: 758 break; 759 } 760 761 return 0; 762 } 763 764 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 765 struct snd_ctl_elem_value *ucontrol) 766 { 767 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 768 struct soc_mixer_control *mc = 769 (struct soc_mixer_control *)kcontrol->private_value; 770 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 771 unsigned int gain_l_val, gain_r_val; 772 unsigned int lvalue, rvalue; 773 const unsigned int interval_offset = 0xc0; 774 775 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 776 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 777 778 /* L Channel */ 779 gain_l_val = ucontrol->value.integer.value[0]; 780 if (gain_l_val > mc->max) 781 gain_l_val = mc->max; 782 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 783 gain_l_val &= 0xffff; 784 785 /* R Channel */ 786 gain_r_val = ucontrol->value.integer.value[1]; 787 if (gain_r_val > mc->max) 788 gain_r_val = mc->max; 789 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 790 gain_r_val &= 0xffff; 791 792 if (lvalue == gain_l_val && rvalue == gain_r_val) 793 return 0; 794 795 /* Lch*/ 796 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 797 /* Rch */ 798 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 799 800 return 1; 801 } 802 803 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 804 struct snd_ctl_elem_value *ucontrol) 805 { 806 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 807 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 808 struct soc_mixer_control *mc = 809 (struct soc_mixer_control *)kcontrol->private_value; 810 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 811 const unsigned int interval_offset = 0xc0; 812 813 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 814 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 815 816 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 817 818 if (read_l != read_r) 819 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 820 else 821 ctl_r = ctl_l; 822 823 ucontrol->value.integer.value[0] = ctl_l; 824 ucontrol->value.integer.value[1] = ctl_r; 825 return 0; 826 } 827 828 static const char * const rt1320_rx_data_ch_select[] = { 829 "L,R", 830 "R,L", 831 "L,L", 832 "R,R", 833 "L,L+R", 834 "R,L+R", 835 "L+R,L", 836 "L+R,R", 837 "L+R,L+R", 838 }; 839 840 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 841 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 842 rt1320_rx_data_ch_select); 843 844 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 845 846 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 847 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 848 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 849 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 850 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 851 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 852 }; 853 854 static const struct snd_kcontrol_new rt1320_spk_l_dac = 855 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 856 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 857 0, 1, 1); 858 static const struct snd_kcontrol_new rt1320_spk_r_dac = 859 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 860 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 861 0, 1, 1); 862 863 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 864 /* Audio Interface */ 865 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 866 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 867 868 /* Digital Interface */ 869 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 870 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 871 rt1320_pde23_event, 872 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 873 874 /* Output */ 875 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 876 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 877 SND_SOC_DAPM_OUTPUT("SPOL"), 878 SND_SOC_DAPM_OUTPUT("SPOR"), 879 880 /* Input */ 881 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 882 SND_SOC_DAPM_SIGGEN("AEC Gen"), 883 }; 884 885 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 886 { "FU21", NULL, "DP1RX" }, 887 { "FU21", NULL, "PDE 23" }, 888 { "OT23 L", "Switch", "FU21" }, 889 { "OT23 R", "Switch", "FU21" }, 890 { "SPOL", NULL, "OT23 L" }, 891 { "SPOR", NULL, "OT23 R" }, 892 893 { "AEC Data", NULL, "AEC Gen" }, 894 { "DP4TX", NULL, "AEC Data" }, 895 }; 896 897 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 898 int direction) 899 { 900 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 901 return 0; 902 } 903 904 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 905 struct snd_soc_dai *dai) 906 { 907 snd_soc_dai_set_dma_data(dai, substream, NULL); 908 } 909 910 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 911 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 912 { 913 struct snd_soc_component *component = dai->component; 914 struct rt1320_sdw_priv *rt1320 = 915 snd_soc_component_get_drvdata(component); 916 struct sdw_stream_config stream_config; 917 struct sdw_port_config port_config; 918 struct sdw_stream_runtime *sdw_stream; 919 int retval; 920 unsigned int sampling_rate; 921 922 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 923 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 924 925 if (!sdw_stream) 926 return -EINVAL; 927 928 if (!rt1320->sdw_slave) 929 return -EINVAL; 930 931 /* SoundWire specific configuration */ 932 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 933 934 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 935 if (dai->id == RT1320_AIF1) 936 port_config.num = 1; 937 else 938 return -EINVAL; 939 } else { 940 if (dai->id == RT1320_AIF1) 941 port_config.num = 4; 942 else 943 return -EINVAL; 944 } 945 946 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 947 &port_config, 1, sdw_stream); 948 if (retval) { 949 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 950 return retval; 951 } 952 953 /* sampling rate configuration */ 954 switch (params_rate(params)) { 955 case 16000: 956 sampling_rate = RT1320_SDCA_RATE_16000HZ; 957 break; 958 case 32000: 959 sampling_rate = RT1320_SDCA_RATE_32000HZ; 960 break; 961 case 44100: 962 sampling_rate = RT1320_SDCA_RATE_44100HZ; 963 break; 964 case 48000: 965 sampling_rate = RT1320_SDCA_RATE_48000HZ; 966 break; 967 case 96000: 968 sampling_rate = RT1320_SDCA_RATE_96000HZ; 969 break; 970 case 192000: 971 sampling_rate = RT1320_SDCA_RATE_192000HZ; 972 break; 973 default: 974 dev_err(component->dev, "%s: Rate %d is not supported\n", 975 __func__, params_rate(params)); 976 return -EINVAL; 977 } 978 979 /* set sampling frequency */ 980 regmap_write(rt1320->regmap, 981 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 982 sampling_rate); 983 984 return 0; 985 } 986 987 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 988 struct snd_soc_dai *dai) 989 { 990 struct snd_soc_component *component = dai->component; 991 struct rt1320_sdw_priv *rt1320 = 992 snd_soc_component_get_drvdata(component); 993 struct sdw_stream_runtime *sdw_stream = 994 snd_soc_dai_get_dma_data(dai, substream); 995 996 if (!rt1320->sdw_slave) 997 return -EINVAL; 998 999 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 1000 return 0; 1001 } 1002 1003 /* 1004 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 1005 * port_prep are not defined for now 1006 */ 1007 static const struct sdw_slave_ops rt1320_slave_ops = { 1008 .read_prop = rt1320_read_prop, 1009 .update_status = rt1320_update_status, 1010 }; 1011 1012 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 1013 { 1014 int ret; 1015 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1016 1017 rt1320->component = component; 1018 1019 if (!rt1320->first_hw_init) 1020 return 0; 1021 1022 ret = pm_runtime_resume(component->dev); 1023 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 1024 if (ret < 0 && ret != -EACCES) 1025 return ret; 1026 1027 return 0; 1028 } 1029 1030 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 1031 .probe = rt1320_sdw_component_probe, 1032 .controls = rt1320_snd_controls, 1033 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 1034 .dapm_widgets = rt1320_dapm_widgets, 1035 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 1036 .dapm_routes = rt1320_dapm_routes, 1037 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 1038 .endianness = 1, 1039 }; 1040 1041 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 1042 .hw_params = rt1320_sdw_hw_params, 1043 .hw_free = rt1320_sdw_pcm_hw_free, 1044 .set_stream = rt1320_set_sdw_stream, 1045 .shutdown = rt1320_sdw_shutdown, 1046 }; 1047 1048 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 1049 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1050 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1051 SNDRV_PCM_FMTBIT_S32_LE) 1052 1053 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 1054 { 1055 .name = "rt1320-aif1", 1056 .id = RT1320_AIF1, 1057 .playback = { 1058 .stream_name = "DP1 Playback", 1059 .channels_min = 1, 1060 .channels_max = 2, 1061 .rates = RT1320_STEREO_RATES, 1062 .formats = RT1320_FORMATS, 1063 }, 1064 .capture = { 1065 .stream_name = "DP4 Capture", 1066 .channels_min = 1, 1067 .channels_max = 2, 1068 .rates = RT1320_STEREO_RATES, 1069 .formats = RT1320_FORMATS, 1070 }, 1071 .ops = &rt1320_aif_dai_ops, 1072 }, 1073 }; 1074 1075 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 1076 struct regmap *mbq_regmap, struct sdw_slave *slave) 1077 { 1078 struct rt1320_sdw_priv *rt1320; 1079 int ret; 1080 1081 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 1082 if (!rt1320) 1083 return -ENOMEM; 1084 1085 dev_set_drvdata(dev, rt1320); 1086 rt1320->sdw_slave = slave; 1087 rt1320->mbq_regmap = mbq_regmap; 1088 rt1320->regmap = regmap; 1089 1090 regcache_cache_only(rt1320->regmap, true); 1091 regcache_cache_only(rt1320->mbq_regmap, true); 1092 1093 /* 1094 * Mark hw_init to false 1095 * HW init will be performed when device reports present 1096 */ 1097 rt1320->hw_init = false; 1098 rt1320->first_hw_init = false; 1099 rt1320->version_id = -1; 1100 1101 ret = devm_snd_soc_register_component(dev, 1102 &soc_component_sdw_rt1320, 1103 rt1320_sdw_dai, 1104 ARRAY_SIZE(rt1320_sdw_dai)); 1105 if (ret < 0) 1106 return ret; 1107 1108 /* set autosuspend parameters */ 1109 pm_runtime_set_autosuspend_delay(dev, 3000); 1110 pm_runtime_use_autosuspend(dev); 1111 1112 /* make sure the device does not suspend immediately */ 1113 pm_runtime_mark_last_busy(dev); 1114 1115 pm_runtime_enable(dev); 1116 1117 /* important note: the device is NOT tagged as 'active' and will remain 1118 * 'suspended' until the hardware is enumerated/initialized. This is required 1119 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 1120 * fail with -EACCESS because of race conditions between card creation and enumeration 1121 */ 1122 1123 dev_dbg(dev, "%s\n", __func__); 1124 1125 return ret; 1126 } 1127 1128 static int rt1320_sdw_probe(struct sdw_slave *slave, 1129 const struct sdw_device_id *id) 1130 { 1131 struct regmap *regmap, *mbq_regmap; 1132 1133 /* Regmap Initialization */ 1134 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 1135 if (IS_ERR(mbq_regmap)) 1136 return PTR_ERR(mbq_regmap); 1137 1138 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 1139 if (IS_ERR(regmap)) 1140 return PTR_ERR(regmap); 1141 1142 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 1143 } 1144 1145 static int rt1320_sdw_remove(struct sdw_slave *slave) 1146 { 1147 pm_runtime_disable(&slave->dev); 1148 1149 return 0; 1150 } 1151 1152 /* 1153 * Version A/B will use the class id 0 1154 * The newer version than A/B will use the class id 1, so add it in advance 1155 */ 1156 static const struct sdw_device_id rt1320_id[] = { 1157 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 1158 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 1159 {}, 1160 }; 1161 MODULE_DEVICE_TABLE(sdw, rt1320_id); 1162 1163 static int __maybe_unused rt1320_dev_suspend(struct device *dev) 1164 { 1165 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1166 1167 if (!rt1320->hw_init) 1168 return 0; 1169 1170 regcache_cache_only(rt1320->regmap, true); 1171 regcache_cache_only(rt1320->mbq_regmap, true); 1172 return 0; 1173 } 1174 1175 #define RT1320_PROBE_TIMEOUT 5000 1176 1177 static int __maybe_unused rt1320_dev_resume(struct device *dev) 1178 { 1179 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1180 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1181 unsigned long time; 1182 1183 if (!rt1320->first_hw_init) 1184 return 0; 1185 1186 if (!slave->unattach_request) 1187 goto regmap_sync; 1188 1189 time = wait_for_completion_timeout(&slave->initialization_complete, 1190 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 1191 if (!time) { 1192 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 1193 return -ETIMEDOUT; 1194 } 1195 1196 regmap_sync: 1197 slave->unattach_request = 0; 1198 regcache_cache_only(rt1320->regmap, false); 1199 regcache_sync(rt1320->regmap); 1200 regcache_cache_only(rt1320->mbq_regmap, false); 1201 regcache_sync(rt1320->mbq_regmap); 1202 return 0; 1203 } 1204 1205 static const struct dev_pm_ops rt1320_pm = { 1206 SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 1207 SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 1208 }; 1209 1210 static struct sdw_driver rt1320_sdw_driver = { 1211 .driver = { 1212 .name = "rt1320-sdca", 1213 .pm = &rt1320_pm, 1214 }, 1215 .probe = rt1320_sdw_probe, 1216 .remove = rt1320_sdw_remove, 1217 .ops = &rt1320_slave_ops, 1218 .id_table = rt1320_id, 1219 }; 1220 module_sdw_driver(rt1320_sdw_driver); 1221 1222 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 1223 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 1224 MODULE_LICENSE("GPL"); 1225