1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 #include "rt-sdw-common.h" 25 26 /* 27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 28 * It might include vendor-specific or SDCA control registers. 29 */ 30 static const struct reg_sequence rt1320_blind_write[] = { 31 { 0xc003, 0xe0 }, 32 { 0xc01b, 0xfc }, 33 { 0xc5c3, 0xf2 }, 34 { 0xc5c2, 0x00 }, 35 { 0xc5c6, 0x10 }, 36 { 0xc5c4, 0x12 }, 37 { 0xc5c8, 0x03 }, 38 { 0xc5d8, 0x0a }, 39 { 0xc5f7, 0x22 }, 40 { 0xc5f6, 0x22 }, 41 { 0xc5d0, 0x0f }, 42 { 0xc5d1, 0x89 }, 43 { 0xc057, 0x51 }, 44 { 0xc054, 0x35 }, 45 { 0xc053, 0x55 }, 46 { 0xc052, 0x55 }, 47 { 0xc051, 0x13 }, 48 { 0xc050, 0x15 }, 49 { 0xc060, 0x77 }, 50 { 0xc061, 0x55 }, 51 { 0xc063, 0x55 }, 52 { 0xc065, 0xa5 }, 53 { 0xc06b, 0x0a }, 54 { 0xca05, 0xd6 }, 55 { 0xca25, 0xd6 }, 56 { 0xcd00, 0x05 }, 57 { 0xc604, 0x40 }, 58 { 0xc609, 0x40 }, 59 { 0xc046, 0xff }, 60 { 0xc045, 0xff }, 61 { 0xc044, 0xff }, 62 { 0xc043, 0xff }, 63 { 0xc042, 0xff }, 64 { 0xc041, 0xff }, 65 { 0xc040, 0xff }, 66 { 0xcc10, 0x01 }, 67 { 0xc700, 0xf0 }, 68 { 0xc701, 0x13 }, 69 { 0xc901, 0x04 }, 70 { 0xc900, 0x73 }, 71 { 0xde03, 0x05 }, 72 { 0xdd0b, 0x0d }, 73 { 0xdd0a, 0xff }, 74 { 0xdd09, 0x0d }, 75 { 0xdd08, 0xff }, 76 { 0xc570, 0x08 }, 77 { 0xe803, 0xbe }, 78 { 0xc003, 0xc0 }, 79 { 0xc081, 0xfe }, 80 { 0xce31, 0x0d }, 81 { 0xce30, 0xae }, 82 { 0xce37, 0x0b }, 83 { 0xce36, 0xd2 }, 84 { 0xce39, 0x04 }, 85 { 0xce38, 0x80 }, 86 { 0xce3f, 0x00 }, 87 { 0xce3e, 0x00 }, 88 { 0xd470, 0x8b }, 89 { 0xd471, 0x18 }, 90 { 0xc019, 0x10 }, 91 { 0xd487, 0x3f }, 92 { 0xd486, 0xc3 }, 93 { 0x3fc2bfc7, 0x00 }, 94 { 0x3fc2bfc6, 0x00 }, 95 { 0x3fc2bfc5, 0x00 }, 96 { 0x3fc2bfc4, 0x01 }, 97 { 0x0000d486, 0x43 }, 98 { 0x1000db00, 0x02 }, 99 { 0x1000db01, 0x00 }, 100 { 0x1000db02, 0x11 }, 101 { 0x1000db03, 0x00 }, 102 { 0x1000db04, 0x00 }, 103 { 0x1000db05, 0x82 }, 104 { 0x1000db06, 0x04 }, 105 { 0x1000db07, 0xf1 }, 106 { 0x1000db08, 0x00 }, 107 { 0x1000db09, 0x00 }, 108 { 0x1000db0a, 0x40 }, 109 { 0x0000d540, 0x01 }, 110 { 0xd172, 0x2a }, 111 { 0xc5d6, 0x01 }, 112 { 0xd478, 0xff }, 113 }; 114 115 static const struct reg_sequence rt1320_vc_blind_write[] = { 116 { 0xc003, 0xe0 }, 117 { 0xe80a, 0x01 }, 118 { 0xc5c3, 0xf2 }, 119 { 0xc5c8, 0x03 }, 120 { 0xc057, 0x51 }, 121 { 0xc054, 0x35 }, 122 { 0xca05, 0xd6 }, 123 { 0xca07, 0x07 }, 124 { 0xca25, 0xd6 }, 125 { 0xca27, 0x07 }, 126 { 0xc604, 0x40 }, 127 { 0xc609, 0x40 }, 128 { 0xc046, 0xff }, 129 { 0xc045, 0xff }, 130 { 0xc044, 0xff }, 131 { 0xc043, 0xff }, 132 { 0xc042, 0xff }, 133 { 0xc041, 0x7f }, 134 { 0xc040, 0xff }, 135 { 0xcc10, 0x01 }, 136 { 0xc700, 0xf0 }, 137 { 0xc701, 0x13 }, 138 { 0xc901, 0x04 }, 139 { 0xc900, 0x73 }, 140 { 0xde03, 0x05 }, 141 { 0xdd0b, 0x0d }, 142 { 0xdd0a, 0xff }, 143 { 0xdd09, 0x0d }, 144 { 0xdd08, 0xff }, 145 { 0xc570, 0x08 }, 146 { 0xc086, 0x02 }, 147 { 0xc085, 0x7f }, 148 { 0xc084, 0x00 }, 149 { 0xc081, 0xfe }, 150 { 0xf084, 0x0f }, 151 { 0xf083, 0xff }, 152 { 0xf082, 0xff }, 153 { 0xf081, 0xff }, 154 { 0xf080, 0xff }, 155 { 0xe801, 0x01 }, 156 { 0xe802, 0xf8 }, 157 { 0xe803, 0xbe }, 158 { 0xc003, 0xc0 }, 159 { 0xd470, 0xec }, 160 { 0xd471, 0x3a }, 161 { 0xd474, 0x11 }, 162 { 0xd475, 0x32 }, 163 { 0xd478, 0xff }, 164 { 0xd479, 0x20 }, 165 { 0xd47a, 0x10 }, 166 { 0xd47c, 0xff }, 167 { 0xc019, 0x10 }, 168 { 0xd487, 0x0b }, 169 { 0xd487, 0x3b }, 170 { 0xd486, 0xc3 }, 171 { 0xc598, 0x04 }, 172 { 0xdb03, 0xf0 }, 173 { 0xdb09, 0x00 }, 174 { 0xdb08, 0x7a }, 175 { 0xdb19, 0x02 }, 176 { 0xdb07, 0x5a }, 177 { 0xdb05, 0x45 }, 178 { 0xd500, 0x00 }, 179 { 0xd500, 0x17 }, 180 { 0xd600, 0x01 }, 181 { 0xd601, 0x02 }, 182 { 0xd602, 0x03 }, 183 { 0xd603, 0x04 }, 184 { 0xd64c, 0x03 }, 185 { 0xd64d, 0x03 }, 186 { 0xd64e, 0x03 }, 187 { 0xd64f, 0x03 }, 188 { 0xd650, 0x03 }, 189 { 0xd651, 0x03 }, 190 { 0xd652, 0x03 }, 191 { 0xd610, 0x01 }, 192 { 0xd608, 0x03 }, 193 { 0xd609, 0x00 }, 194 { 0x3fc2bf83, 0x00 }, 195 { 0x3fc2bf82, 0x00 }, 196 { 0x3fc2bf81, 0x00 }, 197 { 0x3fc2bf80, 0x00 }, 198 { 0x3fc2bfc7, 0x00 }, 199 { 0x3fc2bfc6, 0x00 }, 200 { 0x3fc2bfc5, 0x00 }, 201 { 0x3fc2bfc4, 0x00 }, 202 { 0x3fc2bfc3, 0x00 }, 203 { 0x3fc2bfc2, 0x00 }, 204 { 0x3fc2bfc1, 0x00 }, 205 { 0x3fc2bfc0, 0x07 }, 206 { 0x0000d486, 0x43 }, 207 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 208 { 0x1000db00, 0x07 }, 209 { 0x1000db01, 0x00 }, 210 { 0x1000db02, 0x11 }, 211 { 0x1000db03, 0x00 }, 212 { 0x1000db04, 0x00 }, 213 { 0x1000db05, 0x82 }, 214 { 0x1000db06, 0x04 }, 215 { 0x1000db07, 0xf1 }, 216 { 0x1000db08, 0x00 }, 217 { 0x1000db09, 0x00 }, 218 { 0x1000db0a, 0x40 }, 219 { 0x1000db0b, 0x02 }, 220 { 0x1000db0c, 0xf2 }, 221 { 0x1000db0d, 0x00 }, 222 { 0x1000db0e, 0x00 }, 223 { 0x1000db0f, 0xe0 }, 224 { 0x1000db10, 0x00 }, 225 { 0x1000db11, 0x10 }, 226 { 0x1000db12, 0x00 }, 227 { 0x1000db13, 0x00 }, 228 { 0x1000db14, 0x45 }, 229 { 0x1000db15, 0x0d }, 230 { 0x1000db16, 0x01 }, 231 { 0x1000db17, 0x00 }, 232 { 0x1000db18, 0x00 }, 233 { 0x1000db19, 0xbf }, 234 { 0x1000db1a, 0x13 }, 235 { 0x1000db1b, 0x09 }, 236 { 0x1000db1c, 0x00 }, 237 { 0x1000db1d, 0x00 }, 238 { 0x1000db1e, 0x00 }, 239 { 0x1000db1f, 0x12 }, 240 { 0x1000db20, 0x09 }, 241 { 0x1000db21, 0x00 }, 242 { 0x1000db22, 0x00 }, 243 { 0x1000db23, 0x00 }, 244 { 0x0000d540, 0x21 }, 245 { 0xc01b, 0xfc }, 246 { 0xc5d1, 0x89 }, 247 { 0xc5d8, 0x0a }, 248 { 0xc5f7, 0x22 }, 249 { 0xc5f6, 0x22 }, 250 { 0xc065, 0xa5 }, 251 { 0xc06b, 0x0a }, 252 { 0xd172, 0x2a }, 253 { 0xc5d6, 0x01 }, 254 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 255 }; 256 257 static const struct reg_sequence rt1321_blind_write[] = { 258 { 0x0000c003, 0xf0 }, 259 { 0x0000c01b, 0xfc }, 260 { 0x0000c5c3, 0xf2 }, 261 { 0x0000c5c2, 0x00 }, 262 { 0x0000c5c1, 0x10 }, 263 { 0x0000c5c0, 0x04 }, 264 { 0x0000c5c7, 0x03 }, 265 { 0x0000c5c6, 0x10 }, 266 { 0x0000c526, 0x47 }, 267 { 0x0000c5c4, 0x12 }, 268 { 0x0000c5c5, 0x60 }, 269 { 0x0000c520, 0x10 }, 270 { 0x0000c521, 0x32 }, 271 { 0x0000c5c7, 0x00 }, 272 { 0x0000c5c8, 0x03 }, 273 { 0x0000c5d3, 0x08 }, 274 { 0x0000c5d2, 0x0a }, 275 { 0x0000c5d1, 0x49 }, 276 { 0x0000c5d0, 0x0f }, 277 { 0x0000c580, 0x10 }, 278 { 0x0000c581, 0x32 }, 279 { 0x0000c582, 0x01 }, 280 { 0x0000cb00, 0x03 }, 281 { 0x0000cb02, 0x52 }, 282 { 0x0000cb04, 0x80 }, 283 { 0x0000cb0b, 0x01 }, 284 { 0x0000c682, 0x60 }, 285 { 0x0000c019, 0x10 }, 286 { 0x0000c5f0, 0x01 }, 287 { 0x0000c5f7, 0x22 }, 288 { 0x0000c5f6, 0x22 }, 289 { 0x0000c057, 0x51 }, 290 { 0x0000c054, 0x55 }, 291 { 0x0000c053, 0x55 }, 292 { 0x0000c052, 0x55 }, 293 { 0x0000c051, 0x01 }, 294 { 0x0000c050, 0x15 }, 295 { 0x0000c060, 0x99 }, 296 { 0x0000c030, 0x55 }, 297 { 0x0000c061, 0x55 }, 298 { 0x0000c063, 0x55 }, 299 { 0x0000c065, 0xa5 }, 300 { 0x0000c06b, 0x0a }, 301 { 0x0000ca05, 0xd6 }, 302 { 0x0000ca07, 0x07 }, 303 { 0x0000ca25, 0xd6 }, 304 { 0x0000ca27, 0x07 }, 305 { 0x0000cd00, 0x05 }, 306 { 0x0000c604, 0x40 }, 307 { 0x0000c609, 0x40 }, 308 { 0x0000c046, 0xf7 }, 309 { 0x0000c045, 0xff }, 310 { 0x0000c044, 0xff }, 311 { 0x0000c043, 0xff }, 312 { 0x0000c042, 0xff }, 313 { 0x0000c041, 0xff }, 314 { 0x0000c040, 0xff }, 315 { 0x0000c049, 0xff }, 316 { 0x0000c028, 0x3f }, 317 { 0x0000c020, 0x3f }, 318 { 0x0000c032, 0x13 }, 319 { 0x0000c033, 0x01 }, 320 { 0x0000cc10, 0x01 }, 321 { 0x0000dc20, 0x03 }, 322 { 0x0000de03, 0x05 }, 323 { 0x0000dc00, 0x00 }, 324 { 0x0000c700, 0xf0 }, 325 { 0x0000c701, 0x13 }, 326 { 0x0000c900, 0xc3 }, 327 { 0x0000c570, 0x08 }, 328 { 0x0000c086, 0x02 }, 329 { 0x0000c085, 0x7f }, 330 { 0x0000c084, 0x00 }, 331 { 0x0000c081, 0xff }, 332 { 0x0000f084, 0x0f }, 333 { 0x0000f083, 0xff }, 334 { 0x0000f082, 0xff }, 335 { 0x0000f081, 0xff }, 336 { 0x0000f080, 0xff }, 337 { 0x20003003, 0x3f }, 338 { 0x20005818, 0x81 }, 339 { 0x20009018, 0x81 }, 340 { 0x2000301c, 0x81 }, 341 { 0x0000c003, 0xc0 }, 342 { 0x0000c047, 0x80 }, 343 { 0x0000d541, 0x80 }, 344 { 0x0000d487, 0x0b }, 345 { 0x0000d487, 0x3b }, 346 { 0x0000d486, 0xc3 }, 347 { 0x0000d470, 0x89 }, 348 { 0x0000d471, 0x3a }, 349 { 0x0000d472, 0x1d }, 350 { 0x0000d478, 0xff }, 351 { 0x0000d479, 0x20 }, 352 { 0x0000d47a, 0x10 }, 353 { 0x0000d73c, 0xb7 }, 354 { 0x0000d73d, 0xd7 }, 355 { 0x0000d73e, 0x00 }, 356 { 0x0000d73f, 0x10 }, 357 { 0x3fc2dfc3, 0x00 }, 358 { 0x3fc2dfc2, 0x00 }, 359 { 0x3fc2dfc1, 0x00 }, 360 { 0x3fc2dfc0, 0x07 }, 361 { 0x3fc2dfc7, 0x00 }, 362 { 0x3fc2dfc6, 0x00 }, 363 { 0x3fc2dfc5, 0x00 }, 364 { 0x3fc2dfc4, 0x01 }, 365 { 0x3fc2df83, 0x00 }, 366 { 0x3fc2df82, 0x00 }, 367 { 0x3fc2df81, 0x00 }, 368 { 0x3fc2df80, 0x00 }, 369 { 0x0000d541, 0x40 }, 370 { 0x0000d486, 0x43 }, 371 { 0x1000db00, 0x03 }, 372 { 0x1000db01, 0x00 }, 373 { 0x1000db02, 0x10 }, 374 { 0x1000db03, 0x00 }, 375 { 0x1000db04, 0x00 }, 376 { 0x1000db05, 0x45 }, 377 { 0x1000db06, 0x12 }, 378 { 0x1000db07, 0x09 }, 379 { 0x1000db08, 0x00 }, 380 { 0x1000db09, 0x00 }, 381 { 0x1000db0a, 0x00 }, 382 { 0x1000db0b, 0x13 }, 383 { 0x1000db0c, 0x09 }, 384 { 0x1000db0d, 0x00 }, 385 { 0x1000db0e, 0x00 }, 386 { 0x1000db0f, 0x00 }, 387 { 0x0000d540, 0x21 }, 388 { 0x41000189, 0x00 }, 389 { 0x4100018a, 0x00 }, 390 { 0x41001988, 0x00 }, 391 { 0x41081400, 0x09 }, 392 { 0x40801508, 0x03 }, 393 { 0x40801588, 0x03 }, 394 { 0x40801809, 0x00 }, 395 { 0x4080180a, 0x00 }, 396 { 0x4080180b, 0x00 }, 397 { 0x4080180c, 0x00 }, 398 { 0x40801b09, 0x00 }, 399 { 0x40801b0a, 0x00 }, 400 { 0x40801b0b, 0x00 }, 401 { 0x40801b0c, 0x00 }, 402 { 0x0000d714, 0x17 }, 403 { 0x20009012, 0x00 }, 404 { 0x0000dd0b, 0x0d }, 405 { 0x0000dd0a, 0xff }, 406 { 0x0000dd09, 0x0d }, 407 { 0x0000dd08, 0xff }, 408 { 0x0000d172, 0x2a }, 409 { 0x41001988, 0x03 }, 410 }; 411 412 static const struct reg_default rt1320_reg_defaults[] = { 413 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 414 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 416 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 417 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 418 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 419 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 420 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 421 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 422 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 423 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 424 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 425 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 426 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 427 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 428 }; 429 430 static const struct reg_default rt1320_mbq_defaults[] = { 431 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 432 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 433 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 434 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 435 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 436 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 437 }; 438 439 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 440 { 441 switch (reg) { 442 case 0xc000 ... 0xc086: 443 case 0xc400 ... 0xc409: 444 case 0xc480 ... 0xc48f: 445 case 0xc4c0 ... 0xc4c4: 446 case 0xc4e0 ... 0xc4e7: 447 case 0xc500: 448 case 0xc560 ... 0xc56b: 449 case 0xc570: 450 case 0xc580 ... 0xc59a: 451 case 0xc5b0 ... 0xc60f: 452 case 0xc640 ... 0xc64f: 453 case 0xc670: 454 case 0xc680 ... 0xc683: 455 case 0xc700 ... 0xc76f: 456 case 0xc800 ... 0xc801: 457 case 0xc820: 458 case 0xc900 ... 0xc901: 459 case 0xc920 ... 0xc921: 460 case 0xca00 ... 0xca07: 461 case 0xca20 ... 0xca27: 462 case 0xca40 ... 0xca4b: 463 case 0xca60 ... 0xca68: 464 case 0xca80 ... 0xca88: 465 case 0xcb00 ... 0xcb0c: 466 case 0xcc00 ... 0xcc12: 467 case 0xcc80 ... 0xcc81: 468 case 0xcd00: 469 case 0xcd80 ... 0xcd82: 470 case 0xce00 ... 0xce4d: 471 case 0xcf00 ... 0xcf25: 472 case 0xd000 ... 0xd0ff: 473 case 0xd100 ... 0xd1ff: 474 case 0xd200 ... 0xd2ff: 475 case 0xd300 ... 0xd3ff: 476 case 0xd400 ... 0xd403: 477 case 0xd410 ... 0xd417: 478 case 0xd470 ... 0xd497: 479 case 0xd4dc ... 0xd50f: 480 case 0xd520 ... 0xd543: 481 case 0xd560 ... 0xd5ef: 482 case 0xd600 ... 0xd663: 483 case 0xda00 ... 0xda6e: 484 case 0xda80 ... 0xda9e: 485 case 0xdb00 ... 0xdb7f: 486 case 0xdc00: 487 case 0xdc20 ... 0xdc21: 488 case 0xdd00 ... 0xdd17: 489 case 0xde00 ... 0xde09: 490 case 0xdf00 ... 0xdf1b: 491 case 0xe000 ... 0xe847: 492 case 0xf01e: 493 case 0xf717 ... 0xf719: 494 case 0xf720 ... 0xf723: 495 case 0x1000cd91 ... 0x1000cd96: 496 case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER: 497 case 0x1000f008: 498 case 0x1000f021: 499 case 0x2000300f: 500 case 0x2000301c: 501 case 0x2000900f: 502 case 0x20009018: 503 case 0x3fc000c0 ... 0x3fc2dfc8: 504 case 0x3fe00000 ... 0x3fe36fff: 505 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 506 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 507 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 508 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 509 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 510 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 511 /* 0x40880900/0x40880980 */ 512 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 513 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 514 /* 0x40881500 */ 515 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 516 /* 0x41000189/0x4100018a */ 517 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 518 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 519 /* 0x41001388 */ 520 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 521 /* 0x41001988 */ 522 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 523 /* 0x41080000 */ 524 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 525 /* 0x41080200 */ 526 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 527 /* 0x41080900 */ 528 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 529 /* 0x41080980 */ 530 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 531 /* 0x41081080 */ 532 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 533 /* 0x41081480/0x41081488 */ 534 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 535 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 536 /* 0x41081980 */ 537 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 538 return true; 539 default: 540 return false; 541 } 542 } 543 544 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 545 { 546 switch (reg) { 547 case 0xc000: 548 case 0xc003: 549 case 0xc081: 550 case 0xc402 ... 0xc406: 551 case 0xc48c ... 0xc48f: 552 case 0xc560: 553 case 0xc5b5 ... 0xc5b7: 554 case 0xc5c3: 555 case 0xc5c8: 556 case 0xc5fc ... 0xc5ff: 557 case 0xc680 ... 0xc683: 558 case 0xc820: 559 case 0xc900: 560 case 0xc920: 561 case 0xca42: 562 case 0xca62: 563 case 0xca82: 564 case 0xcd00: 565 case 0xce03: 566 case 0xce10: 567 case 0xce14 ... 0xce17: 568 case 0xce44 ... 0xce49: 569 case 0xce4c ... 0xce4d: 570 case 0xcf0c: 571 case 0xcf10 ... 0xcf25: 572 case 0xd486 ... 0xd487: 573 case 0xd4e5 ... 0xd4e6: 574 case 0xd4e8 ... 0xd4ff: 575 case 0xd530: 576 case 0xd540 ... 0xd541: 577 case 0xd543: 578 case 0xdb58 ... 0xdb5f: 579 case 0xdb60 ... 0xdb63: 580 case 0xdb68 ... 0xdb69: 581 case 0xdb6d: 582 case 0xdb70 ... 0xdb71: 583 case 0xdb76: 584 case 0xdb7a: 585 case 0xdb7c ... 0xdb7f: 586 case 0xdd0c ... 0xdd13: 587 case 0xde02: 588 case 0xdf14 ... 0xdf1b: 589 case 0xe80b: 590 case 0xe83c ... 0xe847: 591 case 0xf01e: 592 case 0xf717 ... 0xf719: 593 case 0xf720 ... 0xf723: 594 case 0x10000000 ... 0x10008fff: 595 case 0x1000c000 ... 0x1000dfff: 596 case 0x1000f008: 597 case 0x1000f021: 598 case 0x2000300f: 599 case 0x2000301c: 600 case 0x2000900f: 601 case 0x20009018: 602 case 0x3fc2ab80 ... 0x3fc2ac4c: 603 case 0x3fc2b780: 604 case 0x3fc2bf80 ... 0x3fc2bf83: 605 case 0x3fc2bfc0 ... 0x3fc2bfc8: 606 case 0x3fc2d300 ... 0x3fc2d354: 607 case 0x3fc2dfc0 ... 0x3fc2dfc8: 608 case 0x3fe2e000 ... 0x3fe2e003: 609 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 610 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 611 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 612 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 613 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 614 return true; 615 default: 616 return false; 617 } 618 } 619 620 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 621 { 622 switch (reg) { 623 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 624 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 625 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 626 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 627 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 628 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 629 return true; 630 default: 631 return false; 632 } 633 } 634 635 static const struct regmap_config rt1320_sdw_regmap = { 636 .reg_bits = 32, 637 .val_bits = 8, 638 .readable_reg = rt1320_readable_register, 639 .volatile_reg = rt1320_volatile_register, 640 .max_register = 0x41081980, 641 .reg_defaults = rt1320_reg_defaults, 642 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 643 .cache_type = REGCACHE_MAPLE, 644 .use_single_read = true, 645 .use_single_write = true, 646 }; 647 648 static const struct regmap_config rt1320_mbq_regmap = { 649 .name = "sdw-mbq", 650 .reg_bits = 32, 651 .val_bits = 16, 652 .readable_reg = rt1320_mbq_readable_register, 653 .max_register = 0x41000192, 654 .reg_defaults = rt1320_mbq_defaults, 655 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 656 .cache_type = REGCACHE_MAPLE, 657 .use_single_read = true, 658 .use_single_write = true, 659 }; 660 661 static int rt1320_read_prop(struct sdw_slave *slave) 662 { 663 struct sdw_slave_prop *prop = &slave->prop; 664 int nval; 665 int i, j; 666 u32 bit; 667 unsigned long addr; 668 struct sdw_dpn_prop *dpn; 669 670 /* 671 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 672 */ 673 sdw_slave_read_prop(slave); 674 675 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 676 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 677 678 prop->paging_support = true; 679 prop->lane_control_support = true; 680 681 /* first we need to allocate memory for set bits in port lists */ 682 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 683 prop->sink_ports = BIT(1); 684 685 nval = hweight32(prop->source_ports); 686 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 687 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 688 if (!prop->src_dpn_prop) 689 return -ENOMEM; 690 691 i = 0; 692 dpn = prop->src_dpn_prop; 693 addr = prop->source_ports; 694 for_each_set_bit(bit, &addr, 32) { 695 dpn[i].num = bit; 696 dpn[i].type = SDW_DPN_FULL; 697 dpn[i].simple_ch_prep_sm = true; 698 dpn[i].ch_prep_timeout = 10; 699 i++; 700 } 701 702 /* do this again for sink now */ 703 nval = hweight32(prop->sink_ports); 704 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 705 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 706 if (!prop->sink_dpn_prop) 707 return -ENOMEM; 708 709 j = 0; 710 dpn = prop->sink_dpn_prop; 711 addr = prop->sink_ports; 712 for_each_set_bit(bit, &addr, 32) { 713 dpn[j].num = bit; 714 dpn[j].type = SDW_DPN_FULL; 715 dpn[j].simple_ch_prep_sm = true; 716 dpn[j].ch_prep_timeout = 10; 717 j++; 718 } 719 720 prop->dp0_prop = devm_kzalloc(&slave->dev, sizeof(*prop->dp0_prop), GFP_KERNEL); 721 if (!prop->dp0_prop) 722 return -ENOMEM; 723 724 prop->dp0_prop->simple_ch_prep_sm = true; 725 prop->dp0_prop->ch_prep_timeout = 10; 726 727 /* set the timeout values */ 728 prop->clk_stop_timeout = 64; 729 730 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */ 731 prop->wake_capable = 0; 732 733 return 0; 734 } 735 736 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 737 unsigned char entity, unsigned char ps) 738 { 739 unsigned int delay = 2000, val; 740 741 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 742 743 /* waiting for Actual PDE becomes to PS0/PS3 */ 744 while (delay) { 745 regmap_read(rt1320->regmap, 746 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 747 if (val == ps) 748 break; 749 750 usleep_range(1000, 1500); 751 delay--; 752 } 753 if (!delay) { 754 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 755 return -ETIMEDOUT; 756 } 757 758 return 0; 759 } 760 761 static void rt1320_data_rw(struct rt1320_sdw_priv *rt1320, unsigned int start, 762 unsigned char *data, unsigned int size, enum rt1320_rw_type rw) 763 { 764 struct device *dev = &rt1320->sdw_slave->dev; 765 unsigned int tmp; 766 int ret = -1; 767 int i, j; 768 769 pm_runtime_set_autosuspend_delay(dev, 20000); 770 pm_runtime_mark_last_busy(dev); 771 772 switch (rw) { 773 case RT1320_BRA_WRITE: 774 case RT1320_BRA_READ: 775 ret = sdw_bpt_send_sync(rt1320->sdw_slave->bus, rt1320->sdw_slave, &rt1320->bra_msg); 776 if (ret < 0) 777 dev_err(dev, "%s: Failed to send BRA message: %d\n", __func__, ret); 778 fallthrough; 779 case RT1320_PARAM_WRITE: 780 case RT1320_PARAM_READ: 781 if (ret < 0) { 782 /* if BRA fails, we try to access by the control word */ 783 if (rw == RT1320_BRA_WRITE || rw == RT1320_BRA_READ) { 784 for (i = 0; i < rt1320->bra_msg.sections; i++) { 785 pm_runtime_mark_last_busy(dev); 786 for (j = 0; j < rt1320->bra_msg.sec[i].len; j++) { 787 if (rw == RT1320_BRA_WRITE) { 788 regmap_write(rt1320->regmap, 789 rt1320->bra_msg.sec[i].addr + j, rt1320->bra_msg.sec[i].buf[j]); 790 } else { 791 regmap_read(rt1320->regmap, rt1320->bra_msg.sec[i].addr + j, &tmp); 792 rt1320->bra_msg.sec[i].buf[j] = tmp; 793 } 794 } 795 } 796 } else { 797 for (i = 0; i < size; i++) { 798 if (rw == RT1320_PARAM_WRITE) 799 regmap_write(rt1320->regmap, start + i, data[i]); 800 else { 801 regmap_read(rt1320->regmap, start + i, &tmp); 802 data[i] = tmp; 803 } 804 } 805 } 806 } 807 break; 808 } 809 810 pm_runtime_set_autosuspend_delay(dev, 3000); 811 pm_runtime_mark_last_busy(dev); 812 } 813 814 static unsigned long long rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv *rt1320, unsigned int rsgain) 815 { 816 unsigned long long base = 1000000000U; 817 unsigned long long step = 1960784U; 818 unsigned long long tmp, result; 819 820 if (rsgain == 0 || rsgain == 0x1ff) 821 result = 1000000000; 822 else if (rsgain & 0x100) { 823 tmp = 0xff - (rsgain & 0xff); 824 tmp = tmp * step; 825 result = base + tmp; 826 } else { 827 tmp = (rsgain & 0xff); 828 tmp = tmp * step; 829 result = base - tmp; 830 } 831 832 return result; 833 } 834 835 static void rt1320_pr_read(struct rt1320_sdw_priv *rt1320, unsigned int reg, unsigned int *val) 836 { 837 unsigned int byte3, byte2, byte1, byte0; 838 839 regmap_write(rt1320->regmap, 0xc483, 0x80); 840 regmap_write(rt1320->regmap, 0xc482, 0x40); 841 regmap_write(rt1320->regmap, 0xc481, 0x0c); 842 regmap_write(rt1320->regmap, 0xc480, 0x10); 843 844 regmap_write(rt1320->regmap, 0xc487, ((reg & 0xff000000) >> 24)); 845 regmap_write(rt1320->regmap, 0xc486, ((reg & 0x00ff0000) >> 16)); 846 regmap_write(rt1320->regmap, 0xc485, ((reg & 0x0000ff00) >> 8)); 847 regmap_write(rt1320->regmap, 0xc484, (reg & 0x000000ff)); 848 849 regmap_write(rt1320->regmap, 0xc482, 0xc0); 850 851 regmap_read(rt1320->regmap, 0xc48f, &byte3); 852 regmap_read(rt1320->regmap, 0xc48e, &byte2); 853 regmap_read(rt1320->regmap, 0xc48d, &byte1); 854 regmap_read(rt1320->regmap, 0xc48c, &byte0); 855 856 *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; 857 } 858 859 static int rt1320_check_fw_ready(struct rt1320_sdw_priv *rt1320) 860 { 861 struct device *dev = &rt1320->sdw_slave->dev; 862 unsigned int tmp, retry = 0; 863 unsigned int cmd_addr; 864 865 switch (rt1320->dev_id) { 866 case RT1320_DEV_ID: 867 cmd_addr = RT1320_CMD_ID; 868 break; 869 case RT1321_DEV_ID: 870 cmd_addr = RT1321_CMD_ID; 871 break; 872 default: 873 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 874 return -EINVAL; 875 } 876 877 pm_runtime_mark_last_busy(dev); 878 /* check the value of cmd_addr becomes to zero */ 879 while (retry < 500) { 880 regmap_read(rt1320->regmap, cmd_addr, &tmp); 881 if (tmp == 0) 882 break; 883 usleep_range(1000, 1100); 884 retry++; 885 } 886 if (retry == 500) { 887 dev_warn(dev, "%s FW is NOT ready!", __func__); 888 return -ETIMEDOUT; 889 } 890 891 return 0; 892 } 893 894 static int rt1320_check_power_state_ready(struct rt1320_sdw_priv *rt1320, enum rt1320_power_state ps) 895 { 896 struct device *dev = &rt1320->sdw_slave->dev; 897 unsigned int retry = 0, tmp; 898 899 pm_runtime_mark_last_busy(dev); 900 while (retry < 200) { 901 regmap_read(rt1320->regmap, RT1320_POWER_STATE, &tmp); 902 dev_dbg(dev, "%s, RT1320_POWER_STATE=0x%x\n", __func__, tmp); 903 if (tmp >= ps) 904 break; 905 usleep_range(1000, 1500); 906 retry++; 907 } 908 if (retry == 200) { 909 dev_warn(dev, "%s FW Power State is NOT ready!", __func__); 910 return -ETIMEDOUT; 911 } 912 913 return 0; 914 } 915 916 static int rt1320_process_fw_param(struct rt1320_sdw_priv *rt1320, unsigned char *buf, unsigned int buf_size) 917 { 918 struct device *dev = &rt1320->sdw_slave->dev; 919 struct rt1320_paramcmd *paramhr = (struct rt1320_paramcmd *)buf; 920 unsigned char moudleid = paramhr->moudleid; 921 unsigned char cmdtype = paramhr->commandtype; 922 unsigned int fw_param_addr; 923 unsigned int start_addr; 924 int ret = 0; 925 926 switch (rt1320->dev_id) { 927 case RT1320_DEV_ID: 928 fw_param_addr = RT1320_FW_PARAM_ADDR; 929 start_addr = RT1320_CMD_PARAM_ADDR; 930 break; 931 case RT1321_DEV_ID: 932 fw_param_addr = RT1321_FW_PARAM_ADDR; 933 start_addr = RT1321_CMD_PARAM_ADDR; 934 break; 935 default: 936 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 937 return -EINVAL; 938 } 939 940 ret = rt1320_check_fw_ready(rt1320); 941 if (ret < 0) 942 goto _timeout_; 943 944 /* don't set offset 0x0/0x1, it will be set later*/ 945 paramhr->moudleid = 0; 946 paramhr->commandtype = 0; 947 rt1320_data_rw(rt1320, fw_param_addr, buf, buf_size, RT1320_PARAM_WRITE); 948 949 dev_dbg(dev, "%s, moudleid=%d, cmdtype=%d, paramid=%d, paramlength=%d\n", __func__, 950 moudleid, cmdtype, paramhr->paramid, paramhr->paramlength); 951 952 if (cmdtype == RT1320_SET_PARAM) { 953 regmap_write(rt1320->regmap, fw_param_addr, moudleid); 954 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x01); 955 } 956 if (cmdtype == RT1320_GET_PARAM) { 957 regmap_write(rt1320->regmap, fw_param_addr, moudleid); 958 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x02); 959 ret = rt1320_check_fw_ready(rt1320); 960 if (ret < 0) 961 goto _timeout_; 962 963 rt1320_data_rw(rt1320, start_addr, buf + 0x10, paramhr->commandlength, RT1320_PARAM_READ); 964 } 965 return 0; 966 967 _timeout_: 968 dev_err(&rt1320->sdw_slave->dev, "%s: FW is NOT ready for SET/GET_PARAM\n", __func__); 969 return ret; 970 } 971 972 static int rt1320_fw_param_protocol(struct rt1320_sdw_priv *rt1320, enum rt1320_fw_cmdid cmdid, 973 unsigned int paramid, void *parambuf, unsigned int paramsize) 974 { 975 struct device *dev = &rt1320->sdw_slave->dev; 976 unsigned char *tempbuf = NULL; 977 struct rt1320_paramcmd paramhr; 978 int ret = 0; 979 980 tempbuf = kzalloc(sizeof(paramhr) + paramsize, GFP_KERNEL); 981 if (!tempbuf) 982 return -ENOMEM; 983 984 paramhr.moudleid = 1; 985 paramhr.commandtype = cmdid; 986 /* 8 is "sizeof(paramid) + sizeof(paramlength)" */ 987 paramhr.commandlength = 8 + paramsize; 988 paramhr.paramid = paramid; 989 paramhr.paramlength = paramsize; 990 991 memcpy(tempbuf, ¶mhr, sizeof(paramhr)); 992 if (cmdid == RT1320_SET_PARAM) 993 memcpy(tempbuf + sizeof(paramhr), parambuf, paramsize); 994 995 ret = rt1320_process_fw_param(rt1320, tempbuf, sizeof(paramhr) + paramsize); 996 if (ret < 0) { 997 dev_err(dev, "%s: process_fw_param failed\n", __func__); 998 goto _finish_; 999 } 1000 1001 if (cmdid == RT1320_GET_PARAM) 1002 memcpy(parambuf, tempbuf + sizeof(paramhr), paramsize); 1003 1004 _finish_: 1005 kfree(tempbuf); 1006 return ret; 1007 } 1008 1009 static void rt1320_set_advancemode(struct rt1320_sdw_priv *rt1320) 1010 { 1011 struct device *dev = &rt1320->sdw_slave->dev; 1012 struct rt1320_datafixpoint r0_data[2]; 1013 unsigned short l_advancegain, r_advancegain; 1014 int ret; 1015 1016 /* Get advance gain/r0 */ 1017 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1018 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1019 l_advancegain = r0_data[0].advancegain; 1020 r_advancegain = r0_data[1].advancegain; 1021 dev_dbg(dev, "%s, LR advanceGain=0x%x 0x%x\n", __func__, l_advancegain, r_advancegain); 1022 1023 /* set R0 and enable protection by SetParameter id 6, 7 */ 1024 r0_data[0].silencedetect = 0; 1025 r0_data[0].r0 = rt1320->r0_l_reg; 1026 r0_data[1].silencedetect = 0; 1027 r0_data[1].r0 = rt1320->r0_r_reg; 1028 dev_dbg(dev, "%s, write LR r0=%d, %d\n", __func__, r0_data[0].r0, r0_data[1].r0); 1029 1030 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1031 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1032 ret = rt1320_check_fw_ready(rt1320); 1033 if (ret < 0) 1034 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__); 1035 1036 if (l_advancegain != 0 && r_advancegain != 0) { 1037 regmap_write(rt1320->regmap, 0xdd0b, (l_advancegain & 0xff00) >> 8); 1038 regmap_write(rt1320->regmap, 0xdd0a, (l_advancegain & 0xff)); 1039 regmap_write(rt1320->regmap, 0xdd09, (r_advancegain & 0xff00) >> 8); 1040 regmap_write(rt1320->regmap, 0xdd08, (r_advancegain & 0xff)); 1041 dev_dbg(dev, "%s, set Advance mode gain\n", __func__); 1042 } 1043 } 1044 1045 static int rt1320_invrs_load(struct rt1320_sdw_priv *rt1320) 1046 { 1047 struct device *dev = &rt1320->sdw_slave->dev; 1048 unsigned long long l_rsratio, r_rsratio; 1049 unsigned int pr_1058, pr_1059, pr_105a; 1050 unsigned long long l_invrs, r_invrs; 1051 unsigned long long factor = (1 << 28); 1052 unsigned int l_rsgain, r_rsgain; 1053 struct rt1320_datafixpoint r0_data[2]; 1054 int ret; 1055 1056 /* read L/Rch Rs Gain - it uses for compensating the R0 value */ 1057 rt1320_pr_read(rt1320, 0x1058, &pr_1058); 1058 rt1320_pr_read(rt1320, 0x1059, &pr_1059); 1059 rt1320_pr_read(rt1320, 0x105a, &pr_105a); 1060 l_rsgain = ((pr_1059 & 0x7f) << 2) | ((pr_105a & 0xc0) >> 6); 1061 r_rsgain = ((pr_1058 & 0xff) << 1) | ((pr_1059 & 0x80) >> 7); 1062 dev_dbg(dev, "%s, LR rsgain=0x%x, 0x%x\n", __func__, l_rsgain, r_rsgain); 1063 1064 l_rsratio = rt1320_rsgain_to_rsratio(rt1320, l_rsgain); 1065 r_rsratio = rt1320_rsgain_to_rsratio(rt1320, r_rsgain); 1066 dev_dbg(dev, "%s, LR rsratio=%lld, %lld\n", __func__, l_rsratio, r_rsratio); 1067 1068 l_invrs = div_u64(l_rsratio * factor, 1000000000U); 1069 r_invrs = div_u64(r_rsratio * factor, 1000000000U); 1070 1071 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1072 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1073 1074 r0_data[0].invrs = l_invrs; 1075 r0_data[1].invrs = r_invrs; 1076 dev_dbg(dev, "%s, write DSP LR invrs=0x%x, 0x%x\n", __func__, r0_data[0].invrs, r0_data[1].invrs); 1077 1078 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1079 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1080 ret = rt1320_check_fw_ready(rt1320); 1081 if (ret < 0) 1082 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__); 1083 1084 return ret; 1085 } 1086 1087 static void rt1320_calc_r0(struct rt1320_sdw_priv *rt1320) 1088 { 1089 struct device *dev = &rt1320->sdw_slave->dev; 1090 unsigned long long l_calir0, r_calir0, l_calir0_lo, r_calir0_lo; 1091 1092 l_calir0 = rt1320->r0_l_reg >> 27; 1093 r_calir0 = rt1320->r0_r_reg >> 27; 1094 l_calir0_lo = ((rt1320->r0_l_reg & ((1ull << 27) - 1)) * 1000) >> 27; 1095 r_calir0_lo = ((rt1320->r0_r_reg & ((1ull << 27) - 1)) * 1000) >> 27; 1096 1097 dev_dbg(dev, "%s, l_calir0=%lld.%03lld ohm, r_calir0=%lld.%03lld ohm\n", __func__, 1098 l_calir0, l_calir0_lo, r_calir0, r_calir0_lo); 1099 } 1100 1101 static void rt1320_calibrate(struct rt1320_sdw_priv *rt1320) 1102 { 1103 struct device *dev = &rt1320->sdw_slave->dev; 1104 struct rt1320_datafixpoint audfixpoint[2]; 1105 unsigned int reg_c5fb, reg_c570, reg_cd00; 1106 unsigned int vol_reg[4], fw_ready; 1107 unsigned long long l_meanr0, r_meanr0; 1108 unsigned int fw_status_addr; 1109 int l_re[5], r_re[5]; 1110 int ret, tmp; 1111 unsigned long long factor = (1 << 27); 1112 unsigned short l_advancegain, r_advancegain; 1113 unsigned int delay_s = 7; /* delay seconds for the calibration */ 1114 1115 if (!rt1320->component) 1116 return; 1117 1118 switch (rt1320->dev_id) { 1119 case RT1320_DEV_ID: 1120 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 1121 break; 1122 case RT1321_DEV_ID: 1123 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 1124 break; 1125 default: 1126 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1127 return; 1128 } 1129 1130 /* set volume 0dB */ 1131 regmap_read(rt1320->regmap, 0xdd0b, &vol_reg[3]); 1132 regmap_read(rt1320->regmap, 0xdd0a, &vol_reg[2]); 1133 regmap_read(rt1320->regmap, 0xdd09, &vol_reg[1]); 1134 regmap_read(rt1320->regmap, 0xdd08, &vol_reg[0]); 1135 regmap_write(rt1320->regmap, 0xdd0b, 0x0f); 1136 regmap_write(rt1320->regmap, 0xdd0a, 0xff); 1137 regmap_write(rt1320->regmap, 0xdd09, 0x0f); 1138 regmap_write(rt1320->regmap, 0xdd08, 0xff); 1139 1140 regmap_read(rt1320->regmap, 0xc5fb, ®_c5fb); 1141 regmap_read(rt1320->regmap, 0xc570, ®_c570); 1142 regmap_read(rt1320->regmap, 0xcd00, ®_cd00); 1143 1144 regmap_write(rt1320->regmap, 1145 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1146 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1147 if (ret < 0) { 1148 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__); 1149 goto _finish_; 1150 } 1151 1152 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 1153 fw_ready &= 0x1; 1154 if (!fw_ready) { 1155 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__); 1156 goto _finish_; 1157 } 1158 1159 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE); 1160 if (ret < 0) { 1161 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__); 1162 goto _finish_; 1163 } 1164 1165 if (rt1320->dev_id == RT1320_DEV_ID) 1166 regmap_write(rt1320->regmap, 0xc5fb, 0x00); 1167 regmap_write(rt1320->regmap, 0xc570, 0x0b); 1168 regmap_write(rt1320->regmap, 0xcd00, 0xc5); 1169 1170 /* disable silence detection */ 1171 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0x00); 1172 dev_dbg(dev, "%s, disable silence detection\n", __func__); 1173 1174 ret = rt1320_check_power_state_ready(rt1320, RT1320_K_R0_STATE); 1175 if (ret < 0) { 1176 dev_dbg(dev, "%s, check class D status before k r0\n", __func__); 1177 goto _finish_; 1178 } 1179 1180 for (tmp = 0; tmp < delay_s; tmp++) { 1181 msleep(1000); 1182 pm_runtime_mark_last_busy(dev); 1183 1184 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re)); 1185 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re)); 1186 1187 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]); 1188 dev_dbg(dev, "%s, waiting for calibration R0...%d seconds\n", __func__, tmp + 1); 1189 } 1190 1191 /* Get Calibration data */ 1192 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re)); 1193 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re)); 1194 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]); 1195 1196 /* Get advance gain/mean r0 */ 1197 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &audfixpoint[0], sizeof(struct rt1320_datafixpoint)); 1198 l_meanr0 = audfixpoint[0].meanr0; 1199 l_advancegain = audfixpoint[0].advancegain; 1200 l_meanr0 = ((l_meanr0 * 1000U) / factor); 1201 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &audfixpoint[1], sizeof(struct rt1320_datafixpoint)); 1202 r_meanr0 = audfixpoint[1].meanr0; 1203 r_advancegain = audfixpoint[1].advancegain; 1204 r_meanr0 = ((r_meanr0 * 1000U) / factor); 1205 dev_dbg(dev, "%s, LR meanr0=%lld, %lld\n", __func__, l_meanr0, r_meanr0); 1206 dev_dbg(dev, "%s, LR advanceGain=0x%x, 0x%x\n", __func__, l_advancegain, r_advancegain); 1207 dev_dbg(dev, "%s, LR invrs=0x%x, 0x%x\n", __func__, audfixpoint[0].invrs, audfixpoint[1].invrs); 1208 1209 /* enable silence detection */ 1210 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0xe0); 1211 dev_dbg(dev, "%s, enable silence detection\n", __func__); 1212 1213 regmap_write(rt1320->regmap, 0xc5fb, reg_c5fb); 1214 regmap_write(rt1320->regmap, 0xc570, reg_c570); 1215 regmap_write(rt1320->regmap, 0xcd00, reg_cd00); 1216 1217 rt1320->r0_l_reg = l_re[4]; 1218 rt1320->r0_r_reg = r_re[4]; 1219 rt1320->cali_done = true; 1220 rt1320_calc_r0(rt1320); 1221 1222 _finish_: 1223 regmap_write(rt1320->regmap, 1224 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1225 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1226 1227 /* advance gain will be set when R0 load, not here */ 1228 regmap_write(rt1320->regmap, 0xdd0b, vol_reg[3]); 1229 regmap_write(rt1320->regmap, 0xdd0a, vol_reg[2]); 1230 regmap_write(rt1320->regmap, 0xdd09, vol_reg[1]); 1231 regmap_write(rt1320->regmap, 0xdd08, vol_reg[0]); 1232 } 1233 1234 static int rt1320_r0_cali_get(struct snd_kcontrol *kcontrol, 1235 struct snd_ctl_elem_value *ucontrol) 1236 { 1237 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1238 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1239 1240 ucontrol->value.integer.value[0] = rt1320->cali_done; 1241 return 0; 1242 } 1243 1244 static int rt1320_r0_cali_put(struct snd_kcontrol *kcontrol, 1245 struct snd_ctl_elem_value *ucontrol) 1246 { 1247 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1248 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1249 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 1250 int ret; 1251 1252 if (!rt1320->hw_init) 1253 return 0; 1254 1255 ret = pm_runtime_resume(component->dev); 1256 if (ret < 0 && ret != -EACCES) 1257 return ret; 1258 1259 rt1320->cali_done = false; 1260 snd_soc_dapm_mutex_lock(dapm); 1261 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF && 1262 ucontrol->value.integer.value[0]) { 1263 rt1320_calibrate(rt1320); 1264 } 1265 snd_soc_dapm_mutex_unlock(dapm); 1266 1267 return 0; 1268 } 1269 1270 /* 1271 * The 'patch code' is written to the patch code area. 1272 * The patch code area is used for SDCA register expansion flexibility. 1273 */ 1274 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 1275 { 1276 struct sdw_slave *slave = rt1320->sdw_slave; 1277 const struct firmware *patch; 1278 const char *filename; 1279 unsigned int addr, val, min_addr, max_addr; 1280 const unsigned char *ptr; 1281 int ret, i; 1282 1283 switch (rt1320->dev_id) { 1284 case RT1320_DEV_ID: 1285 if (rt1320->version_id <= RT1320_VB) 1286 filename = RT1320_VAB_MCU_PATCH; 1287 else 1288 filename = RT1320_VC_MCU_PATCH; 1289 min_addr = 0x10007000; 1290 max_addr = 0x10007fff; 1291 break; 1292 case RT1321_DEV_ID: 1293 filename = RT1321_VA_MCU_PATCH; 1294 min_addr = 0x10008000; 1295 max_addr = 0x10008fff; 1296 break; 1297 default: 1298 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1299 return; 1300 } 1301 1302 /* load the patch code here */ 1303 ret = request_firmware(&patch, filename, &slave->dev); 1304 if (ret) { 1305 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 1306 regmap_write(rt1320->regmap, 0xc598, 0x00); 1307 regmap_write(rt1320->regmap, min_addr, 0x67); 1308 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80); 1309 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00); 1310 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00); 1311 if (rt1320->dev_id == RT1321_DEV_ID) { 1312 regmap_write(rt1320->regmap, 0xd73c, 0x67); 1313 regmap_write(rt1320->regmap, 0xd73d, 0x80); 1314 regmap_write(rt1320->regmap, 0xd73e, 0x00); 1315 regmap_write(rt1320->regmap, 0xd73f, 0x00); 1316 } 1317 } else { 1318 ptr = (const unsigned char *)patch->data; 1319 if ((patch->size % 8) == 0) { 1320 for (i = 0; i < patch->size; i += 8) { 1321 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 1322 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 1323 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 1324 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 1325 1326 if (addr > max_addr || addr < min_addr) { 1327 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 1328 goto _exit_; 1329 } 1330 if (val > 0xff) { 1331 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 1332 goto _exit_; 1333 } 1334 regmap_write(rt1320->regmap, addr, val); 1335 } 1336 } 1337 _exit_: 1338 release_firmware(patch); 1339 } 1340 } 1341 1342 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 1343 { 1344 unsigned int i, reg, val, delay; 1345 1346 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 1347 reg = rt1320_blind_write[i].reg; 1348 val = rt1320_blind_write[i].def; 1349 delay = rt1320_blind_write[i].delay_us; 1350 1351 if (reg == 0x3fc2bfc7) 1352 rt1320_load_mcu_patch(rt1320); 1353 1354 regmap_write(rt1320->regmap, reg, val); 1355 if (delay) 1356 usleep_range(delay, delay + 1000); 1357 } 1358 } 1359 1360 static void rt1320_t0_load(struct rt1320_sdw_priv *rt1320, unsigned int l_t0, unsigned int r_t0) 1361 { 1362 struct device *dev = &rt1320->sdw_slave->dev; 1363 unsigned int factor = (1 << 22), fw_ready; 1364 int l_t0_data[38], r_t0_data[38]; 1365 unsigned int fw_status_addr; 1366 1367 switch (rt1320->dev_id) { 1368 case RT1320_DEV_ID: 1369 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 1370 break; 1371 case RT1321_DEV_ID: 1372 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 1373 break; 1374 default: 1375 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1376 return; 1377 } 1378 1379 regmap_write(rt1320->regmap, 1380 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1381 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1382 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1383 1384 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 1385 fw_ready &= 0x1; 1386 if (!fw_ready) { 1387 dev_warn(dev, "%s, DSP FW is NOT ready\n", __func__); 1388 goto _exit_; 1389 } 1390 1391 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1392 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1393 1394 l_t0_data[37] = l_t0 * factor; 1395 r_t0_data[37] = r_t0 * factor; 1396 1397 dev_dbg(dev, "%s, write LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]); 1398 1399 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1400 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1401 if (rt1320_check_fw_ready(rt1320) < 0) 1402 dev_err(dev, "%s: Failed to set FW param 3,4!\n", __func__); 1403 1404 rt1320->temp_l_calib = l_t0; 1405 rt1320->temp_r_calib = r_t0; 1406 1407 memset(&l_t0_data[0], 0x00, sizeof(l_t0_data)); 1408 memset(&r_t0_data[0], 0x00, sizeof(r_t0_data)); 1409 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1410 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1411 dev_dbg(dev, "%s, read after writing LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]); 1412 1413 _exit_: 1414 regmap_write(rt1320->regmap, 1415 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1416 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1417 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1418 } 1419 1420 static int rt1320_rae_load(struct rt1320_sdw_priv *rt1320) 1421 { 1422 struct device *dev = &rt1320->sdw_slave->dev; 1423 static const char func_tag[] = "FUNC"; 1424 static const char xu_tag[] = "XU"; 1425 const struct firmware *rae_fw = NULL; 1426 unsigned int fw_offset; 1427 unsigned char *fw_data; 1428 unsigned char *param_data; 1429 unsigned int addr, size; 1430 unsigned int func, value; 1431 const char *dmi_vendor, *dmi_product, *dmi_sku; 1432 char vendor[128], product[128], sku[128]; 1433 char *ptr_vendor, *ptr_product, *ptr_sku; 1434 char rae_filename[512]; 1435 char tag[5]; 1436 int ret = 0; 1437 int retry = 200; 1438 1439 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1440 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 1441 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 1442 1443 if (dmi_vendor && dmi_product && dmi_sku) { 1444 strscpy(vendor, dmi_vendor); 1445 strscpy(product, dmi_product); 1446 strscpy(sku, dmi_sku); 1447 ptr_vendor = &vendor[0]; 1448 ptr_product = &product[0]; 1449 ptr_sku = &sku[0]; 1450 ptr_vendor = strsep(&ptr_vendor, " "); 1451 ptr_product = strsep(&ptr_product, " "); 1452 ptr_sku = strsep(&ptr_sku, " "); 1453 1454 dev_dbg(dev, "%s: DMI vendor=%s, product=%s, sku=%s\n", __func__, 1455 vendor, product, sku); 1456 1457 snprintf(rae_filename, sizeof(rae_filename), 1458 "realtek/rt1320/rt1320_RAE_%s_%s_%s.dat", vendor, product, sku); 1459 dev_dbg(dev, "%s: try to load RAE file %s\n", __func__, rae_filename); 1460 } else { 1461 dev_warn(dev, "%s: Can't find proper RAE file name\n", __func__); 1462 return -EINVAL; 1463 } 1464 1465 regmap_write(rt1320->regmap, 1466 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1467 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1468 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1469 1470 request_firmware(&rae_fw, rae_filename, dev); 1471 if (rae_fw) { 1472 1473 /* RAE CRC clear */ 1474 regmap_write(rt1320->regmap, 0xe80b, 0x0f); 1475 1476 /* RAE stop & CRC disable */ 1477 regmap_update_bits(rt1320->regmap, 0xe803, 0xbc, 0x00); 1478 1479 while (--retry) { 1480 regmap_read(rt1320->regmap, 0xe83f, &value); 1481 if (value & 0x40) 1482 break; 1483 usleep_range(1000, 1100); 1484 } 1485 if (!retry && !(value & 0x40)) { 1486 dev_err(dev, "%s: RAE is not ready to load\n", __func__); 1487 return -ETIMEDOUT; 1488 } 1489 1490 dev_dbg(dev, "%s, rae_fw size=0x%zx\n", __func__, rae_fw->size); 1491 regcache_cache_bypass(rt1320->regmap, true); 1492 for (fw_offset = 0; fw_offset < rae_fw->size;) { 1493 1494 dev_dbg(dev, "%s, fw_offset=0x%x\n", __func__, fw_offset); 1495 1496 fw_data = (unsigned char *)&rae_fw->data[fw_offset]; 1497 1498 memcpy(tag, fw_data, 4); 1499 tag[4] = '\0'; 1500 dev_dbg(dev, "%s, tag=%s\n", __func__, tag); 1501 if (strcmp(tag, xu_tag) == 0) { 1502 dev_dbg(dev, "%s: This is a XU tag", __func__); 1503 memcpy(&addr, (fw_data + 4), 4); 1504 memcpy(&size, (fw_data + 8), 4); 1505 param_data = (unsigned char *)(fw_data + 12); 1506 1507 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size); 1508 1509 /* 1510 * UI register ranges from 0x1000d000 to 0x1000d7ff 1511 * UI registers should be accessed by tuning tool. 1512 * So, there registers should be cached. 1513 */ 1514 if (addr <= 0x1000d7ff && addr >= 0x1000d000) 1515 regcache_cache_bypass(rt1320->regmap, false); 1516 1517 rt1320_data_rw(rt1320, addr, param_data, size, RT1320_PARAM_WRITE); 1518 1519 regcache_cache_bypass(rt1320->regmap, true); 1520 1521 fw_offset += (size + 12); 1522 } else if (strcmp(tag, func_tag) == 0) { 1523 dev_err(dev, "%s: This is a FUNC tag", __func__); 1524 1525 memcpy(&func, (fw_data + 4), 4); 1526 memcpy(&value, (fw_data + 8), 4); 1527 1528 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", __func__, func, value); 1529 if (func == 1) //DelayMs 1530 msleep(value); 1531 1532 fw_offset += 12; 1533 } else { 1534 dev_err(dev, "%s: This is NOT a XU file (wrong tag)", __func__); 1535 break; 1536 } 1537 } 1538 1539 regcache_cache_bypass(rt1320->regmap, false); 1540 release_firmware(rae_fw); 1541 1542 } else { 1543 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, rae_filename); 1544 ret = -EINVAL; 1545 goto _exit_; 1546 } 1547 1548 /* RAE CRC enable */ 1549 regmap_update_bits(rt1320->regmap, 0xe803, 0x0c, 0x0c); 1550 1551 /* RAE update */ 1552 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x00); 1553 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x80); 1554 1555 /* RAE run */ 1556 regmap_update_bits(rt1320->regmap, 0xe803, 0x80, 0x80); 1557 1558 regmap_read(rt1320->regmap, 0xe80b, &value); 1559 dev_dbg(dev, "%s: CAE run => 0xe80b reg = 0x%x\n", __func__, value); 1560 1561 rt1320->rae_update_done = true; 1562 1563 _exit_: 1564 regmap_write(rt1320->regmap, 1565 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1566 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1567 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1568 1569 return ret; 1570 } 1571 1572 static void rt1320_dspfw_load_code(struct rt1320_sdw_priv *rt1320) 1573 { 1574 struct rt1320_imageinfo { 1575 unsigned int addr; 1576 unsigned int size; 1577 }; 1578 1579 struct rt1320_dspfwheader { 1580 unsigned int sync; 1581 short num; 1582 short crc; 1583 }; 1584 1585 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 1586 struct device *dev = &rt1320->sdw_slave->dev; 1587 unsigned int val, i, fw_offset, fw_ready; 1588 unsigned int fw_status_addr; 1589 struct rt1320_dspfwheader *fwheader; 1590 struct rt1320_imageinfo *ptr_img; 1591 struct sdw_bpt_section sec[10]; 1592 const struct firmware *fw = NULL; 1593 unsigned char *fw_data; 1594 bool dev_fw_match = false; 1595 static const char hdr_sig[] = "AFX"; 1596 unsigned int hdr_size = 0; 1597 const char *dmi_vendor, *dmi_product, *dmi_sku; 1598 char vendor[128], product[128], sku[128]; 1599 char *ptr_vendor, *ptr_product, *ptr_sku; 1600 char filename[512]; 1601 1602 switch (rt1320->dev_id) { 1603 case RT1320_DEV_ID: 1604 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 1605 break; 1606 case RT1321_DEV_ID: 1607 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 1608 break; 1609 default: 1610 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1611 return; 1612 } 1613 1614 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1615 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 1616 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 1617 1618 if (dmi_vendor && dmi_product && dmi_sku) { 1619 strscpy(vendor, dmi_vendor); 1620 strscpy(product, dmi_product); 1621 strscpy(sku, dmi_sku); 1622 ptr_vendor = &vendor[0]; 1623 ptr_product = &product[0]; 1624 ptr_sku = &sku[0]; 1625 ptr_vendor = strsep(&ptr_vendor, " "); 1626 ptr_product = strsep(&ptr_product, " "); 1627 ptr_sku = strsep(&ptr_sku, " "); 1628 1629 dev_dbg(dev, "%s: DMI vendor=%s, product=%s, sku=%s\n", __func__, 1630 vendor, product, sku); 1631 1632 snprintf(filename, sizeof(filename), 1633 "realtek/rt1320/rt1320_%s_%s_%s.dat", vendor, product, sku); 1634 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename); 1635 } else if (rt1320->dspfw_name) { 1636 snprintf(filename, sizeof(filename), "rt1320_%s.dat", 1637 rt1320->dspfw_name); 1638 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename); 1639 } else { 1640 dev_warn(dev, "%s: Can't find proper FW file name\n", __func__); 1641 return; 1642 } 1643 1644 snd_soc_dapm_mutex_lock(dapm); 1645 regmap_write(rt1320->regmap, 1646 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1647 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1648 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1649 1650 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 1651 fw_ready &= 0x1; 1652 if (fw_ready) { 1653 dev_dbg(dev, "%s, DSP FW was already\n", __func__); 1654 rt1320->fw_load_done = true; 1655 goto _exit_; 1656 } 1657 1658 /* change to IRAM */ 1659 regmap_update_bits(rt1320->regmap, 0xf01e, 0x80, 0x00); 1660 1661 request_firmware(&fw, filename, dev); 1662 if (fw) { 1663 fwheader = (struct rt1320_dspfwheader *)fw->data; 1664 dev_dbg(dev, "%s, fw sync = 0x%x, num=%d, crc=0x%x\n", __func__, 1665 fwheader->sync, fwheader->num, fwheader->crc); 1666 1667 if (fwheader->sync != 0x0a1c5679) { 1668 dev_err(dev, "%s: FW sync error\n", __func__); 1669 release_firmware(fw); 1670 goto _exit_; 1671 } 1672 1673 fw_offset = sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * fwheader->num); 1674 dev_dbg(dev, "%s, fw_offset = 0x%x\n", __func__, fw_offset); 1675 1676 regcache_cache_bypass(rt1320->regmap, true); 1677 1678 for (i = 0; i < fwheader->num; i++) { 1679 ptr_img = (struct rt1320_imageinfo *)&fw->data[sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * i)]; 1680 1681 dev_dbg(dev, "%s, fw_offset=0x%x, load fw addr=0x%x, size=%d\n", __func__, 1682 fw_offset, ptr_img->addr, ptr_img->size); 1683 1684 fw_data = (unsigned char *)&fw->data[fw_offset]; 1685 1686 /* The binary file has a header of 64 bytes */ 1687 if (memcmp(fw_data, hdr_sig, sizeof(hdr_sig)) == 0) 1688 hdr_size = 64; 1689 else 1690 hdr_size = 0; 1691 1692 sec[i].addr = ptr_img->addr; 1693 sec[i].len = ptr_img->size - hdr_size; 1694 sec[i].buf = fw_data + hdr_size; 1695 1696 dev_dbg(dev, "%s, hdr_size=%d, sec[%d].buf[0]=0x%x\n", 1697 __func__, hdr_size, i, sec[i].buf[0]); 1698 1699 switch (rt1320->dev_id) { 1700 case RT1320_DEV_ID: 1701 if (ptr_img->addr == 0x3fc29d80) 1702 if (fw_data[9] == '0') 1703 dev_fw_match = true; 1704 break; 1705 case RT1321_DEV_ID: 1706 if (ptr_img->addr == 0x3fc00000) 1707 if (fw_data[9] == '1') 1708 dev_fw_match = true; 1709 break; 1710 default: 1711 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1712 goto _exit_; 1713 } 1714 1715 fw_offset += ptr_img->size; 1716 } 1717 1718 if (dev_fw_match) { 1719 dev_dbg(dev, "%s, starting BRA downloading FW..\n", __func__); 1720 rt1320->bra_msg.dev_num = rt1320->sdw_slave->dev_num; 1721 rt1320->bra_msg.flags = SDW_MSG_FLAG_WRITE; 1722 rt1320->bra_msg.sections = fwheader->num; 1723 rt1320->bra_msg.sec = &sec[0]; 1724 rt1320_data_rw(rt1320, 0, NULL, 0, RT1320_BRA_WRITE); 1725 dev_dbg(dev, "%s, BRA downloading FW done..\n", __func__); 1726 } 1727 1728 regcache_cache_bypass(rt1320->regmap, false); 1729 release_firmware(fw); 1730 1731 if (!dev_fw_match) { 1732 dev_err(dev, "%s: FW file doesn't match to device\n", __func__); 1733 goto _exit_; 1734 } 1735 } else { 1736 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, filename); 1737 goto _exit_; 1738 } 1739 1740 /* run RAM code */ 1741 regmap_read(rt1320->regmap, 0x3fc2bfc0, &val); 1742 val |= 0x8; 1743 regmap_write(rt1320->regmap, 0x3fc2bfc0, val); 1744 1745 /* clear frame counter */ 1746 switch (rt1320->dev_id) { 1747 case RT1320_DEV_ID: 1748 regmap_write(rt1320->regmap, 0x3fc2bfcb, 0x00); 1749 regmap_write(rt1320->regmap, 0x3fc2bfca, 0x00); 1750 regmap_write(rt1320->regmap, 0x3fc2bfc9, 0x00); 1751 regmap_write(rt1320->regmap, 0x3fc2bfc8, 0x00); 1752 break; 1753 case RT1321_DEV_ID: 1754 regmap_write(rt1320->regmap, 0x3fc2dfcb, 0x00); 1755 regmap_write(rt1320->regmap, 0x3fc2dfca, 0x00); 1756 regmap_write(rt1320->regmap, 0x3fc2dfc9, 0x00); 1757 regmap_write(rt1320->regmap, 0x3fc2dfc8, 0x00); 1758 break; 1759 } 1760 1761 /* enable DSP FW */ 1762 regmap_write(rt1320->regmap, 0xc081, 0xfc); 1763 regmap_update_bits(rt1320->regmap, 0xf01e, 0x1, 0x0); 1764 1765 /* RsRatio should restore into DSP FW when FW was ready */ 1766 rt1320_invrs_load(rt1320); 1767 1768 /* DSP clock switches to PLL */ 1769 regmap_write(rt1320->regmap, 0xc081, 0xfc); 1770 /* pass DSP settings */ 1771 regmap_write(rt1320->regmap, 0xc5c3, 0xf3); 1772 regmap_write(rt1320->regmap, 0xc5c8, 0x05); 1773 1774 rt1320->fw_load_done = true; 1775 1776 pm_runtime_set_autosuspend_delay(dev, 3000); 1777 pm_runtime_mark_last_busy(dev); 1778 1779 _exit_: 1780 regmap_write(rt1320->regmap, 1781 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1782 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1783 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1784 1785 snd_soc_dapm_mutex_unlock(dapm); 1786 } 1787 1788 static void rt1320_load_dspfw_work(struct work_struct *work) 1789 { 1790 struct rt1320_sdw_priv *rt1320 = 1791 container_of(work, struct rt1320_sdw_priv, load_dspfw_work); 1792 int ret; 1793 1794 ret = pm_runtime_resume(rt1320->component->dev); 1795 if (ret < 0 && ret != -EACCES) 1796 return; 1797 1798 dev_dbg(&rt1320->sdw_slave->dev, "%s, Starting to reload DSP FW", __func__); 1799 rt1320_dspfw_load_code(rt1320); 1800 } 1801 1802 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 1803 { 1804 struct sdw_slave *slave = rt1320->sdw_slave; 1805 unsigned int i, reg, val, delay, retry, tmp; 1806 1807 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 1808 reg = rt1320_vc_blind_write[i].reg; 1809 val = rt1320_vc_blind_write[i].def; 1810 delay = rt1320_vc_blind_write[i].delay_us; 1811 1812 if (reg == 0x3fc2bf83) 1813 rt1320_load_mcu_patch(rt1320); 1814 1815 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 1816 (val == 0x00)) { 1817 retry = 200; 1818 while (retry) { 1819 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 1820 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 1821 if (tmp == 0x1f) 1822 break; 1823 usleep_range(1000, 1500); 1824 retry--; 1825 } 1826 if (!retry) 1827 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 1828 } 1829 regmap_write(rt1320->regmap, reg, val); 1830 if (delay) 1831 usleep_range(delay, delay + 1000); 1832 1833 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 1834 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 1835 } 1836 } 1837 1838 static void rt1321_preset(struct rt1320_sdw_priv *rt1320) 1839 { 1840 unsigned int i, reg, val, delay; 1841 1842 for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) { 1843 reg = rt1321_blind_write[i].reg; 1844 val = rt1321_blind_write[i].def; 1845 delay = rt1321_blind_write[i].delay_us; 1846 1847 if (reg == 0x3fc2dfc3) 1848 rt1320_load_mcu_patch(rt1320); 1849 1850 regmap_write(rt1320->regmap, reg, val); 1851 1852 if (delay) 1853 usleep_range(delay, delay + 1000); 1854 1855 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 1856 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 1857 } 1858 } 1859 1860 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 1861 { 1862 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1863 unsigned int amp_func_status, val, tmp; 1864 1865 if (rt1320->hw_init) 1866 return 0; 1867 1868 regcache_cache_only(rt1320->regmap, false); 1869 regcache_cache_only(rt1320->mbq_regmap, false); 1870 if (rt1320->first_hw_init) { 1871 regcache_cache_bypass(rt1320->regmap, true); 1872 regcache_cache_bypass(rt1320->mbq_regmap, true); 1873 } else { 1874 /* 1875 * PM runtime status is marked as 'active' only when a Slave reports as Attached 1876 */ 1877 /* update count of parent 'active' children */ 1878 pm_runtime_set_active(&slave->dev); 1879 } 1880 1881 pm_runtime_get_noresume(&slave->dev); 1882 1883 if (rt1320->version_id < 0) { 1884 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 1885 rt1320->version_id = val; 1886 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val); 1887 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp); 1888 rt1320->dev_id = (val << 8) | tmp; 1889 } 1890 1891 regmap_read(rt1320->regmap, 1892 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 1893 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 1894 1895 /* initialization write */ 1896 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 1897 switch (rt1320->dev_id) { 1898 case RT1320_DEV_ID: 1899 if (rt1320->version_id < RT1320_VC) 1900 rt1320_vab_preset(rt1320); 1901 else 1902 rt1320_vc_preset(rt1320); 1903 break; 1904 case RT1321_DEV_ID: 1905 rt1321_preset(rt1320); 1906 break; 1907 default: 1908 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1909 } 1910 1911 regmap_write(rt1320->regmap, 1912 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 1913 FUNCTION_NEEDS_INITIALIZATION); 1914 1915 /* reload DSP FW */ 1916 if (rt1320->fw_load_done) 1917 schedule_work(&rt1320->load_dspfw_work); 1918 } 1919 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) { 1920 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1921 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 1922 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 1923 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 1924 val = (tmp << 8) | val; 1925 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 1926 val = (tmp << 16) | val; 1927 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 1928 val = (tmp << 24) | val; 1929 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 1930 /* 1931 * We call the version b which has the new DSP ROM code against version a. 1932 * Therefore, we read the DSP address to check the ID. 1933 */ 1934 if (val == RT1320_VER_B_ID) 1935 rt1320->version_id = RT1320_VB; 1936 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1937 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 1938 } 1939 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id); 1940 1941 if (rt1320->first_hw_init) { 1942 regcache_cache_bypass(rt1320->regmap, false); 1943 regcache_cache_bypass(rt1320->mbq_regmap, false); 1944 regcache_mark_dirty(rt1320->regmap); 1945 regcache_mark_dirty(rt1320->mbq_regmap); 1946 } 1947 1948 /* Mark Slave initialization complete */ 1949 rt1320->first_hw_init = true; 1950 rt1320->hw_init = true; 1951 1952 pm_runtime_put_autosuspend(&slave->dev); 1953 1954 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1955 return 0; 1956 } 1957 1958 static int rt1320_update_status(struct sdw_slave *slave, 1959 enum sdw_slave_status status) 1960 { 1961 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 1962 1963 if (status == SDW_SLAVE_UNATTACHED) 1964 rt1320->hw_init = false; 1965 1966 /* 1967 * Perform initialization only if slave status is present and 1968 * hw_init flag is false 1969 */ 1970 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 1971 return 0; 1972 1973 /* perform I/O transfers required for Slave initialization */ 1974 return rt1320_io_init(&slave->dev, slave); 1975 } 1976 1977 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 1978 struct snd_kcontrol *kcontrol, int event) 1979 { 1980 struct snd_soc_component *component = 1981 snd_soc_dapm_to_component(w->dapm); 1982 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1983 unsigned char ps0 = 0x0, ps3 = 0x3; 1984 1985 switch (event) { 1986 case SND_SOC_DAPM_POST_PMU: 1987 regmap_write(rt1320->regmap, 1988 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 1989 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1990 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 1991 break; 1992 case SND_SOC_DAPM_PRE_PMD: 1993 regmap_write(rt1320->regmap, 1994 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 1995 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1996 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 1997 break; 1998 default: 1999 break; 2000 } 2001 2002 return 0; 2003 } 2004 2005 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 2006 struct snd_kcontrol *kcontrol, int event) 2007 { 2008 struct snd_soc_component *component = 2009 snd_soc_dapm_to_component(w->dapm); 2010 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2011 unsigned char ps0 = 0x0, ps3 = 0x3; 2012 2013 switch (event) { 2014 case SND_SOC_DAPM_POST_PMU: 2015 regmap_write(rt1320->regmap, 2016 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2017 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 2018 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 2019 break; 2020 case SND_SOC_DAPM_PRE_PMD: 2021 regmap_write(rt1320->regmap, 2022 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2023 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 2024 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 2025 break; 2026 default: 2027 break; 2028 } 2029 2030 return 0; 2031 } 2032 2033 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 2034 struct snd_ctl_elem_value *ucontrol) 2035 { 2036 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2037 struct soc_mixer_control *mc = 2038 (struct soc_mixer_control *)kcontrol->private_value; 2039 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2040 unsigned int gain_l_val, gain_r_val; 2041 unsigned int lvalue, rvalue; 2042 const unsigned int interval_offset = 0xc0; 2043 unsigned int changed = 0, reg_base; 2044 struct rt_sdca_dmic_kctrl_priv *p; 2045 unsigned int regvalue[4], gain_val[4], i; 2046 int err; 2047 2048 if (strstr(ucontrol->id.name, "FU Capture Volume")) 2049 goto _dmic_vol_; 2050 2051 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 2052 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 2053 2054 /* L Channel */ 2055 gain_l_val = ucontrol->value.integer.value[0]; 2056 if (gain_l_val > mc->max) 2057 gain_l_val = mc->max; 2058 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 2059 gain_l_val &= 0xffff; 2060 2061 /* R Channel */ 2062 gain_r_val = ucontrol->value.integer.value[1]; 2063 if (gain_r_val > mc->max) 2064 gain_r_val = mc->max; 2065 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 2066 gain_r_val &= 0xffff; 2067 2068 if (lvalue == gain_l_val && rvalue == gain_r_val) 2069 return 0; 2070 2071 /* Lch*/ 2072 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 2073 /* Rch */ 2074 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 2075 goto _done_; 2076 2077 _dmic_vol_: 2078 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2079 2080 /* check all channels */ 2081 for (i = 0; i < p->count; i++) { 2082 switch (rt1320->dev_id) { 2083 case RT1320_DEV_ID: 2084 if (i < 2) { 2085 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2086 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 2087 } else { 2088 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2089 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 2090 } 2091 break; 2092 case RT1321_DEV_ID: 2093 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2094 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 2095 break; 2096 } 2097 2098 gain_val[i] = ucontrol->value.integer.value[i]; 2099 if (gain_val[i] > p->max) 2100 gain_val[i] = p->max; 2101 2102 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 2103 gain_val[i] &= 0xffff; 2104 if (regvalue[i] != gain_val[i]) 2105 changed = 1; 2106 } 2107 2108 if (!changed) 2109 return 0; 2110 2111 for (i = 0; i < p->count; i++) { 2112 switch (rt1320->dev_id) { 2113 case RT1320_DEV_ID: 2114 if (i < 2) { 2115 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2116 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 2117 } else { 2118 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2119 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 2120 } 2121 break; 2122 case RT1321_DEV_ID: 2123 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2124 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 2125 break; 2126 } 2127 2128 if (err < 0) 2129 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 2130 } 2131 2132 _done_: 2133 return 1; 2134 } 2135 2136 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 2137 struct snd_ctl_elem_value *ucontrol) 2138 { 2139 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2140 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2141 struct soc_mixer_control *mc = 2142 (struct soc_mixer_control *)kcontrol->private_value; 2143 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 2144 const unsigned int interval_offset = 0xc0; 2145 unsigned int reg_base, regvalue, ctl, i; 2146 struct rt_sdca_dmic_kctrl_priv *p; 2147 2148 if (strstr(ucontrol->id.name, "FU Capture Volume")) 2149 goto _dmic_vol_; 2150 2151 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 2152 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 2153 2154 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 2155 2156 if (read_l != read_r) 2157 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 2158 else 2159 ctl_r = ctl_l; 2160 2161 ucontrol->value.integer.value[0] = ctl_l; 2162 ucontrol->value.integer.value[1] = ctl_r; 2163 goto _done_; 2164 2165 _dmic_vol_: 2166 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2167 2168 /* check all channels */ 2169 for (i = 0; i < p->count; i++) { 2170 switch (rt1320->dev_id) { 2171 case RT1320_DEV_ID: 2172 if (i < 2) { 2173 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2174 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 2175 } else { 2176 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2177 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 2178 } 2179 break; 2180 case RT1321_DEV_ID: 2181 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2182 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 2183 break; 2184 } 2185 2186 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 2187 ucontrol->value.integer.value[i] = ctl; 2188 } 2189 _done_: 2190 return 0; 2191 } 2192 2193 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 2194 { 2195 int err, i; 2196 unsigned int ch_mute; 2197 2198 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 2199 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 2200 2201 switch (rt1320->dev_id) { 2202 case RT1320_DEV_ID: 2203 if (i < 2) 2204 err = regmap_write(rt1320->regmap, 2205 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 2206 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 2207 else 2208 err = regmap_write(rt1320->regmap, 2209 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 2210 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 2211 break; 2212 case RT1321_DEV_ID: 2213 err = regmap_write(rt1320->regmap, 2214 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 2215 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 2216 break; 2217 default: 2218 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2219 return -EINVAL; 2220 } 2221 if (err < 0) 2222 return err; 2223 } 2224 2225 return 0; 2226 } 2227 2228 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 2229 struct snd_ctl_elem_value *ucontrol) 2230 { 2231 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2232 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2233 struct rt_sdca_dmic_kctrl_priv *p = 2234 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2235 unsigned int i; 2236 2237 for (i = 0; i < p->count; i++) 2238 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 2239 2240 return 0; 2241 } 2242 2243 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 2244 struct snd_ctl_elem_value *ucontrol) 2245 { 2246 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2247 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2248 struct rt_sdca_dmic_kctrl_priv *p = 2249 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2250 int err, changed = 0, i; 2251 2252 for (i = 0; i < p->count; i++) { 2253 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 2254 changed = 1; 2255 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 2256 } 2257 2258 err = rt1320_set_fu_capture_ctl(rt1320); 2259 if (err < 0) 2260 return err; 2261 2262 return changed; 2263 } 2264 2265 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 2266 struct snd_ctl_elem_info *uinfo) 2267 { 2268 struct rt_sdca_dmic_kctrl_priv *p = 2269 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2270 2271 if (p->max == 1) 2272 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2273 else 2274 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2275 uinfo->count = p->count; 2276 uinfo->value.integer.min = 0; 2277 uinfo->value.integer.max = p->max; 2278 return 0; 2279 } 2280 2281 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 2282 struct snd_kcontrol *kcontrol, int event) 2283 { 2284 struct snd_soc_component *component = 2285 snd_soc_dapm_to_component(w->dapm); 2286 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2287 2288 switch (event) { 2289 case SND_SOC_DAPM_POST_PMU: 2290 rt1320->fu_dapm_mute = false; 2291 rt1320_set_fu_capture_ctl(rt1320); 2292 break; 2293 case SND_SOC_DAPM_PRE_PMD: 2294 rt1320->fu_dapm_mute = true; 2295 rt1320_set_fu_capture_ctl(rt1320); 2296 break; 2297 } 2298 return 0; 2299 } 2300 2301 static const char * const rt1320_rx_data_ch_select[] = { 2302 "L,R", 2303 "R,L", 2304 "L,L", 2305 "R,R", 2306 "L,L+R", 2307 "R,L+R", 2308 "L+R,L", 2309 "L+R,R", 2310 "L+R,L+R", 2311 }; 2312 2313 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 2314 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 2315 rt1320_rx_data_ch_select); 2316 2317 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 2318 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 2319 2320 static int rt1320_r0_load(struct rt1320_sdw_priv *rt1320) 2321 { 2322 struct device *dev = regmap_get_device(rt1320->regmap); 2323 unsigned int fw_status_addr; 2324 unsigned int fw_ready; 2325 int ret = 0; 2326 2327 if (!rt1320->r0_l_reg || !rt1320->r0_r_reg) 2328 return -EINVAL; 2329 2330 switch (rt1320->dev_id) { 2331 case RT1320_DEV_ID: 2332 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 2333 break; 2334 case RT1321_DEV_ID: 2335 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 2336 break; 2337 default: 2338 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2339 return -EINVAL; 2340 } 2341 2342 regmap_write(rt1320->regmap, 2343 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 2344 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 2345 if (ret < 0) { 2346 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__); 2347 goto _timeout_; 2348 } 2349 2350 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 2351 fw_ready &= 0x1; 2352 if (!fw_ready) { 2353 dev_dbg(dev, "%s, DSP FW is NOT ready\n", __func__); 2354 goto _timeout_; 2355 } 2356 2357 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE); 2358 if (ret < 0) { 2359 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__); 2360 goto _timeout_; 2361 } 2362 2363 rt1320_set_advancemode(rt1320); 2364 2365 _timeout_: 2366 regmap_write(rt1320->regmap, 2367 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 2368 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 2369 2370 return ret; 2371 } 2372 2373 static int rt1320_r0_load_mode_get(struct snd_kcontrol *kcontrol, 2374 struct snd_ctl_elem_value *ucontrol) 2375 { 2376 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2377 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2378 2379 ucontrol->value.integer.value[0] = rt1320->r0_l_reg; 2380 ucontrol->value.integer.value[1] = rt1320->r0_r_reg; 2381 2382 return 0; 2383 } 2384 2385 static int rt1320_r0_load_mode_put(struct snd_kcontrol *kcontrol, 2386 struct snd_ctl_elem_value *ucontrol) 2387 { 2388 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2389 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2390 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 2391 int ret; 2392 2393 if (!rt1320->hw_init) 2394 return 0; 2395 2396 if (ucontrol->value.integer.value[0] == 0 || 2397 ucontrol->value.integer.value[1] == 0) 2398 return -EINVAL; 2399 2400 ret = pm_runtime_resume(component->dev); 2401 if (ret < 0 && ret != -EACCES) 2402 return ret; 2403 2404 snd_soc_dapm_mutex_lock(dapm); 2405 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 2406 rt1320->r0_l_reg = ucontrol->value.integer.value[0]; 2407 rt1320->r0_r_reg = ucontrol->value.integer.value[1]; 2408 rt1320_calc_r0(rt1320); 2409 rt1320_r0_load(rt1320); 2410 } 2411 snd_soc_dapm_mutex_unlock(dapm); 2412 2413 return 0; 2414 } 2415 2416 static int rt1320_t0_r0_load_info(struct snd_kcontrol *kcontrol, 2417 struct snd_ctl_elem_info *uinfo) 2418 { 2419 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2420 uinfo->count = 2; 2421 uinfo->value.integer.max = kcontrol->private_value; 2422 2423 return 0; 2424 } 2425 2426 #define RT1320_T0_R0_LOAD(xname, xmax, xhandler_get, xhandler_put) \ 2427 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2428 .info = rt1320_t0_r0_load_info, \ 2429 .get = xhandler_get, \ 2430 .put = xhandler_put, \ 2431 .private_value = xmax, \ 2432 } 2433 2434 static int rt1320_dspfw_load_get(struct snd_kcontrol *kcontrol, 2435 struct snd_ctl_elem_value *ucontrol) 2436 { 2437 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2438 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2439 2440 ucontrol->value.integer.value[0] = rt1320->fw_load_done; 2441 return 0; 2442 } 2443 2444 static int rt1320_dspfw_load_put(struct snd_kcontrol *kcontrol, 2445 struct snd_ctl_elem_value *ucontrol) 2446 { 2447 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2448 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2449 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2450 int ret; 2451 2452 if (!rt1320->hw_init) 2453 return 0; 2454 2455 ret = pm_runtime_resume(component->dev); 2456 if (ret < 0 && ret != -EACCES) 2457 return ret; 2458 2459 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF && 2460 ucontrol->value.integer.value[0]) 2461 rt1320_dspfw_load_code(rt1320); 2462 2463 if (!ucontrol->value.integer.value[0]) 2464 rt1320->fw_load_done = false; 2465 2466 return 0; 2467 } 2468 2469 static int rt1320_rae_update_get(struct snd_kcontrol *kcontrol, 2470 struct snd_ctl_elem_value *ucontrol) 2471 { 2472 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2473 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2474 2475 ucontrol->value.integer.value[0] = rt1320->rae_update_done; 2476 return 0; 2477 } 2478 2479 static int rt1320_rae_update_put(struct snd_kcontrol *kcontrol, 2480 struct snd_ctl_elem_value *ucontrol) 2481 { 2482 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2483 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2484 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2485 int ret; 2486 2487 if (!rt1320->hw_init) 2488 return 0; 2489 2490 ret = pm_runtime_resume(component->dev); 2491 if (ret < 0 && ret != -EACCES) 2492 return ret; 2493 2494 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF && 2495 ucontrol->value.integer.value[0] && rt1320->fw_load_done) 2496 rt1320_rae_load(rt1320); 2497 2498 if (!ucontrol->value.integer.value[0]) 2499 rt1320->rae_update_done = false; 2500 2501 return 0; 2502 } 2503 2504 static int rt1320_r0_temperature_get(struct snd_kcontrol *kcontrol, 2505 struct snd_ctl_elem_value *ucontrol) 2506 { 2507 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2508 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2509 2510 ucontrol->value.integer.value[0] = rt1320->temp_l_calib; 2511 ucontrol->value.integer.value[1] = rt1320->temp_r_calib; 2512 return 0; 2513 } 2514 2515 static int rt1320_r0_temperature_put(struct snd_kcontrol *kcontrol, 2516 struct snd_ctl_elem_value *ucontrol) 2517 { 2518 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2519 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2520 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 2521 int ret; 2522 2523 if (!rt1320->hw_init) 2524 return 0; 2525 2526 ret = pm_runtime_resume(component->dev); 2527 if (ret < 0 && ret != -EACCES) 2528 return ret; 2529 2530 snd_soc_dapm_mutex_lock(dapm); 2531 if ((snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) && 2532 ucontrol->value.integer.value[0] && ucontrol->value.integer.value[1]) 2533 rt1320_t0_load(rt1320, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1]); 2534 snd_soc_dapm_mutex_unlock(dapm); 2535 2536 return 0; 2537 } 2538 2539 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 2540 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 2541 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 2542 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 2543 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 2544 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 2545 2546 RT_SDCA_FU_CTRL("FU Capture Switch", 2547 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 2548 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 2549 RT_SDCA_EXT_TLV("FU Capture Volume", 2550 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 2551 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 2552 2553 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0, 2554 rt1320_r0_cali_get, rt1320_r0_cali_put), 2555 SOC_SINGLE_EXT("DSP FW Update", SND_SOC_NOPM, 0, 1, 0, 2556 rt1320_dspfw_load_get, rt1320_dspfw_load_put), 2557 RT1320_T0_R0_LOAD("R0 Load Mode", 0xffffffff, 2558 rt1320_r0_load_mode_get, rt1320_r0_load_mode_put), 2559 RT1320_T0_R0_LOAD("R0 Temperature", 0xff, 2560 rt1320_r0_temperature_get, rt1320_r0_temperature_put), 2561 SOC_SINGLE_EXT("RAE Update", SND_SOC_NOPM, 0, 1, 0, 2562 rt1320_rae_update_get, rt1320_rae_update_put), 2563 }; 2564 2565 static const struct snd_kcontrol_new rt1320_spk_l_dac = 2566 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 2567 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 2568 0, 1, 1); 2569 static const struct snd_kcontrol_new rt1320_spk_r_dac = 2570 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 2571 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 2572 0, 1, 1); 2573 2574 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 2575 /* Audio Interface */ 2576 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 2577 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 2578 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 2579 2580 /* Digital Interface */ 2581 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 2582 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 2583 rt1320_pde23_event, 2584 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2585 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 2586 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2587 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 2588 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 2589 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 2590 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2591 2592 /* Output */ 2593 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 2594 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 2595 SND_SOC_DAPM_OUTPUT("SPOL"), 2596 SND_SOC_DAPM_OUTPUT("SPOR"), 2597 2598 /* Input */ 2599 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 2600 SND_SOC_DAPM_SIGGEN("AEC Gen"), 2601 SND_SOC_DAPM_INPUT("DMIC1"), 2602 SND_SOC_DAPM_INPUT("DMIC2"), 2603 }; 2604 2605 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 2606 { "FU21", NULL, "DP1RX" }, 2607 { "FU21", NULL, "PDE 23" }, 2608 { "OT23 L", "Switch", "FU21" }, 2609 { "OT23 R", "Switch", "FU21" }, 2610 { "SPOL", NULL, "OT23 L" }, 2611 { "SPOR", NULL, "OT23 R" }, 2612 2613 { "AEC Data", NULL, "AEC Gen" }, 2614 { "DP4TX", NULL, "AEC Data" }, 2615 2616 {"DP8-10TX", NULL, "FU"}, 2617 {"FU", NULL, "PDE 11"}, 2618 {"FU", NULL, "FU 113"}, 2619 {"FU", NULL, "FU 14"}, 2620 {"FU 113", NULL, "DMIC1"}, 2621 {"FU 14", NULL, "DMIC2"}, 2622 }; 2623 2624 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 2625 int direction) 2626 { 2627 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 2628 return 0; 2629 } 2630 2631 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 2632 struct snd_soc_dai *dai) 2633 { 2634 snd_soc_dai_set_dma_data(dai, substream, NULL); 2635 } 2636 2637 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 2638 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2639 { 2640 struct snd_soc_component *component = dai->component; 2641 struct rt1320_sdw_priv *rt1320 = 2642 snd_soc_component_get_drvdata(component); 2643 struct sdw_stream_config stream_config; 2644 struct sdw_port_config port_config; 2645 struct sdw_port_config dmic_port_config[2]; 2646 struct sdw_stream_runtime *sdw_stream; 2647 int retval; 2648 unsigned int sampling_rate; 2649 2650 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 2651 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 2652 2653 if (!sdw_stream) 2654 return -EINVAL; 2655 2656 if (!rt1320->sdw_slave) 2657 return -EINVAL; 2658 2659 /* SoundWire specific configuration */ 2660 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 2661 2662 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2663 if (dai->id == RT1320_AIF1) 2664 port_config.num = 1; 2665 else 2666 return -EINVAL; 2667 } else { 2668 if (dai->id == RT1320_AIF1) 2669 port_config.num = 4; 2670 else if (dai->id == RT1320_AIF2) { 2671 switch (rt1320->dev_id) { 2672 case RT1320_DEV_ID: 2673 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 2674 dmic_port_config[0].num = 8; 2675 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 2676 dmic_port_config[1].num = 10; 2677 break; 2678 case RT1321_DEV_ID: 2679 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 2680 dmic_port_config[0].num = 8; 2681 break; 2682 default: 2683 return -EINVAL; 2684 } 2685 } else 2686 return -EINVAL; 2687 } 2688 2689 if (dai->id == RT1320_AIF1) 2690 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 2691 &port_config, 1, sdw_stream); 2692 else if (dai->id == RT1320_AIF2) { 2693 switch (rt1320->dev_id) { 2694 case RT1320_DEV_ID: 2695 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 2696 dmic_port_config, 2, sdw_stream); 2697 break; 2698 case RT1321_DEV_ID: 2699 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 2700 dmic_port_config, 1, sdw_stream); 2701 break; 2702 default: 2703 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2704 return -EINVAL; 2705 } 2706 } else 2707 return -EINVAL; 2708 if (retval) { 2709 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 2710 return retval; 2711 } 2712 2713 /* sampling rate configuration */ 2714 switch (params_rate(params)) { 2715 case 16000: 2716 sampling_rate = RT1320_SDCA_RATE_16000HZ; 2717 break; 2718 case 32000: 2719 sampling_rate = RT1320_SDCA_RATE_32000HZ; 2720 break; 2721 case 44100: 2722 sampling_rate = RT1320_SDCA_RATE_44100HZ; 2723 break; 2724 case 48000: 2725 sampling_rate = RT1320_SDCA_RATE_48000HZ; 2726 break; 2727 case 96000: 2728 sampling_rate = RT1320_SDCA_RATE_96000HZ; 2729 break; 2730 case 192000: 2731 sampling_rate = RT1320_SDCA_RATE_192000HZ; 2732 break; 2733 default: 2734 dev_err(component->dev, "%s: Rate %d is not supported\n", 2735 __func__, params_rate(params)); 2736 return -EINVAL; 2737 } 2738 2739 /* set sampling frequency */ 2740 if (dai->id == RT1320_AIF1) 2741 regmap_write(rt1320->regmap, 2742 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 2743 sampling_rate); 2744 else { 2745 regmap_write(rt1320->regmap, 2746 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 2747 sampling_rate); 2748 2749 if (rt1320->dev_id == RT1320_DEV_ID) 2750 regmap_write(rt1320->regmap, 2751 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 2752 sampling_rate); 2753 } 2754 2755 return 0; 2756 } 2757 2758 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 2759 struct snd_soc_dai *dai) 2760 { 2761 struct snd_soc_component *component = dai->component; 2762 struct rt1320_sdw_priv *rt1320 = 2763 snd_soc_component_get_drvdata(component); 2764 struct sdw_stream_runtime *sdw_stream = 2765 snd_soc_dai_get_dma_data(dai, substream); 2766 2767 if (!rt1320->sdw_slave) 2768 return -EINVAL; 2769 2770 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 2771 return 0; 2772 } 2773 2774 /* 2775 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 2776 * port_prep are not defined for now 2777 */ 2778 static const struct sdw_slave_ops rt1320_slave_ops = { 2779 .read_prop = rt1320_read_prop, 2780 .update_status = rt1320_update_status, 2781 }; 2782 2783 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 2784 { 2785 int ret; 2786 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2787 2788 rt1320->component = component; 2789 2790 if (!rt1320->first_hw_init) 2791 return 0; 2792 2793 ret = pm_runtime_resume(component->dev); 2794 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 2795 if (ret < 0 && ret != -EACCES) 2796 return ret; 2797 2798 /* Apply temperature and calibration data from device property */ 2799 if ((rt1320->temp_l_calib <= 0xff) && (rt1320->temp_l_calib > 0) && 2800 (rt1320->temp_r_calib <= 0xff) && (rt1320->temp_r_calib > 0)) 2801 rt1320_t0_load(rt1320, rt1320->temp_l_calib, rt1320->temp_r_calib); 2802 2803 if (rt1320->r0_l_calib && rt1320->r0_r_calib) { 2804 rt1320->r0_l_reg = rt1320->r0_l_calib; 2805 rt1320->r0_r_reg = rt1320->r0_r_calib; 2806 rt1320_calc_r0(rt1320); 2807 rt1320_r0_load(rt1320); 2808 } 2809 2810 return 0; 2811 } 2812 2813 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 2814 .probe = rt1320_sdw_component_probe, 2815 .controls = rt1320_snd_controls, 2816 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 2817 .dapm_widgets = rt1320_dapm_widgets, 2818 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 2819 .dapm_routes = rt1320_dapm_routes, 2820 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 2821 .endianness = 1, 2822 }; 2823 2824 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 2825 .hw_params = rt1320_sdw_hw_params, 2826 .hw_free = rt1320_sdw_pcm_hw_free, 2827 .set_stream = rt1320_set_sdw_stream, 2828 .shutdown = rt1320_sdw_shutdown, 2829 }; 2830 2831 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 2832 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 2833 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 2834 SNDRV_PCM_FMTBIT_S32_LE) 2835 2836 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 2837 { 2838 .name = "rt1320-aif1", 2839 .id = RT1320_AIF1, 2840 .playback = { 2841 .stream_name = "DP1 Playback", 2842 .channels_min = 1, 2843 .channels_max = 2, 2844 .rates = RT1320_STEREO_RATES, 2845 .formats = RT1320_FORMATS, 2846 }, 2847 .capture = { 2848 .stream_name = "DP4 Capture", 2849 .channels_min = 1, 2850 .channels_max = 2, 2851 .rates = RT1320_STEREO_RATES, 2852 .formats = RT1320_FORMATS, 2853 }, 2854 .ops = &rt1320_aif_dai_ops, 2855 }, 2856 /* DMIC: DP8 2ch + DP10 2ch */ 2857 { 2858 .name = "rt1320-aif2", 2859 .id = RT1320_AIF2, 2860 .capture = { 2861 .stream_name = "DP8-10 Capture", 2862 .channels_min = 1, 2863 .channels_max = 4, 2864 .rates = RT1320_STEREO_RATES, 2865 .formats = RT1320_FORMATS, 2866 }, 2867 .ops = &rt1320_aif_dai_ops, 2868 }, 2869 }; 2870 2871 static int rt1320_parse_dp(struct rt1320_sdw_priv *rt1320, struct device *dev) 2872 { 2873 device_property_read_u32(dev, "realtek,temperature_l_calib", 2874 &rt1320->temp_l_calib); 2875 device_property_read_u32(dev, "realtek,temperature_r_calib", 2876 &rt1320->temp_r_calib); 2877 device_property_read_u32(dev, "realtek,r0_l_calib", 2878 &rt1320->r0_l_calib); 2879 device_property_read_u32(dev, "realtek,r0_r_calib", 2880 &rt1320->r0_r_calib); 2881 device_property_read_string(dev, "realtek,dspfw-name", 2882 &rt1320->dspfw_name); 2883 2884 dev_dbg(dev, "%s: temp_l_calib: %d temp_r_calib: %d r0_l_calib: %d, r0_r_calib: %d", 2885 __func__, rt1320->temp_l_calib, rt1320->temp_r_calib, rt1320->r0_l_calib, rt1320->r0_r_calib); 2886 dev_dbg(dev, "%s: dspfw_name: %s", __func__, rt1320->dspfw_name); 2887 2888 return 0; 2889 } 2890 2891 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 2892 struct regmap *mbq_regmap, struct sdw_slave *slave) 2893 { 2894 struct rt1320_sdw_priv *rt1320; 2895 int ret; 2896 2897 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 2898 if (!rt1320) 2899 return -ENOMEM; 2900 2901 dev_set_drvdata(dev, rt1320); 2902 rt1320->sdw_slave = slave; 2903 rt1320->mbq_regmap = mbq_regmap; 2904 rt1320->regmap = regmap; 2905 2906 regcache_cache_only(rt1320->regmap, true); 2907 regcache_cache_only(rt1320->mbq_regmap, true); 2908 2909 rt1320_parse_dp(rt1320, dev); 2910 2911 /* 2912 * Mark hw_init to false 2913 * HW init will be performed when device reports present 2914 */ 2915 rt1320->hw_init = false; 2916 rt1320->first_hw_init = false; 2917 rt1320->version_id = -1; 2918 rt1320->fu_dapm_mute = true; 2919 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 2920 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 2921 2922 INIT_WORK(&rt1320->load_dspfw_work, rt1320_load_dspfw_work); 2923 2924 ret = devm_snd_soc_register_component(dev, 2925 &soc_component_sdw_rt1320, 2926 rt1320_sdw_dai, 2927 ARRAY_SIZE(rt1320_sdw_dai)); 2928 if (ret < 0) 2929 return ret; 2930 2931 /* set autosuspend parameters */ 2932 pm_runtime_set_autosuspend_delay(dev, 3000); 2933 pm_runtime_use_autosuspend(dev); 2934 2935 /* make sure the device does not suspend immediately */ 2936 pm_runtime_mark_last_busy(dev); 2937 2938 pm_runtime_enable(dev); 2939 2940 /* important note: the device is NOT tagged as 'active' and will remain 2941 * 'suspended' until the hardware is enumerated/initialized. This is required 2942 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 2943 * fail with -EACCESS because of race conditions between card creation and enumeration 2944 */ 2945 2946 dev_dbg(dev, "%s\n", __func__); 2947 2948 return ret; 2949 } 2950 2951 static int rt1320_sdw_probe(struct sdw_slave *slave, 2952 const struct sdw_device_id *id) 2953 { 2954 struct regmap *regmap, *mbq_regmap; 2955 2956 /* Regmap Initialization */ 2957 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 2958 if (IS_ERR(mbq_regmap)) 2959 return PTR_ERR(mbq_regmap); 2960 2961 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 2962 if (IS_ERR(regmap)) 2963 return PTR_ERR(regmap); 2964 2965 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 2966 } 2967 2968 static int rt1320_sdw_remove(struct sdw_slave *slave) 2969 { 2970 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 2971 2972 cancel_work_sync(&rt1320->load_dspfw_work); 2973 pm_runtime_disable(&slave->dev); 2974 2975 return 0; 2976 } 2977 2978 /* 2979 * Version A/B will use the class id 0 2980 * The newer version than A/B will use the class id 1, so add it in advance 2981 */ 2982 static const struct sdw_device_id rt1320_id[] = { 2983 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 2984 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 2985 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0), 2986 {}, 2987 }; 2988 MODULE_DEVICE_TABLE(sdw, rt1320_id); 2989 2990 static int rt1320_dev_suspend(struct device *dev) 2991 { 2992 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 2993 2994 if (!rt1320->hw_init) 2995 return 0; 2996 2997 regcache_cache_only(rt1320->regmap, true); 2998 regcache_cache_only(rt1320->mbq_regmap, true); 2999 return 0; 3000 } 3001 3002 #define RT1320_PROBE_TIMEOUT 5000 3003 3004 static int rt1320_dev_resume(struct device *dev) 3005 { 3006 struct sdw_slave *slave = dev_to_sdw_dev(dev); 3007 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 3008 unsigned long time; 3009 3010 if (!rt1320->first_hw_init) 3011 return 0; 3012 3013 if (!slave->unattach_request) 3014 goto regmap_sync; 3015 3016 time = wait_for_completion_timeout(&slave->initialization_complete, 3017 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 3018 if (!time) { 3019 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 3020 return -ETIMEDOUT; 3021 } 3022 3023 regmap_sync: 3024 slave->unattach_request = 0; 3025 regcache_cache_only(rt1320->regmap, false); 3026 regcache_sync(rt1320->regmap); 3027 regcache_cache_only(rt1320->mbq_regmap, false); 3028 regcache_sync(rt1320->mbq_regmap); 3029 return 0; 3030 } 3031 3032 static const struct dev_pm_ops rt1320_pm = { 3033 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 3034 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 3035 }; 3036 3037 static struct sdw_driver rt1320_sdw_driver = { 3038 .driver = { 3039 .name = "rt1320-sdca", 3040 .pm = pm_ptr(&rt1320_pm), 3041 }, 3042 .probe = rt1320_sdw_probe, 3043 .remove = rt1320_sdw_remove, 3044 .ops = &rt1320_slave_ops, 3045 .id_table = rt1320_id, 3046 }; 3047 module_sdw_driver(rt1320_sdw_driver); 3048 3049 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 3050 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 3051 MODULE_LICENSE("GPL"); 3052