1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 #include "rt-sdw-common.h" 25 26 /* 27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 28 * It might include vendor-specific or SDCA control registers. 29 */ 30 static const struct reg_sequence rt1320_blind_write[] = { 31 { 0xc003, 0xe0 }, 32 { 0xc01b, 0xfc }, 33 { 0xc5c3, 0xf2 }, 34 { 0xc5c2, 0x00 }, 35 { 0xc5c6, 0x10 }, 36 { 0xc5c4, 0x12 }, 37 { 0xc5c8, 0x03 }, 38 { 0xc5d8, 0x0a }, 39 { 0xc5f7, 0x22 }, 40 { 0xc5f6, 0x22 }, 41 { 0xc5d0, 0x0f }, 42 { 0xc5d1, 0x89 }, 43 { 0xc057, 0x51 }, 44 { 0xc054, 0x35 }, 45 { 0xc053, 0x55 }, 46 { 0xc052, 0x55 }, 47 { 0xc051, 0x13 }, 48 { 0xc050, 0x15 }, 49 { 0xc060, 0x77 }, 50 { 0xc061, 0x55 }, 51 { 0xc063, 0x55 }, 52 { 0xc065, 0xa5 }, 53 { 0xc06b, 0x0a }, 54 { 0xca05, 0xd6 }, 55 { 0xca25, 0xd6 }, 56 { 0xcd00, 0x05 }, 57 { 0xc604, 0x40 }, 58 { 0xc609, 0x40 }, 59 { 0xc046, 0xff }, 60 { 0xc045, 0xff }, 61 { 0xc044, 0xff }, 62 { 0xc043, 0xff }, 63 { 0xc042, 0xff }, 64 { 0xc041, 0xff }, 65 { 0xc040, 0xff }, 66 { 0xcc10, 0x01 }, 67 { 0xc700, 0xf0 }, 68 { 0xc701, 0x13 }, 69 { 0xc901, 0x04 }, 70 { 0xc900, 0x73 }, 71 { 0xde03, 0x05 }, 72 { 0xdd0b, 0x0d }, 73 { 0xdd0a, 0xff }, 74 { 0xdd09, 0x0d }, 75 { 0xdd08, 0xff }, 76 { 0xc570, 0x08 }, 77 { 0xe803, 0xbe }, 78 { 0xc003, 0xc0 }, 79 { 0xc081, 0xfe }, 80 { 0xce31, 0x0d }, 81 { 0xce30, 0xae }, 82 { 0xce37, 0x0b }, 83 { 0xce36, 0xd2 }, 84 { 0xce39, 0x04 }, 85 { 0xce38, 0x80 }, 86 { 0xce3f, 0x00 }, 87 { 0xce3e, 0x00 }, 88 { 0xd470, 0x8b }, 89 { 0xd471, 0x18 }, 90 { 0xc019, 0x10 }, 91 { 0xd487, 0x3f }, 92 { 0xd486, 0xc3 }, 93 { 0x3fc2bfc7, 0x00 }, 94 { 0x3fc2bfc6, 0x00 }, 95 { 0x3fc2bfc5, 0x00 }, 96 { 0x3fc2bfc4, 0x01 }, 97 { 0x0000d486, 0x43 }, 98 { 0x1000db00, 0x02 }, 99 { 0x1000db01, 0x00 }, 100 { 0x1000db02, 0x11 }, 101 { 0x1000db03, 0x00 }, 102 { 0x1000db04, 0x00 }, 103 { 0x1000db05, 0x82 }, 104 { 0x1000db06, 0x04 }, 105 { 0x1000db07, 0xf1 }, 106 { 0x1000db08, 0x00 }, 107 { 0x1000db09, 0x00 }, 108 { 0x1000db0a, 0x40 }, 109 { 0x0000d540, 0x01 }, 110 { 0xd172, 0x2a }, 111 { 0xc5d6, 0x01 }, 112 }; 113 114 static const struct reg_sequence rt1320_vc_blind_write[] = { 115 { 0xc003, 0xe0 }, 116 { 0xe80a, 0x01 }, 117 { 0xc5c3, 0xf3 }, 118 { 0xc057, 0x51 }, 119 { 0xc054, 0x35 }, 120 { 0xca05, 0xd6 }, 121 { 0xca07, 0x07 }, 122 { 0xca25, 0xd6 }, 123 { 0xca27, 0x07 }, 124 { 0xc604, 0x40 }, 125 { 0xc609, 0x40 }, 126 { 0xc046, 0xff }, 127 { 0xc045, 0xff }, 128 { 0xda81, 0x14 }, 129 { 0xda8d, 0x14 }, 130 { 0xc044, 0xff }, 131 { 0xc043, 0xff }, 132 { 0xc042, 0xff }, 133 { 0xc041, 0x7f }, 134 { 0xc040, 0xff }, 135 { 0xcc10, 0x01 }, 136 { 0xc700, 0xf0 }, 137 { 0xc701, 0x13 }, 138 { 0xc901, 0x09 }, 139 { 0xc900, 0xd0 }, 140 { 0xde03, 0x05 }, 141 { 0xdd0b, 0x0d }, 142 { 0xdd0a, 0xff }, 143 { 0xdd09, 0x0d }, 144 { 0xdd08, 0xff }, 145 { 0xc570, 0x08 }, 146 { 0xc086, 0x02 }, 147 { 0xc085, 0x7f }, 148 { 0xc084, 0x00 }, 149 { 0xc081, 0xfe }, 150 { 0xf084, 0x0f }, 151 { 0xf083, 0xff }, 152 { 0xf082, 0xff }, 153 { 0xf081, 0xff }, 154 { 0xf080, 0xff }, 155 { 0xe802, 0xf8 }, 156 { 0xe803, 0xbe }, 157 { 0xc003, 0xc0 }, 158 { 0xd470, 0xec }, 159 { 0xd471, 0x3a }, 160 { 0xd474, 0x11 }, 161 { 0xd475, 0x32 }, 162 { 0xd478, 0x64 }, 163 { 0xd479, 0x20 }, 164 { 0xd47a, 0x10 }, 165 { 0xd47c, 0xff }, 166 { 0xc019, 0x10 }, 167 { 0xd487, 0x0b }, 168 { 0xd487, 0x3b }, 169 { 0xd486, 0xc3 }, 170 { 0xc598, 0x04 }, 171 { 0xdb03, 0xf0 }, 172 { 0xdb09, 0x00 }, 173 { 0xdb08, 0x7a }, 174 { 0xdb19, 0x02 }, 175 { 0xdb07, 0x5a }, 176 { 0xdb05, 0x45 }, 177 { 0xd500, 0x00 }, 178 { 0xd500, 0x17 }, 179 { 0xd600, 0x01 }, 180 { 0xd601, 0x02 }, 181 { 0xd602, 0x03 }, 182 { 0xd603, 0x04 }, 183 { 0xd64c, 0x03 }, 184 { 0xd64d, 0x03 }, 185 { 0xd64e, 0x03 }, 186 { 0xd64f, 0x03 }, 187 { 0xd650, 0x03 }, 188 { 0xd651, 0x03 }, 189 { 0xd652, 0x03 }, 190 { 0xd610, 0x01 }, 191 { 0xd608, 0x03 }, 192 { 0xd609, 0x00 }, 193 { 0x3fc2bf83, 0x00 }, 194 { 0x3fc2bf82, 0x00 }, 195 { 0x3fc2bf81, 0x00 }, 196 { 0x3fc2bf80, 0x00 }, 197 { 0x3fc2bfc7, 0x00 }, 198 { 0x3fc2bfc6, 0x00 }, 199 { 0x3fc2bfc5, 0x00 }, 200 { 0x3fc2bfc4, 0x00 }, 201 { 0x3fc2bfc3, 0x00 }, 202 { 0x3fc2bfc2, 0x00 }, 203 { 0x3fc2bfc1, 0x00 }, 204 { 0x3fc2bfc0, 0x03 }, 205 { 0x0000d486, 0x43 }, 206 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 207 { 0x1000db00, 0x07 }, 208 { 0x1000db01, 0x00 }, 209 { 0x1000db02, 0x11 }, 210 { 0x1000db03, 0x00 }, 211 { 0x1000db04, 0x00 }, 212 { 0x1000db05, 0x82 }, 213 { 0x1000db06, 0x04 }, 214 { 0x1000db07, 0xf1 }, 215 { 0x1000db08, 0x00 }, 216 { 0x1000db09, 0x00 }, 217 { 0x1000db0a, 0x40 }, 218 { 0x1000db0b, 0x02 }, 219 { 0x1000db0c, 0xf2 }, 220 { 0x1000db0d, 0x00 }, 221 { 0x1000db0e, 0x00 }, 222 { 0x1000db0f, 0xe0 }, 223 { 0x1000db10, 0x00 }, 224 { 0x1000db11, 0x10 }, 225 { 0x1000db12, 0x00 }, 226 { 0x1000db13, 0x00 }, 227 { 0x1000db14, 0x45 }, 228 { 0x1000db15, 0x0d }, 229 { 0x1000db16, 0x01 }, 230 { 0x1000db17, 0x00 }, 231 { 0x1000db18, 0x00 }, 232 { 0x1000db19, 0xbf }, 233 { 0x1000db1a, 0x13 }, 234 { 0x1000db1b, 0x09 }, 235 { 0x1000db1c, 0x00 }, 236 { 0x1000db1d, 0x00 }, 237 { 0x1000db1e, 0x00 }, 238 { 0x1000db1f, 0x12 }, 239 { 0x1000db20, 0x09 }, 240 { 0x1000db21, 0x00 }, 241 { 0x1000db22, 0x00 }, 242 { 0x1000db23, 0x00 }, 243 { 0x0000d540, 0x01 }, 244 { 0x0000c081, 0xfc }, 245 { 0x0000f01e, 0x80 }, 246 { 0xc01b, 0xfc }, 247 { 0xc5d1, 0x89 }, 248 { 0xc5d8, 0x0a }, 249 { 0xc5f7, 0x22 }, 250 { 0xc5f6, 0x22 }, 251 { 0xc065, 0xa5 }, 252 { 0xc06b, 0x0a }, 253 { 0xd172, 0x2a }, 254 { 0xc5d6, 0x01 }, 255 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 256 }; 257 258 static const struct reg_default rt1320_reg_defaults[] = { 259 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 260 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 261 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 262 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 263 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 264 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 265 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 266 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 267 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 268 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 269 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 270 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 271 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 272 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 273 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 274 }; 275 276 static const struct reg_default rt1320_mbq_defaults[] = { 277 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 278 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 279 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 280 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 281 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 282 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 283 }; 284 285 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 286 { 287 switch (reg) { 288 case 0xc000 ... 0xc086: 289 case 0xc400 ... 0xc409: 290 case 0xc480 ... 0xc48f: 291 case 0xc4c0 ... 0xc4c4: 292 case 0xc4e0 ... 0xc4e7: 293 case 0xc500: 294 case 0xc560 ... 0xc56b: 295 case 0xc570: 296 case 0xc580 ... 0xc59a: 297 case 0xc5b0 ... 0xc60f: 298 case 0xc640 ... 0xc64f: 299 case 0xc670: 300 case 0xc680 ... 0xc683: 301 case 0xc700 ... 0xc76f: 302 case 0xc800 ... 0xc801: 303 case 0xc820: 304 case 0xc900 ... 0xc901: 305 case 0xc920 ... 0xc921: 306 case 0xca00 ... 0xca07: 307 case 0xca20 ... 0xca27: 308 case 0xca40 ... 0xca4b: 309 case 0xca60 ... 0xca68: 310 case 0xca80 ... 0xca88: 311 case 0xcb00 ... 0xcb0c: 312 case 0xcc00 ... 0xcc12: 313 case 0xcc80 ... 0xcc81: 314 case 0xcd00: 315 case 0xcd80 ... 0xcd82: 316 case 0xce00 ... 0xce4d: 317 case 0xcf00 ... 0xcf25: 318 case 0xd000 ... 0xd0ff: 319 case 0xd100 ... 0xd1ff: 320 case 0xd200 ... 0xd2ff: 321 case 0xd300 ... 0xd3ff: 322 case 0xd400 ... 0xd403: 323 case 0xd410 ... 0xd417: 324 case 0xd470 ... 0xd497: 325 case 0xd4dc ... 0xd50f: 326 case 0xd520 ... 0xd543: 327 case 0xd560 ... 0xd5ef: 328 case 0xd600 ... 0xd663: 329 case 0xda00 ... 0xda6e: 330 case 0xda80 ... 0xda9e: 331 case 0xdb00 ... 0xdb7f: 332 case 0xdc00: 333 case 0xdc20 ... 0xdc21: 334 case 0xdd00 ... 0xdd17: 335 case 0xde00 ... 0xde09: 336 case 0xdf00 ... 0xdf1b: 337 case 0xe000 ... 0xe847: 338 case 0xf01e: 339 case 0xf717 ... 0xf719: 340 case 0xf720 ... 0xf723: 341 case 0x1000cd91 ... 0x1000cd96: 342 case 0x1000f008: 343 case 0x1000f021: 344 case 0x3fe2e000 ... 0x3fe2e003: 345 case 0x3fc2ab80 ... 0x3fc2abd4: 346 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 347 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 348 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 349 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 350 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 351 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 352 /* 0x40880900/0x40880980 */ 353 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 354 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 355 /* 0x40881500 */ 356 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 357 /* 0x41000189/0x4100018a */ 358 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 359 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 360 /* 0x41001388 */ 361 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 362 /* 0x41001988 */ 363 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 364 /* 0x41080000 */ 365 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 366 /* 0x41080200 */ 367 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 368 /* 0x41080900 */ 369 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 370 /* 0x41080980 */ 371 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 372 /* 0x41081080 */ 373 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 374 /* 0x41081480/0x41081488 */ 375 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 376 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 377 /* 0x41081980 */ 378 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 379 return true; 380 default: 381 return false; 382 } 383 } 384 385 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 386 { 387 switch (reg) { 388 case 0xc000: 389 case 0xc003: 390 case 0xc081: 391 case 0xc402 ... 0xc406: 392 case 0xc48c ... 0xc48f: 393 case 0xc560: 394 case 0xc5b5 ... 0xc5b7: 395 case 0xc5fc ... 0xc5ff: 396 case 0xc820: 397 case 0xc900: 398 case 0xc920: 399 case 0xca42: 400 case 0xca62: 401 case 0xca82: 402 case 0xcd00: 403 case 0xce03: 404 case 0xce10: 405 case 0xce14 ... 0xce17: 406 case 0xce44 ... 0xce49: 407 case 0xce4c ... 0xce4d: 408 case 0xcf0c: 409 case 0xcf10 ... 0xcf25: 410 case 0xd486 ... 0xd487: 411 case 0xd4e5 ... 0xd4e6: 412 case 0xd4e8 ... 0xd4ff: 413 case 0xd530: 414 case 0xd540: 415 case 0xd543: 416 case 0xdb58 ... 0xdb5f: 417 case 0xdb60 ... 0xdb63: 418 case 0xdb68 ... 0xdb69: 419 case 0xdb6d: 420 case 0xdb70 ... 0xdb71: 421 case 0xdb76: 422 case 0xdb7a: 423 case 0xdb7c ... 0xdb7f: 424 case 0xdd0c ... 0xdd13: 425 case 0xde02: 426 case 0xdf14 ... 0xdf1b: 427 case 0xe83c ... 0xe847: 428 case 0xf01e: 429 case 0xf717 ... 0xf719: 430 case 0xf720 ... 0xf723: 431 case 0x10000000 ... 0x10007fff: 432 case 0x1000c000 ... 0x1000dfff: 433 case 0x1000f008: 434 case 0x1000f021: 435 case 0x3fc2ab80 ... 0x3fc2abd4: 436 case 0x3fc2bf80 ... 0x3fc2bf83: 437 case 0x3fc2bfc0 ... 0x3fc2bfc7: 438 case 0x3fe2e000 ... 0x3fe2e003: 439 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 440 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 441 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 442 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 443 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 444 return true; 445 default: 446 return false; 447 } 448 } 449 450 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 451 { 452 switch (reg) { 453 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 454 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 455 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 456 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 457 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 458 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 459 return true; 460 default: 461 return false; 462 } 463 } 464 465 static const struct regmap_config rt1320_sdw_regmap = { 466 .reg_bits = 32, 467 .val_bits = 8, 468 .readable_reg = rt1320_readable_register, 469 .volatile_reg = rt1320_volatile_register, 470 .max_register = 0x41081980, 471 .reg_defaults = rt1320_reg_defaults, 472 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 473 .cache_type = REGCACHE_MAPLE, 474 .use_single_read = true, 475 .use_single_write = true, 476 }; 477 478 static const struct regmap_config rt1320_mbq_regmap = { 479 .name = "sdw-mbq", 480 .reg_bits = 32, 481 .val_bits = 16, 482 .readable_reg = rt1320_mbq_readable_register, 483 .max_register = 0x41000192, 484 .reg_defaults = rt1320_mbq_defaults, 485 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 486 .cache_type = REGCACHE_MAPLE, 487 .use_single_read = true, 488 .use_single_write = true, 489 }; 490 491 static int rt1320_read_prop(struct sdw_slave *slave) 492 { 493 struct sdw_slave_prop *prop = &slave->prop; 494 int nval; 495 int i, j; 496 u32 bit; 497 unsigned long addr; 498 struct sdw_dpn_prop *dpn; 499 500 /* 501 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 502 */ 503 sdw_slave_read_prop(slave); 504 505 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 506 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 507 508 prop->paging_support = true; 509 prop->lane_control_support = true; 510 511 /* first we need to allocate memory for set bits in port lists */ 512 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 513 prop->sink_ports = BIT(1); 514 515 nval = hweight32(prop->source_ports); 516 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 517 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 518 if (!prop->src_dpn_prop) 519 return -ENOMEM; 520 521 i = 0; 522 dpn = prop->src_dpn_prop; 523 addr = prop->source_ports; 524 for_each_set_bit(bit, &addr, 32) { 525 dpn[i].num = bit; 526 dpn[i].type = SDW_DPN_FULL; 527 dpn[i].simple_ch_prep_sm = true; 528 dpn[i].ch_prep_timeout = 10; 529 i++; 530 } 531 532 /* do this again for sink now */ 533 nval = hweight32(prop->sink_ports); 534 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 535 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 536 if (!prop->sink_dpn_prop) 537 return -ENOMEM; 538 539 j = 0; 540 dpn = prop->sink_dpn_prop; 541 addr = prop->sink_ports; 542 for_each_set_bit(bit, &addr, 32) { 543 dpn[j].num = bit; 544 dpn[j].type = SDW_DPN_FULL; 545 dpn[j].simple_ch_prep_sm = true; 546 dpn[j].ch_prep_timeout = 10; 547 j++; 548 } 549 550 /* set the timeout values */ 551 prop->clk_stop_timeout = 64; 552 553 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */ 554 prop->wake_capable = 0; 555 556 return 0; 557 } 558 559 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 560 unsigned char entity, unsigned char ps) 561 { 562 unsigned int delay = 1000, val; 563 564 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 565 566 /* waiting for Actual PDE becomes to PS0/PS3 */ 567 while (delay) { 568 regmap_read(rt1320->regmap, 569 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 570 if (val == ps) 571 break; 572 573 usleep_range(1000, 1500); 574 delay--; 575 } 576 if (!delay) { 577 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 578 return -ETIMEDOUT; 579 } 580 581 return 0; 582 } 583 584 /* 585 * The 'patch code' is written to the patch code area. 586 * The patch code area is used for SDCA register expansion flexibility. 587 */ 588 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 589 { 590 struct sdw_slave *slave = rt1320->sdw_slave; 591 const struct firmware *patch; 592 const char *filename; 593 unsigned int addr, val; 594 const unsigned char *ptr; 595 int ret, i; 596 597 if (rt1320->version_id <= RT1320_VB) 598 filename = RT1320_VAB_MCU_PATCH; 599 else 600 filename = RT1320_VC_MCU_PATCH; 601 602 /* load the patch code here */ 603 ret = request_firmware(&patch, filename, &slave->dev); 604 if (ret) { 605 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 606 regmap_write(rt1320->regmap, 0xc598, 0x00); 607 regmap_write(rt1320->regmap, 0x10007000, 0x67); 608 regmap_write(rt1320->regmap, 0x10007001, 0x80); 609 regmap_write(rt1320->regmap, 0x10007002, 0x00); 610 regmap_write(rt1320->regmap, 0x10007003, 0x00); 611 } else { 612 ptr = (const unsigned char *)patch->data; 613 if ((patch->size % 8) == 0) { 614 for (i = 0; i < patch->size; i += 8) { 615 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 616 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 617 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 618 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 619 620 if (addr > 0x10007fff || addr < 0x10007000) { 621 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 622 goto _exit_; 623 } 624 if (val > 0xff) { 625 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 626 goto _exit_; 627 } 628 regmap_write(rt1320->regmap, addr, val); 629 } 630 } 631 _exit_: 632 release_firmware(patch); 633 } 634 } 635 636 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 637 { 638 unsigned int i, reg, val, delay; 639 640 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 641 reg = rt1320_blind_write[i].reg; 642 val = rt1320_blind_write[i].def; 643 delay = rt1320_blind_write[i].delay_us; 644 645 if (reg == 0x3fc2bfc7) 646 rt1320_load_mcu_patch(rt1320); 647 648 regmap_write(rt1320->regmap, reg, val); 649 if (delay) 650 usleep_range(delay, delay + 1000); 651 } 652 } 653 654 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 655 { 656 struct sdw_slave *slave = rt1320->sdw_slave; 657 unsigned int i, reg, val, delay, retry, tmp; 658 659 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 660 reg = rt1320_vc_blind_write[i].reg; 661 val = rt1320_vc_blind_write[i].def; 662 delay = rt1320_vc_blind_write[i].delay_us; 663 664 if (reg == 0x3fc2bf83) 665 rt1320_load_mcu_patch(rt1320); 666 667 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 668 (val == 0x00)) { 669 retry = 200; 670 while (retry) { 671 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 672 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 673 if (tmp == 0x1f) 674 break; 675 usleep_range(1000, 1500); 676 retry--; 677 } 678 if (!retry) 679 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 680 } 681 regmap_write(rt1320->regmap, reg, val); 682 if (delay) 683 usleep_range(delay, delay + 1000); 684 685 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 686 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 687 } 688 } 689 690 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 691 { 692 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 693 unsigned int amp_func_status, val, tmp; 694 695 if (rt1320->hw_init) 696 return 0; 697 698 regcache_cache_only(rt1320->regmap, false); 699 regcache_cache_only(rt1320->mbq_regmap, false); 700 if (rt1320->first_hw_init) { 701 regcache_cache_bypass(rt1320->regmap, true); 702 regcache_cache_bypass(rt1320->mbq_regmap, true); 703 } else { 704 /* 705 * PM runtime status is marked as 'active' only when a Slave reports as Attached 706 */ 707 /* update count of parent 'active' children */ 708 pm_runtime_set_active(&slave->dev); 709 } 710 711 pm_runtime_get_noresume(&slave->dev); 712 713 if (rt1320->version_id < 0) { 714 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 715 rt1320->version_id = val; 716 } 717 718 regmap_read(rt1320->regmap, 719 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 720 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 721 722 /* initialization write */ 723 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 724 if (rt1320->version_id < RT1320_VC) 725 rt1320_vab_preset(rt1320); 726 else 727 rt1320_vc_preset(rt1320); 728 729 regmap_write(rt1320->regmap, 730 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 731 FUNCTION_NEEDS_INITIALIZATION); 732 } 733 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA) { 734 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 735 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 736 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 737 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 738 val = (tmp << 8) | val; 739 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 740 val = (tmp << 16) | val; 741 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 742 val = (tmp << 24) | val; 743 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 744 /* 745 * We call the version b which has the new DSP ROM code against version a. 746 * Therefore, we read the DSP address to check the ID. 747 */ 748 if (val == RT1320_VER_B_ID) 749 rt1320->version_id = RT1320_VB; 750 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 751 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 752 } 753 dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); 754 755 if (rt1320->first_hw_init) { 756 regcache_cache_bypass(rt1320->regmap, false); 757 regcache_cache_bypass(rt1320->mbq_regmap, false); 758 regcache_mark_dirty(rt1320->regmap); 759 regcache_mark_dirty(rt1320->mbq_regmap); 760 } 761 762 /* Mark Slave initialization complete */ 763 rt1320->first_hw_init = true; 764 rt1320->hw_init = true; 765 766 pm_runtime_put_autosuspend(&slave->dev); 767 768 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 769 return 0; 770 } 771 772 static int rt1320_update_status(struct sdw_slave *slave, 773 enum sdw_slave_status status) 774 { 775 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 776 777 if (status == SDW_SLAVE_UNATTACHED) 778 rt1320->hw_init = false; 779 780 /* 781 * Perform initialization only if slave status is present and 782 * hw_init flag is false 783 */ 784 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 785 return 0; 786 787 /* perform I/O transfers required for Slave initialization */ 788 return rt1320_io_init(&slave->dev, slave); 789 } 790 791 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 792 struct snd_kcontrol *kcontrol, int event) 793 { 794 struct snd_soc_component *component = 795 snd_soc_dapm_to_component(w->dapm); 796 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 797 unsigned char ps0 = 0x0, ps3 = 0x3; 798 799 switch (event) { 800 case SND_SOC_DAPM_POST_PMU: 801 regmap_write(rt1320->regmap, 802 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 803 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 804 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 805 break; 806 case SND_SOC_DAPM_PRE_PMD: 807 regmap_write(rt1320->regmap, 808 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 809 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 810 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 811 break; 812 default: 813 break; 814 } 815 816 return 0; 817 } 818 819 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 820 struct snd_kcontrol *kcontrol, int event) 821 { 822 struct snd_soc_component *component = 823 snd_soc_dapm_to_component(w->dapm); 824 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 825 unsigned char ps0 = 0x0, ps3 = 0x3; 826 827 switch (event) { 828 case SND_SOC_DAPM_POST_PMU: 829 regmap_write(rt1320->regmap, 830 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 831 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 832 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 833 break; 834 case SND_SOC_DAPM_PRE_PMD: 835 regmap_write(rt1320->regmap, 836 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 837 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 838 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 839 break; 840 default: 841 break; 842 } 843 844 return 0; 845 } 846 847 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 848 struct snd_ctl_elem_value *ucontrol) 849 { 850 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 851 struct soc_mixer_control *mc = 852 (struct soc_mixer_control *)kcontrol->private_value; 853 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 854 unsigned int gain_l_val, gain_r_val; 855 unsigned int lvalue, rvalue; 856 const unsigned int interval_offset = 0xc0; 857 unsigned int changed = 0, reg_base; 858 struct rt_sdca_dmic_kctrl_priv *p; 859 unsigned int regvalue[4], gain_val[4], i; 860 int err; 861 862 if (strstr(ucontrol->id.name, "FU Capture Volume")) 863 goto _dmic_vol_; 864 865 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 866 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 867 868 /* L Channel */ 869 gain_l_val = ucontrol->value.integer.value[0]; 870 if (gain_l_val > mc->max) 871 gain_l_val = mc->max; 872 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 873 gain_l_val &= 0xffff; 874 875 /* R Channel */ 876 gain_r_val = ucontrol->value.integer.value[1]; 877 if (gain_r_val > mc->max) 878 gain_r_val = mc->max; 879 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 880 gain_r_val &= 0xffff; 881 882 if (lvalue == gain_l_val && rvalue == gain_r_val) 883 return 0; 884 885 /* Lch*/ 886 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 887 /* Rch */ 888 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 889 goto _done_; 890 891 _dmic_vol_: 892 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 893 894 /* check all channels */ 895 for (i = 0; i < p->count; i++) { 896 if (i < 2) { 897 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 898 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 899 } else { 900 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 901 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 902 } 903 904 gain_val[i] = ucontrol->value.integer.value[i]; 905 if (gain_val[i] > p->max) 906 gain_val[i] = p->max; 907 908 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 909 gain_val[i] &= 0xffff; 910 if (regvalue[i] != gain_val[i]) 911 changed = 1; 912 } 913 914 if (!changed) 915 return 0; 916 917 for (i = 0; i < p->count; i++) { 918 if (i < 2) { 919 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 920 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 921 } else { 922 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 923 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 924 } 925 926 if (err < 0) 927 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 928 } 929 930 _done_: 931 return 1; 932 } 933 934 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 935 struct snd_ctl_elem_value *ucontrol) 936 { 937 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 938 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 939 struct soc_mixer_control *mc = 940 (struct soc_mixer_control *)kcontrol->private_value; 941 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 942 const unsigned int interval_offset = 0xc0; 943 unsigned int reg_base, regvalue, ctl, i; 944 struct rt_sdca_dmic_kctrl_priv *p; 945 946 if (strstr(ucontrol->id.name, "FU Capture Volume")) 947 goto _dmic_vol_; 948 949 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 950 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 951 952 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 953 954 if (read_l != read_r) 955 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 956 else 957 ctl_r = ctl_l; 958 959 ucontrol->value.integer.value[0] = ctl_l; 960 ucontrol->value.integer.value[1] = ctl_r; 961 goto _done_; 962 963 _dmic_vol_: 964 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 965 966 /* check all channels */ 967 for (i = 0; i < p->count; i++) { 968 if (i < 2) { 969 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 970 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 971 } else { 972 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 973 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 974 } 975 976 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 977 ucontrol->value.integer.value[i] = ctl; 978 } 979 _done_: 980 return 0; 981 } 982 983 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 984 { 985 int err, i; 986 unsigned int ch_mute; 987 988 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 989 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 990 991 if (i < 2) 992 err = regmap_write(rt1320->regmap, 993 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 994 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 995 else 996 err = regmap_write(rt1320->regmap, 997 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 998 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 999 if (err < 0) 1000 return err; 1001 } 1002 1003 return 0; 1004 } 1005 1006 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 1007 struct snd_ctl_elem_value *ucontrol) 1008 { 1009 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1010 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1011 struct rt_sdca_dmic_kctrl_priv *p = 1012 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1013 unsigned int i; 1014 1015 for (i = 0; i < p->count; i++) 1016 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 1017 1018 return 0; 1019 } 1020 1021 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 1022 struct snd_ctl_elem_value *ucontrol) 1023 { 1024 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1025 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1026 struct rt_sdca_dmic_kctrl_priv *p = 1027 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1028 int err, changed = 0, i; 1029 1030 for (i = 0; i < p->count; i++) { 1031 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 1032 changed = 1; 1033 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 1034 } 1035 1036 err = rt1320_set_fu_capture_ctl(rt1320); 1037 if (err < 0) 1038 return err; 1039 1040 return changed; 1041 } 1042 1043 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 1044 struct snd_ctl_elem_info *uinfo) 1045 { 1046 struct rt_sdca_dmic_kctrl_priv *p = 1047 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1048 1049 if (p->max == 1) 1050 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1051 else 1052 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1053 uinfo->count = p->count; 1054 uinfo->value.integer.min = 0; 1055 uinfo->value.integer.max = p->max; 1056 return 0; 1057 } 1058 1059 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 1060 struct snd_kcontrol *kcontrol, int event) 1061 { 1062 struct snd_soc_component *component = 1063 snd_soc_dapm_to_component(w->dapm); 1064 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1065 1066 switch (event) { 1067 case SND_SOC_DAPM_POST_PMU: 1068 rt1320->fu_dapm_mute = false; 1069 rt1320_set_fu_capture_ctl(rt1320); 1070 break; 1071 case SND_SOC_DAPM_PRE_PMD: 1072 rt1320->fu_dapm_mute = true; 1073 rt1320_set_fu_capture_ctl(rt1320); 1074 break; 1075 } 1076 return 0; 1077 } 1078 1079 static const char * const rt1320_rx_data_ch_select[] = { 1080 "L,R", 1081 "R,L", 1082 "L,L", 1083 "R,R", 1084 "L,L+R", 1085 "R,L+R", 1086 "L+R,L", 1087 "L+R,R", 1088 "L+R,L+R", 1089 }; 1090 1091 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 1092 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 1093 rt1320_rx_data_ch_select); 1094 1095 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 1096 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 1097 1098 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 1099 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 1100 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1101 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 1102 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 1103 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 1104 1105 RT_SDCA_FU_CTRL("FU Capture Switch", 1106 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1107 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 1108 RT_SDCA_EXT_TLV("FU Capture Volume", 1109 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1110 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 1111 }; 1112 1113 static const struct snd_kcontrol_new rt1320_spk_l_dac = 1114 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1115 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1116 0, 1, 1); 1117 static const struct snd_kcontrol_new rt1320_spk_r_dac = 1118 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1119 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 1120 0, 1, 1); 1121 1122 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 1123 /* Audio Interface */ 1124 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 1125 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 1126 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 1127 1128 /* Digital Interface */ 1129 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 1130 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1131 rt1320_pde23_event, 1132 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1133 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1134 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1135 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 1136 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 1137 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 1138 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1139 1140 /* Output */ 1141 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 1142 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 1143 SND_SOC_DAPM_OUTPUT("SPOL"), 1144 SND_SOC_DAPM_OUTPUT("SPOR"), 1145 1146 /* Input */ 1147 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 1148 SND_SOC_DAPM_SIGGEN("AEC Gen"), 1149 SND_SOC_DAPM_INPUT("DMIC1"), 1150 SND_SOC_DAPM_INPUT("DMIC2"), 1151 }; 1152 1153 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 1154 { "FU21", NULL, "DP1RX" }, 1155 { "FU21", NULL, "PDE 23" }, 1156 { "OT23 L", "Switch", "FU21" }, 1157 { "OT23 R", "Switch", "FU21" }, 1158 { "SPOL", NULL, "OT23 L" }, 1159 { "SPOR", NULL, "OT23 R" }, 1160 1161 { "AEC Data", NULL, "AEC Gen" }, 1162 { "DP4TX", NULL, "AEC Data" }, 1163 1164 {"DP8-10TX", NULL, "FU"}, 1165 {"FU", NULL, "PDE 11"}, 1166 {"FU", NULL, "FU 113"}, 1167 {"FU", NULL, "FU 14"}, 1168 {"FU 113", NULL, "DMIC1"}, 1169 {"FU 14", NULL, "DMIC2"}, 1170 }; 1171 1172 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1173 int direction) 1174 { 1175 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1176 return 0; 1177 } 1178 1179 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 1180 struct snd_soc_dai *dai) 1181 { 1182 snd_soc_dai_set_dma_data(dai, substream, NULL); 1183 } 1184 1185 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 1186 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1187 { 1188 struct snd_soc_component *component = dai->component; 1189 struct rt1320_sdw_priv *rt1320 = 1190 snd_soc_component_get_drvdata(component); 1191 struct sdw_stream_config stream_config; 1192 struct sdw_port_config port_config; 1193 struct sdw_port_config dmic_port_config[2]; 1194 struct sdw_stream_runtime *sdw_stream; 1195 int retval; 1196 unsigned int sampling_rate; 1197 1198 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1199 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1200 1201 if (!sdw_stream) 1202 return -EINVAL; 1203 1204 if (!rt1320->sdw_slave) 1205 return -EINVAL; 1206 1207 /* SoundWire specific configuration */ 1208 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 1209 1210 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1211 if (dai->id == RT1320_AIF1) 1212 port_config.num = 1; 1213 else 1214 return -EINVAL; 1215 } else { 1216 if (dai->id == RT1320_AIF1) 1217 port_config.num = 4; 1218 else if (dai->id == RT1320_AIF2) { 1219 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1220 dmic_port_config[0].num = 8; 1221 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 1222 dmic_port_config[1].num = 10; 1223 } else 1224 return -EINVAL; 1225 } 1226 1227 if (dai->id == RT1320_AIF1) 1228 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1229 &port_config, 1, sdw_stream); 1230 else if (dai->id == RT1320_AIF2) 1231 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1232 dmic_port_config, 2, sdw_stream); 1233 else 1234 return -EINVAL; 1235 if (retval) { 1236 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1237 return retval; 1238 } 1239 1240 /* sampling rate configuration */ 1241 switch (params_rate(params)) { 1242 case 16000: 1243 sampling_rate = RT1320_SDCA_RATE_16000HZ; 1244 break; 1245 case 32000: 1246 sampling_rate = RT1320_SDCA_RATE_32000HZ; 1247 break; 1248 case 44100: 1249 sampling_rate = RT1320_SDCA_RATE_44100HZ; 1250 break; 1251 case 48000: 1252 sampling_rate = RT1320_SDCA_RATE_48000HZ; 1253 break; 1254 case 96000: 1255 sampling_rate = RT1320_SDCA_RATE_96000HZ; 1256 break; 1257 case 192000: 1258 sampling_rate = RT1320_SDCA_RATE_192000HZ; 1259 break; 1260 default: 1261 dev_err(component->dev, "%s: Rate %d is not supported\n", 1262 __func__, params_rate(params)); 1263 return -EINVAL; 1264 } 1265 1266 /* set sampling frequency */ 1267 if (dai->id == RT1320_AIF1) 1268 regmap_write(rt1320->regmap, 1269 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1270 sampling_rate); 1271 else { 1272 regmap_write(rt1320->regmap, 1273 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1274 sampling_rate); 1275 regmap_write(rt1320->regmap, 1276 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1277 sampling_rate); 1278 } 1279 1280 return 0; 1281 } 1282 1283 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 1284 struct snd_soc_dai *dai) 1285 { 1286 struct snd_soc_component *component = dai->component; 1287 struct rt1320_sdw_priv *rt1320 = 1288 snd_soc_component_get_drvdata(component); 1289 struct sdw_stream_runtime *sdw_stream = 1290 snd_soc_dai_get_dma_data(dai, substream); 1291 1292 if (!rt1320->sdw_slave) 1293 return -EINVAL; 1294 1295 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 1296 return 0; 1297 } 1298 1299 /* 1300 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 1301 * port_prep are not defined for now 1302 */ 1303 static const struct sdw_slave_ops rt1320_slave_ops = { 1304 .read_prop = rt1320_read_prop, 1305 .update_status = rt1320_update_status, 1306 }; 1307 1308 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 1309 { 1310 int ret; 1311 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1312 1313 rt1320->component = component; 1314 1315 if (!rt1320->first_hw_init) 1316 return 0; 1317 1318 ret = pm_runtime_resume(component->dev); 1319 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 1320 if (ret < 0 && ret != -EACCES) 1321 return ret; 1322 1323 return 0; 1324 } 1325 1326 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 1327 .probe = rt1320_sdw_component_probe, 1328 .controls = rt1320_snd_controls, 1329 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 1330 .dapm_widgets = rt1320_dapm_widgets, 1331 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 1332 .dapm_routes = rt1320_dapm_routes, 1333 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 1334 .endianness = 1, 1335 }; 1336 1337 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 1338 .hw_params = rt1320_sdw_hw_params, 1339 .hw_free = rt1320_sdw_pcm_hw_free, 1340 .set_stream = rt1320_set_sdw_stream, 1341 .shutdown = rt1320_sdw_shutdown, 1342 }; 1343 1344 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 1345 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1346 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1347 SNDRV_PCM_FMTBIT_S32_LE) 1348 1349 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 1350 { 1351 .name = "rt1320-aif1", 1352 .id = RT1320_AIF1, 1353 .playback = { 1354 .stream_name = "DP1 Playback", 1355 .channels_min = 1, 1356 .channels_max = 2, 1357 .rates = RT1320_STEREO_RATES, 1358 .formats = RT1320_FORMATS, 1359 }, 1360 .capture = { 1361 .stream_name = "DP4 Capture", 1362 .channels_min = 1, 1363 .channels_max = 2, 1364 .rates = RT1320_STEREO_RATES, 1365 .formats = RT1320_FORMATS, 1366 }, 1367 .ops = &rt1320_aif_dai_ops, 1368 }, 1369 /* DMIC: DP8 2ch + DP10 2ch */ 1370 { 1371 .name = "rt1320-aif2", 1372 .id = RT1320_AIF2, 1373 .capture = { 1374 .stream_name = "DP8-10 Capture", 1375 .channels_min = 1, 1376 .channels_max = 4, 1377 .rates = RT1320_STEREO_RATES, 1378 .formats = RT1320_FORMATS, 1379 }, 1380 .ops = &rt1320_aif_dai_ops, 1381 }, 1382 }; 1383 1384 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 1385 struct regmap *mbq_regmap, struct sdw_slave *slave) 1386 { 1387 struct rt1320_sdw_priv *rt1320; 1388 int ret; 1389 1390 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 1391 if (!rt1320) 1392 return -ENOMEM; 1393 1394 dev_set_drvdata(dev, rt1320); 1395 rt1320->sdw_slave = slave; 1396 rt1320->mbq_regmap = mbq_regmap; 1397 rt1320->regmap = regmap; 1398 1399 regcache_cache_only(rt1320->regmap, true); 1400 regcache_cache_only(rt1320->mbq_regmap, true); 1401 1402 /* 1403 * Mark hw_init to false 1404 * HW init will be performed when device reports present 1405 */ 1406 rt1320->hw_init = false; 1407 rt1320->first_hw_init = false; 1408 rt1320->version_id = -1; 1409 rt1320->fu_dapm_mute = true; 1410 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 1411 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 1412 1413 ret = devm_snd_soc_register_component(dev, 1414 &soc_component_sdw_rt1320, 1415 rt1320_sdw_dai, 1416 ARRAY_SIZE(rt1320_sdw_dai)); 1417 if (ret < 0) 1418 return ret; 1419 1420 /* set autosuspend parameters */ 1421 pm_runtime_set_autosuspend_delay(dev, 3000); 1422 pm_runtime_use_autosuspend(dev); 1423 1424 /* make sure the device does not suspend immediately */ 1425 pm_runtime_mark_last_busy(dev); 1426 1427 pm_runtime_enable(dev); 1428 1429 /* important note: the device is NOT tagged as 'active' and will remain 1430 * 'suspended' until the hardware is enumerated/initialized. This is required 1431 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 1432 * fail with -EACCESS because of race conditions between card creation and enumeration 1433 */ 1434 1435 dev_dbg(dev, "%s\n", __func__); 1436 1437 return ret; 1438 } 1439 1440 static int rt1320_sdw_probe(struct sdw_slave *slave, 1441 const struct sdw_device_id *id) 1442 { 1443 struct regmap *regmap, *mbq_regmap; 1444 1445 /* Regmap Initialization */ 1446 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 1447 if (IS_ERR(mbq_regmap)) 1448 return PTR_ERR(mbq_regmap); 1449 1450 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 1451 if (IS_ERR(regmap)) 1452 return PTR_ERR(regmap); 1453 1454 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 1455 } 1456 1457 static int rt1320_sdw_remove(struct sdw_slave *slave) 1458 { 1459 pm_runtime_disable(&slave->dev); 1460 1461 return 0; 1462 } 1463 1464 /* 1465 * Version A/B will use the class id 0 1466 * The newer version than A/B will use the class id 1, so add it in advance 1467 */ 1468 static const struct sdw_device_id rt1320_id[] = { 1469 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 1470 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 1471 {}, 1472 }; 1473 MODULE_DEVICE_TABLE(sdw, rt1320_id); 1474 1475 static int rt1320_dev_suspend(struct device *dev) 1476 { 1477 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1478 1479 if (!rt1320->hw_init) 1480 return 0; 1481 1482 regcache_cache_only(rt1320->regmap, true); 1483 regcache_cache_only(rt1320->mbq_regmap, true); 1484 return 0; 1485 } 1486 1487 #define RT1320_PROBE_TIMEOUT 5000 1488 1489 static int rt1320_dev_resume(struct device *dev) 1490 { 1491 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1492 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1493 unsigned long time; 1494 1495 if (!rt1320->first_hw_init) 1496 return 0; 1497 1498 if (!slave->unattach_request) 1499 goto regmap_sync; 1500 1501 time = wait_for_completion_timeout(&slave->initialization_complete, 1502 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 1503 if (!time) { 1504 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 1505 return -ETIMEDOUT; 1506 } 1507 1508 regmap_sync: 1509 slave->unattach_request = 0; 1510 regcache_cache_only(rt1320->regmap, false); 1511 regcache_sync(rt1320->regmap); 1512 regcache_cache_only(rt1320->mbq_regmap, false); 1513 regcache_sync(rt1320->mbq_regmap); 1514 return 0; 1515 } 1516 1517 static const struct dev_pm_ops rt1320_pm = { 1518 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 1519 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 1520 }; 1521 1522 static struct sdw_driver rt1320_sdw_driver = { 1523 .driver = { 1524 .name = "rt1320-sdca", 1525 .pm = pm_ptr(&rt1320_pm), 1526 }, 1527 .probe = rt1320_sdw_probe, 1528 .remove = rt1320_sdw_remove, 1529 .ops = &rt1320_slave_ops, 1530 .id_table = rt1320_id, 1531 }; 1532 module_sdw_driver(rt1320_sdw_driver); 1533 1534 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 1535 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 1536 MODULE_LICENSE("GPL"); 1537