1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 #include "rt-sdw-common.h" 25 26 /* 27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 28 * It might include vendor-specific or SDCA control registers. 29 */ 30 static const struct reg_sequence rt1320_blind_write[] = { 31 { 0xc003, 0xe0 }, 32 { 0xc01b, 0xfc }, 33 { 0xc5c3, 0xf2 }, 34 { 0xc5c2, 0x00 }, 35 { 0xc5c6, 0x10 }, 36 { 0xc5c4, 0x12 }, 37 { 0xc5c8, 0x03 }, 38 { 0xc5d8, 0x0a }, 39 { 0xc5f7, 0x22 }, 40 { 0xc5f6, 0x22 }, 41 { 0xc5d0, 0x0f }, 42 { 0xc5d1, 0x89 }, 43 { 0xc057, 0x51 }, 44 { 0xc054, 0x35 }, 45 { 0xc053, 0x55 }, 46 { 0xc052, 0x55 }, 47 { 0xc051, 0x13 }, 48 { 0xc050, 0x15 }, 49 { 0xc060, 0x77 }, 50 { 0xc061, 0x55 }, 51 { 0xc063, 0x55 }, 52 { 0xc065, 0xa5 }, 53 { 0xc06b, 0x0a }, 54 { 0xca05, 0xd6 }, 55 { 0xca25, 0xd6 }, 56 { 0xcd00, 0x05 }, 57 { 0xc604, 0x40 }, 58 { 0xc609, 0x40 }, 59 { 0xc046, 0xff }, 60 { 0xc045, 0xff }, 61 { 0xc044, 0xff }, 62 { 0xc043, 0xff }, 63 { 0xc042, 0xff }, 64 { 0xc041, 0xff }, 65 { 0xc040, 0xff }, 66 { 0xcc10, 0x01 }, 67 { 0xc700, 0xf0 }, 68 { 0xc701, 0x13 }, 69 { 0xc901, 0x04 }, 70 { 0xc900, 0x73 }, 71 { 0xde03, 0x05 }, 72 { 0xdd0b, 0x0d }, 73 { 0xdd0a, 0xff }, 74 { 0xdd09, 0x0d }, 75 { 0xdd08, 0xff }, 76 { 0xc570, 0x08 }, 77 { 0xe803, 0xbe }, 78 { 0xc003, 0xc0 }, 79 { 0xc081, 0xfe }, 80 { 0xce31, 0x0d }, 81 { 0xce30, 0xae }, 82 { 0xce37, 0x0b }, 83 { 0xce36, 0xd2 }, 84 { 0xce39, 0x04 }, 85 { 0xce38, 0x80 }, 86 { 0xce3f, 0x00 }, 87 { 0xce3e, 0x00 }, 88 { 0xd470, 0x8b }, 89 { 0xd471, 0x18 }, 90 { 0xc019, 0x10 }, 91 { 0xd487, 0x3f }, 92 { 0xd486, 0xc3 }, 93 { 0x3fc2bfc7, 0x00 }, 94 { 0x3fc2bfc6, 0x00 }, 95 { 0x3fc2bfc5, 0x00 }, 96 { 0x3fc2bfc4, 0x01 }, 97 { 0x0000d486, 0x43 }, 98 { 0x1000db00, 0x02 }, 99 { 0x1000db01, 0x00 }, 100 { 0x1000db02, 0x11 }, 101 { 0x1000db03, 0x00 }, 102 { 0x1000db04, 0x00 }, 103 { 0x1000db05, 0x82 }, 104 { 0x1000db06, 0x04 }, 105 { 0x1000db07, 0xf1 }, 106 { 0x1000db08, 0x00 }, 107 { 0x1000db09, 0x00 }, 108 { 0x1000db0a, 0x40 }, 109 { 0x0000d540, 0x01 }, 110 { 0xd172, 0x2a }, 111 { 0xc5d6, 0x01 }, 112 { 0xd478, 0xff }, 113 }; 114 115 static const struct reg_sequence rt1320_vc_blind_write[] = { 116 { 0xc003, 0xe0 }, 117 { 0xe80a, 0x01 }, 118 { 0xc5c3, 0xf2 }, 119 { 0xc5c8, 0x03 }, 120 { 0xc057, 0x51 }, 121 { 0xc054, 0x35 }, 122 { 0xca05, 0xd6 }, 123 { 0xca07, 0x07 }, 124 { 0xca25, 0xd6 }, 125 { 0xca27, 0x07 }, 126 { 0xc604, 0x40 }, 127 { 0xc609, 0x40 }, 128 { 0xc046, 0xff }, 129 { 0xc045, 0xff }, 130 { 0xc044, 0xff }, 131 { 0xc043, 0xff }, 132 { 0xc042, 0xff }, 133 { 0xc041, 0x7f }, 134 { 0xc040, 0xff }, 135 { 0xcc10, 0x01 }, 136 { 0xc700, 0xf0 }, 137 { 0xc701, 0x13 }, 138 { 0xc901, 0x04 }, 139 { 0xc900, 0x73 }, 140 { 0xde03, 0x05 }, 141 { 0xdd0b, 0x0d }, 142 { 0xdd0a, 0xff }, 143 { 0xdd09, 0x0d }, 144 { 0xdd08, 0xff }, 145 { 0xc570, 0x08 }, 146 { 0xc086, 0x02 }, 147 { 0xc085, 0x7f }, 148 { 0xc084, 0x00 }, 149 { 0xc081, 0xfe }, 150 { 0xf084, 0x0f }, 151 { 0xf083, 0xff }, 152 { 0xf082, 0xff }, 153 { 0xf081, 0xff }, 154 { 0xf080, 0xff }, 155 { 0xe801, 0x01 }, 156 { 0xe802, 0xf8 }, 157 { 0xe803, 0xbe }, 158 { 0xc003, 0xc0 }, 159 { 0xd470, 0xec }, 160 { 0xd471, 0x3a }, 161 { 0xd474, 0x11 }, 162 { 0xd475, 0x32 }, 163 { 0xd478, 0xff }, 164 { 0xd479, 0x20 }, 165 { 0xd47a, 0x10 }, 166 { 0xd47c, 0xff }, 167 { 0xc019, 0x10 }, 168 { 0xd487, 0x0b }, 169 { 0xd487, 0x3b }, 170 { 0xd486, 0xc3 }, 171 { 0xc598, 0x04 }, 172 { 0xdb03, 0xf0 }, 173 { 0xdb09, 0x00 }, 174 { 0xdb08, 0x7a }, 175 { 0xdb19, 0x02 }, 176 { 0xdb07, 0x5a }, 177 { 0xdb05, 0x45 }, 178 { 0xd500, 0x00 }, 179 { 0xd500, 0x17 }, 180 { 0xd600, 0x01 }, 181 { 0xd601, 0x02 }, 182 { 0xd602, 0x03 }, 183 { 0xd603, 0x04 }, 184 { 0xd64c, 0x03 }, 185 { 0xd64d, 0x03 }, 186 { 0xd64e, 0x03 }, 187 { 0xd64f, 0x03 }, 188 { 0xd650, 0x03 }, 189 { 0xd651, 0x03 }, 190 { 0xd652, 0x03 }, 191 { 0xd610, 0x01 }, 192 { 0xd608, 0x03 }, 193 { 0xd609, 0x00 }, 194 { 0x3fc2bf83, 0x00 }, 195 { 0x3fc2bf82, 0x00 }, 196 { 0x3fc2bf81, 0x00 }, 197 { 0x3fc2bf80, 0x00 }, 198 { 0x3fc2bfc7, 0x00 }, 199 { 0x3fc2bfc6, 0x00 }, 200 { 0x3fc2bfc5, 0x00 }, 201 { 0x3fc2bfc4, 0x00 }, 202 { 0x3fc2bfc3, 0x00 }, 203 { 0x3fc2bfc2, 0x00 }, 204 { 0x3fc2bfc1, 0x00 }, 205 { 0x3fc2bfc0, 0x07 }, 206 { 0x0000d486, 0x43 }, 207 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 208 { 0x1000db00, 0x07 }, 209 { 0x1000db01, 0x00 }, 210 { 0x1000db02, 0x11 }, 211 { 0x1000db03, 0x00 }, 212 { 0x1000db04, 0x00 }, 213 { 0x1000db05, 0x82 }, 214 { 0x1000db06, 0x04 }, 215 { 0x1000db07, 0xf1 }, 216 { 0x1000db08, 0x00 }, 217 { 0x1000db09, 0x00 }, 218 { 0x1000db0a, 0x40 }, 219 { 0x1000db0b, 0x02 }, 220 { 0x1000db0c, 0xf2 }, 221 { 0x1000db0d, 0x00 }, 222 { 0x1000db0e, 0x00 }, 223 { 0x1000db0f, 0xe0 }, 224 { 0x1000db10, 0x00 }, 225 { 0x1000db11, 0x10 }, 226 { 0x1000db12, 0x00 }, 227 { 0x1000db13, 0x00 }, 228 { 0x1000db14, 0x45 }, 229 { 0x1000db15, 0x0d }, 230 { 0x1000db16, 0x01 }, 231 { 0x1000db17, 0x00 }, 232 { 0x1000db18, 0x00 }, 233 { 0x1000db19, 0xbf }, 234 { 0x1000db1a, 0x13 }, 235 { 0x1000db1b, 0x09 }, 236 { 0x1000db1c, 0x00 }, 237 { 0x1000db1d, 0x00 }, 238 { 0x1000db1e, 0x00 }, 239 { 0x1000db1f, 0x12 }, 240 { 0x1000db20, 0x09 }, 241 { 0x1000db21, 0x00 }, 242 { 0x1000db22, 0x00 }, 243 { 0x1000db23, 0x00 }, 244 { 0x0000d540, 0x21 }, 245 { 0xc01b, 0xfc }, 246 { 0xc5d1, 0x89 }, 247 { 0xc5d8, 0x0a }, 248 { 0xc5f7, 0x22 }, 249 { 0xc5f6, 0x22 }, 250 { 0xc065, 0xa5 }, 251 { 0xc06b, 0x0a }, 252 { 0xd172, 0x2a }, 253 { 0xc5d6, 0x01 }, 254 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 255 }; 256 257 static const struct reg_sequence rt1321_blind_write[] = { 258 { 0x0000c003, 0xf0 }, 259 { 0x0000c01b, 0xfc }, 260 { 0x0000c5c3, 0xf2 }, 261 { 0x0000c5c2, 0x00 }, 262 { 0x0000c5c1, 0x10 }, 263 { 0x0000c5c0, 0x04 }, 264 { 0x0000c5c7, 0x03 }, 265 { 0x0000c5c6, 0x10 }, 266 { 0x0000c526, 0x47 }, 267 { 0x0000c5c4, 0x12 }, 268 { 0x0000c5c5, 0x60 }, 269 { 0x0000c520, 0x10 }, 270 { 0x0000c521, 0x32 }, 271 { 0x0000c5c7, 0x00 }, 272 { 0x0000c5c8, 0x03 }, 273 { 0x0000c5d3, 0x08 }, 274 { 0x0000c5d2, 0x0a }, 275 { 0x0000c5d1, 0x49 }, 276 { 0x0000c5d0, 0x0f }, 277 { 0x0000c580, 0x10 }, 278 { 0x0000c581, 0x32 }, 279 { 0x0000c582, 0x01 }, 280 { 0x0000cb00, 0x03 }, 281 { 0x0000cb02, 0x52 }, 282 { 0x0000cb04, 0x80 }, 283 { 0x0000cb0b, 0x01 }, 284 { 0x0000c682, 0x60 }, 285 { 0x0000c019, 0x10 }, 286 { 0x0000c5f0, 0x01 }, 287 { 0x0000c5f7, 0x22 }, 288 { 0x0000c5f6, 0x22 }, 289 { 0x0000c057, 0x51 }, 290 { 0x0000c054, 0x55 }, 291 { 0x0000c053, 0x55 }, 292 { 0x0000c052, 0x55 }, 293 { 0x0000c051, 0x01 }, 294 { 0x0000c050, 0x15 }, 295 { 0x0000c060, 0x99 }, 296 { 0x0000c030, 0x55 }, 297 { 0x0000c061, 0x55 }, 298 { 0x0000c063, 0x55 }, 299 { 0x0000c065, 0xa5 }, 300 { 0x0000c06b, 0x0a }, 301 { 0x0000ca05, 0xd6 }, 302 { 0x0000ca07, 0x07 }, 303 { 0x0000ca25, 0xd6 }, 304 { 0x0000ca27, 0x07 }, 305 { 0x0000cd00, 0x05 }, 306 { 0x0000c604, 0x40 }, 307 { 0x0000c609, 0x40 }, 308 { 0x0000c046, 0xf7 }, 309 { 0x0000c045, 0xff }, 310 { 0x0000c044, 0xff }, 311 { 0x0000c043, 0xff }, 312 { 0x0000c042, 0xff }, 313 { 0x0000c041, 0xff }, 314 { 0x0000c040, 0xff }, 315 { 0x0000c049, 0xff }, 316 { 0x0000c028, 0x3f }, 317 { 0x0000c020, 0x3f }, 318 { 0x0000c032, 0x13 }, 319 { 0x0000c033, 0x01 }, 320 { 0x0000cc10, 0x01 }, 321 { 0x0000dc20, 0x03 }, 322 { 0x0000de03, 0x05 }, 323 { 0x0000dc00, 0x00 }, 324 { 0x0000c700, 0xf0 }, 325 { 0x0000c701, 0x13 }, 326 { 0x0000c900, 0xc3 }, 327 { 0x0000c570, 0x08 }, 328 { 0x0000c086, 0x02 }, 329 { 0x0000c085, 0x7f }, 330 { 0x0000c084, 0x00 }, 331 { 0x0000c081, 0xff }, 332 { 0x0000f084, 0x0f }, 333 { 0x0000f083, 0xff }, 334 { 0x0000f082, 0xff }, 335 { 0x0000f081, 0xff }, 336 { 0x0000f080, 0xff }, 337 { 0x20003003, 0x3f }, 338 { 0x20005818, 0x81 }, 339 { 0x20009018, 0x81 }, 340 { 0x2000301c, 0x81 }, 341 { 0x0000c003, 0xc0 }, 342 { 0x0000c047, 0x80 }, 343 { 0x0000d541, 0x80 }, 344 { 0x0000d487, 0x0b }, 345 { 0x0000d487, 0x3b }, 346 { 0x0000d486, 0xc3 }, 347 { 0x0000d470, 0x89 }, 348 { 0x0000d471, 0x3a }, 349 { 0x0000d472, 0x1d }, 350 { 0x0000d478, 0xff }, 351 { 0x0000d479, 0x20 }, 352 { 0x0000d47a, 0x10 }, 353 { 0x0000d73c, 0xb7 }, 354 { 0x0000d73d, 0xd7 }, 355 { 0x0000d73e, 0x00 }, 356 { 0x0000d73f, 0x10 }, 357 { 0x3fc2dfc3, 0x00 }, 358 { 0x3fc2dfc2, 0x00 }, 359 { 0x3fc2dfc1, 0x00 }, 360 { 0x3fc2dfc0, 0x07 }, 361 { 0x3fc2dfc7, 0x00 }, 362 { 0x3fc2dfc6, 0x00 }, 363 { 0x3fc2dfc5, 0x00 }, 364 { 0x3fc2dfc4, 0x01 }, 365 { 0x3fc2df83, 0x00 }, 366 { 0x3fc2df82, 0x00 }, 367 { 0x3fc2df81, 0x00 }, 368 { 0x3fc2df80, 0x00 }, 369 { 0x0000d541, 0x40 }, 370 { 0x0000d486, 0x43 }, 371 { 0x1000db00, 0x03 }, 372 { 0x1000db01, 0x00 }, 373 { 0x1000db02, 0x10 }, 374 { 0x1000db03, 0x00 }, 375 { 0x1000db04, 0x00 }, 376 { 0x1000db05, 0x45 }, 377 { 0x1000db06, 0x12 }, 378 { 0x1000db07, 0x09 }, 379 { 0x1000db08, 0x00 }, 380 { 0x1000db09, 0x00 }, 381 { 0x1000db0a, 0x00 }, 382 { 0x1000db0b, 0x13 }, 383 { 0x1000db0c, 0x09 }, 384 { 0x1000db0d, 0x00 }, 385 { 0x1000db0e, 0x00 }, 386 { 0x1000db0f, 0x00 }, 387 { 0x0000d540, 0x21 }, 388 { 0x41000189, 0x00 }, 389 { 0x4100018a, 0x00 }, 390 { 0x41001988, 0x00 }, 391 { 0x41081400, 0x09 }, 392 { 0x40801508, 0x03 }, 393 { 0x40801588, 0x03 }, 394 { 0x40801809, 0x00 }, 395 { 0x4080180a, 0x00 }, 396 { 0x4080180b, 0x00 }, 397 { 0x4080180c, 0x00 }, 398 { 0x40801b09, 0x00 }, 399 { 0x40801b0a, 0x00 }, 400 { 0x40801b0b, 0x00 }, 401 { 0x40801b0c, 0x00 }, 402 { 0x0000d714, 0x17 }, 403 { 0x20009012, 0x00 }, 404 { 0x0000dd0b, 0x0d }, 405 { 0x0000dd0a, 0xff }, 406 { 0x0000dd09, 0x0d }, 407 { 0x0000dd08, 0xff }, 408 { 0x0000d172, 0x2a }, 409 { 0x41001988, 0x03 }, 410 }; 411 412 static const struct reg_default rt1320_reg_defaults[] = { 413 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 414 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 416 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 417 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 418 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 419 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 420 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 421 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 422 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 423 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 424 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 425 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 426 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 427 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 428 }; 429 430 static const struct reg_default rt1320_mbq_defaults[] = { 431 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 432 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 433 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 434 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 435 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 436 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 437 }; 438 439 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 440 { 441 switch (reg) { 442 case 0xc000 ... 0xc086: 443 case 0xc400 ... 0xc409: 444 case 0xc480 ... 0xc48f: 445 case 0xc4c0 ... 0xc4c4: 446 case 0xc4e0 ... 0xc4e7: 447 case 0xc500: 448 case 0xc560 ... 0xc56b: 449 case 0xc570: 450 case 0xc580 ... 0xc59a: 451 case 0xc5b0 ... 0xc60f: 452 case 0xc640 ... 0xc64f: 453 case 0xc670: 454 case 0xc680 ... 0xc683: 455 case 0xc700 ... 0xc76f: 456 case 0xc800 ... 0xc801: 457 case 0xc820: 458 case 0xc900 ... 0xc901: 459 case 0xc920 ... 0xc921: 460 case 0xca00 ... 0xca07: 461 case 0xca20 ... 0xca27: 462 case 0xca40 ... 0xca4b: 463 case 0xca60 ... 0xca68: 464 case 0xca80 ... 0xca88: 465 case 0xcb00 ... 0xcb0c: 466 case 0xcc00 ... 0xcc12: 467 case 0xcc80 ... 0xcc81: 468 case 0xcd00: 469 case 0xcd80 ... 0xcd82: 470 case 0xce00 ... 0xce4d: 471 case 0xcf00 ... 0xcf25: 472 case 0xd000 ... 0xd0ff: 473 case 0xd100 ... 0xd1ff: 474 case 0xd200 ... 0xd2ff: 475 case 0xd300 ... 0xd3ff: 476 case 0xd400 ... 0xd403: 477 case 0xd410 ... 0xd417: 478 case 0xd470 ... 0xd497: 479 case 0xd4dc ... 0xd50f: 480 case 0xd520 ... 0xd543: 481 case 0xd560 ... 0xd5ef: 482 case 0xd600 ... 0xd663: 483 case 0xda00 ... 0xda6e: 484 case 0xda80 ... 0xda9e: 485 case 0xdb00 ... 0xdb7f: 486 case 0xdc00: 487 case 0xdc20 ... 0xdc21: 488 case 0xdd00 ... 0xdd17: 489 case 0xde00 ... 0xde09: 490 case 0xdf00 ... 0xdf1b: 491 case 0xe000 ... 0xe847: 492 case 0xf01e: 493 case 0xf717 ... 0xf719: 494 case 0xf720 ... 0xf723: 495 case 0x1000cd91 ... 0x1000cd96: 496 case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER: 497 case 0x1000f008: 498 case 0x1000f021: 499 case 0x2000300f: 500 case 0x2000301c: 501 case 0x2000900f: 502 case 0x20009018: 503 case 0x3fc29d80 ... 0x3fc29d83: 504 case 0x3fe2e000 ... 0x3fe2e003: 505 case 0x3fc2ab80 ... 0x3fc2abd4: 506 case 0x3fc2bfc0 ... 0x3fc2bfc8: 507 case 0x3fc2d300 ... 0x3fc2d354: 508 case 0x3fc2dfc0 ... 0x3fc2dfc8: 509 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 510 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 511 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 512 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 513 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 514 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 515 /* 0x40880900/0x40880980 */ 516 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 517 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 518 /* 0x40881500 */ 519 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 520 /* 0x41000189/0x4100018a */ 521 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 522 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 523 /* 0x41001388 */ 524 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 525 /* 0x41001988 */ 526 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 527 /* 0x41080000 */ 528 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 529 /* 0x41080200 */ 530 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 531 /* 0x41080900 */ 532 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 533 /* 0x41080980 */ 534 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 535 /* 0x41081080 */ 536 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 537 /* 0x41081480/0x41081488 */ 538 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 539 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 540 /* 0x41081980 */ 541 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 542 return true; 543 default: 544 return false; 545 } 546 } 547 548 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 549 { 550 switch (reg) { 551 case 0xc000: 552 case 0xc003: 553 case 0xc081: 554 case 0xc402 ... 0xc406: 555 case 0xc48c ... 0xc48f: 556 case 0xc560: 557 case 0xc5b5 ... 0xc5b7: 558 case 0xc5fc ... 0xc5ff: 559 case 0xc680 ... 0xc683: 560 case 0xc820: 561 case 0xc900: 562 case 0xc920: 563 case 0xca42: 564 case 0xca62: 565 case 0xca82: 566 case 0xcd00: 567 case 0xce03: 568 case 0xce10: 569 case 0xce14 ... 0xce17: 570 case 0xce44 ... 0xce49: 571 case 0xce4c ... 0xce4d: 572 case 0xcf0c: 573 case 0xcf10 ... 0xcf25: 574 case 0xd486 ... 0xd487: 575 case 0xd4e5 ... 0xd4e6: 576 case 0xd4e8 ... 0xd4ff: 577 case 0xd530: 578 case 0xd540 ... 0xd541: 579 case 0xd543: 580 case 0xdb58 ... 0xdb5f: 581 case 0xdb60 ... 0xdb63: 582 case 0xdb68 ... 0xdb69: 583 case 0xdb6d: 584 case 0xdb70 ... 0xdb71: 585 case 0xdb76: 586 case 0xdb7a: 587 case 0xdb7c ... 0xdb7f: 588 case 0xdd0c ... 0xdd13: 589 case 0xde02: 590 case 0xdf14 ... 0xdf1b: 591 case 0xe83c ... 0xe847: 592 case 0xf01e: 593 case 0xf717 ... 0xf719: 594 case 0xf720 ... 0xf723: 595 case 0x10000000 ... 0x10008fff: 596 case 0x1000c000 ... 0x1000dfff: 597 case 0x1000f008: 598 case 0x1000f021: 599 case 0x2000300f: 600 case 0x2000301c: 601 case 0x2000900f: 602 case 0x20009018: 603 case 0x3fc2ab80 ... 0x3fc2abd4: 604 case 0x3fc2b780: 605 case 0x3fc2bf80 ... 0x3fc2bf83: 606 case 0x3fc2bfc0 ... 0x3fc2bfc8: 607 case 0x3fc2d300 ... 0x3fc2d354: 608 case 0x3fc2dfc0 ... 0x3fc2dfc8: 609 case 0x3fe2e000 ... 0x3fe2e003: 610 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 611 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 612 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 613 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 614 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 615 return true; 616 default: 617 return false; 618 } 619 } 620 621 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 622 { 623 switch (reg) { 624 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 625 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 626 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 627 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 628 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 629 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 630 return true; 631 default: 632 return false; 633 } 634 } 635 636 static const struct regmap_config rt1320_sdw_regmap = { 637 .reg_bits = 32, 638 .val_bits = 8, 639 .readable_reg = rt1320_readable_register, 640 .volatile_reg = rt1320_volatile_register, 641 .max_register = 0x41081980, 642 .reg_defaults = rt1320_reg_defaults, 643 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 644 .cache_type = REGCACHE_MAPLE, 645 .use_single_read = true, 646 .use_single_write = true, 647 }; 648 649 static const struct regmap_config rt1320_mbq_regmap = { 650 .name = "sdw-mbq", 651 .reg_bits = 32, 652 .val_bits = 16, 653 .readable_reg = rt1320_mbq_readable_register, 654 .max_register = 0x41000192, 655 .reg_defaults = rt1320_mbq_defaults, 656 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 657 .cache_type = REGCACHE_MAPLE, 658 .use_single_read = true, 659 .use_single_write = true, 660 }; 661 662 static int rt1320_read_prop(struct sdw_slave *slave) 663 { 664 struct sdw_slave_prop *prop = &slave->prop; 665 int nval; 666 int i, j; 667 u32 bit; 668 unsigned long addr; 669 struct sdw_dpn_prop *dpn; 670 671 /* 672 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 673 */ 674 sdw_slave_read_prop(slave); 675 676 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 677 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 678 679 prop->paging_support = true; 680 prop->lane_control_support = true; 681 682 /* first we need to allocate memory for set bits in port lists */ 683 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 684 prop->sink_ports = BIT(1); 685 686 nval = hweight32(prop->source_ports); 687 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 688 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 689 if (!prop->src_dpn_prop) 690 return -ENOMEM; 691 692 i = 0; 693 dpn = prop->src_dpn_prop; 694 addr = prop->source_ports; 695 for_each_set_bit(bit, &addr, 32) { 696 dpn[i].num = bit; 697 dpn[i].type = SDW_DPN_FULL; 698 dpn[i].simple_ch_prep_sm = true; 699 dpn[i].ch_prep_timeout = 10; 700 i++; 701 } 702 703 /* do this again for sink now */ 704 nval = hweight32(prop->sink_ports); 705 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 706 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 707 if (!prop->sink_dpn_prop) 708 return -ENOMEM; 709 710 j = 0; 711 dpn = prop->sink_dpn_prop; 712 addr = prop->sink_ports; 713 for_each_set_bit(bit, &addr, 32) { 714 dpn[j].num = bit; 715 dpn[j].type = SDW_DPN_FULL; 716 dpn[j].simple_ch_prep_sm = true; 717 dpn[j].ch_prep_timeout = 10; 718 j++; 719 } 720 721 /* set the timeout values */ 722 prop->clk_stop_timeout = 64; 723 724 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */ 725 prop->wake_capable = 0; 726 727 return 0; 728 } 729 730 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 731 unsigned char entity, unsigned char ps) 732 { 733 unsigned int delay = 2000, val; 734 735 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 736 737 /* waiting for Actual PDE becomes to PS0/PS3 */ 738 while (delay) { 739 regmap_read(rt1320->regmap, 740 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 741 if (val == ps) 742 break; 743 744 usleep_range(1000, 1500); 745 delay--; 746 } 747 if (!delay) { 748 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 749 return -ETIMEDOUT; 750 } 751 752 return 0; 753 } 754 755 /* 756 * The 'patch code' is written to the patch code area. 757 * The patch code area is used for SDCA register expansion flexibility. 758 */ 759 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 760 { 761 struct sdw_slave *slave = rt1320->sdw_slave; 762 const struct firmware *patch; 763 const char *filename; 764 unsigned int addr, val, min_addr, max_addr; 765 const unsigned char *ptr; 766 int ret, i; 767 768 switch (rt1320->dev_id) { 769 case RT1320_DEV_ID: 770 if (rt1320->version_id <= RT1320_VB) 771 filename = RT1320_VAB_MCU_PATCH; 772 else 773 filename = RT1320_VC_MCU_PATCH; 774 min_addr = 0x10007000; 775 max_addr = 0x10007fff; 776 break; 777 case RT1321_DEV_ID: 778 filename = RT1321_VA_MCU_PATCH; 779 min_addr = 0x10008000; 780 max_addr = 0x10008fff; 781 break; 782 default: 783 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 784 return; 785 } 786 787 /* load the patch code here */ 788 ret = request_firmware(&patch, filename, &slave->dev); 789 if (ret) { 790 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 791 regmap_write(rt1320->regmap, 0xc598, 0x00); 792 regmap_write(rt1320->regmap, min_addr, 0x67); 793 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80); 794 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00); 795 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00); 796 if (rt1320->dev_id == RT1321_DEV_ID) { 797 regmap_write(rt1320->regmap, 0xd73c, 0x67); 798 regmap_write(rt1320->regmap, 0xd73d, 0x80); 799 regmap_write(rt1320->regmap, 0xd73e, 0x00); 800 regmap_write(rt1320->regmap, 0xd73f, 0x00); 801 } 802 } else { 803 ptr = (const unsigned char *)patch->data; 804 if ((patch->size % 8) == 0) { 805 for (i = 0; i < patch->size; i += 8) { 806 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 807 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 808 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 809 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 810 811 if (addr > max_addr || addr < min_addr) { 812 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 813 goto _exit_; 814 } 815 if (val > 0xff) { 816 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 817 goto _exit_; 818 } 819 regmap_write(rt1320->regmap, addr, val); 820 } 821 } 822 _exit_: 823 release_firmware(patch); 824 } 825 } 826 827 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 828 { 829 unsigned int i, reg, val, delay; 830 831 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 832 reg = rt1320_blind_write[i].reg; 833 val = rt1320_blind_write[i].def; 834 delay = rt1320_blind_write[i].delay_us; 835 836 if (reg == 0x3fc2bfc7) 837 rt1320_load_mcu_patch(rt1320); 838 839 regmap_write(rt1320->regmap, reg, val); 840 if (delay) 841 usleep_range(delay, delay + 1000); 842 } 843 } 844 845 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 846 { 847 struct sdw_slave *slave = rt1320->sdw_slave; 848 unsigned int i, reg, val, delay, retry, tmp; 849 850 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 851 reg = rt1320_vc_blind_write[i].reg; 852 val = rt1320_vc_blind_write[i].def; 853 delay = rt1320_vc_blind_write[i].delay_us; 854 855 if (reg == 0x3fc2bf83) 856 rt1320_load_mcu_patch(rt1320); 857 858 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 859 (val == 0x00)) { 860 retry = 200; 861 while (retry) { 862 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 863 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 864 if (tmp == 0x1f) 865 break; 866 usleep_range(1000, 1500); 867 retry--; 868 } 869 if (!retry) 870 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 871 } 872 regmap_write(rt1320->regmap, reg, val); 873 if (delay) 874 usleep_range(delay, delay + 1000); 875 876 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 877 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 878 } 879 } 880 881 static void rt1321_preset(struct rt1320_sdw_priv *rt1320) 882 { 883 unsigned int i, reg, val, delay; 884 885 for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) { 886 reg = rt1321_blind_write[i].reg; 887 val = rt1321_blind_write[i].def; 888 delay = rt1321_blind_write[i].delay_us; 889 890 if (reg == 0x3fc2dfc3) 891 rt1320_load_mcu_patch(rt1320); 892 893 regmap_write(rt1320->regmap, reg, val); 894 895 if (delay) 896 usleep_range(delay, delay + 1000); 897 898 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 899 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 900 } 901 } 902 903 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 904 { 905 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 906 unsigned int amp_func_status, val, tmp; 907 908 if (rt1320->hw_init) 909 return 0; 910 911 regcache_cache_only(rt1320->regmap, false); 912 regcache_cache_only(rt1320->mbq_regmap, false); 913 if (rt1320->first_hw_init) { 914 regcache_cache_bypass(rt1320->regmap, true); 915 regcache_cache_bypass(rt1320->mbq_regmap, true); 916 } else { 917 /* 918 * PM runtime status is marked as 'active' only when a Slave reports as Attached 919 */ 920 /* update count of parent 'active' children */ 921 pm_runtime_set_active(&slave->dev); 922 } 923 924 pm_runtime_get_noresume(&slave->dev); 925 926 if (rt1320->version_id < 0) { 927 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 928 rt1320->version_id = val; 929 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val); 930 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp); 931 rt1320->dev_id = (val << 8) | tmp; 932 } 933 934 regmap_read(rt1320->regmap, 935 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 936 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 937 938 /* initialization write */ 939 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 940 switch (rt1320->dev_id) { 941 case RT1320_DEV_ID: 942 if (rt1320->version_id < RT1320_VC) 943 rt1320_vab_preset(rt1320); 944 else 945 rt1320_vc_preset(rt1320); 946 break; 947 case RT1321_DEV_ID: 948 rt1321_preset(rt1320); 949 break; 950 default: 951 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 952 } 953 954 regmap_write(rt1320->regmap, 955 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 956 FUNCTION_NEEDS_INITIALIZATION); 957 } 958 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) { 959 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 960 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 961 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 962 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 963 val = (tmp << 8) | val; 964 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 965 val = (tmp << 16) | val; 966 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 967 val = (tmp << 24) | val; 968 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 969 /* 970 * We call the version b which has the new DSP ROM code against version a. 971 * Therefore, we read the DSP address to check the ID. 972 */ 973 if (val == RT1320_VER_B_ID) 974 rt1320->version_id = RT1320_VB; 975 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 976 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 977 } 978 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id); 979 980 if (rt1320->first_hw_init) { 981 regcache_cache_bypass(rt1320->regmap, false); 982 regcache_cache_bypass(rt1320->mbq_regmap, false); 983 regcache_mark_dirty(rt1320->regmap); 984 regcache_mark_dirty(rt1320->mbq_regmap); 985 } 986 987 /* Mark Slave initialization complete */ 988 rt1320->first_hw_init = true; 989 rt1320->hw_init = true; 990 991 pm_runtime_put_autosuspend(&slave->dev); 992 993 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 994 return 0; 995 } 996 997 static int rt1320_update_status(struct sdw_slave *slave, 998 enum sdw_slave_status status) 999 { 1000 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 1001 1002 if (status == SDW_SLAVE_UNATTACHED) 1003 rt1320->hw_init = false; 1004 1005 /* 1006 * Perform initialization only if slave status is present and 1007 * hw_init flag is false 1008 */ 1009 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 1010 return 0; 1011 1012 /* perform I/O transfers required for Slave initialization */ 1013 return rt1320_io_init(&slave->dev, slave); 1014 } 1015 1016 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 1017 struct snd_kcontrol *kcontrol, int event) 1018 { 1019 struct snd_soc_component *component = 1020 snd_soc_dapm_to_component(w->dapm); 1021 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1022 unsigned char ps0 = 0x0, ps3 = 0x3; 1023 1024 switch (event) { 1025 case SND_SOC_DAPM_POST_PMU: 1026 regmap_write(rt1320->regmap, 1027 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 1028 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1029 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 1030 break; 1031 case SND_SOC_DAPM_PRE_PMD: 1032 regmap_write(rt1320->regmap, 1033 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 1034 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1035 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 1036 break; 1037 default: 1038 break; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 1045 struct snd_kcontrol *kcontrol, int event) 1046 { 1047 struct snd_soc_component *component = 1048 snd_soc_dapm_to_component(w->dapm); 1049 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1050 unsigned char ps0 = 0x0, ps3 = 0x3; 1051 1052 switch (event) { 1053 case SND_SOC_DAPM_POST_PMU: 1054 regmap_write(rt1320->regmap, 1055 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1056 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1057 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 1058 break; 1059 case SND_SOC_DAPM_PRE_PMD: 1060 regmap_write(rt1320->regmap, 1061 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1062 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1063 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 1073 struct snd_ctl_elem_value *ucontrol) 1074 { 1075 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1076 struct soc_mixer_control *mc = 1077 (struct soc_mixer_control *)kcontrol->private_value; 1078 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1079 unsigned int gain_l_val, gain_r_val; 1080 unsigned int lvalue, rvalue; 1081 const unsigned int interval_offset = 0xc0; 1082 unsigned int changed = 0, reg_base; 1083 struct rt_sdca_dmic_kctrl_priv *p; 1084 unsigned int regvalue[4], gain_val[4], i; 1085 int err; 1086 1087 if (strstr(ucontrol->id.name, "FU Capture Volume")) 1088 goto _dmic_vol_; 1089 1090 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 1091 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 1092 1093 /* L Channel */ 1094 gain_l_val = ucontrol->value.integer.value[0]; 1095 if (gain_l_val > mc->max) 1096 gain_l_val = mc->max; 1097 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 1098 gain_l_val &= 0xffff; 1099 1100 /* R Channel */ 1101 gain_r_val = ucontrol->value.integer.value[1]; 1102 if (gain_r_val > mc->max) 1103 gain_r_val = mc->max; 1104 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 1105 gain_r_val &= 0xffff; 1106 1107 if (lvalue == gain_l_val && rvalue == gain_r_val) 1108 return 0; 1109 1110 /* Lch*/ 1111 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 1112 /* Rch */ 1113 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 1114 goto _done_; 1115 1116 _dmic_vol_: 1117 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1118 1119 /* check all channels */ 1120 for (i = 0; i < p->count; i++) { 1121 switch (rt1320->dev_id) { 1122 case RT1320_DEV_ID: 1123 if (i < 2) { 1124 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1125 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 1126 } else { 1127 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1128 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 1129 } 1130 break; 1131 case RT1321_DEV_ID: 1132 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1133 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 1134 break; 1135 } 1136 1137 gain_val[i] = ucontrol->value.integer.value[i]; 1138 if (gain_val[i] > p->max) 1139 gain_val[i] = p->max; 1140 1141 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 1142 gain_val[i] &= 0xffff; 1143 if (regvalue[i] != gain_val[i]) 1144 changed = 1; 1145 } 1146 1147 if (!changed) 1148 return 0; 1149 1150 for (i = 0; i < p->count; i++) { 1151 switch (rt1320->dev_id) { 1152 case RT1320_DEV_ID: 1153 if (i < 2) { 1154 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1155 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 1156 } else { 1157 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1158 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 1159 } 1160 break; 1161 case RT1321_DEV_ID: 1162 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1163 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 1164 break; 1165 } 1166 1167 if (err < 0) 1168 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 1169 } 1170 1171 _done_: 1172 return 1; 1173 } 1174 1175 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 1176 struct snd_ctl_elem_value *ucontrol) 1177 { 1178 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1179 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1180 struct soc_mixer_control *mc = 1181 (struct soc_mixer_control *)kcontrol->private_value; 1182 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 1183 const unsigned int interval_offset = 0xc0; 1184 unsigned int reg_base, regvalue, ctl, i; 1185 struct rt_sdca_dmic_kctrl_priv *p; 1186 1187 if (strstr(ucontrol->id.name, "FU Capture Volume")) 1188 goto _dmic_vol_; 1189 1190 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 1191 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 1192 1193 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 1194 1195 if (read_l != read_r) 1196 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 1197 else 1198 ctl_r = ctl_l; 1199 1200 ucontrol->value.integer.value[0] = ctl_l; 1201 ucontrol->value.integer.value[1] = ctl_r; 1202 goto _done_; 1203 1204 _dmic_vol_: 1205 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1206 1207 /* check all channels */ 1208 for (i = 0; i < p->count; i++) { 1209 switch (rt1320->dev_id) { 1210 case RT1320_DEV_ID: 1211 if (i < 2) { 1212 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1213 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 1214 } else { 1215 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1216 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 1217 } 1218 break; 1219 case RT1321_DEV_ID: 1220 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 1221 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 1222 break; 1223 } 1224 1225 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 1226 ucontrol->value.integer.value[i] = ctl; 1227 } 1228 _done_: 1229 return 0; 1230 } 1231 1232 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 1233 { 1234 int err, i; 1235 unsigned int ch_mute; 1236 1237 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 1238 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 1239 1240 switch (rt1320->dev_id) { 1241 case RT1320_DEV_ID: 1242 if (i < 2) 1243 err = regmap_write(rt1320->regmap, 1244 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 1245 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 1246 else 1247 err = regmap_write(rt1320->regmap, 1248 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 1249 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 1250 break; 1251 case RT1321_DEV_ID: 1252 err = regmap_write(rt1320->regmap, 1253 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 1254 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 1255 break; 1256 default: 1257 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1258 return -EINVAL; 1259 } 1260 if (err < 0) 1261 return err; 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 1268 struct snd_ctl_elem_value *ucontrol) 1269 { 1270 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1271 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1272 struct rt_sdca_dmic_kctrl_priv *p = 1273 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1274 unsigned int i; 1275 1276 for (i = 0; i < p->count; i++) 1277 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 1278 1279 return 0; 1280 } 1281 1282 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 1283 struct snd_ctl_elem_value *ucontrol) 1284 { 1285 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1286 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1287 struct rt_sdca_dmic_kctrl_priv *p = 1288 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1289 int err, changed = 0, i; 1290 1291 for (i = 0; i < p->count; i++) { 1292 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 1293 changed = 1; 1294 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 1295 } 1296 1297 err = rt1320_set_fu_capture_ctl(rt1320); 1298 if (err < 0) 1299 return err; 1300 1301 return changed; 1302 } 1303 1304 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 1305 struct snd_ctl_elem_info *uinfo) 1306 { 1307 struct rt_sdca_dmic_kctrl_priv *p = 1308 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1309 1310 if (p->max == 1) 1311 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1312 else 1313 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1314 uinfo->count = p->count; 1315 uinfo->value.integer.min = 0; 1316 uinfo->value.integer.max = p->max; 1317 return 0; 1318 } 1319 1320 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 1321 struct snd_kcontrol *kcontrol, int event) 1322 { 1323 struct snd_soc_component *component = 1324 snd_soc_dapm_to_component(w->dapm); 1325 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1326 1327 switch (event) { 1328 case SND_SOC_DAPM_POST_PMU: 1329 rt1320->fu_dapm_mute = false; 1330 rt1320_set_fu_capture_ctl(rt1320); 1331 break; 1332 case SND_SOC_DAPM_PRE_PMD: 1333 rt1320->fu_dapm_mute = true; 1334 rt1320_set_fu_capture_ctl(rt1320); 1335 break; 1336 } 1337 return 0; 1338 } 1339 1340 static const char * const rt1320_rx_data_ch_select[] = { 1341 "L,R", 1342 "R,L", 1343 "L,L", 1344 "R,R", 1345 "L,L+R", 1346 "R,L+R", 1347 "L+R,L", 1348 "L+R,R", 1349 "L+R,L+R", 1350 }; 1351 1352 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 1353 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 1354 rt1320_rx_data_ch_select); 1355 1356 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 1357 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 1358 1359 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 1360 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 1361 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1362 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 1363 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 1364 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 1365 1366 RT_SDCA_FU_CTRL("FU Capture Switch", 1367 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1368 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 1369 RT_SDCA_EXT_TLV("FU Capture Volume", 1370 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1371 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 1372 }; 1373 1374 static const struct snd_kcontrol_new rt1320_spk_l_dac = 1375 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1376 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1377 0, 1, 1); 1378 static const struct snd_kcontrol_new rt1320_spk_r_dac = 1379 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1380 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 1381 0, 1, 1); 1382 1383 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 1384 /* Audio Interface */ 1385 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 1386 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 1387 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 1388 1389 /* Digital Interface */ 1390 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 1391 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1392 rt1320_pde23_event, 1393 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1394 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1395 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1396 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 1397 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 1398 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 1399 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1400 1401 /* Output */ 1402 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 1403 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 1404 SND_SOC_DAPM_OUTPUT("SPOL"), 1405 SND_SOC_DAPM_OUTPUT("SPOR"), 1406 1407 /* Input */ 1408 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 1409 SND_SOC_DAPM_SIGGEN("AEC Gen"), 1410 SND_SOC_DAPM_INPUT("DMIC1"), 1411 SND_SOC_DAPM_INPUT("DMIC2"), 1412 }; 1413 1414 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 1415 { "FU21", NULL, "DP1RX" }, 1416 { "FU21", NULL, "PDE 23" }, 1417 { "OT23 L", "Switch", "FU21" }, 1418 { "OT23 R", "Switch", "FU21" }, 1419 { "SPOL", NULL, "OT23 L" }, 1420 { "SPOR", NULL, "OT23 R" }, 1421 1422 { "AEC Data", NULL, "AEC Gen" }, 1423 { "DP4TX", NULL, "AEC Data" }, 1424 1425 {"DP8-10TX", NULL, "FU"}, 1426 {"FU", NULL, "PDE 11"}, 1427 {"FU", NULL, "FU 113"}, 1428 {"FU", NULL, "FU 14"}, 1429 {"FU 113", NULL, "DMIC1"}, 1430 {"FU 14", NULL, "DMIC2"}, 1431 }; 1432 1433 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1434 int direction) 1435 { 1436 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1437 return 0; 1438 } 1439 1440 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 1441 struct snd_soc_dai *dai) 1442 { 1443 snd_soc_dai_set_dma_data(dai, substream, NULL); 1444 } 1445 1446 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 1447 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1448 { 1449 struct snd_soc_component *component = dai->component; 1450 struct rt1320_sdw_priv *rt1320 = 1451 snd_soc_component_get_drvdata(component); 1452 struct sdw_stream_config stream_config; 1453 struct sdw_port_config port_config; 1454 struct sdw_port_config dmic_port_config[2]; 1455 struct sdw_stream_runtime *sdw_stream; 1456 int retval; 1457 unsigned int sampling_rate; 1458 1459 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1460 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1461 1462 if (!sdw_stream) 1463 return -EINVAL; 1464 1465 if (!rt1320->sdw_slave) 1466 return -EINVAL; 1467 1468 /* SoundWire specific configuration */ 1469 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 1470 1471 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1472 if (dai->id == RT1320_AIF1) 1473 port_config.num = 1; 1474 else 1475 return -EINVAL; 1476 } else { 1477 if (dai->id == RT1320_AIF1) 1478 port_config.num = 4; 1479 else if (dai->id == RT1320_AIF2) { 1480 switch (rt1320->dev_id) { 1481 case RT1320_DEV_ID: 1482 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1483 dmic_port_config[0].num = 8; 1484 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 1485 dmic_port_config[1].num = 10; 1486 break; 1487 case RT1321_DEV_ID: 1488 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1489 dmic_port_config[0].num = 8; 1490 break; 1491 default: 1492 return -EINVAL; 1493 } 1494 } else 1495 return -EINVAL; 1496 } 1497 1498 if (dai->id == RT1320_AIF1) 1499 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1500 &port_config, 1, sdw_stream); 1501 else if (dai->id == RT1320_AIF2) { 1502 switch (rt1320->dev_id) { 1503 case RT1320_DEV_ID: 1504 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1505 dmic_port_config, 2, sdw_stream); 1506 break; 1507 case RT1321_DEV_ID: 1508 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1509 dmic_port_config, 1, sdw_stream); 1510 break; 1511 default: 1512 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1513 return -EINVAL; 1514 } 1515 } else 1516 return -EINVAL; 1517 if (retval) { 1518 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1519 return retval; 1520 } 1521 1522 /* sampling rate configuration */ 1523 switch (params_rate(params)) { 1524 case 16000: 1525 sampling_rate = RT1320_SDCA_RATE_16000HZ; 1526 break; 1527 case 32000: 1528 sampling_rate = RT1320_SDCA_RATE_32000HZ; 1529 break; 1530 case 44100: 1531 sampling_rate = RT1320_SDCA_RATE_44100HZ; 1532 break; 1533 case 48000: 1534 sampling_rate = RT1320_SDCA_RATE_48000HZ; 1535 break; 1536 case 96000: 1537 sampling_rate = RT1320_SDCA_RATE_96000HZ; 1538 break; 1539 case 192000: 1540 sampling_rate = RT1320_SDCA_RATE_192000HZ; 1541 break; 1542 default: 1543 dev_err(component->dev, "%s: Rate %d is not supported\n", 1544 __func__, params_rate(params)); 1545 return -EINVAL; 1546 } 1547 1548 /* set sampling frequency */ 1549 if (dai->id == RT1320_AIF1) 1550 regmap_write(rt1320->regmap, 1551 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1552 sampling_rate); 1553 else { 1554 regmap_write(rt1320->regmap, 1555 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1556 sampling_rate); 1557 1558 if (rt1320->dev_id == RT1320_DEV_ID) 1559 regmap_write(rt1320->regmap, 1560 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1561 sampling_rate); 1562 } 1563 1564 return 0; 1565 } 1566 1567 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 1568 struct snd_soc_dai *dai) 1569 { 1570 struct snd_soc_component *component = dai->component; 1571 struct rt1320_sdw_priv *rt1320 = 1572 snd_soc_component_get_drvdata(component); 1573 struct sdw_stream_runtime *sdw_stream = 1574 snd_soc_dai_get_dma_data(dai, substream); 1575 1576 if (!rt1320->sdw_slave) 1577 return -EINVAL; 1578 1579 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 1580 return 0; 1581 } 1582 1583 /* 1584 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 1585 * port_prep are not defined for now 1586 */ 1587 static const struct sdw_slave_ops rt1320_slave_ops = { 1588 .read_prop = rt1320_read_prop, 1589 .update_status = rt1320_update_status, 1590 }; 1591 1592 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 1593 { 1594 int ret; 1595 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1596 1597 rt1320->component = component; 1598 1599 if (!rt1320->first_hw_init) 1600 return 0; 1601 1602 ret = pm_runtime_resume(component->dev); 1603 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 1604 if (ret < 0 && ret != -EACCES) 1605 return ret; 1606 1607 return 0; 1608 } 1609 1610 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 1611 .probe = rt1320_sdw_component_probe, 1612 .controls = rt1320_snd_controls, 1613 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 1614 .dapm_widgets = rt1320_dapm_widgets, 1615 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 1616 .dapm_routes = rt1320_dapm_routes, 1617 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 1618 .endianness = 1, 1619 }; 1620 1621 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 1622 .hw_params = rt1320_sdw_hw_params, 1623 .hw_free = rt1320_sdw_pcm_hw_free, 1624 .set_stream = rt1320_set_sdw_stream, 1625 .shutdown = rt1320_sdw_shutdown, 1626 }; 1627 1628 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 1629 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1630 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1631 SNDRV_PCM_FMTBIT_S32_LE) 1632 1633 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 1634 { 1635 .name = "rt1320-aif1", 1636 .id = RT1320_AIF1, 1637 .playback = { 1638 .stream_name = "DP1 Playback", 1639 .channels_min = 1, 1640 .channels_max = 2, 1641 .rates = RT1320_STEREO_RATES, 1642 .formats = RT1320_FORMATS, 1643 }, 1644 .capture = { 1645 .stream_name = "DP4 Capture", 1646 .channels_min = 1, 1647 .channels_max = 2, 1648 .rates = RT1320_STEREO_RATES, 1649 .formats = RT1320_FORMATS, 1650 }, 1651 .ops = &rt1320_aif_dai_ops, 1652 }, 1653 /* DMIC: DP8 2ch + DP10 2ch */ 1654 { 1655 .name = "rt1320-aif2", 1656 .id = RT1320_AIF2, 1657 .capture = { 1658 .stream_name = "DP8-10 Capture", 1659 .channels_min = 1, 1660 .channels_max = 4, 1661 .rates = RT1320_STEREO_RATES, 1662 .formats = RT1320_FORMATS, 1663 }, 1664 .ops = &rt1320_aif_dai_ops, 1665 }, 1666 }; 1667 1668 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 1669 struct regmap *mbq_regmap, struct sdw_slave *slave) 1670 { 1671 struct rt1320_sdw_priv *rt1320; 1672 int ret; 1673 1674 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 1675 if (!rt1320) 1676 return -ENOMEM; 1677 1678 dev_set_drvdata(dev, rt1320); 1679 rt1320->sdw_slave = slave; 1680 rt1320->mbq_regmap = mbq_regmap; 1681 rt1320->regmap = regmap; 1682 1683 regcache_cache_only(rt1320->regmap, true); 1684 regcache_cache_only(rt1320->mbq_regmap, true); 1685 1686 /* 1687 * Mark hw_init to false 1688 * HW init will be performed when device reports present 1689 */ 1690 rt1320->hw_init = false; 1691 rt1320->first_hw_init = false; 1692 rt1320->version_id = -1; 1693 rt1320->fu_dapm_mute = true; 1694 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 1695 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 1696 1697 ret = devm_snd_soc_register_component(dev, 1698 &soc_component_sdw_rt1320, 1699 rt1320_sdw_dai, 1700 ARRAY_SIZE(rt1320_sdw_dai)); 1701 if (ret < 0) 1702 return ret; 1703 1704 /* set autosuspend parameters */ 1705 pm_runtime_set_autosuspend_delay(dev, 3000); 1706 pm_runtime_use_autosuspend(dev); 1707 1708 /* make sure the device does not suspend immediately */ 1709 pm_runtime_mark_last_busy(dev); 1710 1711 pm_runtime_enable(dev); 1712 1713 /* important note: the device is NOT tagged as 'active' and will remain 1714 * 'suspended' until the hardware is enumerated/initialized. This is required 1715 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 1716 * fail with -EACCESS because of race conditions between card creation and enumeration 1717 */ 1718 1719 dev_dbg(dev, "%s\n", __func__); 1720 1721 return ret; 1722 } 1723 1724 static int rt1320_sdw_probe(struct sdw_slave *slave, 1725 const struct sdw_device_id *id) 1726 { 1727 struct regmap *regmap, *mbq_regmap; 1728 1729 /* Regmap Initialization */ 1730 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 1731 if (IS_ERR(mbq_regmap)) 1732 return PTR_ERR(mbq_regmap); 1733 1734 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 1735 if (IS_ERR(regmap)) 1736 return PTR_ERR(regmap); 1737 1738 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 1739 } 1740 1741 static int rt1320_sdw_remove(struct sdw_slave *slave) 1742 { 1743 pm_runtime_disable(&slave->dev); 1744 1745 return 0; 1746 } 1747 1748 /* 1749 * Version A/B will use the class id 0 1750 * The newer version than A/B will use the class id 1, so add it in advance 1751 */ 1752 static const struct sdw_device_id rt1320_id[] = { 1753 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 1754 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 1755 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0), 1756 {}, 1757 }; 1758 MODULE_DEVICE_TABLE(sdw, rt1320_id); 1759 1760 static int rt1320_dev_suspend(struct device *dev) 1761 { 1762 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1763 1764 if (!rt1320->hw_init) 1765 return 0; 1766 1767 regcache_cache_only(rt1320->regmap, true); 1768 regcache_cache_only(rt1320->mbq_regmap, true); 1769 return 0; 1770 } 1771 1772 #define RT1320_PROBE_TIMEOUT 5000 1773 1774 static int rt1320_dev_resume(struct device *dev) 1775 { 1776 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1777 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1778 unsigned long time; 1779 1780 if (!rt1320->first_hw_init) 1781 return 0; 1782 1783 if (!slave->unattach_request) 1784 goto regmap_sync; 1785 1786 time = wait_for_completion_timeout(&slave->initialization_complete, 1787 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 1788 if (!time) { 1789 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 1790 return -ETIMEDOUT; 1791 } 1792 1793 regmap_sync: 1794 slave->unattach_request = 0; 1795 regcache_cache_only(rt1320->regmap, false); 1796 regcache_sync(rt1320->regmap); 1797 regcache_cache_only(rt1320->mbq_regmap, false); 1798 regcache_sync(rt1320->mbq_regmap); 1799 return 0; 1800 } 1801 1802 static const struct dev_pm_ops rt1320_pm = { 1803 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 1804 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 1805 }; 1806 1807 static struct sdw_driver rt1320_sdw_driver = { 1808 .driver = { 1809 .name = "rt1320-sdca", 1810 .pm = pm_ptr(&rt1320_pm), 1811 }, 1812 .probe = rt1320_sdw_probe, 1813 .remove = rt1320_sdw_remove, 1814 .ops = &rt1320_slave_ops, 1815 .id_table = rt1320_id, 1816 }; 1817 module_sdw_driver(rt1320_sdw_driver); 1818 1819 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 1820 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 1821 MODULE_LICENSE("GPL"); 1822