1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 #include "rt-sdw-common.h" 25 26 /* 27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 28 * It might include vendor-specific or SDCA control registers. 29 */ 30 static const struct reg_sequence rt1320_blind_write[] = { 31 { 0xc003, 0xe0 }, 32 { 0xc01b, 0xfc }, 33 { 0xc5c3, 0xf2 }, 34 { 0xc5c2, 0x00 }, 35 { 0xc5c6, 0x10 }, 36 { 0xc5c4, 0x12 }, 37 { 0xc5c8, 0x03 }, 38 { 0xc5d8, 0x0a }, 39 { 0xc5f7, 0x22 }, 40 { 0xc5f6, 0x22 }, 41 { 0xc5d0, 0x0f }, 42 { 0xc5d1, 0x89 }, 43 { 0xc057, 0x51 }, 44 { 0xc054, 0x35 }, 45 { 0xc053, 0x55 }, 46 { 0xc052, 0x55 }, 47 { 0xc051, 0x13 }, 48 { 0xc050, 0x15 }, 49 { 0xc060, 0x77 }, 50 { 0xc061, 0x55 }, 51 { 0xc063, 0x55 }, 52 { 0xc065, 0xa5 }, 53 { 0xc06b, 0x0a }, 54 { 0xca05, 0xd6 }, 55 { 0xca25, 0xd6 }, 56 { 0xcd00, 0x05 }, 57 { 0xc604, 0x40 }, 58 { 0xc609, 0x40 }, 59 { 0xc046, 0xff }, 60 { 0xc045, 0xff }, 61 { 0xc044, 0xff }, 62 { 0xc043, 0xff }, 63 { 0xc042, 0xff }, 64 { 0xc041, 0xff }, 65 { 0xc040, 0xff }, 66 { 0xcc10, 0x01 }, 67 { 0xc700, 0xf0 }, 68 { 0xc701, 0x13 }, 69 { 0xc901, 0x04 }, 70 { 0xc900, 0x73 }, 71 { 0xde03, 0x05 }, 72 { 0xdd0b, 0x0d }, 73 { 0xdd0a, 0xff }, 74 { 0xdd09, 0x0d }, 75 { 0xdd08, 0xff }, 76 { 0xc570, 0x08 }, 77 { 0xe803, 0xbe }, 78 { 0xc003, 0xc0 }, 79 { 0xc081, 0xfe }, 80 { 0xce31, 0x0d }, 81 { 0xce30, 0xae }, 82 { 0xce37, 0x0b }, 83 { 0xce36, 0xd2 }, 84 { 0xce39, 0x04 }, 85 { 0xce38, 0x80 }, 86 { 0xce3f, 0x00 }, 87 { 0xce3e, 0x00 }, 88 { 0xd470, 0x8b }, 89 { 0xd471, 0x18 }, 90 { 0xc019, 0x10 }, 91 { 0xd487, 0x3f }, 92 { 0xd486, 0xc3 }, 93 { 0x3fc2bfc7, 0x00 }, 94 { 0x3fc2bfc6, 0x00 }, 95 { 0x3fc2bfc5, 0x00 }, 96 { 0x3fc2bfc4, 0x01 }, 97 { 0x0000d486, 0x43 }, 98 { 0x1000db00, 0x02 }, 99 { 0x1000db01, 0x00 }, 100 { 0x1000db02, 0x11 }, 101 { 0x1000db03, 0x00 }, 102 { 0x1000db04, 0x00 }, 103 { 0x1000db05, 0x82 }, 104 { 0x1000db06, 0x04 }, 105 { 0x1000db07, 0xf1 }, 106 { 0x1000db08, 0x00 }, 107 { 0x1000db09, 0x00 }, 108 { 0x1000db0a, 0x40 }, 109 { 0x0000d540, 0x01 }, 110 { 0xd172, 0x2a }, 111 { 0xc5d6, 0x01 }, 112 }; 113 114 static const struct reg_sequence rt1320_vc_blind_write[] = { 115 { 0xc003, 0xe0 }, 116 { 0xe80a, 0x01 }, 117 { 0xc5c3, 0xf3 }, 118 { 0xc057, 0x51 }, 119 { 0xc054, 0x35 }, 120 { 0xca05, 0xd6 }, 121 { 0xca07, 0x07 }, 122 { 0xca25, 0xd6 }, 123 { 0xca27, 0x07 }, 124 { 0xc604, 0x40 }, 125 { 0xc609, 0x40 }, 126 { 0xc046, 0xff }, 127 { 0xc045, 0xff }, 128 { 0xda81, 0x14 }, 129 { 0xda8d, 0x14 }, 130 { 0xc044, 0xff }, 131 { 0xc043, 0xff }, 132 { 0xc042, 0xff }, 133 { 0xc041, 0x7f }, 134 { 0xc040, 0xff }, 135 { 0xcc10, 0x01 }, 136 { 0xc700, 0xf0 }, 137 { 0xc701, 0x13 }, 138 { 0xc901, 0x09 }, 139 { 0xc900, 0xd0 }, 140 { 0xde03, 0x05 }, 141 { 0xdd0b, 0x0d }, 142 { 0xdd0a, 0xff }, 143 { 0xdd09, 0x0d }, 144 { 0xdd08, 0xff }, 145 { 0xc570, 0x08 }, 146 { 0xc086, 0x02 }, 147 { 0xc085, 0x7f }, 148 { 0xc084, 0x00 }, 149 { 0xc081, 0xfe }, 150 { 0xf084, 0x0f }, 151 { 0xf083, 0xff }, 152 { 0xf082, 0xff }, 153 { 0xf081, 0xff }, 154 { 0xf080, 0xff }, 155 { 0xe802, 0xf8 }, 156 { 0xe803, 0xbe }, 157 { 0xc003, 0xc0 }, 158 { 0xd470, 0xec }, 159 { 0xd471, 0x3a }, 160 { 0xd474, 0x11 }, 161 { 0xd475, 0x32 }, 162 { 0xd478, 0x64 }, 163 { 0xd479, 0x20 }, 164 { 0xd47a, 0x10 }, 165 { 0xd47c, 0xff }, 166 { 0xc019, 0x10 }, 167 { 0xd487, 0x0b }, 168 { 0xd487, 0x3b }, 169 { 0xd486, 0xc3 }, 170 { 0xc598, 0x04 }, 171 { 0xdb03, 0xf0 }, 172 { 0xdb09, 0x00 }, 173 { 0xdb08, 0x7a }, 174 { 0xdb19, 0x02 }, 175 { 0xdb07, 0x5a }, 176 { 0xdb05, 0x45 }, 177 { 0xd500, 0x00 }, 178 { 0xd500, 0x17 }, 179 { 0xd600, 0x01 }, 180 { 0xd601, 0x02 }, 181 { 0xd602, 0x03 }, 182 { 0xd603, 0x04 }, 183 { 0xd64c, 0x03 }, 184 { 0xd64d, 0x03 }, 185 { 0xd64e, 0x03 }, 186 { 0xd64f, 0x03 }, 187 { 0xd650, 0x03 }, 188 { 0xd651, 0x03 }, 189 { 0xd652, 0x03 }, 190 { 0xd610, 0x01 }, 191 { 0xd608, 0x03 }, 192 { 0xd609, 0x00 }, 193 { 0x3fc2bf83, 0x00 }, 194 { 0x3fc2bf82, 0x00 }, 195 { 0x3fc2bf81, 0x00 }, 196 { 0x3fc2bf80, 0x00 }, 197 { 0x3fc2bfc7, 0x00 }, 198 { 0x3fc2bfc6, 0x00 }, 199 { 0x3fc2bfc5, 0x00 }, 200 { 0x3fc2bfc4, 0x00 }, 201 { 0x3fc2bfc3, 0x00 }, 202 { 0x3fc2bfc2, 0x00 }, 203 { 0x3fc2bfc1, 0x00 }, 204 { 0x3fc2bfc0, 0x03 }, 205 { 0x0000d486, 0x43 }, 206 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 207 { 0x1000db00, 0x04 }, 208 { 0x1000db01, 0x00 }, 209 { 0x1000db02, 0x11 }, 210 { 0x1000db03, 0x00 }, 211 { 0x1000db04, 0x00 }, 212 { 0x1000db05, 0x82 }, 213 { 0x1000db06, 0x04 }, 214 { 0x1000db07, 0xf1 }, 215 { 0x1000db08, 0x00 }, 216 { 0x1000db09, 0x00 }, 217 { 0x1000db0a, 0x40 }, 218 { 0x1000db0b, 0x02 }, 219 { 0x1000db0c, 0xf2 }, 220 { 0x1000db0d, 0x00 }, 221 { 0x1000db0e, 0x00 }, 222 { 0x1000db0f, 0xe0 }, 223 { 0x1000db10, 0x00 }, 224 { 0x1000db11, 0x10 }, 225 { 0x1000db12, 0x00 }, 226 { 0x1000db13, 0x00 }, 227 { 0x1000db14, 0x45 }, 228 { 0x0000d540, 0x01 }, 229 { 0x0000c081, 0xfc }, 230 { 0x0000f01e, 0x80 }, 231 { 0xc01b, 0xfc }, 232 { 0xc5d1, 0x89 }, 233 { 0xc5d8, 0x0a }, 234 { 0xc5f7, 0x22 }, 235 { 0xc5f6, 0x22 }, 236 { 0xc065, 0xa5 }, 237 { 0xc06b, 0x0a }, 238 { 0xd172, 0x2a }, 239 { 0xc5d6, 0x01 }, 240 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 241 }; 242 243 static const struct reg_default rt1320_reg_defaults[] = { 244 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 245 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 246 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 247 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 248 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 249 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 250 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 251 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 252 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 253 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 254 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 255 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 256 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 257 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 258 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 259 }; 260 261 static const struct reg_default rt1320_mbq_defaults[] = { 262 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 263 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 264 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 265 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 266 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 267 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 268 }; 269 270 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 271 { 272 switch (reg) { 273 case 0xc000 ... 0xc086: 274 case 0xc400 ... 0xc409: 275 case 0xc480 ... 0xc48f: 276 case 0xc4c0 ... 0xc4c4: 277 case 0xc4e0 ... 0xc4e7: 278 case 0xc500: 279 case 0xc560 ... 0xc56b: 280 case 0xc570: 281 case 0xc580 ... 0xc59a: 282 case 0xc5b0 ... 0xc60f: 283 case 0xc640 ... 0xc64f: 284 case 0xc670: 285 case 0xc680 ... 0xc683: 286 case 0xc700 ... 0xc76f: 287 case 0xc800 ... 0xc801: 288 case 0xc820: 289 case 0xc900 ... 0xc901: 290 case 0xc920 ... 0xc921: 291 case 0xca00 ... 0xca07: 292 case 0xca20 ... 0xca27: 293 case 0xca40 ... 0xca4b: 294 case 0xca60 ... 0xca68: 295 case 0xca80 ... 0xca88: 296 case 0xcb00 ... 0xcb0c: 297 case 0xcc00 ... 0xcc12: 298 case 0xcc80 ... 0xcc81: 299 case 0xcd00: 300 case 0xcd80 ... 0xcd82: 301 case 0xce00 ... 0xce4d: 302 case 0xcf00 ... 0xcf25: 303 case 0xd000 ... 0xd0ff: 304 case 0xd100 ... 0xd1ff: 305 case 0xd200 ... 0xd2ff: 306 case 0xd300 ... 0xd3ff: 307 case 0xd400 ... 0xd403: 308 case 0xd410 ... 0xd417: 309 case 0xd470 ... 0xd497: 310 case 0xd4dc ... 0xd50f: 311 case 0xd520 ... 0xd543: 312 case 0xd560 ... 0xd5ef: 313 case 0xd600 ... 0xd663: 314 case 0xda00 ... 0xda6e: 315 case 0xda80 ... 0xda9e: 316 case 0xdb00 ... 0xdb7f: 317 case 0xdc00: 318 case 0xdc20 ... 0xdc21: 319 case 0xdd00 ... 0xdd17: 320 case 0xde00 ... 0xde09: 321 case 0xdf00 ... 0xdf1b: 322 case 0xe000 ... 0xe847: 323 case 0xf01e: 324 case 0xf717 ... 0xf719: 325 case 0xf720 ... 0xf723: 326 case 0x1000cd91 ... 0x1000cd96: 327 case 0x1000f008: 328 case 0x1000f021: 329 case 0x3fe2e000 ... 0x3fe2e003: 330 case 0x3fc2ab80 ... 0x3fc2abd4: 331 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 332 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 333 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 334 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 335 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 336 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 337 /* 0x40880900/0x40880980 */ 338 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 339 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 340 /* 0x40881500 */ 341 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 342 /* 0x41000189/0x4100018a */ 343 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 344 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 345 /* 0x41001388 */ 346 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 347 /* 0x41001988 */ 348 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 349 /* 0x41080000 */ 350 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 351 /* 0x41080200 */ 352 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 353 /* 0x41080900 */ 354 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 355 /* 0x41080980 */ 356 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 357 /* 0x41081080 */ 358 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 359 /* 0x41081480/0x41081488 */ 360 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 361 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 362 /* 0x41081980 */ 363 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 364 return true; 365 default: 366 return false; 367 } 368 } 369 370 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 371 { 372 switch (reg) { 373 case 0xc000: 374 case 0xc003: 375 case 0xc081: 376 case 0xc402 ... 0xc406: 377 case 0xc48c ... 0xc48f: 378 case 0xc560: 379 case 0xc5b5 ... 0xc5b7: 380 case 0xc5fc ... 0xc5ff: 381 case 0xc820: 382 case 0xc900: 383 case 0xc920: 384 case 0xca42: 385 case 0xca62: 386 case 0xca82: 387 case 0xcd00: 388 case 0xce03: 389 case 0xce10: 390 case 0xce14 ... 0xce17: 391 case 0xce44 ... 0xce49: 392 case 0xce4c ... 0xce4d: 393 case 0xcf0c: 394 case 0xcf10 ... 0xcf25: 395 case 0xd486 ... 0xd487: 396 case 0xd4e5 ... 0xd4e6: 397 case 0xd4e8 ... 0xd4ff: 398 case 0xd530: 399 case 0xd540: 400 case 0xd543: 401 case 0xdb58 ... 0xdb5f: 402 case 0xdb60 ... 0xdb63: 403 case 0xdb68 ... 0xdb69: 404 case 0xdb6d: 405 case 0xdb70 ... 0xdb71: 406 case 0xdb76: 407 case 0xdb7a: 408 case 0xdb7c ... 0xdb7f: 409 case 0xdd0c ... 0xdd13: 410 case 0xde02: 411 case 0xdf14 ... 0xdf1b: 412 case 0xe83c ... 0xe847: 413 case 0xf01e: 414 case 0xf717 ... 0xf719: 415 case 0xf720 ... 0xf723: 416 case 0x10000000 ... 0x10007fff: 417 case 0x1000c000 ... 0x1000dfff: 418 case 0x1000f008: 419 case 0x1000f021: 420 case 0x3fc2ab80 ... 0x3fc2abd4: 421 case 0x3fc2bf80 ... 0x3fc2bf83: 422 case 0x3fc2bfc0 ... 0x3fc2bfc7: 423 case 0x3fe2e000 ... 0x3fe2e003: 424 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 425 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 426 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 427 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 428 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 429 return true; 430 default: 431 return false; 432 } 433 } 434 435 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 436 { 437 switch (reg) { 438 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 439 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 440 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 441 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 442 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 443 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 444 return true; 445 default: 446 return false; 447 } 448 } 449 450 static const struct regmap_config rt1320_sdw_regmap = { 451 .reg_bits = 32, 452 .val_bits = 8, 453 .readable_reg = rt1320_readable_register, 454 .volatile_reg = rt1320_volatile_register, 455 .max_register = 0x41081980, 456 .reg_defaults = rt1320_reg_defaults, 457 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 458 .cache_type = REGCACHE_MAPLE, 459 .use_single_read = true, 460 .use_single_write = true, 461 }; 462 463 static const struct regmap_config rt1320_mbq_regmap = { 464 .name = "sdw-mbq", 465 .reg_bits = 32, 466 .val_bits = 16, 467 .readable_reg = rt1320_mbq_readable_register, 468 .max_register = 0x41000192, 469 .reg_defaults = rt1320_mbq_defaults, 470 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 471 .cache_type = REGCACHE_MAPLE, 472 .use_single_read = true, 473 .use_single_write = true, 474 }; 475 476 static int rt1320_read_prop(struct sdw_slave *slave) 477 { 478 struct sdw_slave_prop *prop = &slave->prop; 479 int nval; 480 int i, j; 481 u32 bit; 482 unsigned long addr; 483 struct sdw_dpn_prop *dpn; 484 485 /* 486 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 487 */ 488 sdw_slave_read_prop(slave); 489 490 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 491 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 492 493 prop->paging_support = true; 494 prop->lane_control_support = true; 495 496 /* first we need to allocate memory for set bits in port lists */ 497 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 498 prop->sink_ports = BIT(1); 499 500 nval = hweight32(prop->source_ports); 501 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 502 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 503 if (!prop->src_dpn_prop) 504 return -ENOMEM; 505 506 i = 0; 507 dpn = prop->src_dpn_prop; 508 addr = prop->source_ports; 509 for_each_set_bit(bit, &addr, 32) { 510 dpn[i].num = bit; 511 dpn[i].type = SDW_DPN_FULL; 512 dpn[i].simple_ch_prep_sm = true; 513 dpn[i].ch_prep_timeout = 10; 514 i++; 515 } 516 517 /* do this again for sink now */ 518 nval = hweight32(prop->sink_ports); 519 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 520 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 521 if (!prop->sink_dpn_prop) 522 return -ENOMEM; 523 524 j = 0; 525 dpn = prop->sink_dpn_prop; 526 addr = prop->sink_ports; 527 for_each_set_bit(bit, &addr, 32) { 528 dpn[j].num = bit; 529 dpn[j].type = SDW_DPN_FULL; 530 dpn[j].simple_ch_prep_sm = true; 531 dpn[j].ch_prep_timeout = 10; 532 j++; 533 } 534 535 /* set the timeout values */ 536 prop->clk_stop_timeout = 64; 537 538 return 0; 539 } 540 541 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 542 unsigned char entity, unsigned char ps) 543 { 544 unsigned int delay = 1000, val; 545 546 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 547 548 /* waiting for Actual PDE becomes to PS0/PS3 */ 549 while (delay) { 550 regmap_read(rt1320->regmap, 551 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 552 if (val == ps) 553 break; 554 555 usleep_range(1000, 1500); 556 delay--; 557 } 558 if (!delay) { 559 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 560 return -ETIMEDOUT; 561 } 562 563 return 0; 564 } 565 566 /* 567 * The 'patch code' is written to the patch code area. 568 * The patch code area is used for SDCA register expansion flexibility. 569 */ 570 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 571 { 572 struct sdw_slave *slave = rt1320->sdw_slave; 573 const struct firmware *patch; 574 const char *filename; 575 unsigned int addr, val; 576 const unsigned char *ptr; 577 int ret, i; 578 579 if (rt1320->version_id <= RT1320_VB) 580 filename = RT1320_VAB_MCU_PATCH; 581 else 582 filename = RT1320_VC_MCU_PATCH; 583 584 /* load the patch code here */ 585 ret = request_firmware(&patch, filename, &slave->dev); 586 if (ret) { 587 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 588 regmap_write(rt1320->regmap, 0xc598, 0x00); 589 regmap_write(rt1320->regmap, 0x10007000, 0x67); 590 regmap_write(rt1320->regmap, 0x10007001, 0x80); 591 regmap_write(rt1320->regmap, 0x10007002, 0x00); 592 regmap_write(rt1320->regmap, 0x10007003, 0x00); 593 } else { 594 ptr = (const unsigned char *)patch->data; 595 if ((patch->size % 8) == 0) { 596 for (i = 0; i < patch->size; i += 8) { 597 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 598 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 599 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 600 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 601 602 if (addr > 0x10007fff || addr < 0x10007000) { 603 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 604 goto _exit_; 605 } 606 if (val > 0xff) { 607 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 608 goto _exit_; 609 } 610 regmap_write(rt1320->regmap, addr, val); 611 } 612 } 613 _exit_: 614 release_firmware(patch); 615 } 616 } 617 618 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 619 { 620 unsigned int i, reg, val, delay; 621 622 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 623 reg = rt1320_blind_write[i].reg; 624 val = rt1320_blind_write[i].def; 625 delay = rt1320_blind_write[i].delay_us; 626 627 if (reg == 0x3fc2bfc7) 628 rt1320_load_mcu_patch(rt1320); 629 630 regmap_write(rt1320->regmap, reg, val); 631 if (delay) 632 usleep_range(delay, delay + 1000); 633 } 634 } 635 636 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 637 { 638 struct sdw_slave *slave = rt1320->sdw_slave; 639 unsigned int i, reg, val, delay, retry, tmp; 640 641 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 642 reg = rt1320_vc_blind_write[i].reg; 643 val = rt1320_vc_blind_write[i].def; 644 delay = rt1320_vc_blind_write[i].delay_us; 645 646 if (reg == 0x3fc2bf83) 647 rt1320_load_mcu_patch(rt1320); 648 649 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 650 (val == 0x00)) { 651 retry = 200; 652 while (retry) { 653 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 654 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 655 if (tmp == 0x1f) 656 break; 657 usleep_range(1000, 1500); 658 retry--; 659 } 660 if (!retry) 661 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 662 } 663 regmap_write(rt1320->regmap, reg, val); 664 if (delay) 665 usleep_range(delay, delay + 1000); 666 667 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 668 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 669 } 670 } 671 672 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 673 { 674 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 675 unsigned int amp_func_status, val, tmp; 676 677 if (rt1320->hw_init) 678 return 0; 679 680 regcache_cache_only(rt1320->regmap, false); 681 regcache_cache_only(rt1320->mbq_regmap, false); 682 if (rt1320->first_hw_init) { 683 regcache_cache_bypass(rt1320->regmap, true); 684 regcache_cache_bypass(rt1320->mbq_regmap, true); 685 } else { 686 /* 687 * PM runtime status is marked as 'active' only when a Slave reports as Attached 688 */ 689 /* update count of parent 'active' children */ 690 pm_runtime_set_active(&slave->dev); 691 } 692 693 pm_runtime_get_noresume(&slave->dev); 694 695 if (rt1320->version_id < 0) { 696 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 697 rt1320->version_id = val; 698 } 699 700 regmap_read(rt1320->regmap, 701 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 702 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 703 704 /* initialization write */ 705 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 706 if (rt1320->version_id < RT1320_VC) 707 rt1320_vab_preset(rt1320); 708 else 709 rt1320_vc_preset(rt1320); 710 711 regmap_write(rt1320->regmap, 712 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 713 FUNCTION_NEEDS_INITIALIZATION); 714 } 715 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA) { 716 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 717 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 718 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 719 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 720 val = (tmp << 8) | val; 721 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 722 val = (tmp << 16) | val; 723 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 724 val = (tmp << 24) | val; 725 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 726 /* 727 * We call the version b which has the new DSP ROM code against version a. 728 * Therefore, we read the DSP address to check the ID. 729 */ 730 if (val == RT1320_VER_B_ID) 731 rt1320->version_id = RT1320_VB; 732 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 733 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 734 } 735 dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); 736 737 if (rt1320->first_hw_init) { 738 regcache_cache_bypass(rt1320->regmap, false); 739 regcache_cache_bypass(rt1320->mbq_regmap, false); 740 regcache_mark_dirty(rt1320->regmap); 741 regcache_mark_dirty(rt1320->mbq_regmap); 742 } 743 744 /* Mark Slave initialization complete */ 745 rt1320->first_hw_init = true; 746 rt1320->hw_init = true; 747 748 pm_runtime_mark_last_busy(&slave->dev); 749 pm_runtime_put_autosuspend(&slave->dev); 750 751 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 752 return 0; 753 } 754 755 static int rt1320_update_status(struct sdw_slave *slave, 756 enum sdw_slave_status status) 757 { 758 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 759 760 if (status == SDW_SLAVE_UNATTACHED) 761 rt1320->hw_init = false; 762 763 /* 764 * Perform initialization only if slave status is present and 765 * hw_init flag is false 766 */ 767 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 768 return 0; 769 770 /* perform I/O transfers required for Slave initialization */ 771 return rt1320_io_init(&slave->dev, slave); 772 } 773 774 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 775 struct snd_kcontrol *kcontrol, int event) 776 { 777 struct snd_soc_component *component = 778 snd_soc_dapm_to_component(w->dapm); 779 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 780 unsigned char ps0 = 0x0, ps3 = 0x3; 781 782 switch (event) { 783 case SND_SOC_DAPM_POST_PMU: 784 regmap_write(rt1320->regmap, 785 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 786 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 787 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 788 break; 789 case SND_SOC_DAPM_PRE_PMD: 790 regmap_write(rt1320->regmap, 791 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 792 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 793 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 794 break; 795 default: 796 break; 797 } 798 799 return 0; 800 } 801 802 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 803 struct snd_kcontrol *kcontrol, int event) 804 { 805 struct snd_soc_component *component = 806 snd_soc_dapm_to_component(w->dapm); 807 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 808 unsigned char ps0 = 0x0, ps3 = 0x3; 809 810 switch (event) { 811 case SND_SOC_DAPM_POST_PMU: 812 regmap_write(rt1320->regmap, 813 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 814 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 815 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 816 break; 817 case SND_SOC_DAPM_PRE_PMD: 818 regmap_write(rt1320->regmap, 819 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 820 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 821 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 822 break; 823 default: 824 break; 825 } 826 827 return 0; 828 } 829 830 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 831 struct snd_ctl_elem_value *ucontrol) 832 { 833 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 834 struct soc_mixer_control *mc = 835 (struct soc_mixer_control *)kcontrol->private_value; 836 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 837 unsigned int gain_l_val, gain_r_val; 838 unsigned int lvalue, rvalue; 839 const unsigned int interval_offset = 0xc0; 840 unsigned int changed = 0, reg_base; 841 struct rt_sdca_dmic_kctrl_priv *p; 842 unsigned int regvalue[4], gain_val[4], i; 843 int err; 844 845 if (strstr(ucontrol->id.name, "FU Capture Volume")) 846 goto _dmic_vol_; 847 848 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 849 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 850 851 /* L Channel */ 852 gain_l_val = ucontrol->value.integer.value[0]; 853 if (gain_l_val > mc->max) 854 gain_l_val = mc->max; 855 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 856 gain_l_val &= 0xffff; 857 858 /* R Channel */ 859 gain_r_val = ucontrol->value.integer.value[1]; 860 if (gain_r_val > mc->max) 861 gain_r_val = mc->max; 862 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 863 gain_r_val &= 0xffff; 864 865 if (lvalue == gain_l_val && rvalue == gain_r_val) 866 return 0; 867 868 /* Lch*/ 869 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 870 /* Rch */ 871 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 872 goto _done_; 873 874 _dmic_vol_: 875 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 876 877 /* check all channels */ 878 for (i = 0; i < p->count; i++) { 879 if (i < 2) { 880 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 881 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 882 } else { 883 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 884 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 885 } 886 887 gain_val[i] = ucontrol->value.integer.value[i]; 888 if (gain_val[i] > p->max) 889 gain_val[i] = p->max; 890 891 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 892 gain_val[i] &= 0xffff; 893 if (regvalue[i] != gain_val[i]) 894 changed = 1; 895 } 896 897 if (!changed) 898 return 0; 899 900 for (i = 0; i < p->count; i++) { 901 if (i < 2) { 902 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 903 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 904 } else { 905 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 906 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 907 } 908 909 if (err < 0) 910 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 911 } 912 913 _done_: 914 return 1; 915 } 916 917 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 918 struct snd_ctl_elem_value *ucontrol) 919 { 920 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 921 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 922 struct soc_mixer_control *mc = 923 (struct soc_mixer_control *)kcontrol->private_value; 924 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 925 const unsigned int interval_offset = 0xc0; 926 unsigned int reg_base, regvalue, ctl, i; 927 struct rt_sdca_dmic_kctrl_priv *p; 928 929 if (strstr(ucontrol->id.name, "FU Capture Volume")) 930 goto _dmic_vol_; 931 932 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 933 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 934 935 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 936 937 if (read_l != read_r) 938 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 939 else 940 ctl_r = ctl_l; 941 942 ucontrol->value.integer.value[0] = ctl_l; 943 ucontrol->value.integer.value[1] = ctl_r; 944 goto _done_; 945 946 _dmic_vol_: 947 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 948 949 /* check all channels */ 950 for (i = 0; i < p->count; i++) { 951 if (i < 2) { 952 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 953 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 954 } else { 955 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 956 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 957 } 958 959 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 960 ucontrol->value.integer.value[i] = ctl; 961 } 962 _done_: 963 return 0; 964 } 965 966 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 967 { 968 int err, i; 969 unsigned int ch_mute; 970 971 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 972 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 973 974 if (i < 2) 975 err = regmap_write(rt1320->regmap, 976 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 977 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 978 else 979 err = regmap_write(rt1320->regmap, 980 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 981 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 982 if (err < 0) 983 return err; 984 } 985 986 return 0; 987 } 988 989 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 990 struct snd_ctl_elem_value *ucontrol) 991 { 992 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 993 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 994 struct rt_sdca_dmic_kctrl_priv *p = 995 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 996 unsigned int i; 997 998 for (i = 0; i < p->count; i++) 999 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 1000 1001 return 0; 1002 } 1003 1004 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 1005 struct snd_ctl_elem_value *ucontrol) 1006 { 1007 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1008 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1009 struct rt_sdca_dmic_kctrl_priv *p = 1010 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1011 int err, changed = 0, i; 1012 1013 for (i = 0; i < p->count; i++) { 1014 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 1015 changed = 1; 1016 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 1017 } 1018 1019 err = rt1320_set_fu_capture_ctl(rt1320); 1020 if (err < 0) 1021 return err; 1022 1023 return changed; 1024 } 1025 1026 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 1027 struct snd_ctl_elem_info *uinfo) 1028 { 1029 struct rt_sdca_dmic_kctrl_priv *p = 1030 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1031 1032 if (p->max == 1) 1033 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1034 else 1035 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1036 uinfo->count = p->count; 1037 uinfo->value.integer.min = 0; 1038 uinfo->value.integer.max = p->max; 1039 return 0; 1040 } 1041 1042 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 1043 struct snd_kcontrol *kcontrol, int event) 1044 { 1045 struct snd_soc_component *component = 1046 snd_soc_dapm_to_component(w->dapm); 1047 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1048 1049 switch (event) { 1050 case SND_SOC_DAPM_POST_PMU: 1051 rt1320->fu_dapm_mute = false; 1052 rt1320_set_fu_capture_ctl(rt1320); 1053 break; 1054 case SND_SOC_DAPM_PRE_PMD: 1055 rt1320->fu_dapm_mute = true; 1056 rt1320_set_fu_capture_ctl(rt1320); 1057 break; 1058 } 1059 return 0; 1060 } 1061 1062 static const char * const rt1320_rx_data_ch_select[] = { 1063 "L,R", 1064 "R,L", 1065 "L,L", 1066 "R,R", 1067 "L,L+R", 1068 "R,L+R", 1069 "L+R,L", 1070 "L+R,R", 1071 "L+R,L+R", 1072 }; 1073 1074 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 1075 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 1076 rt1320_rx_data_ch_select); 1077 1078 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 1079 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 1080 1081 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 1082 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 1083 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1084 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 1085 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 1086 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 1087 1088 RT_SDCA_FU_CTRL("FU Capture Switch", 1089 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1090 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 1091 RT_SDCA_EXT_TLV("FU Capture Volume", 1092 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1093 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 1094 }; 1095 1096 static const struct snd_kcontrol_new rt1320_spk_l_dac = 1097 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1098 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1099 0, 1, 1); 1100 static const struct snd_kcontrol_new rt1320_spk_r_dac = 1101 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1102 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 1103 0, 1, 1); 1104 1105 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 1106 /* Audio Interface */ 1107 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 1108 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 1109 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 1110 1111 /* Digital Interface */ 1112 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 1113 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1114 rt1320_pde23_event, 1115 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1116 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1117 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1118 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 1119 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 1120 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 1121 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1122 1123 /* Output */ 1124 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 1125 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 1126 SND_SOC_DAPM_OUTPUT("SPOL"), 1127 SND_SOC_DAPM_OUTPUT("SPOR"), 1128 1129 /* Input */ 1130 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 1131 SND_SOC_DAPM_SIGGEN("AEC Gen"), 1132 SND_SOC_DAPM_INPUT("DMIC1"), 1133 SND_SOC_DAPM_INPUT("DMIC2"), 1134 }; 1135 1136 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 1137 { "FU21", NULL, "DP1RX" }, 1138 { "FU21", NULL, "PDE 23" }, 1139 { "OT23 L", "Switch", "FU21" }, 1140 { "OT23 R", "Switch", "FU21" }, 1141 { "SPOL", NULL, "OT23 L" }, 1142 { "SPOR", NULL, "OT23 R" }, 1143 1144 { "AEC Data", NULL, "AEC Gen" }, 1145 { "DP4TX", NULL, "AEC Data" }, 1146 1147 {"DP8-10TX", NULL, "FU"}, 1148 {"FU", NULL, "PDE 11"}, 1149 {"FU", NULL, "FU 113"}, 1150 {"FU", NULL, "FU 14"}, 1151 {"FU 113", NULL, "DMIC1"}, 1152 {"FU 14", NULL, "DMIC2"}, 1153 }; 1154 1155 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1156 int direction) 1157 { 1158 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1159 return 0; 1160 } 1161 1162 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 1163 struct snd_soc_dai *dai) 1164 { 1165 snd_soc_dai_set_dma_data(dai, substream, NULL); 1166 } 1167 1168 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 1169 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1170 { 1171 struct snd_soc_component *component = dai->component; 1172 struct rt1320_sdw_priv *rt1320 = 1173 snd_soc_component_get_drvdata(component); 1174 struct sdw_stream_config stream_config; 1175 struct sdw_port_config port_config; 1176 struct sdw_port_config dmic_port_config[2]; 1177 struct sdw_stream_runtime *sdw_stream; 1178 int retval; 1179 unsigned int sampling_rate; 1180 1181 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1182 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1183 1184 if (!sdw_stream) 1185 return -EINVAL; 1186 1187 if (!rt1320->sdw_slave) 1188 return -EINVAL; 1189 1190 /* SoundWire specific configuration */ 1191 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 1192 1193 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1194 if (dai->id == RT1320_AIF1) 1195 port_config.num = 1; 1196 else 1197 return -EINVAL; 1198 } else { 1199 if (dai->id == RT1320_AIF1) 1200 port_config.num = 4; 1201 else if (dai->id == RT1320_AIF2) { 1202 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1203 dmic_port_config[0].num = 8; 1204 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 1205 dmic_port_config[1].num = 10; 1206 } else 1207 return -EINVAL; 1208 } 1209 1210 if (dai->id == RT1320_AIF1) 1211 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1212 &port_config, 1, sdw_stream); 1213 else if (dai->id == RT1320_AIF2) 1214 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1215 dmic_port_config, 2, sdw_stream); 1216 else 1217 return -EINVAL; 1218 if (retval) { 1219 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1220 return retval; 1221 } 1222 1223 /* sampling rate configuration */ 1224 switch (params_rate(params)) { 1225 case 16000: 1226 sampling_rate = RT1320_SDCA_RATE_16000HZ; 1227 break; 1228 case 32000: 1229 sampling_rate = RT1320_SDCA_RATE_32000HZ; 1230 break; 1231 case 44100: 1232 sampling_rate = RT1320_SDCA_RATE_44100HZ; 1233 break; 1234 case 48000: 1235 sampling_rate = RT1320_SDCA_RATE_48000HZ; 1236 break; 1237 case 96000: 1238 sampling_rate = RT1320_SDCA_RATE_96000HZ; 1239 break; 1240 case 192000: 1241 sampling_rate = RT1320_SDCA_RATE_192000HZ; 1242 break; 1243 default: 1244 dev_err(component->dev, "%s: Rate %d is not supported\n", 1245 __func__, params_rate(params)); 1246 return -EINVAL; 1247 } 1248 1249 /* set sampling frequency */ 1250 if (dai->id == RT1320_AIF1) 1251 regmap_write(rt1320->regmap, 1252 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1253 sampling_rate); 1254 else { 1255 regmap_write(rt1320->regmap, 1256 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1257 sampling_rate); 1258 regmap_write(rt1320->regmap, 1259 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1260 sampling_rate); 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 1267 struct snd_soc_dai *dai) 1268 { 1269 struct snd_soc_component *component = dai->component; 1270 struct rt1320_sdw_priv *rt1320 = 1271 snd_soc_component_get_drvdata(component); 1272 struct sdw_stream_runtime *sdw_stream = 1273 snd_soc_dai_get_dma_data(dai, substream); 1274 1275 if (!rt1320->sdw_slave) 1276 return -EINVAL; 1277 1278 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 1279 return 0; 1280 } 1281 1282 /* 1283 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 1284 * port_prep are not defined for now 1285 */ 1286 static const struct sdw_slave_ops rt1320_slave_ops = { 1287 .read_prop = rt1320_read_prop, 1288 .update_status = rt1320_update_status, 1289 }; 1290 1291 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 1292 { 1293 int ret; 1294 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1295 1296 rt1320->component = component; 1297 1298 if (!rt1320->first_hw_init) 1299 return 0; 1300 1301 ret = pm_runtime_resume(component->dev); 1302 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 1303 if (ret < 0 && ret != -EACCES) 1304 return ret; 1305 1306 return 0; 1307 } 1308 1309 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 1310 .probe = rt1320_sdw_component_probe, 1311 .controls = rt1320_snd_controls, 1312 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 1313 .dapm_widgets = rt1320_dapm_widgets, 1314 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 1315 .dapm_routes = rt1320_dapm_routes, 1316 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 1317 .endianness = 1, 1318 }; 1319 1320 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 1321 .hw_params = rt1320_sdw_hw_params, 1322 .hw_free = rt1320_sdw_pcm_hw_free, 1323 .set_stream = rt1320_set_sdw_stream, 1324 .shutdown = rt1320_sdw_shutdown, 1325 }; 1326 1327 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 1328 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1329 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1330 SNDRV_PCM_FMTBIT_S32_LE) 1331 1332 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 1333 { 1334 .name = "rt1320-aif1", 1335 .id = RT1320_AIF1, 1336 .playback = { 1337 .stream_name = "DP1 Playback", 1338 .channels_min = 1, 1339 .channels_max = 2, 1340 .rates = RT1320_STEREO_RATES, 1341 .formats = RT1320_FORMATS, 1342 }, 1343 .capture = { 1344 .stream_name = "DP4 Capture", 1345 .channels_min = 1, 1346 .channels_max = 2, 1347 .rates = RT1320_STEREO_RATES, 1348 .formats = RT1320_FORMATS, 1349 }, 1350 .ops = &rt1320_aif_dai_ops, 1351 }, 1352 /* DMIC: DP8 2ch + DP10 2ch */ 1353 { 1354 .name = "rt1320-aif2", 1355 .id = RT1320_AIF2, 1356 .capture = { 1357 .stream_name = "DP8-10 Capture", 1358 .channels_min = 1, 1359 .channels_max = 4, 1360 .rates = RT1320_STEREO_RATES, 1361 .formats = RT1320_FORMATS, 1362 }, 1363 .ops = &rt1320_aif_dai_ops, 1364 }, 1365 }; 1366 1367 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 1368 struct regmap *mbq_regmap, struct sdw_slave *slave) 1369 { 1370 struct rt1320_sdw_priv *rt1320; 1371 int ret; 1372 1373 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 1374 if (!rt1320) 1375 return -ENOMEM; 1376 1377 dev_set_drvdata(dev, rt1320); 1378 rt1320->sdw_slave = slave; 1379 rt1320->mbq_regmap = mbq_regmap; 1380 rt1320->regmap = regmap; 1381 1382 regcache_cache_only(rt1320->regmap, true); 1383 regcache_cache_only(rt1320->mbq_regmap, true); 1384 1385 /* 1386 * Mark hw_init to false 1387 * HW init will be performed when device reports present 1388 */ 1389 rt1320->hw_init = false; 1390 rt1320->first_hw_init = false; 1391 rt1320->version_id = -1; 1392 rt1320->fu_dapm_mute = true; 1393 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 1394 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 1395 1396 ret = devm_snd_soc_register_component(dev, 1397 &soc_component_sdw_rt1320, 1398 rt1320_sdw_dai, 1399 ARRAY_SIZE(rt1320_sdw_dai)); 1400 if (ret < 0) 1401 return ret; 1402 1403 /* set autosuspend parameters */ 1404 pm_runtime_set_autosuspend_delay(dev, 3000); 1405 pm_runtime_use_autosuspend(dev); 1406 1407 /* make sure the device does not suspend immediately */ 1408 pm_runtime_mark_last_busy(dev); 1409 1410 pm_runtime_enable(dev); 1411 1412 /* important note: the device is NOT tagged as 'active' and will remain 1413 * 'suspended' until the hardware is enumerated/initialized. This is required 1414 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 1415 * fail with -EACCESS because of race conditions between card creation and enumeration 1416 */ 1417 1418 dev_dbg(dev, "%s\n", __func__); 1419 1420 return ret; 1421 } 1422 1423 static int rt1320_sdw_probe(struct sdw_slave *slave, 1424 const struct sdw_device_id *id) 1425 { 1426 struct regmap *regmap, *mbq_regmap; 1427 1428 /* Regmap Initialization */ 1429 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 1430 if (IS_ERR(mbq_regmap)) 1431 return PTR_ERR(mbq_regmap); 1432 1433 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 1434 if (IS_ERR(regmap)) 1435 return PTR_ERR(regmap); 1436 1437 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 1438 } 1439 1440 static int rt1320_sdw_remove(struct sdw_slave *slave) 1441 { 1442 pm_runtime_disable(&slave->dev); 1443 1444 return 0; 1445 } 1446 1447 /* 1448 * Version A/B will use the class id 0 1449 * The newer version than A/B will use the class id 1, so add it in advance 1450 */ 1451 static const struct sdw_device_id rt1320_id[] = { 1452 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 1453 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 1454 {}, 1455 }; 1456 MODULE_DEVICE_TABLE(sdw, rt1320_id); 1457 1458 static int __maybe_unused rt1320_dev_suspend(struct device *dev) 1459 { 1460 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1461 1462 if (!rt1320->hw_init) 1463 return 0; 1464 1465 regcache_cache_only(rt1320->regmap, true); 1466 regcache_cache_only(rt1320->mbq_regmap, true); 1467 return 0; 1468 } 1469 1470 #define RT1320_PROBE_TIMEOUT 5000 1471 1472 static int __maybe_unused rt1320_dev_resume(struct device *dev) 1473 { 1474 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1475 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1476 unsigned long time; 1477 1478 if (!rt1320->first_hw_init) 1479 return 0; 1480 1481 if (!slave->unattach_request) 1482 goto regmap_sync; 1483 1484 time = wait_for_completion_timeout(&slave->initialization_complete, 1485 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 1486 if (!time) { 1487 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 1488 return -ETIMEDOUT; 1489 } 1490 1491 regmap_sync: 1492 slave->unattach_request = 0; 1493 regcache_cache_only(rt1320->regmap, false); 1494 regcache_sync(rt1320->regmap); 1495 regcache_cache_only(rt1320->mbq_regmap, false); 1496 regcache_sync(rt1320->mbq_regmap); 1497 return 0; 1498 } 1499 1500 static const struct dev_pm_ops rt1320_pm = { 1501 SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 1502 SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 1503 }; 1504 1505 static struct sdw_driver rt1320_sdw_driver = { 1506 .driver = { 1507 .name = "rt1320-sdca", 1508 .pm = &rt1320_pm, 1509 }, 1510 .probe = rt1320_sdw_probe, 1511 .remove = rt1320_sdw_remove, 1512 .ops = &rt1320_slave_ops, 1513 .id_table = rt1320_id, 1514 }; 1515 module_sdw_driver(rt1320_sdw_driver); 1516 1517 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 1518 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 1519 MODULE_LICENSE("GPL"); 1520