1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/dmi.h> 15 #include <linux/firmware.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/sdw.h> 23 #include "rt1320-sdw.h" 24 #include "rt-sdw-common.h" 25 26 /* 27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 28 * It might include vendor-specific or SDCA control registers. 29 */ 30 static const struct reg_sequence rt1320_blind_write[] = { 31 { 0xc003, 0xe0 }, 32 { 0xc01b, 0xfc }, 33 { 0xc5c3, 0xf2 }, 34 { 0xc5c2, 0x00 }, 35 { 0xc5c6, 0x10 }, 36 { 0xc5c4, 0x12 }, 37 { 0xc5c8, 0x03 }, 38 { 0xc5d8, 0x0a }, 39 { 0xc5f7, 0x22 }, 40 { 0xc5f6, 0x22 }, 41 { 0xc5d0, 0x0f }, 42 { 0xc5d1, 0x89 }, 43 { 0xc057, 0x51 }, 44 { 0xc054, 0x35 }, 45 { 0xc053, 0x55 }, 46 { 0xc052, 0x55 }, 47 { 0xc051, 0x13 }, 48 { 0xc050, 0x15 }, 49 { 0xc060, 0x77 }, 50 { 0xc061, 0x55 }, 51 { 0xc063, 0x55 }, 52 { 0xc065, 0xa5 }, 53 { 0xc06b, 0x0a }, 54 { 0xca05, 0xd6 }, 55 { 0xca25, 0xd6 }, 56 { 0xcd00, 0x05 }, 57 { 0xc604, 0x40 }, 58 { 0xc609, 0x40 }, 59 { 0xc046, 0xff }, 60 { 0xc045, 0xff }, 61 { 0xc044, 0xff }, 62 { 0xc043, 0xff }, 63 { 0xc042, 0xff }, 64 { 0xc041, 0xff }, 65 { 0xc040, 0xff }, 66 { 0xcc10, 0x01 }, 67 { 0xc700, 0xf0 }, 68 { 0xc701, 0x13 }, 69 { 0xc901, 0x04 }, 70 { 0xc900, 0x73 }, 71 { 0xde03, 0x05 }, 72 { 0xdd0b, 0x0d }, 73 { 0xdd0a, 0xff }, 74 { 0xdd09, 0x0d }, 75 { 0xdd08, 0xff }, 76 { 0xc570, 0x08 }, 77 { 0xe803, 0xbe }, 78 { 0xc003, 0xc0 }, 79 { 0xc081, 0xfe }, 80 { 0xce31, 0x0d }, 81 { 0xce30, 0xae }, 82 { 0xce37, 0x0b }, 83 { 0xce36, 0xd2 }, 84 { 0xce39, 0x04 }, 85 { 0xce38, 0x80 }, 86 { 0xce3f, 0x00 }, 87 { 0xce3e, 0x00 }, 88 { 0xd470, 0x8b }, 89 { 0xd471, 0x18 }, 90 { 0xc019, 0x10 }, 91 { 0xd487, 0x3f }, 92 { 0xd486, 0xc3 }, 93 { 0x3fc2bfc7, 0x00 }, 94 { 0x3fc2bfc6, 0x00 }, 95 { 0x3fc2bfc5, 0x00 }, 96 { 0x3fc2bfc4, 0x01 }, 97 { 0x0000d486, 0x43 }, 98 { 0x1000db00, 0x02 }, 99 { 0x1000db01, 0x00 }, 100 { 0x1000db02, 0x11 }, 101 { 0x1000db03, 0x00 }, 102 { 0x1000db04, 0x00 }, 103 { 0x1000db05, 0x82 }, 104 { 0x1000db06, 0x04 }, 105 { 0x1000db07, 0xf1 }, 106 { 0x1000db08, 0x00 }, 107 { 0x1000db09, 0x00 }, 108 { 0x1000db0a, 0x40 }, 109 { 0x0000d540, 0x01 }, 110 { 0xd172, 0x2a }, 111 { 0xc5d6, 0x01 }, 112 }; 113 114 static const struct reg_sequence rt1320_vc_blind_write[] = { 115 { 0xc003, 0xe0 }, 116 { 0xe80a, 0x01 }, 117 { 0xc5c3, 0xf3 }, 118 { 0xc057, 0x51 }, 119 { 0xc054, 0x35 }, 120 { 0xca05, 0xd6 }, 121 { 0xca07, 0x07 }, 122 { 0xca25, 0xd6 }, 123 { 0xca27, 0x07 }, 124 { 0xc604, 0x40 }, 125 { 0xc609, 0x40 }, 126 { 0xc046, 0xff }, 127 { 0xc045, 0xff }, 128 { 0xda81, 0x14 }, 129 { 0xda8d, 0x14 }, 130 { 0xc044, 0xff }, 131 { 0xc043, 0xff }, 132 { 0xc042, 0xff }, 133 { 0xc041, 0x7f }, 134 { 0xc040, 0xff }, 135 { 0xcc10, 0x01 }, 136 { 0xc700, 0xf0 }, 137 { 0xc701, 0x13 }, 138 { 0xc901, 0x09 }, 139 { 0xc900, 0xd0 }, 140 { 0xde03, 0x05 }, 141 { 0xdd0b, 0x0d }, 142 { 0xdd0a, 0xff }, 143 { 0xdd09, 0x0d }, 144 { 0xdd08, 0xff }, 145 { 0xc570, 0x08 }, 146 { 0xc086, 0x02 }, 147 { 0xc085, 0x7f }, 148 { 0xc084, 0x00 }, 149 { 0xc081, 0xfe }, 150 { 0xf084, 0x0f }, 151 { 0xf083, 0xff }, 152 { 0xf082, 0xff }, 153 { 0xf081, 0xff }, 154 { 0xf080, 0xff }, 155 { 0xe802, 0xf8 }, 156 { 0xe803, 0xbe }, 157 { 0xc003, 0xc0 }, 158 { 0xd470, 0xec }, 159 { 0xd471, 0x3a }, 160 { 0xd474, 0x11 }, 161 { 0xd475, 0x32 }, 162 { 0xd478, 0x64 }, 163 { 0xd479, 0x20 }, 164 { 0xd47a, 0x10 }, 165 { 0xd47c, 0xff }, 166 { 0xc019, 0x10 }, 167 { 0xd487, 0x0b }, 168 { 0xd487, 0x3b }, 169 { 0xd486, 0xc3 }, 170 { 0xc598, 0x04 }, 171 { 0xdb03, 0xf0 }, 172 { 0xdb09, 0x00 }, 173 { 0xdb08, 0x7a }, 174 { 0xdb19, 0x02 }, 175 { 0xdb07, 0x5a }, 176 { 0xdb05, 0x45 }, 177 { 0xd500, 0x00 }, 178 { 0xd500, 0x17 }, 179 { 0xd600, 0x01 }, 180 { 0xd601, 0x02 }, 181 { 0xd602, 0x03 }, 182 { 0xd603, 0x04 }, 183 { 0xd64c, 0x03 }, 184 { 0xd64d, 0x03 }, 185 { 0xd64e, 0x03 }, 186 { 0xd64f, 0x03 }, 187 { 0xd650, 0x03 }, 188 { 0xd651, 0x03 }, 189 { 0xd652, 0x03 }, 190 { 0xd610, 0x01 }, 191 { 0xd608, 0x03 }, 192 { 0xd609, 0x00 }, 193 { 0x3fc2bf83, 0x00 }, 194 { 0x3fc2bf82, 0x00 }, 195 { 0x3fc2bf81, 0x00 }, 196 { 0x3fc2bf80, 0x00 }, 197 { 0x3fc2bfc7, 0x00 }, 198 { 0x3fc2bfc6, 0x00 }, 199 { 0x3fc2bfc5, 0x00 }, 200 { 0x3fc2bfc4, 0x00 }, 201 { 0x3fc2bfc3, 0x00 }, 202 { 0x3fc2bfc2, 0x00 }, 203 { 0x3fc2bfc1, 0x00 }, 204 { 0x3fc2bfc0, 0x03 }, 205 { 0x0000d486, 0x43 }, 206 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 207 { 0x1000db00, 0x04 }, 208 { 0x1000db01, 0x00 }, 209 { 0x1000db02, 0x11 }, 210 { 0x1000db03, 0x00 }, 211 { 0x1000db04, 0x00 }, 212 { 0x1000db05, 0x82 }, 213 { 0x1000db06, 0x04 }, 214 { 0x1000db07, 0xf1 }, 215 { 0x1000db08, 0x00 }, 216 { 0x1000db09, 0x00 }, 217 { 0x1000db0a, 0x40 }, 218 { 0x1000db0b, 0x02 }, 219 { 0x1000db0c, 0xf2 }, 220 { 0x1000db0d, 0x00 }, 221 { 0x1000db0e, 0x00 }, 222 { 0x1000db0f, 0xe0 }, 223 { 0x1000db10, 0x00 }, 224 { 0x1000db11, 0x10 }, 225 { 0x1000db12, 0x00 }, 226 { 0x1000db13, 0x00 }, 227 { 0x1000db14, 0x45 }, 228 { 0x0000d540, 0x01 }, 229 { 0x0000c081, 0xfc }, 230 { 0x0000f01e, 0x80 }, 231 { 0xc01b, 0xfc }, 232 { 0xc5d1, 0x89 }, 233 { 0xc5d8, 0x0a }, 234 { 0xc5f7, 0x22 }, 235 { 0xc5f6, 0x22 }, 236 { 0xc065, 0xa5 }, 237 { 0xc06b, 0x0a }, 238 { 0xd172, 0x2a }, 239 { 0xc5d6, 0x01 }, 240 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 241 }; 242 243 static const struct reg_default rt1320_reg_defaults[] = { 244 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 245 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 246 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 247 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 248 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 249 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 250 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 251 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 252 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 253 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 254 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 255 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 256 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 257 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 258 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 259 }; 260 261 static const struct reg_default rt1320_mbq_defaults[] = { 262 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 263 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 264 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 265 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 266 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 267 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 268 }; 269 270 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 271 { 272 switch (reg) { 273 case 0xc000 ... 0xc086: 274 case 0xc400 ... 0xc409: 275 case 0xc480 ... 0xc48f: 276 case 0xc4c0 ... 0xc4c4: 277 case 0xc4e0 ... 0xc4e7: 278 case 0xc500: 279 case 0xc560 ... 0xc56b: 280 case 0xc570: 281 case 0xc580 ... 0xc59a: 282 case 0xc5b0 ... 0xc60f: 283 case 0xc640 ... 0xc64f: 284 case 0xc670: 285 case 0xc680 ... 0xc683: 286 case 0xc700 ... 0xc76f: 287 case 0xc800 ... 0xc801: 288 case 0xc820: 289 case 0xc900 ... 0xc901: 290 case 0xc920 ... 0xc921: 291 case 0xca00 ... 0xca07: 292 case 0xca20 ... 0xca27: 293 case 0xca40 ... 0xca4b: 294 case 0xca60 ... 0xca68: 295 case 0xca80 ... 0xca88: 296 case 0xcb00 ... 0xcb0c: 297 case 0xcc00 ... 0xcc12: 298 case 0xcc80 ... 0xcc81: 299 case 0xcd00: 300 case 0xcd80 ... 0xcd82: 301 case 0xce00 ... 0xce4d: 302 case 0xcf00 ... 0xcf25: 303 case 0xd000 ... 0xd0ff: 304 case 0xd100 ... 0xd1ff: 305 case 0xd200 ... 0xd2ff: 306 case 0xd300 ... 0xd3ff: 307 case 0xd400 ... 0xd403: 308 case 0xd410 ... 0xd417: 309 case 0xd470 ... 0xd497: 310 case 0xd4dc ... 0xd50f: 311 case 0xd520 ... 0xd543: 312 case 0xd560 ... 0xd5ef: 313 case 0xd600 ... 0xd663: 314 case 0xda00 ... 0xda6e: 315 case 0xda80 ... 0xda9e: 316 case 0xdb00 ... 0xdb7f: 317 case 0xdc00: 318 case 0xdc20 ... 0xdc21: 319 case 0xdd00 ... 0xdd17: 320 case 0xde00 ... 0xde09: 321 case 0xdf00 ... 0xdf1b: 322 case 0xe000 ... 0xe847: 323 case 0xf01e: 324 case 0xf717 ... 0xf719: 325 case 0xf720 ... 0xf723: 326 case 0x1000cd91 ... 0x1000cd96: 327 case 0x1000f008: 328 case 0x1000f021: 329 case 0x3fe2e000 ... 0x3fe2e003: 330 case 0x3fc2ab80 ... 0x3fc2abd4: 331 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 332 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 333 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 334 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 335 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 336 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 337 /* 0x40880900/0x40880980 */ 338 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 339 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 340 /* 0x40881500 */ 341 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 342 /* 0x41000189/0x4100018a */ 343 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 344 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 345 /* 0x41001388 */ 346 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 347 /* 0x41001988 */ 348 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 349 /* 0x41080000 */ 350 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 351 /* 0x41080200 */ 352 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 353 /* 0x41080900 */ 354 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 355 /* 0x41080980 */ 356 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 357 /* 0x41081080 */ 358 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 359 /* 0x41081480/0x41081488 */ 360 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 361 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 362 /* 0x41081980 */ 363 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 364 return true; 365 default: 366 return false; 367 } 368 } 369 370 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 371 { 372 switch (reg) { 373 case 0xc000: 374 case 0xc003: 375 case 0xc081: 376 case 0xc402 ... 0xc406: 377 case 0xc48c ... 0xc48f: 378 case 0xc560: 379 case 0xc5b5 ... 0xc5b7: 380 case 0xc5fc ... 0xc5ff: 381 case 0xc820: 382 case 0xc900: 383 case 0xc920: 384 case 0xca42: 385 case 0xca62: 386 case 0xca82: 387 case 0xcd00: 388 case 0xce03: 389 case 0xce10: 390 case 0xce14 ... 0xce17: 391 case 0xce44 ... 0xce49: 392 case 0xce4c ... 0xce4d: 393 case 0xcf0c: 394 case 0xcf10 ... 0xcf25: 395 case 0xd486 ... 0xd487: 396 case 0xd4e5 ... 0xd4e6: 397 case 0xd4e8 ... 0xd4ff: 398 case 0xd530: 399 case 0xd540: 400 case 0xd543: 401 case 0xdb58 ... 0xdb5f: 402 case 0xdb60 ... 0xdb63: 403 case 0xdb68 ... 0xdb69: 404 case 0xdb6d: 405 case 0xdb70 ... 0xdb71: 406 case 0xdb76: 407 case 0xdb7a: 408 case 0xdb7c ... 0xdb7f: 409 case 0xdd0c ... 0xdd13: 410 case 0xde02: 411 case 0xdf14 ... 0xdf1b: 412 case 0xe83c ... 0xe847: 413 case 0xf01e: 414 case 0xf717 ... 0xf719: 415 case 0xf720 ... 0xf723: 416 case 0x10000000 ... 0x10007fff: 417 case 0x1000c000 ... 0x1000dfff: 418 case 0x1000f008: 419 case 0x1000f021: 420 case 0x3fc2ab80 ... 0x3fc2abd4: 421 case 0x3fc2bf80 ... 0x3fc2bf83: 422 case 0x3fc2bfc0 ... 0x3fc2bfc7: 423 case 0x3fe2e000 ... 0x3fe2e003: 424 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 425 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 426 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 427 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 428 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 429 return true; 430 default: 431 return false; 432 } 433 } 434 435 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 436 { 437 switch (reg) { 438 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 439 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 440 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 441 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 442 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 443 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 444 return true; 445 default: 446 return false; 447 } 448 } 449 450 static const struct regmap_config rt1320_sdw_regmap = { 451 .reg_bits = 32, 452 .val_bits = 8, 453 .readable_reg = rt1320_readable_register, 454 .volatile_reg = rt1320_volatile_register, 455 .max_register = 0x41081980, 456 .reg_defaults = rt1320_reg_defaults, 457 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 458 .cache_type = REGCACHE_MAPLE, 459 .use_single_read = true, 460 .use_single_write = true, 461 }; 462 463 static const struct regmap_config rt1320_mbq_regmap = { 464 .name = "sdw-mbq", 465 .reg_bits = 32, 466 .val_bits = 16, 467 .readable_reg = rt1320_mbq_readable_register, 468 .max_register = 0x41000192, 469 .reg_defaults = rt1320_mbq_defaults, 470 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 471 .cache_type = REGCACHE_MAPLE, 472 .use_single_read = true, 473 .use_single_write = true, 474 }; 475 476 static int rt1320_read_prop(struct sdw_slave *slave) 477 { 478 struct sdw_slave_prop *prop = &slave->prop; 479 int nval; 480 int i, j; 481 u32 bit; 482 unsigned long addr; 483 struct sdw_dpn_prop *dpn; 484 485 /* 486 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 487 */ 488 sdw_slave_read_prop(slave); 489 490 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 491 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 492 493 prop->paging_support = true; 494 prop->lane_control_support = true; 495 496 /* first we need to allocate memory for set bits in port lists */ 497 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 498 prop->sink_ports = BIT(1); 499 500 nval = hweight32(prop->source_ports); 501 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 502 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 503 if (!prop->src_dpn_prop) 504 return -ENOMEM; 505 506 i = 0; 507 dpn = prop->src_dpn_prop; 508 addr = prop->source_ports; 509 for_each_set_bit(bit, &addr, 32) { 510 dpn[i].num = bit; 511 dpn[i].type = SDW_DPN_FULL; 512 dpn[i].simple_ch_prep_sm = true; 513 dpn[i].ch_prep_timeout = 10; 514 i++; 515 } 516 517 /* do this again for sink now */ 518 nval = hweight32(prop->sink_ports); 519 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 520 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 521 if (!prop->sink_dpn_prop) 522 return -ENOMEM; 523 524 j = 0; 525 dpn = prop->sink_dpn_prop; 526 addr = prop->sink_ports; 527 for_each_set_bit(bit, &addr, 32) { 528 dpn[j].num = bit; 529 dpn[j].type = SDW_DPN_FULL; 530 dpn[j].simple_ch_prep_sm = true; 531 dpn[j].ch_prep_timeout = 10; 532 j++; 533 } 534 535 /* set the timeout values */ 536 prop->clk_stop_timeout = 64; 537 538 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */ 539 prop->wake_capable = 0; 540 541 return 0; 542 } 543 544 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 545 unsigned char entity, unsigned char ps) 546 { 547 unsigned int delay = 1000, val; 548 549 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 550 551 /* waiting for Actual PDE becomes to PS0/PS3 */ 552 while (delay) { 553 regmap_read(rt1320->regmap, 554 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 555 if (val == ps) 556 break; 557 558 usleep_range(1000, 1500); 559 delay--; 560 } 561 if (!delay) { 562 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 563 return -ETIMEDOUT; 564 } 565 566 return 0; 567 } 568 569 /* 570 * The 'patch code' is written to the patch code area. 571 * The patch code area is used for SDCA register expansion flexibility. 572 */ 573 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 574 { 575 struct sdw_slave *slave = rt1320->sdw_slave; 576 const struct firmware *patch; 577 const char *filename; 578 unsigned int addr, val; 579 const unsigned char *ptr; 580 int ret, i; 581 582 if (rt1320->version_id <= RT1320_VB) 583 filename = RT1320_VAB_MCU_PATCH; 584 else 585 filename = RT1320_VC_MCU_PATCH; 586 587 /* load the patch code here */ 588 ret = request_firmware(&patch, filename, &slave->dev); 589 if (ret) { 590 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 591 regmap_write(rt1320->regmap, 0xc598, 0x00); 592 regmap_write(rt1320->regmap, 0x10007000, 0x67); 593 regmap_write(rt1320->regmap, 0x10007001, 0x80); 594 regmap_write(rt1320->regmap, 0x10007002, 0x00); 595 regmap_write(rt1320->regmap, 0x10007003, 0x00); 596 } else { 597 ptr = (const unsigned char *)patch->data; 598 if ((patch->size % 8) == 0) { 599 for (i = 0; i < patch->size; i += 8) { 600 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 601 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 602 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 603 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 604 605 if (addr > 0x10007fff || addr < 0x10007000) { 606 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 607 goto _exit_; 608 } 609 if (val > 0xff) { 610 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 611 goto _exit_; 612 } 613 regmap_write(rt1320->regmap, addr, val); 614 } 615 } 616 _exit_: 617 release_firmware(patch); 618 } 619 } 620 621 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 622 { 623 unsigned int i, reg, val, delay; 624 625 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 626 reg = rt1320_blind_write[i].reg; 627 val = rt1320_blind_write[i].def; 628 delay = rt1320_blind_write[i].delay_us; 629 630 if (reg == 0x3fc2bfc7) 631 rt1320_load_mcu_patch(rt1320); 632 633 regmap_write(rt1320->regmap, reg, val); 634 if (delay) 635 usleep_range(delay, delay + 1000); 636 } 637 } 638 639 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 640 { 641 struct sdw_slave *slave = rt1320->sdw_slave; 642 unsigned int i, reg, val, delay, retry, tmp; 643 644 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 645 reg = rt1320_vc_blind_write[i].reg; 646 val = rt1320_vc_blind_write[i].def; 647 delay = rt1320_vc_blind_write[i].delay_us; 648 649 if (reg == 0x3fc2bf83) 650 rt1320_load_mcu_patch(rt1320); 651 652 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 653 (val == 0x00)) { 654 retry = 200; 655 while (retry) { 656 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 657 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 658 if (tmp == 0x1f) 659 break; 660 usleep_range(1000, 1500); 661 retry--; 662 } 663 if (!retry) 664 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 665 } 666 regmap_write(rt1320->regmap, reg, val); 667 if (delay) 668 usleep_range(delay, delay + 1000); 669 670 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 671 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 672 } 673 } 674 675 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 676 { 677 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 678 unsigned int amp_func_status, val, tmp; 679 680 if (rt1320->hw_init) 681 return 0; 682 683 regcache_cache_only(rt1320->regmap, false); 684 regcache_cache_only(rt1320->mbq_regmap, false); 685 if (rt1320->first_hw_init) { 686 regcache_cache_bypass(rt1320->regmap, true); 687 regcache_cache_bypass(rt1320->mbq_regmap, true); 688 } else { 689 /* 690 * PM runtime status is marked as 'active' only when a Slave reports as Attached 691 */ 692 /* update count of parent 'active' children */ 693 pm_runtime_set_active(&slave->dev); 694 } 695 696 pm_runtime_get_noresume(&slave->dev); 697 698 if (rt1320->version_id < 0) { 699 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 700 rt1320->version_id = val; 701 } 702 703 regmap_read(rt1320->regmap, 704 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 705 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 706 707 /* initialization write */ 708 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 709 if (rt1320->version_id < RT1320_VC) 710 rt1320_vab_preset(rt1320); 711 else 712 rt1320_vc_preset(rt1320); 713 714 regmap_write(rt1320->regmap, 715 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 716 FUNCTION_NEEDS_INITIALIZATION); 717 } 718 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA) { 719 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 720 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 721 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 722 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 723 val = (tmp << 8) | val; 724 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 725 val = (tmp << 16) | val; 726 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 727 val = (tmp << 24) | val; 728 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 729 /* 730 * We call the version b which has the new DSP ROM code against version a. 731 * Therefore, we read the DSP address to check the ID. 732 */ 733 if (val == RT1320_VER_B_ID) 734 rt1320->version_id = RT1320_VB; 735 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 736 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 737 } 738 dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); 739 740 if (rt1320->first_hw_init) { 741 regcache_cache_bypass(rt1320->regmap, false); 742 regcache_cache_bypass(rt1320->mbq_regmap, false); 743 regcache_mark_dirty(rt1320->regmap); 744 regcache_mark_dirty(rt1320->mbq_regmap); 745 } 746 747 /* Mark Slave initialization complete */ 748 rt1320->first_hw_init = true; 749 rt1320->hw_init = true; 750 751 pm_runtime_mark_last_busy(&slave->dev); 752 pm_runtime_put_autosuspend(&slave->dev); 753 754 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 755 return 0; 756 } 757 758 static int rt1320_update_status(struct sdw_slave *slave, 759 enum sdw_slave_status status) 760 { 761 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 762 763 if (status == SDW_SLAVE_UNATTACHED) 764 rt1320->hw_init = false; 765 766 /* 767 * Perform initialization only if slave status is present and 768 * hw_init flag is false 769 */ 770 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 771 return 0; 772 773 /* perform I/O transfers required for Slave initialization */ 774 return rt1320_io_init(&slave->dev, slave); 775 } 776 777 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 778 struct snd_kcontrol *kcontrol, int event) 779 { 780 struct snd_soc_component *component = 781 snd_soc_dapm_to_component(w->dapm); 782 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 783 unsigned char ps0 = 0x0, ps3 = 0x3; 784 785 switch (event) { 786 case SND_SOC_DAPM_POST_PMU: 787 regmap_write(rt1320->regmap, 788 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 789 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 790 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 791 break; 792 case SND_SOC_DAPM_PRE_PMD: 793 regmap_write(rt1320->regmap, 794 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 795 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 796 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 797 break; 798 default: 799 break; 800 } 801 802 return 0; 803 } 804 805 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 806 struct snd_kcontrol *kcontrol, int event) 807 { 808 struct snd_soc_component *component = 809 snd_soc_dapm_to_component(w->dapm); 810 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 811 unsigned char ps0 = 0x0, ps3 = 0x3; 812 813 switch (event) { 814 case SND_SOC_DAPM_POST_PMU: 815 regmap_write(rt1320->regmap, 816 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 817 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 818 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 819 break; 820 case SND_SOC_DAPM_PRE_PMD: 821 regmap_write(rt1320->regmap, 822 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 823 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 824 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 825 break; 826 default: 827 break; 828 } 829 830 return 0; 831 } 832 833 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 834 struct snd_ctl_elem_value *ucontrol) 835 { 836 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 837 struct soc_mixer_control *mc = 838 (struct soc_mixer_control *)kcontrol->private_value; 839 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 840 unsigned int gain_l_val, gain_r_val; 841 unsigned int lvalue, rvalue; 842 const unsigned int interval_offset = 0xc0; 843 unsigned int changed = 0, reg_base; 844 struct rt_sdca_dmic_kctrl_priv *p; 845 unsigned int regvalue[4], gain_val[4], i; 846 int err; 847 848 if (strstr(ucontrol->id.name, "FU Capture Volume")) 849 goto _dmic_vol_; 850 851 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 852 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 853 854 /* L Channel */ 855 gain_l_val = ucontrol->value.integer.value[0]; 856 if (gain_l_val > mc->max) 857 gain_l_val = mc->max; 858 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 859 gain_l_val &= 0xffff; 860 861 /* R Channel */ 862 gain_r_val = ucontrol->value.integer.value[1]; 863 if (gain_r_val > mc->max) 864 gain_r_val = mc->max; 865 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 866 gain_r_val &= 0xffff; 867 868 if (lvalue == gain_l_val && rvalue == gain_r_val) 869 return 0; 870 871 /* Lch*/ 872 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 873 /* Rch */ 874 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 875 goto _done_; 876 877 _dmic_vol_: 878 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 879 880 /* check all channels */ 881 for (i = 0; i < p->count; i++) { 882 if (i < 2) { 883 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 884 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 885 } else { 886 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 887 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 888 } 889 890 gain_val[i] = ucontrol->value.integer.value[i]; 891 if (gain_val[i] > p->max) 892 gain_val[i] = p->max; 893 894 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 895 gain_val[i] &= 0xffff; 896 if (regvalue[i] != gain_val[i]) 897 changed = 1; 898 } 899 900 if (!changed) 901 return 0; 902 903 for (i = 0; i < p->count; i++) { 904 if (i < 2) { 905 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 906 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 907 } else { 908 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 909 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 910 } 911 912 if (err < 0) 913 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 914 } 915 916 _done_: 917 return 1; 918 } 919 920 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 921 struct snd_ctl_elem_value *ucontrol) 922 { 923 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 924 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 925 struct soc_mixer_control *mc = 926 (struct soc_mixer_control *)kcontrol->private_value; 927 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 928 const unsigned int interval_offset = 0xc0; 929 unsigned int reg_base, regvalue, ctl, i; 930 struct rt_sdca_dmic_kctrl_priv *p; 931 932 if (strstr(ucontrol->id.name, "FU Capture Volume")) 933 goto _dmic_vol_; 934 935 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 936 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 937 938 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 939 940 if (read_l != read_r) 941 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 942 else 943 ctl_r = ctl_l; 944 945 ucontrol->value.integer.value[0] = ctl_l; 946 ucontrol->value.integer.value[1] = ctl_r; 947 goto _done_; 948 949 _dmic_vol_: 950 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 951 952 /* check all channels */ 953 for (i = 0; i < p->count; i++) { 954 if (i < 2) { 955 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 956 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 957 } else { 958 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 959 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 960 } 961 962 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 963 ucontrol->value.integer.value[i] = ctl; 964 } 965 _done_: 966 return 0; 967 } 968 969 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 970 { 971 int err, i; 972 unsigned int ch_mute; 973 974 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 975 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 976 977 if (i < 2) 978 err = regmap_write(rt1320->regmap, 979 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 980 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 981 else 982 err = regmap_write(rt1320->regmap, 983 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 984 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 985 if (err < 0) 986 return err; 987 } 988 989 return 0; 990 } 991 992 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 993 struct snd_ctl_elem_value *ucontrol) 994 { 995 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 996 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 997 struct rt_sdca_dmic_kctrl_priv *p = 998 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 999 unsigned int i; 1000 1001 for (i = 0; i < p->count; i++) 1002 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 1003 1004 return 0; 1005 } 1006 1007 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 1008 struct snd_ctl_elem_value *ucontrol) 1009 { 1010 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1011 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1012 struct rt_sdca_dmic_kctrl_priv *p = 1013 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1014 int err, changed = 0, i; 1015 1016 for (i = 0; i < p->count; i++) { 1017 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 1018 changed = 1; 1019 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 1020 } 1021 1022 err = rt1320_set_fu_capture_ctl(rt1320); 1023 if (err < 0) 1024 return err; 1025 1026 return changed; 1027 } 1028 1029 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 1030 struct snd_ctl_elem_info *uinfo) 1031 { 1032 struct rt_sdca_dmic_kctrl_priv *p = 1033 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 1034 1035 if (p->max == 1) 1036 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1037 else 1038 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1039 uinfo->count = p->count; 1040 uinfo->value.integer.min = 0; 1041 uinfo->value.integer.max = p->max; 1042 return 0; 1043 } 1044 1045 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 1046 struct snd_kcontrol *kcontrol, int event) 1047 { 1048 struct snd_soc_component *component = 1049 snd_soc_dapm_to_component(w->dapm); 1050 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1051 1052 switch (event) { 1053 case SND_SOC_DAPM_POST_PMU: 1054 rt1320->fu_dapm_mute = false; 1055 rt1320_set_fu_capture_ctl(rt1320); 1056 break; 1057 case SND_SOC_DAPM_PRE_PMD: 1058 rt1320->fu_dapm_mute = true; 1059 rt1320_set_fu_capture_ctl(rt1320); 1060 break; 1061 } 1062 return 0; 1063 } 1064 1065 static const char * const rt1320_rx_data_ch_select[] = { 1066 "L,R", 1067 "R,L", 1068 "L,L", 1069 "R,R", 1070 "L,L+R", 1071 "R,L+R", 1072 "L+R,L", 1073 "L+R,R", 1074 "L+R,L+R", 1075 }; 1076 1077 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 1078 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 1079 rt1320_rx_data_ch_select); 1080 1081 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 1082 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 1083 1084 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 1085 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 1086 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1087 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 1088 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 1089 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 1090 1091 RT_SDCA_FU_CTRL("FU Capture Switch", 1092 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1093 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 1094 RT_SDCA_EXT_TLV("FU Capture Volume", 1095 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 1096 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 1097 }; 1098 1099 static const struct snd_kcontrol_new rt1320_spk_l_dac = 1100 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1101 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 1102 0, 1, 1); 1103 static const struct snd_kcontrol_new rt1320_spk_r_dac = 1104 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 1105 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 1106 0, 1, 1); 1107 1108 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 1109 /* Audio Interface */ 1110 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 1111 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 1112 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 1113 1114 /* Digital Interface */ 1115 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 1116 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1117 rt1320_pde23_event, 1118 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1119 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1120 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1121 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 1122 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 1123 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 1124 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1125 1126 /* Output */ 1127 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 1128 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 1129 SND_SOC_DAPM_OUTPUT("SPOL"), 1130 SND_SOC_DAPM_OUTPUT("SPOR"), 1131 1132 /* Input */ 1133 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 1134 SND_SOC_DAPM_SIGGEN("AEC Gen"), 1135 SND_SOC_DAPM_INPUT("DMIC1"), 1136 SND_SOC_DAPM_INPUT("DMIC2"), 1137 }; 1138 1139 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 1140 { "FU21", NULL, "DP1RX" }, 1141 { "FU21", NULL, "PDE 23" }, 1142 { "OT23 L", "Switch", "FU21" }, 1143 { "OT23 R", "Switch", "FU21" }, 1144 { "SPOL", NULL, "OT23 L" }, 1145 { "SPOR", NULL, "OT23 R" }, 1146 1147 { "AEC Data", NULL, "AEC Gen" }, 1148 { "DP4TX", NULL, "AEC Data" }, 1149 1150 {"DP8-10TX", NULL, "FU"}, 1151 {"FU", NULL, "PDE 11"}, 1152 {"FU", NULL, "FU 113"}, 1153 {"FU", NULL, "FU 14"}, 1154 {"FU 113", NULL, "DMIC1"}, 1155 {"FU 14", NULL, "DMIC2"}, 1156 }; 1157 1158 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1159 int direction) 1160 { 1161 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1162 return 0; 1163 } 1164 1165 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 1166 struct snd_soc_dai *dai) 1167 { 1168 snd_soc_dai_set_dma_data(dai, substream, NULL); 1169 } 1170 1171 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 1172 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1173 { 1174 struct snd_soc_component *component = dai->component; 1175 struct rt1320_sdw_priv *rt1320 = 1176 snd_soc_component_get_drvdata(component); 1177 struct sdw_stream_config stream_config; 1178 struct sdw_port_config port_config; 1179 struct sdw_port_config dmic_port_config[2]; 1180 struct sdw_stream_runtime *sdw_stream; 1181 int retval; 1182 unsigned int sampling_rate; 1183 1184 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1185 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1186 1187 if (!sdw_stream) 1188 return -EINVAL; 1189 1190 if (!rt1320->sdw_slave) 1191 return -EINVAL; 1192 1193 /* SoundWire specific configuration */ 1194 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 1195 1196 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1197 if (dai->id == RT1320_AIF1) 1198 port_config.num = 1; 1199 else 1200 return -EINVAL; 1201 } else { 1202 if (dai->id == RT1320_AIF1) 1203 port_config.num = 4; 1204 else if (dai->id == RT1320_AIF2) { 1205 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 1206 dmic_port_config[0].num = 8; 1207 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 1208 dmic_port_config[1].num = 10; 1209 } else 1210 return -EINVAL; 1211 } 1212 1213 if (dai->id == RT1320_AIF1) 1214 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1215 &port_config, 1, sdw_stream); 1216 else if (dai->id == RT1320_AIF2) 1217 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 1218 dmic_port_config, 2, sdw_stream); 1219 else 1220 return -EINVAL; 1221 if (retval) { 1222 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1223 return retval; 1224 } 1225 1226 /* sampling rate configuration */ 1227 switch (params_rate(params)) { 1228 case 16000: 1229 sampling_rate = RT1320_SDCA_RATE_16000HZ; 1230 break; 1231 case 32000: 1232 sampling_rate = RT1320_SDCA_RATE_32000HZ; 1233 break; 1234 case 44100: 1235 sampling_rate = RT1320_SDCA_RATE_44100HZ; 1236 break; 1237 case 48000: 1238 sampling_rate = RT1320_SDCA_RATE_48000HZ; 1239 break; 1240 case 96000: 1241 sampling_rate = RT1320_SDCA_RATE_96000HZ; 1242 break; 1243 case 192000: 1244 sampling_rate = RT1320_SDCA_RATE_192000HZ; 1245 break; 1246 default: 1247 dev_err(component->dev, "%s: Rate %d is not supported\n", 1248 __func__, params_rate(params)); 1249 return -EINVAL; 1250 } 1251 1252 /* set sampling frequency */ 1253 if (dai->id == RT1320_AIF1) 1254 regmap_write(rt1320->regmap, 1255 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1256 sampling_rate); 1257 else { 1258 regmap_write(rt1320->regmap, 1259 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1260 sampling_rate); 1261 regmap_write(rt1320->regmap, 1262 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 1263 sampling_rate); 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 1270 struct snd_soc_dai *dai) 1271 { 1272 struct snd_soc_component *component = dai->component; 1273 struct rt1320_sdw_priv *rt1320 = 1274 snd_soc_component_get_drvdata(component); 1275 struct sdw_stream_runtime *sdw_stream = 1276 snd_soc_dai_get_dma_data(dai, substream); 1277 1278 if (!rt1320->sdw_slave) 1279 return -EINVAL; 1280 1281 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 1282 return 0; 1283 } 1284 1285 /* 1286 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 1287 * port_prep are not defined for now 1288 */ 1289 static const struct sdw_slave_ops rt1320_slave_ops = { 1290 .read_prop = rt1320_read_prop, 1291 .update_status = rt1320_update_status, 1292 }; 1293 1294 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 1295 { 1296 int ret; 1297 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1298 1299 rt1320->component = component; 1300 1301 if (!rt1320->first_hw_init) 1302 return 0; 1303 1304 ret = pm_runtime_resume(component->dev); 1305 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 1306 if (ret < 0 && ret != -EACCES) 1307 return ret; 1308 1309 return 0; 1310 } 1311 1312 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 1313 .probe = rt1320_sdw_component_probe, 1314 .controls = rt1320_snd_controls, 1315 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 1316 .dapm_widgets = rt1320_dapm_widgets, 1317 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 1318 .dapm_routes = rt1320_dapm_routes, 1319 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 1320 .endianness = 1, 1321 }; 1322 1323 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 1324 .hw_params = rt1320_sdw_hw_params, 1325 .hw_free = rt1320_sdw_pcm_hw_free, 1326 .set_stream = rt1320_set_sdw_stream, 1327 .shutdown = rt1320_sdw_shutdown, 1328 }; 1329 1330 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 1331 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1332 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1333 SNDRV_PCM_FMTBIT_S32_LE) 1334 1335 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 1336 { 1337 .name = "rt1320-aif1", 1338 .id = RT1320_AIF1, 1339 .playback = { 1340 .stream_name = "DP1 Playback", 1341 .channels_min = 1, 1342 .channels_max = 2, 1343 .rates = RT1320_STEREO_RATES, 1344 .formats = RT1320_FORMATS, 1345 }, 1346 .capture = { 1347 .stream_name = "DP4 Capture", 1348 .channels_min = 1, 1349 .channels_max = 2, 1350 .rates = RT1320_STEREO_RATES, 1351 .formats = RT1320_FORMATS, 1352 }, 1353 .ops = &rt1320_aif_dai_ops, 1354 }, 1355 /* DMIC: DP8 2ch + DP10 2ch */ 1356 { 1357 .name = "rt1320-aif2", 1358 .id = RT1320_AIF2, 1359 .capture = { 1360 .stream_name = "DP8-10 Capture", 1361 .channels_min = 1, 1362 .channels_max = 4, 1363 .rates = RT1320_STEREO_RATES, 1364 .formats = RT1320_FORMATS, 1365 }, 1366 .ops = &rt1320_aif_dai_ops, 1367 }, 1368 }; 1369 1370 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 1371 struct regmap *mbq_regmap, struct sdw_slave *slave) 1372 { 1373 struct rt1320_sdw_priv *rt1320; 1374 int ret; 1375 1376 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 1377 if (!rt1320) 1378 return -ENOMEM; 1379 1380 dev_set_drvdata(dev, rt1320); 1381 rt1320->sdw_slave = slave; 1382 rt1320->mbq_regmap = mbq_regmap; 1383 rt1320->regmap = regmap; 1384 1385 regcache_cache_only(rt1320->regmap, true); 1386 regcache_cache_only(rt1320->mbq_regmap, true); 1387 1388 /* 1389 * Mark hw_init to false 1390 * HW init will be performed when device reports present 1391 */ 1392 rt1320->hw_init = false; 1393 rt1320->first_hw_init = false; 1394 rt1320->version_id = -1; 1395 rt1320->fu_dapm_mute = true; 1396 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 1397 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 1398 1399 ret = devm_snd_soc_register_component(dev, 1400 &soc_component_sdw_rt1320, 1401 rt1320_sdw_dai, 1402 ARRAY_SIZE(rt1320_sdw_dai)); 1403 if (ret < 0) 1404 return ret; 1405 1406 /* set autosuspend parameters */ 1407 pm_runtime_set_autosuspend_delay(dev, 3000); 1408 pm_runtime_use_autosuspend(dev); 1409 1410 /* make sure the device does not suspend immediately */ 1411 pm_runtime_mark_last_busy(dev); 1412 1413 pm_runtime_enable(dev); 1414 1415 /* important note: the device is NOT tagged as 'active' and will remain 1416 * 'suspended' until the hardware is enumerated/initialized. This is required 1417 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 1418 * fail with -EACCESS because of race conditions between card creation and enumeration 1419 */ 1420 1421 dev_dbg(dev, "%s\n", __func__); 1422 1423 return ret; 1424 } 1425 1426 static int rt1320_sdw_probe(struct sdw_slave *slave, 1427 const struct sdw_device_id *id) 1428 { 1429 struct regmap *regmap, *mbq_regmap; 1430 1431 /* Regmap Initialization */ 1432 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 1433 if (IS_ERR(mbq_regmap)) 1434 return PTR_ERR(mbq_regmap); 1435 1436 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 1437 if (IS_ERR(regmap)) 1438 return PTR_ERR(regmap); 1439 1440 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 1441 } 1442 1443 static int rt1320_sdw_remove(struct sdw_slave *slave) 1444 { 1445 pm_runtime_disable(&slave->dev); 1446 1447 return 0; 1448 } 1449 1450 /* 1451 * Version A/B will use the class id 0 1452 * The newer version than A/B will use the class id 1, so add it in advance 1453 */ 1454 static const struct sdw_device_id rt1320_id[] = { 1455 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 1456 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 1457 {}, 1458 }; 1459 MODULE_DEVICE_TABLE(sdw, rt1320_id); 1460 1461 static int __maybe_unused rt1320_dev_suspend(struct device *dev) 1462 { 1463 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1464 1465 if (!rt1320->hw_init) 1466 return 0; 1467 1468 regcache_cache_only(rt1320->regmap, true); 1469 regcache_cache_only(rt1320->mbq_regmap, true); 1470 return 0; 1471 } 1472 1473 #define RT1320_PROBE_TIMEOUT 5000 1474 1475 static int __maybe_unused rt1320_dev_resume(struct device *dev) 1476 { 1477 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1478 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 1479 unsigned long time; 1480 1481 if (!rt1320->first_hw_init) 1482 return 0; 1483 1484 if (!slave->unattach_request) 1485 goto regmap_sync; 1486 1487 time = wait_for_completion_timeout(&slave->initialization_complete, 1488 msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); 1489 if (!time) { 1490 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); 1491 return -ETIMEDOUT; 1492 } 1493 1494 regmap_sync: 1495 slave->unattach_request = 0; 1496 regcache_cache_only(rt1320->regmap, false); 1497 regcache_sync(rt1320->regmap); 1498 regcache_cache_only(rt1320->mbq_regmap, false); 1499 regcache_sync(rt1320->mbq_regmap); 1500 return 0; 1501 } 1502 1503 static const struct dev_pm_ops rt1320_pm = { 1504 SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 1505 SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 1506 }; 1507 1508 static struct sdw_driver rt1320_sdw_driver = { 1509 .driver = { 1510 .name = "rt1320-sdca", 1511 .pm = &rt1320_pm, 1512 }, 1513 .probe = rt1320_sdw_probe, 1514 .remove = rt1320_sdw_remove, 1515 .ops = &rt1320_slave_ops, 1516 .id_table = rt1320_id, 1517 }; 1518 module_sdw_driver(rt1320_sdw_driver); 1519 1520 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 1521 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 1522 MODULE_LICENSE("GPL"); 1523