1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1318-sdw.c -- rt1318 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2022 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/dmi.h> 14 #include <linux/firmware.h> 15 #include <sound/core.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <sound/initval.h> 20 #include "rt1318-sdw.h" 21 22 static const struct reg_sequence rt1318_blind_write[] = { 23 { 0xc001, 0x43 }, 24 { 0xc003, 0xa2 }, 25 { 0xc004, 0x44 }, 26 { 0xc005, 0x44 }, 27 { 0xc006, 0x33 }, 28 { 0xc007, 0x64 }, 29 { 0xc320, 0x20 }, 30 { 0xf203, 0x18 }, 31 { 0xf211, 0x00 }, 32 { 0xf212, 0x26 }, 33 { 0xf20d, 0x17 }, 34 { 0xf214, 0x06 }, 35 { 0xf20e, 0x00 }, 36 { 0xf223, 0x7f }, 37 { 0xf224, 0xdb }, 38 { 0xf225, 0xee }, 39 { 0xf226, 0x3f }, 40 { 0xf227, 0x0f }, 41 { 0xf21a, 0x78 }, 42 { 0xf242, 0x3c }, 43 { 0xc321, 0x0b }, 44 { 0xc200, 0xd8 }, 45 { 0xc201, 0x27 }, 46 { 0xc202, 0x0f }, 47 { 0xf800, 0x20 }, 48 { 0xdf00, 0x10 }, 49 { 0xdf5f, 0x01 }, 50 { 0xdf60, 0xa7 }, 51 { 0xc400, 0x0e }, 52 { 0xc401, 0x43 }, 53 { 0xc402, 0xe0 }, 54 { 0xc403, 0x00 }, 55 { 0xc404, 0x4c }, 56 { 0xc407, 0x02 }, 57 { 0xc408, 0x3f }, 58 { 0xc300, 0x01 }, 59 { 0xc206, 0x78 }, 60 { 0xc203, 0x84 }, 61 { 0xc120, 0xc0 }, 62 { 0xc121, 0x03 }, 63 { 0xe000, 0x88 }, 64 { 0xc321, 0x09 }, 65 { 0xc322, 0x01 }, 66 { 0xe706, 0x0f }, 67 { 0xe707, 0x30 }, 68 { 0xe806, 0x0f }, 69 { 0xe807, 0x30 }, 70 { 0xed00, 0xb0 }, 71 { 0xce04, 0x02 }, 72 { 0xce05, 0x63 }, 73 { 0xce06, 0x68 }, 74 { 0xce07, 0x07 }, 75 { 0xcf04, 0x02 }, 76 { 0xcf05, 0x63 }, 77 { 0xcf06, 0x68 }, 78 { 0xcf07, 0x07 }, 79 { 0xce60, 0xe3 }, 80 { 0xc130, 0x51 }, 81 { 0xf102, 0x00 }, 82 { 0xf103, 0x00 }, 83 { 0xf104, 0xf5 }, 84 { 0xf105, 0x06 }, 85 { 0xf109, 0x9b }, 86 { 0xf10a, 0x0b }, 87 { 0xf10b, 0x4c }, 88 { 0xf10b, 0x5c }, 89 { 0xf102, 0x00 }, 90 { 0xf103, 0x00 }, 91 { 0xf104, 0xf5 }, 92 { 0xf105, 0x0b }, 93 { 0xf109, 0x03 }, 94 { 0xf10a, 0x0b }, 95 { 0xf10b, 0x4c }, 96 { 0xf10b, 0x5c }, 97 { 0xf102, 0x00 }, 98 { 0xf103, 0x00 }, 99 { 0xf104, 0xf5 }, 100 { 0xf105, 0x0c }, 101 { 0xf109, 0x7f }, 102 { 0xf10a, 0x0b }, 103 { 0xf10b, 0x4c }, 104 { 0xf10b, 0x5c }, 105 106 { 0xe604, 0x00 }, 107 { 0xdb00, 0x0c }, 108 { 0xdd00, 0x0c }, 109 { 0xdc19, 0x00 }, 110 { 0xdc1a, 0xff }, 111 { 0xdc1b, 0xff }, 112 { 0xdc1c, 0xff }, 113 { 0xdc1d, 0x00 }, 114 { 0xdc1e, 0x00 }, 115 { 0xdc1f, 0x00 }, 116 { 0xdc20, 0xff }, 117 { 0xde19, 0x00 }, 118 { 0xde1a, 0xff }, 119 { 0xde1b, 0xff }, 120 { 0xde1c, 0xff }, 121 { 0xde1d, 0x00 }, 122 { 0xde1e, 0x00 }, 123 { 0xde1f, 0x00 }, 124 { 0xde20, 0xff }, 125 { 0xdb32, 0x00 }, 126 { 0xdd32, 0x00 }, 127 { 0xdb33, 0x0a }, 128 { 0xdd33, 0x0a }, 129 { 0xdb34, 0x1a }, 130 { 0xdd34, 0x1a }, 131 { 0xdb17, 0xef }, 132 { 0xdd17, 0xef }, 133 { 0xdba7, 0x00 }, 134 { 0xdba8, 0x64 }, 135 { 0xdda7, 0x00 }, 136 { 0xdda8, 0x64 }, 137 { 0xdb19, 0x40 }, 138 { 0xdd19, 0x40 }, 139 { 0xdb00, 0x4c }, 140 { 0xdb01, 0x79 }, 141 { 0xdd01, 0x79 }, 142 { 0xdb04, 0x05 }, 143 { 0xdb05, 0x03 }, 144 { 0xdd04, 0x05 }, 145 { 0xdd05, 0x03 }, 146 { 0xdbbb, 0x09 }, 147 { 0xdbbc, 0x30 }, 148 { 0xdbbd, 0xf0 }, 149 { 0xdbbe, 0xf1 }, 150 { 0xddbb, 0x09 }, 151 { 0xddbc, 0x30 }, 152 { 0xddbd, 0xf0 }, 153 { 0xddbe, 0xf1 }, 154 { 0xdb01, 0x79 }, 155 { 0xdd01, 0x79 }, 156 { 0xdc52, 0xef }, 157 { 0xde52, 0xef }, 158 { 0x2f55, 0x22 }, 159 }; 160 161 static const struct reg_default rt1318_reg_defaults[] = { 162 { 0x3000, 0x00 }, 163 { 0x3004, 0x01 }, 164 { 0x3005, 0x23 }, 165 { 0x3202, 0x00 }, 166 { 0x3203, 0x01 }, 167 { 0x3206, 0x00 }, 168 { 0xc000, 0x00 }, 169 { 0xc001, 0x43 }, 170 { 0xc003, 0x22 }, 171 { 0xc004, 0x44 }, 172 { 0xc005, 0x44 }, 173 { 0xc006, 0x33 }, 174 { 0xc007, 0x64 }, 175 { 0xc008, 0x05 }, 176 { 0xc00a, 0xfc }, 177 { 0xc00b, 0x0f }, 178 { 0xc00c, 0x0e }, 179 { 0xc00d, 0xef }, 180 { 0xc00e, 0xe5 }, 181 { 0xc00f, 0xff }, 182 { 0xc120, 0xc0 }, 183 { 0xc121, 0x00 }, 184 { 0xc122, 0x00 }, 185 { 0xc123, 0x14 }, 186 { 0xc125, 0x00 }, 187 { 0xc200, 0x00 }, 188 { 0xc201, 0x00 }, 189 { 0xc202, 0x00 }, 190 { 0xc203, 0x04 }, 191 { 0xc204, 0x00 }, 192 { 0xc205, 0x00 }, 193 { 0xc206, 0x68 }, 194 { 0xc207, 0x70 }, 195 { 0xc208, 0x00 }, 196 { 0xc20a, 0x00 }, 197 { 0xc20b, 0x01 }, 198 { 0xc20c, 0x7f }, 199 { 0xc20d, 0x01 }, 200 { 0xc20e, 0x7f }, 201 { 0xc300, 0x00 }, 202 { 0xc301, 0x00 }, 203 { 0xc303, 0x80 }, 204 { 0xc320, 0x00 }, 205 { 0xc321, 0x09 }, 206 { 0xc322, 0x02 }, 207 { 0xc410, 0x04 }, 208 { 0xc430, 0x00 }, 209 { 0xc431, 0x00 }, 210 { 0xca00, 0x10 }, 211 { 0xca01, 0x00 }, 212 { 0xca02, 0x0b }, 213 { 0xca10, 0x10 }, 214 { 0xca11, 0x00 }, 215 { 0xca12, 0x0b }, 216 { 0xdd93, 0x00 }, 217 { 0xdd94, 0x64 }, 218 { 0xe300, 0xa0 }, 219 { 0xed00, 0x80 }, 220 { 0xed01, 0x0f }, 221 { 0xed02, 0xff }, 222 { 0xed03, 0x00 }, 223 { 0xed04, 0x00 }, 224 { 0xed05, 0x0f }, 225 { 0xed06, 0xff }, 226 { 0xf010, 0x10 }, 227 { 0xf011, 0xec }, 228 { 0xf012, 0x68 }, 229 { 0xf013, 0x21 }, 230 { 0xf800, 0x00 }, 231 { 0xf801, 0x12 }, 232 { 0xf802, 0xe0 }, 233 { 0xf803, 0x2f }, 234 { 0xf804, 0x00 }, 235 { 0xf805, 0x00 }, 236 { 0xf806, 0x07 }, 237 { 0xf807, 0xff }, 238 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 239 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 240 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 241 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 }, 242 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 243 }; 244 245 static bool rt1318_readable_register(struct device *dev, unsigned int reg) 246 { 247 switch (reg) { 248 case 0x2f55: 249 case 0x3000: 250 case 0x3004 ... 0x3005: 251 case 0x3202 ... 0x3203: 252 case 0x3206: 253 case 0xc000 ... 0xc00f: 254 case 0xc120 ... 0xc125: 255 case 0xc200 ... 0xc20e: 256 case 0xc300 ... 0xc303: 257 case 0xc320 ... 0xc322: 258 case 0xc410: 259 case 0xc430 ... 0xc431: 260 case 0xca00 ... 0xca02: 261 case 0xca10 ... 0xca12: 262 case 0xcb00 ... 0xcb0b: 263 case 0xcc00 ... 0xcce5: 264 case 0xcd00 ... 0xcde5: 265 case 0xce00 ... 0xce6a: 266 case 0xcf00 ... 0xcf53: 267 case 0xd000 ... 0xd0cc: 268 case 0xd100 ... 0xd1b9: 269 case 0xdb00 ... 0xdc53: 270 case 0xdd00 ... 0xde53: 271 case 0xdf00 ... 0xdf6b: 272 case 0xe300: 273 case 0xeb00 ... 0xebcc: 274 case 0xec00 ... 0xecb9: 275 case 0xed00 ... 0xed06: 276 case 0xf010 ... 0xf014: 277 case 0xf800 ... 0xf807: 278 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0): 279 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L): 280 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R): 281 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, RT1318_SDCA_CTL_REQ_POWER_STATE, 0): 282 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 283 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 284 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 285 return true; 286 default: 287 return false; 288 } 289 } 290 291 static bool rt1318_volatile_register(struct device *dev, unsigned int reg) 292 { 293 switch (reg) { 294 case 0x2f55: 295 case 0x3000 ... 0x3001: 296 case 0xc000: 297 case 0xc301: 298 case 0xc410: 299 case 0xc430 ... 0xc431: 300 case 0xdb06: 301 case 0xdb12: 302 case 0xdb1d ... 0xdb1f: 303 case 0xdb35: 304 case 0xdb37: 305 case 0xdb8a ... 0xdb92: 306 case 0xdbc5 ... 0xdbc8: 307 case 0xdc2b ... 0xdc49: 308 case 0xdd0b: 309 case 0xdd12: 310 case 0xdd1d ... 0xdd1f: 311 case 0xdd35: 312 case 0xdd8a ... 0xdd92: 313 case 0xddc5 ... 0xddc8: 314 case 0xde2b ... 0xde44: 315 case 0xdf4a ... 0xdf55: 316 case 0xe224 ... 0xe23b: 317 case 0xea01: 318 case 0xebc5: 319 case 0xebc8: 320 case 0xebcb ... 0xebcc: 321 case 0xed03 ... 0xed06: 322 case 0xf010 ... 0xf014: 323 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 324 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_SAPU, RT1318_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 325 return true; 326 default: 327 return false; 328 } 329 } 330 331 static const struct regmap_config rt1318_sdw_regmap = { 332 .reg_bits = 32, 333 .val_bits = 8, 334 .readable_reg = rt1318_readable_register, 335 .volatile_reg = rt1318_volatile_register, 336 .max_register = 0x41081488, 337 .reg_defaults = rt1318_reg_defaults, 338 .num_reg_defaults = ARRAY_SIZE(rt1318_reg_defaults), 339 .cache_type = REGCACHE_MAPLE, 340 .use_single_read = true, 341 .use_single_write = true, 342 }; 343 344 static int rt1318_read_prop(struct sdw_slave *slave) 345 { 346 struct sdw_slave_prop *prop = &slave->prop; 347 int nval; 348 int i, j; 349 u32 bit; 350 unsigned long addr; 351 struct sdw_dpn_prop *dpn; 352 353 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 354 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 355 356 prop->paging_support = true; 357 358 /* first we need to allocate memory for set bits in port lists */ 359 prop->source_ports = BIT(2); 360 prop->sink_ports = BIT(1); 361 362 nval = hweight32(prop->source_ports); 363 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 364 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 365 if (!prop->src_dpn_prop) 366 return -ENOMEM; 367 368 i = 0; 369 dpn = prop->src_dpn_prop; 370 addr = prop->source_ports; 371 for_each_set_bit(bit, &addr, 32) { 372 dpn[i].num = bit; 373 dpn[i].type = SDW_DPN_FULL; 374 dpn[i].simple_ch_prep_sm = true; 375 dpn[i].ch_prep_timeout = 10; 376 i++; 377 } 378 379 /* do this again for sink now */ 380 nval = hweight32(prop->sink_ports); 381 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 382 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 383 if (!prop->sink_dpn_prop) 384 return -ENOMEM; 385 386 j = 0; 387 dpn = prop->sink_dpn_prop; 388 addr = prop->sink_ports; 389 for_each_set_bit(bit, &addr, 32) { 390 dpn[j].num = bit; 391 dpn[j].type = SDW_DPN_FULL; 392 dpn[j].simple_ch_prep_sm = true; 393 dpn[j].ch_prep_timeout = 10; 394 j++; 395 } 396 397 /* set the timeout values */ 398 prop->clk_stop_timeout = 20; 399 400 return 0; 401 } 402 403 static int rt1318_io_init(struct device *dev, struct sdw_slave *slave) 404 { 405 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev); 406 407 if (rt1318->hw_init) 408 return 0; 409 410 regcache_cache_only(rt1318->regmap, false); 411 if (rt1318->first_hw_init) { 412 regcache_cache_bypass(rt1318->regmap, true); 413 } else { 414 /* 415 * PM runtime status is marked as 'active' only when a Slave reports as Attached 416 */ 417 /* update count of parent 'active' children */ 418 pm_runtime_set_active(&slave->dev); 419 } 420 421 pm_runtime_get_noresume(&slave->dev); 422 423 /* blind write */ 424 regmap_multi_reg_write(rt1318->regmap, rt1318_blind_write, 425 ARRAY_SIZE(rt1318_blind_write)); 426 427 if (rt1318->first_hw_init) { 428 regcache_cache_bypass(rt1318->regmap, false); 429 regcache_mark_dirty(rt1318->regmap); 430 } 431 432 /* Mark Slave initialization complete */ 433 rt1318->first_hw_init = true; 434 rt1318->hw_init = true; 435 436 pm_runtime_put_autosuspend(&slave->dev); 437 438 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 439 return 0; 440 } 441 442 static int rt1318_update_status(struct sdw_slave *slave, 443 enum sdw_slave_status status) 444 { 445 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(&slave->dev); 446 447 if (status == SDW_SLAVE_UNATTACHED) 448 rt1318->hw_init = false; 449 450 /* 451 * Perform initialization only if slave status is present and 452 * hw_init flag is false 453 */ 454 if (rt1318->hw_init || status != SDW_SLAVE_ATTACHED) 455 return 0; 456 457 /* perform I/O transfers required for Slave initialization */ 458 return rt1318_io_init(&slave->dev, slave); 459 } 460 461 static int rt1318_classd_event(struct snd_soc_dapm_widget *w, 462 struct snd_kcontrol *kcontrol, int event) 463 { 464 struct snd_soc_component *component = 465 snd_soc_dapm_to_component(w->dapm); 466 struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component); 467 unsigned char ps0 = 0x0, ps3 = 0x3; 468 469 switch (event) { 470 case SND_SOC_DAPM_POST_PMU: 471 regmap_write(rt1318->regmap, 472 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, 473 RT1318_SDCA_CTL_REQ_POWER_STATE, 0), 474 ps0); 475 break; 476 case SND_SOC_DAPM_PRE_PMD: 477 regmap_write(rt1318->regmap, 478 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_PDE23, 479 RT1318_SDCA_CTL_REQ_POWER_STATE, 0), 480 ps3); 481 break; 482 483 default: 484 break; 485 } 486 487 return 0; 488 } 489 490 static const char * const rt1318_rx_data_ch_select[] = { 491 "L,R", 492 "L,L", 493 "L,R", 494 "L,L+R", 495 "R,L", 496 "R,R", 497 "R,L+R", 498 "L+R,L", 499 "L+R,R", 500 "L+R,L+R", 501 }; 502 503 static SOC_ENUM_SINGLE_DECL(rt1318_rx_data_ch_enum, 504 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_UDMPU21, RT1318_SDCA_CTL_UDMPU_CLUSTER, 0), 0, 505 rt1318_rx_data_ch_select); 506 507 static const struct snd_kcontrol_new rt1318_snd_controls[] = { 508 509 /* UDMPU Cluster Selection */ 510 SOC_ENUM("RX Channel Select", rt1318_rx_data_ch_enum), 511 }; 512 513 static const struct snd_kcontrol_new rt1318_sto_dac = 514 SOC_DAPM_DOUBLE_R("Switch", 515 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_L), 516 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_FU21, RT1318_SDCA_CTL_FU_MUTE, CH_R), 517 0, 1, 1); 518 519 static const struct snd_soc_dapm_widget rt1318_dapm_widgets[] = { 520 /* Audio Interface */ 521 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 522 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0), 523 524 /* Digital Interface */ 525 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1318_sto_dac), 526 527 /* Output */ 528 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 529 rt1318_classd_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 530 SND_SOC_DAPM_OUTPUT("SPOL"), 531 SND_SOC_DAPM_OUTPUT("SPOR"), 532 /* Input */ 533 SND_SOC_DAPM_PGA("FB Data", SND_SOC_NOPM, 0, 0, NULL, 0), 534 SND_SOC_DAPM_SIGGEN("FB Gen"), 535 }; 536 537 static const struct snd_soc_dapm_route rt1318_dapm_routes[] = { 538 { "DAC", "Switch", "DP1RX" }, 539 { "CLASS D", NULL, "DAC" }, 540 { "SPOL", NULL, "CLASS D" }, 541 { "SPOR", NULL, "CLASS D" }, 542 543 { "FB Data", NULL, "FB Gen" }, 544 { "DP2TX", NULL, "FB Data" }, 545 }; 546 547 static int rt1318_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 548 int direction) 549 { 550 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 551 552 return 0; 553 } 554 555 static void rt1318_sdw_shutdown(struct snd_pcm_substream *substream, 556 struct snd_soc_dai *dai) 557 { 558 snd_soc_dai_set_dma_data(dai, substream, NULL); 559 } 560 561 static int rt1318_sdw_hw_params(struct snd_pcm_substream *substream, 562 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 563 { 564 struct snd_soc_component *component = dai->component; 565 struct rt1318_sdw_priv *rt1318 = 566 snd_soc_component_get_drvdata(component); 567 struct sdw_stream_config stream_config; 568 struct sdw_port_config port_config; 569 enum sdw_data_direction direction; 570 struct sdw_stream_runtime *sdw_stream; 571 int retval, port, num_channels, ch_mask; 572 unsigned int sampling_rate; 573 574 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 575 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 576 577 if (!sdw_stream) 578 return -EINVAL; 579 580 if (!rt1318->sdw_slave) 581 return -EINVAL; 582 583 /* SoundWire specific configuration */ 584 /* port 1 for playback */ 585 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 586 direction = SDW_DATA_DIR_RX; 587 port = 1; 588 } else { 589 direction = SDW_DATA_DIR_TX; 590 port = 2; 591 } 592 593 num_channels = params_channels(params); 594 ch_mask = (1 << num_channels) - 1; 595 596 stream_config.frame_rate = params_rate(params); 597 stream_config.ch_count = num_channels; 598 stream_config.bps = snd_pcm_format_width(params_format(params)); 599 stream_config.direction = direction; 600 601 port_config.ch_mask = ch_mask; 602 port_config.num = port; 603 604 retval = sdw_stream_add_slave(rt1318->sdw_slave, &stream_config, 605 &port_config, 1, sdw_stream); 606 if (retval) { 607 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 608 return retval; 609 } 610 611 /* sampling rate configuration */ 612 switch (params_rate(params)) { 613 case 16000: 614 sampling_rate = RT1318_SDCA_RATE_16000HZ; 615 break; 616 case 32000: 617 sampling_rate = RT1318_SDCA_RATE_32000HZ; 618 break; 619 case 44100: 620 sampling_rate = RT1318_SDCA_RATE_44100HZ; 621 break; 622 case 48000: 623 sampling_rate = RT1318_SDCA_RATE_48000HZ; 624 break; 625 case 96000: 626 sampling_rate = RT1318_SDCA_RATE_96000HZ; 627 break; 628 case 192000: 629 sampling_rate = RT1318_SDCA_RATE_192000HZ; 630 break; 631 default: 632 dev_err(component->dev, "%s: Rate %d is not supported\n", 633 __func__, params_rate(params)); 634 return -EINVAL; 635 } 636 637 /* set sampling frequency */ 638 regmap_write(rt1318->regmap, 639 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1318_SDCA_ENT_CS21, RT1318_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 640 sampling_rate); 641 642 return 0; 643 } 644 645 static int rt1318_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 646 struct snd_soc_dai *dai) 647 { 648 struct snd_soc_component *component = dai->component; 649 struct rt1318_sdw_priv *rt1318 = 650 snd_soc_component_get_drvdata(component); 651 struct sdw_stream_runtime *sdw_stream = 652 snd_soc_dai_get_dma_data(dai, substream); 653 654 if (!rt1318->sdw_slave) 655 return -EINVAL; 656 657 sdw_stream_remove_slave(rt1318->sdw_slave, sdw_stream); 658 return 0; 659 } 660 661 /* 662 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 663 * port_prep are not defined for now 664 */ 665 static const struct sdw_slave_ops rt1318_slave_ops = { 666 .read_prop = rt1318_read_prop, 667 .update_status = rt1318_update_status, 668 }; 669 670 static int rt1318_sdw_component_probe(struct snd_soc_component *component) 671 { 672 int ret; 673 struct rt1318_sdw_priv *rt1318 = snd_soc_component_get_drvdata(component); 674 675 rt1318->component = component; 676 677 if (!rt1318->first_hw_init) 678 return 0; 679 680 ret = pm_runtime_resume(component->dev); 681 dev_dbg(&rt1318->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 682 if (ret < 0 && ret != -EACCES) 683 return ret; 684 685 return 0; 686 } 687 688 static const struct snd_soc_component_driver soc_component_sdw_rt1318 = { 689 .probe = rt1318_sdw_component_probe, 690 .controls = rt1318_snd_controls, 691 .num_controls = ARRAY_SIZE(rt1318_snd_controls), 692 .dapm_widgets = rt1318_dapm_widgets, 693 .num_dapm_widgets = ARRAY_SIZE(rt1318_dapm_widgets), 694 .dapm_routes = rt1318_dapm_routes, 695 .num_dapm_routes = ARRAY_SIZE(rt1318_dapm_routes), 696 .endianness = 1, 697 }; 698 699 static const struct snd_soc_dai_ops rt1318_aif_dai_ops = { 700 .hw_params = rt1318_sdw_hw_params, 701 .hw_free = rt1318_sdw_pcm_hw_free, 702 .set_stream = rt1318_set_sdw_stream, 703 .shutdown = rt1318_sdw_shutdown, 704 }; 705 706 #define RT1318_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 707 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 708 #define RT1318_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 709 SNDRV_PCM_FMTBIT_S32_LE) 710 711 static struct snd_soc_dai_driver rt1318_sdw_dai[] = { 712 { 713 .name = "rt1318-aif", 714 .playback = { 715 .stream_name = "DP1 Playback", 716 .channels_min = 1, 717 .channels_max = 2, 718 .rates = RT1318_STEREO_RATES, 719 .formats = RT1318_FORMATS, 720 }, 721 .capture = { 722 .stream_name = "DP2 Capture", 723 .channels_min = 1, 724 .channels_max = 2, 725 .rates = RT1318_STEREO_RATES, 726 .formats = RT1318_FORMATS, 727 }, 728 .ops = &rt1318_aif_dai_ops, 729 }, 730 }; 731 732 static int rt1318_sdw_init(struct device *dev, struct regmap *regmap, 733 struct sdw_slave *slave) 734 { 735 struct rt1318_sdw_priv *rt1318; 736 int ret; 737 738 rt1318 = devm_kzalloc(dev, sizeof(*rt1318), GFP_KERNEL); 739 if (!rt1318) 740 return -ENOMEM; 741 742 dev_set_drvdata(dev, rt1318); 743 rt1318->sdw_slave = slave; 744 rt1318->regmap = regmap; 745 746 regcache_cache_only(rt1318->regmap, true); 747 748 /* 749 * Mark hw_init to false 750 * HW init will be performed when device reports present 751 */ 752 rt1318->hw_init = false; 753 rt1318->first_hw_init = false; 754 755 ret = devm_snd_soc_register_component(dev, 756 &soc_component_sdw_rt1318, 757 rt1318_sdw_dai, 758 ARRAY_SIZE(rt1318_sdw_dai)); 759 if (ret < 0) 760 return ret; 761 762 /* set autosuspend parameters */ 763 pm_runtime_set_autosuspend_delay(dev, 3000); 764 pm_runtime_use_autosuspend(dev); 765 766 /* make sure the device does not suspend immediately */ 767 pm_runtime_mark_last_busy(dev); 768 769 pm_runtime_enable(dev); 770 771 /* important note: the device is NOT tagged as 'active' and will remain 772 * 'suspended' until the hardware is enumerated/initialized. This is required 773 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 774 * fail with -EACCESS because of race conditions between card creation and enumeration 775 */ 776 777 dev_dbg(dev, "%s\n", __func__); 778 779 return ret; 780 } 781 782 static int rt1318_sdw_probe(struct sdw_slave *slave, 783 const struct sdw_device_id *id) 784 { 785 struct regmap *regmap; 786 787 /* Regmap Initialization */ 788 regmap = devm_regmap_init_sdw(slave, &rt1318_sdw_regmap); 789 if (IS_ERR(regmap)) 790 return PTR_ERR(regmap); 791 792 return rt1318_sdw_init(&slave->dev, regmap, slave); 793 } 794 795 static void rt1318_sdw_remove(struct sdw_slave *slave) 796 { 797 pm_runtime_disable(&slave->dev); 798 } 799 800 static const struct sdw_device_id rt1318_id[] = { 801 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1318, 0x3, 0x1, 0), 802 {}, 803 }; 804 MODULE_DEVICE_TABLE(sdw, rt1318_id); 805 806 static int rt1318_dev_suspend(struct device *dev) 807 { 808 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev); 809 810 if (!rt1318->hw_init) 811 return 0; 812 813 regcache_cache_only(rt1318->regmap, true); 814 return 0; 815 } 816 817 #define RT1318_PROBE_TIMEOUT 5000 818 819 static int rt1318_dev_resume(struct device *dev) 820 { 821 struct sdw_slave *slave = dev_to_sdw_dev(dev); 822 struct rt1318_sdw_priv *rt1318 = dev_get_drvdata(dev); 823 int ret; 824 825 if (!rt1318->first_hw_init) 826 return 0; 827 828 ret = sdw_slave_wait_for_init(slave, RT1318_PROBE_TIMEOUT); 829 if (ret) 830 return ret; 831 832 regcache_cache_only(rt1318->regmap, false); 833 ret = regcache_sync(rt1318->regmap); 834 if (ret) { 835 regcache_cache_only(rt1318->regmap, true); 836 regcache_mark_dirty(rt1318->regmap); 837 return ret; 838 } 839 840 return 0; 841 } 842 843 static const struct dev_pm_ops rt1318_pm = { 844 SYSTEM_SLEEP_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume) 845 RUNTIME_PM_OPS(rt1318_dev_suspend, rt1318_dev_resume, NULL) 846 }; 847 848 static struct sdw_driver rt1318_sdw_driver = { 849 .driver = { 850 .name = "rt1318-sdca", 851 .pm = pm_ptr(&rt1318_pm), 852 }, 853 .probe = rt1318_sdw_probe, 854 .remove = rt1318_sdw_remove, 855 .ops = &rt1318_slave_ops, 856 .id_table = rt1318_id, 857 }; 858 module_sdw_driver(rt1318_sdw_driver); 859 860 MODULE_DESCRIPTION("ASoC RT1318 driver SDCA SDW"); 861 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 862 MODULE_LICENSE("GPL"); 863