1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2021 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <sound/core.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <sound/sdw.h> 17 #include <sound/soc-dapm.h> 18 #include <sound/initval.h> 19 #include "rt1316-sdw.h" 20 21 static const struct reg_default rt1316_reg_defaults[] = { 22 { 0x3004, 0x00 }, 23 { 0x3005, 0x00 }, 24 { 0x3206, 0x00 }, 25 { 0xc001, 0x00 }, 26 { 0xc002, 0x00 }, 27 { 0xc003, 0x00 }, 28 { 0xc004, 0x00 }, 29 { 0xc005, 0x00 }, 30 { 0xc006, 0x00 }, 31 { 0xc007, 0x00 }, 32 { 0xc008, 0x00 }, 33 { 0xc009, 0x00 }, 34 { 0xc00a, 0x00 }, 35 { 0xc00b, 0x00 }, 36 { 0xc00c, 0x00 }, 37 { 0xc00d, 0x00 }, 38 { 0xc00e, 0x00 }, 39 { 0xc00f, 0x00 }, 40 { 0xc010, 0xa5 }, 41 { 0xc011, 0x00 }, 42 { 0xc012, 0xff }, 43 { 0xc013, 0xff }, 44 { 0xc014, 0x40 }, 45 { 0xc015, 0x00 }, 46 { 0xc016, 0x00 }, 47 { 0xc017, 0x00 }, 48 { 0xc605, 0x30 }, 49 { 0xc700, 0x0a }, 50 { 0xc701, 0xaa }, 51 { 0xc702, 0x1a }, 52 { 0xc703, 0x0a }, 53 { 0xc710, 0x80 }, 54 { 0xc711, 0x00 }, 55 { 0xc712, 0x3e }, 56 { 0xc713, 0x80 }, 57 { 0xc714, 0x80 }, 58 { 0xc715, 0x06 }, 59 { 0xd101, 0x00 }, 60 { 0xd102, 0x30 }, 61 { 0xd103, 0x00 }, 62 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 63 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 64 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 }, 65 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 66 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 67 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 68 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 }, 69 }; 70 71 static const struct reg_sequence rt1316_blind_write[] = { 72 { 0xc710, 0x17 }, 73 { 0xc711, 0x80 }, 74 { 0xc712, 0x26 }, 75 { 0xc713, 0x06 }, 76 { 0xc714, 0x80 }, 77 { 0xc715, 0x06 }, 78 { 0xc702, 0x0a }, 79 { 0xc703, 0x0a }, 80 { 0xc001, 0x45 }, 81 { 0xc003, 0x00 }, 82 { 0xc004, 0x11 }, 83 { 0xc005, 0x00 }, 84 { 0xc006, 0x00 }, 85 { 0xc106, 0x00 }, 86 { 0xc007, 0x11 }, 87 { 0xc008, 0x11 }, 88 { 0xc009, 0x00 }, 89 90 { 0x2f0a, 0x00 }, 91 { 0xd101, 0xf0 }, 92 { 0xd103, 0x9b }, 93 { 0x2f36, 0x8e }, 94 { 0x3206, 0x80 }, 95 { 0x3211, 0x0b }, 96 { 0x3216, 0x06 }, 97 { 0xc614, 0x20 }, 98 { 0xc615, 0x0a }, 99 { 0xc616, 0x02 }, 100 { 0xc617, 0x00 }, 101 { 0xc60b, 0x10 }, 102 { 0xc60e, 0x05 }, 103 { 0xc102, 0x00 }, 104 { 0xc090, 0xb0 }, 105 { 0xc00f, 0x01 }, 106 { 0xc09c, 0x7b }, 107 108 { 0xc602, 0x07 }, 109 { 0xc603, 0x07 }, 110 { 0xc0a3, 0x71 }, 111 { 0xc00b, 0x30 }, 112 { 0xc093, 0x80 }, 113 { 0xc09d, 0x80 }, 114 { 0xc0b0, 0x77 }, 115 { 0xc010, 0xa5 }, 116 { 0xc050, 0x83 }, 117 { 0x2f55, 0x03 }, 118 { 0x3217, 0xb5 }, 119 { 0x3202, 0x02 }, 120 121 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 }, 122 123 /* for IV sense */ 124 { 0x2232, 0x80 }, 125 { 0xc0b0, 0x77 }, 126 { 0xc011, 0x00 }, 127 { 0xc020, 0x00 }, 128 { 0xc023, 0x00 }, 129 { 0x3101, 0x00 }, 130 { 0x3004, 0xa0 }, 131 { 0x3005, 0xb1 }, 132 { 0xc007, 0x11 }, 133 { 0xc008, 0x11 }, 134 { 0xc009, 0x00 }, 135 { 0xc022, 0xd6 }, 136 { 0xc025, 0xd6 }, 137 138 { 0xd001, 0x03 }, 139 { 0xd002, 0xbf }, 140 { 0xd003, 0x03 }, 141 { 0xd004, 0xbf }, 142 }; 143 144 static bool rt1316_readable_register(struct device *dev, unsigned int reg) 145 { 146 switch (reg) { 147 case 0x2f0a: 148 case 0x2f36: 149 case 0x3203 ... 0x320e: 150 case 0xc000 ... 0xc7b4: 151 case 0xcf00 ... 0xcf03: 152 case 0xd101 ... 0xd103: 153 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0): 154 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L): 155 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R): 156 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 157 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 158 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 159 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): 160 return true; 161 default: 162 return false; 163 } 164 } 165 166 static bool rt1316_volatile_register(struct device *dev, unsigned int reg) 167 { 168 switch (reg) { 169 case 0xc000: 170 case 0xc093: 171 case 0xc09d: 172 case 0xc0a3: 173 case 0xc201: 174 case 0xc427 ... 0xc428: 175 case 0xd102: 176 return true; 177 default: 178 return false; 179 } 180 } 181 182 static const struct regmap_config rt1316_sdw_regmap = { 183 .reg_bits = 32, 184 .val_bits = 8, 185 .readable_reg = rt1316_readable_register, 186 .volatile_reg = rt1316_volatile_register, 187 .max_register = 0x4108ffff, 188 .reg_defaults = rt1316_reg_defaults, 189 .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults), 190 .cache_type = REGCACHE_MAPLE, 191 .use_single_read = true, 192 .use_single_write = true, 193 }; 194 195 static int rt1316_read_prop(struct sdw_slave *slave) 196 { 197 struct sdw_slave_prop *prop = &slave->prop; 198 int nval; 199 int i, j; 200 u32 bit; 201 unsigned long addr; 202 struct sdw_dpn_prop *dpn; 203 204 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 205 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 206 207 prop->paging_support = true; 208 209 /* first we need to allocate memory for set bits in port lists */ 210 prop->source_ports = 0x04; /* BITMAP: 00000100 */ 211 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 212 213 nval = hweight32(prop->source_ports); 214 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 215 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 216 if (!prop->src_dpn_prop) 217 return -ENOMEM; 218 219 i = 0; 220 dpn = prop->src_dpn_prop; 221 addr = prop->source_ports; 222 for_each_set_bit(bit, &addr, 32) { 223 dpn[i].num = bit; 224 dpn[i].type = SDW_DPN_FULL; 225 dpn[i].simple_ch_prep_sm = true; 226 dpn[i].ch_prep_timeout = 10; 227 i++; 228 } 229 230 /* do this again for sink now */ 231 nval = hweight32(prop->sink_ports); 232 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 233 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 234 if (!prop->sink_dpn_prop) 235 return -ENOMEM; 236 237 j = 0; 238 dpn = prop->sink_dpn_prop; 239 addr = prop->sink_ports; 240 for_each_set_bit(bit, &addr, 32) { 241 dpn[j].num = bit; 242 dpn[j].type = SDW_DPN_FULL; 243 dpn[j].simple_ch_prep_sm = true; 244 dpn[j].ch_prep_timeout = 10; 245 j++; 246 } 247 248 /* set the timeout values */ 249 prop->clk_stop_timeout = 20; 250 251 dev_dbg(&slave->dev, "%s\n", __func__); 252 253 return 0; 254 } 255 256 static void rt1316_apply_bq_params(struct rt1316_sdw_priv *rt1316) 257 { 258 unsigned int i, reg, data; 259 260 for (i = 0; i < rt1316->bq_params_cnt; i += 3) { 261 reg = rt1316->bq_params[i] | (rt1316->bq_params[i + 1] << 8); 262 data = rt1316->bq_params[i + 2]; 263 regmap_write(rt1316->regmap, reg, data); 264 } 265 } 266 267 static int rt1316_io_init(struct device *dev, struct sdw_slave *slave) 268 { 269 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 270 271 if (rt1316->hw_init) 272 return 0; 273 274 regcache_cache_only(rt1316->regmap, false); 275 if (rt1316->first_hw_init) { 276 regcache_cache_bypass(rt1316->regmap, true); 277 } else { 278 /* 279 * PM runtime status is marked as 'active' only when a Slave reports as Attached 280 */ 281 282 /* update count of parent 'active' children */ 283 pm_runtime_set_active(&slave->dev); 284 } 285 286 pm_runtime_get_noresume(&slave->dev); 287 288 /* sw reset */ 289 regmap_write(rt1316->regmap, 0xc000, 0x02); 290 291 /* initial settings - blind write */ 292 regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write, 293 ARRAY_SIZE(rt1316_blind_write)); 294 295 if (rt1316->first_hw_init) { 296 regcache_cache_bypass(rt1316->regmap, false); 297 regcache_mark_dirty(rt1316->regmap); 298 } else 299 rt1316->first_hw_init = true; 300 301 /* Mark Slave initialization complete */ 302 rt1316->hw_init = true; 303 304 pm_runtime_put_autosuspend(&slave->dev); 305 306 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 307 return 0; 308 } 309 310 static int rt1316_update_status(struct sdw_slave *slave, 311 enum sdw_slave_status status) 312 { 313 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev); 314 315 if (status == SDW_SLAVE_UNATTACHED) 316 rt1316->hw_init = false; 317 318 /* 319 * Perform initialization only if slave status is present and 320 * hw_init flag is false 321 */ 322 if (rt1316->hw_init || status != SDW_SLAVE_ATTACHED) 323 return 0; 324 325 /* perform I/O transfers required for Slave initialization */ 326 return rt1316_io_init(&slave->dev, slave); 327 } 328 329 static int rt1316_classd_event(struct snd_soc_dapm_widget *w, 330 struct snd_kcontrol *kcontrol, int event) 331 { 332 struct snd_soc_component *component = 333 snd_soc_dapm_to_component(w->dapm); 334 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 335 unsigned char ps0 = 0x0, ps3 = 0x3; 336 337 switch (event) { 338 case SND_SOC_DAPM_POST_PMU: 339 regmap_write(rt1316->regmap, 340 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 341 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 342 ps0); 343 regmap_write(rt1316->regmap, 344 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 345 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 346 ps0); 347 regmap_write(rt1316->regmap, 348 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 349 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 350 ps0); 351 break; 352 case SND_SOC_DAPM_PRE_PMD: 353 regmap_write(rt1316->regmap, 354 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, 355 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 356 ps3); 357 regmap_write(rt1316->regmap, 358 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, 359 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 360 ps3); 361 regmap_write(rt1316->regmap, 362 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, 363 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 364 ps3); 365 break; 366 367 default: 368 break; 369 } 370 371 return 0; 372 } 373 374 static int rt1316_pde24_event(struct snd_soc_dapm_widget *w, 375 struct snd_kcontrol *kcontrol, int event) 376 { 377 struct snd_soc_component *component = 378 snd_soc_dapm_to_component(w->dapm); 379 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 380 unsigned char ps0 = 0x0, ps3 = 0x3; 381 382 switch (event) { 383 case SND_SOC_DAPM_POST_PMU: 384 regmap_write(rt1316->regmap, 385 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 386 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 387 ps0); 388 break; 389 case SND_SOC_DAPM_PRE_PMD: 390 regmap_write(rt1316->regmap, 391 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, 392 RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 393 ps3); 394 break; 395 } 396 return 0; 397 } 398 399 static const char * const rt1316_rx_data_ch_select[] = { 400 "L,R", 401 "L,L", 402 "L,R", 403 "L,L+R", 404 "R,L", 405 "R,R", 406 "R,L+R", 407 "L+R,L", 408 "L+R,R", 409 "L+R,L+R", 410 }; 411 412 static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum, 413 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0, 414 rt1316_rx_data_ch_select); 415 416 static const char * const rt1316_dac_output_vol_select[] = { 417 "immediately", 418 "zero crossing", 419 "zero crossing with soft ramp", 420 }; 421 422 static SOC_ENUM_SINGLE_DECL(rt1316_dac_vol_ctl_enum, 423 0xc010, 6, rt1316_dac_output_vol_select); 424 425 static const struct snd_kcontrol_new rt1316_snd_controls[] = { 426 427 /* I2S Data Channel Selection */ 428 SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum), 429 430 /* XU24 Bypass Control */ 431 SOC_SINGLE("XU24 Bypass Switch", 432 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0), 433 434 /* Left/Right IV tag */ 435 SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0), 436 SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0), 437 SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0), 438 SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0), 439 440 /* IV mixer Control */ 441 SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1), 442 SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1), 443 444 /* DAC Output Volume Control */ 445 SOC_ENUM("DAC Output Vol Control", rt1316_dac_vol_ctl_enum), 446 }; 447 448 static const struct snd_kcontrol_new rt1316_sto_dac = 449 SOC_DAPM_DOUBLE_R("Switch", 450 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 451 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 452 0, 1, 1); 453 454 static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = { 455 /* Audio Interface */ 456 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 457 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0), 458 459 /* Digital Interface */ 460 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac), 461 462 /* Output Lines */ 463 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 464 rt1316_classd_event, 465 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 466 SND_SOC_DAPM_OUTPUT("SPOL"), 467 SND_SOC_DAPM_OUTPUT("SPOR"), 468 469 SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0, 470 rt1316_pde24_event, 471 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 472 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 473 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 474 SND_SOC_DAPM_SIGGEN("I Gen"), 475 SND_SOC_DAPM_SIGGEN("V Gen"), 476 }; 477 478 static const struct snd_soc_dapm_route rt1316_dapm_routes[] = { 479 { "DAC", "Switch", "DP1RX" }, 480 { "CLASS D", NULL, "DAC" }, 481 { "SPOL", NULL, "CLASS D" }, 482 { "SPOR", NULL, "CLASS D" }, 483 484 { "I Sense", NULL, "I Gen" }, 485 { "V Sense", NULL, "V Gen" }, 486 { "I Sense", NULL, "PDE 24" }, 487 { "V Sense", NULL, "PDE 24" }, 488 { "DP2TX", NULL, "I Sense" }, 489 { "DP2TX", NULL, "V Sense" }, 490 }; 491 492 static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 493 int direction) 494 { 495 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 496 497 return 0; 498 } 499 500 static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream, 501 struct snd_soc_dai *dai) 502 { 503 snd_soc_dai_set_dma_data(dai, substream, NULL); 504 } 505 506 static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream, 507 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 508 { 509 struct snd_soc_component *component = dai->component; 510 struct rt1316_sdw_priv *rt1316 = 511 snd_soc_component_get_drvdata(component); 512 struct sdw_stream_config stream_config = {0}; 513 struct sdw_port_config port_config = {0}; 514 struct sdw_stream_runtime *sdw_stream; 515 int retval; 516 517 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 518 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 519 520 if (!sdw_stream) 521 return -EINVAL; 522 523 if (!rt1316->sdw_slave) 524 return -EINVAL; 525 526 /* SoundWire specific configuration */ 527 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 528 529 /* port 1 for playback */ 530 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 531 port_config.num = 1; 532 else 533 port_config.num = 2; 534 535 retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config, 536 &port_config, 1, sdw_stream); 537 if (retval) { 538 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 539 return retval; 540 } 541 542 return 0; 543 } 544 545 static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 546 struct snd_soc_dai *dai) 547 { 548 struct snd_soc_component *component = dai->component; 549 struct rt1316_sdw_priv *rt1316 = 550 snd_soc_component_get_drvdata(component); 551 struct sdw_stream_runtime *sdw_stream = 552 snd_soc_dai_get_dma_data(dai, substream); 553 554 if (!rt1316->sdw_slave) 555 return -EINVAL; 556 557 sdw_stream_remove_slave(rt1316->sdw_slave, sdw_stream); 558 return 0; 559 } 560 561 /* 562 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 563 * port_prep are not defined for now 564 */ 565 static const struct sdw_slave_ops rt1316_slave_ops = { 566 .read_prop = rt1316_read_prop, 567 .update_status = rt1316_update_status, 568 }; 569 570 static int rt1316_sdw_parse_dt(struct rt1316_sdw_priv *rt1316, struct device *dev) 571 { 572 int ret = 0; 573 574 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1316->bq_params_cnt); 575 if (rt1316->bq_params_cnt) { 576 rt1316->bq_params = devm_kzalloc(dev, rt1316->bq_params_cnt, GFP_KERNEL); 577 if (!rt1316->bq_params) { 578 dev_err(dev, "%s: Could not allocate bq_params memory\n", __func__); 579 ret = -ENOMEM; 580 } else { 581 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1316->bq_params, rt1316->bq_params_cnt); 582 if (ret < 0) 583 dev_err(dev, "%s: Could not read list of realtek,bq-params\n", __func__); 584 } 585 } 586 587 dev_dbg(dev, "bq_params_cnt=%d\n", rt1316->bq_params_cnt); 588 return ret; 589 } 590 591 static int rt1316_sdw_component_probe(struct snd_soc_component *component) 592 { 593 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component); 594 int ret; 595 596 rt1316->component = component; 597 rt1316_sdw_parse_dt(rt1316, &rt1316->sdw_slave->dev); 598 599 if (!rt1316->first_hw_init) 600 return 0; 601 602 ret = pm_runtime_resume(component->dev); 603 if (ret < 0 && ret != -EACCES) 604 return ret; 605 606 /* apply BQ params */ 607 rt1316_apply_bq_params(rt1316); 608 609 return 0; 610 } 611 612 static const struct snd_soc_component_driver soc_component_sdw_rt1316 = { 613 .probe = rt1316_sdw_component_probe, 614 .controls = rt1316_snd_controls, 615 .num_controls = ARRAY_SIZE(rt1316_snd_controls), 616 .dapm_widgets = rt1316_dapm_widgets, 617 .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets), 618 .dapm_routes = rt1316_dapm_routes, 619 .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes), 620 .endianness = 1, 621 }; 622 623 static const struct snd_soc_dai_ops rt1316_aif_dai_ops = { 624 .hw_params = rt1316_sdw_hw_params, 625 .hw_free = rt1316_sdw_pcm_hw_free, 626 .set_stream = rt1316_set_sdw_stream, 627 .shutdown = rt1316_sdw_shutdown, 628 }; 629 630 #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000 631 #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 632 SNDRV_PCM_FMTBIT_S24_LE) 633 634 static struct snd_soc_dai_driver rt1316_sdw_dai[] = { 635 { 636 .name = "rt1316-aif", 637 .playback = { 638 .stream_name = "DP1 Playback", 639 .channels_min = 1, 640 .channels_max = 2, 641 .rates = RT1316_STEREO_RATES, 642 .formats = RT1316_FORMATS, 643 }, 644 .capture = { 645 .stream_name = "DP2 Capture", 646 .channels_min = 1, 647 .channels_max = 2, 648 .rates = RT1316_STEREO_RATES, 649 .formats = RT1316_FORMATS, 650 }, 651 .ops = &rt1316_aif_dai_ops, 652 }, 653 }; 654 655 static int rt1316_sdw_init(struct device *dev, struct regmap *regmap, 656 struct sdw_slave *slave) 657 { 658 struct rt1316_sdw_priv *rt1316; 659 int ret; 660 661 rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL); 662 if (!rt1316) 663 return -ENOMEM; 664 665 dev_set_drvdata(dev, rt1316); 666 rt1316->sdw_slave = slave; 667 rt1316->regmap = regmap; 668 669 regcache_cache_only(rt1316->regmap, true); 670 671 /* 672 * Mark hw_init to false 673 * HW init will be performed when device reports present 674 */ 675 rt1316->hw_init = false; 676 rt1316->first_hw_init = false; 677 678 ret = devm_snd_soc_register_component(dev, 679 &soc_component_sdw_rt1316, 680 rt1316_sdw_dai, 681 ARRAY_SIZE(rt1316_sdw_dai)); 682 if (ret < 0) 683 return ret; 684 685 /* set autosuspend parameters */ 686 pm_runtime_set_autosuspend_delay(dev, 3000); 687 pm_runtime_use_autosuspend(dev); 688 689 /* make sure the device does not suspend immediately */ 690 pm_runtime_mark_last_busy(dev); 691 692 pm_runtime_enable(dev); 693 694 /* important note: the device is NOT tagged as 'active' and will remain 695 * 'suspended' until the hardware is enumerated/initialized. This is required 696 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 697 * fail with -EACCESS because of race conditions between card creation and enumeration 698 */ 699 700 dev_dbg(dev, "%s\n", __func__); 701 702 return 0; 703 } 704 705 static int rt1316_sdw_probe(struct sdw_slave *slave, 706 const struct sdw_device_id *id) 707 { 708 struct regmap *regmap; 709 710 /* Regmap Initialization */ 711 regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap); 712 if (IS_ERR(regmap)) 713 return PTR_ERR(regmap); 714 715 return rt1316_sdw_init(&slave->dev, regmap, slave); 716 } 717 718 static void rt1316_sdw_remove(struct sdw_slave *slave) 719 { 720 pm_runtime_disable(&slave->dev); 721 } 722 723 static const struct sdw_device_id rt1316_id[] = { 724 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0), 725 {}, 726 }; 727 MODULE_DEVICE_TABLE(sdw, rt1316_id); 728 729 static int rt1316_dev_suspend(struct device *dev) 730 { 731 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 732 733 if (!rt1316->hw_init) 734 return 0; 735 736 regcache_cache_only(rt1316->regmap, true); 737 738 return 0; 739 } 740 741 #define RT1316_PROBE_TIMEOUT 5000 742 743 static int rt1316_dev_resume(struct device *dev) 744 { 745 struct sdw_slave *slave = dev_to_sdw_dev(dev); 746 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); 747 int ret; 748 749 if (!rt1316->first_hw_init) 750 return 0; 751 752 ret = sdw_slave_wait_for_init(slave, RT1316_PROBE_TIMEOUT); 753 if (ret) { 754 sdw_show_ping_status(slave->bus, true); 755 return ret; 756 } 757 758 regcache_cache_only(rt1316->regmap, false); 759 ret = regcache_sync(rt1316->regmap); 760 if (ret) { 761 regcache_cache_only(rt1316->regmap, true); 762 regcache_mark_dirty(rt1316->regmap); 763 return ret; 764 } 765 766 return 0; 767 } 768 769 static const struct dev_pm_ops rt1316_pm = { 770 SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume) 771 RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL) 772 }; 773 774 static struct sdw_driver rt1316_sdw_driver = { 775 .driver = { 776 .name = "rt1316-sdca", 777 .pm = pm_ptr(&rt1316_pm), 778 }, 779 .probe = rt1316_sdw_probe, 780 .remove = rt1316_sdw_remove, 781 .ops = &rt1316_slave_ops, 782 .id_table = rt1316_id, 783 }; 784 module_sdw_driver(rt1316_sdw_driver); 785 786 MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW"); 787 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 788 MODULE_LICENSE("GPL"); 789