1*a789adaeSShuming Fan /* SPDX-License-Identifier: GPL-2.0 */ 22b9def8cSDerek Fang /* 3*a789adaeSShuming Fan * rt1308.h -- RT1308 ALSA SoC amplifier component driver 42b9def8cSDerek Fang * 52b9def8cSDerek Fang * Copyright 2019 Realtek Semiconductor Corp. 62b9def8cSDerek Fang * Author: Derek Fang <derek.fang@realtek.com> 72b9def8cSDerek Fang * 82b9def8cSDerek Fang */ 92b9def8cSDerek Fang 102b9def8cSDerek Fang #ifndef _RT1308_H_ 112b9def8cSDerek Fang #define _RT1308_H_ 122b9def8cSDerek Fang 132b9def8cSDerek Fang #define RT1308_DEVICE_ID_NUM 0x10ec1300 142b9def8cSDerek Fang 152b9def8cSDerek Fang #define RT1308_RESET 0x00 162b9def8cSDerek Fang #define RT1308_RESET_N 0x01 172b9def8cSDerek Fang #define RT1308_CLK_GATING 0x02 182b9def8cSDerek Fang #define RT1308_PLL_1 0x03 192b9def8cSDerek Fang #define RT1308_PLL_2 0x04 202b9def8cSDerek Fang #define RT1308_PLL_INT 0x05 212b9def8cSDerek Fang #define RT1308_CLK_1 0x06 222b9def8cSDerek Fang #define RT1308_DATA_PATH 0x07 232b9def8cSDerek Fang #define RT1308_CLK_2 0x08 242b9def8cSDerek Fang #define RT1308_SIL_DET 0x09 252b9def8cSDerek Fang #define RT1308_CLK_DET 0x0a 262b9def8cSDerek Fang #define RT1308_DC_DET 0x0b 272b9def8cSDerek Fang #define RT1308_DC_DET_THRES 0x0c 282b9def8cSDerek Fang #define RT1308_DAC_SET 0x10 292b9def8cSDerek Fang #define RT1308_SRC_SET 0x11 302b9def8cSDerek Fang #define RT1308_DAC_BUF 0x12 312b9def8cSDerek Fang #define RT1308_ADC_SET 0x13 322b9def8cSDerek Fang #define RT1308_ADC_SET_INT 0x14 332b9def8cSDerek Fang #define RT1308_I2S_SET_1 0x15 342b9def8cSDerek Fang #define RT1308_I2S_SET_2 0x16 352b9def8cSDerek Fang #define RT1308_I2C_I2S_SDW_SET 0x17 362b9def8cSDerek Fang #define RT1308_SDW_REG_RW 0x18 372b9def8cSDerek Fang #define RT1308_SDW_REG_RDATA 0x19 382b9def8cSDerek Fang #define RT1308_IV_SENSE 0x1a 392b9def8cSDerek Fang #define RT1308_I2S_TX_DAC_SET 0x1b 402b9def8cSDerek Fang #define RT1308_AD_FILTER_SET 0x1c 412b9def8cSDerek Fang #define RT1308_DC_CAL_1 0x20 422b9def8cSDerek Fang #define RT1308_DC_CAL_2 0x21 432b9def8cSDerek Fang #define RT1308_DC_CAL_L_OFFSET 0x22 442b9def8cSDerek Fang #define RT1308_DC_CAL_R_OFFSET 0x23 452b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_CTL 0x24 462b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_L 0x25 472b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_R 0x26 482b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_PBTL 0x27 492b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_PVDD 0x28 502b9def8cSDerek Fang #define RT1308_CAL_OFFSET_DAC_PBTL 0x29 512b9def8cSDerek Fang #define RT1308_CAL_OFFSET_DAC_L 0x2a 522b9def8cSDerek Fang #define RT1308_CAL_OFFSET_DAC_R 0x2b 532b9def8cSDerek Fang #define RT1308_CAL_OFFSET_PWM_L 0x2c 542b9def8cSDerek Fang #define RT1308_CAL_OFFSET_PWM_R 0x2d 552b9def8cSDerek Fang #define RT1308_CAL_PWM_VOS_ADC_L 0x2e 562b9def8cSDerek Fang #define RT1308_CAL_PWM_VOS_ADC_R 0x2f 572b9def8cSDerek Fang #define RT1308_CLASS_D_SET_1 0x30 582b9def8cSDerek Fang #define RT1308_CLASS_D_SET_2 0x31 592b9def8cSDerek Fang #define RT1308_POWER 0x32 602b9def8cSDerek Fang #define RT1308_LDO 0x33 612b9def8cSDerek Fang #define RT1308_VREF 0x34 622b9def8cSDerek Fang #define RT1308_MBIAS 0x35 632b9def8cSDerek Fang #define RT1308_POWER_STATUS 0x36 642b9def8cSDerek Fang #define RT1308_POWER_INT 0x37 652b9def8cSDerek Fang #define RT1308_SINE_TONE_GEN_1 0x50 662b9def8cSDerek Fang #define RT1308_SINE_TONE_GEN_2 0x51 672b9def8cSDerek Fang #define RT1308_BQ_SET 0x54 682b9def8cSDerek Fang #define RT1308_BQ_PARA_UPDATE 0x55 692b9def8cSDerek Fang #define RT1308_BQ_PRE_VOL_L 0x56 702b9def8cSDerek Fang #define RT1308_BQ_PRE_VOL_R 0x57 712b9def8cSDerek Fang #define RT1308_BQ_POST_VOL_L 0x58 722b9def8cSDerek Fang #define RT1308_BQ_POST_VOL_R 0x59 732b9def8cSDerek Fang #define RT1308_BQ1_L_H0 0x5b 742b9def8cSDerek Fang #define RT1308_BQ1_L_B1 0x5c 752b9def8cSDerek Fang #define RT1308_BQ1_L_B2 0x5d 762b9def8cSDerek Fang #define RT1308_BQ1_L_A1 0x5e 772b9def8cSDerek Fang #define RT1308_BQ1_L_A2 0x5f 782b9def8cSDerek Fang #define RT1308_BQ1_R_H0 0x60 792b9def8cSDerek Fang #define RT1308_BQ1_R_B1 0x61 802b9def8cSDerek Fang #define RT1308_BQ1_R_B2 0x62 812b9def8cSDerek Fang #define RT1308_BQ1_R_A1 0x63 822b9def8cSDerek Fang #define RT1308_BQ1_R_A2 0x64 832b9def8cSDerek Fang #define RT1308_BQ2_L_H0 0x65 842b9def8cSDerek Fang #define RT1308_BQ2_L_B1 0x66 852b9def8cSDerek Fang #define RT1308_BQ2_L_B2 0x67 862b9def8cSDerek Fang #define RT1308_BQ2_L_A1 0x68 872b9def8cSDerek Fang #define RT1308_BQ2_L_A2 0x69 882b9def8cSDerek Fang #define RT1308_BQ2_R_H0 0x6a 892b9def8cSDerek Fang #define RT1308_BQ2_R_B1 0x6b 902b9def8cSDerek Fang #define RT1308_BQ2_R_B2 0x6c 912b9def8cSDerek Fang #define RT1308_BQ2_R_A1 0x6d 922b9def8cSDerek Fang #define RT1308_BQ2_R_A2 0x6e 932b9def8cSDerek Fang #define RT1308_VEN_DEV_ID 0x70 942b9def8cSDerek Fang #define RT1308_VERSION_ID 0x71 952b9def8cSDerek Fang #define RT1308_SPK_BOUND 0x72 962b9def8cSDerek Fang #define RT1308_BQ1_EQ_L_1 0x73 972b9def8cSDerek Fang #define RT1308_BQ1_EQ_L_2 0x74 982b9def8cSDerek Fang #define RT1308_BQ1_EQ_L_3 0x75 992b9def8cSDerek Fang #define RT1308_BQ1_EQ_R_1 0x76 1002b9def8cSDerek Fang #define RT1308_BQ1_EQ_R_2 0x77 1012b9def8cSDerek Fang #define RT1308_BQ1_EQ_R_3 0x78 1022b9def8cSDerek Fang #define RT1308_BQ2_EQ_L_1 0x79 1032b9def8cSDerek Fang #define RT1308_BQ2_EQ_L_2 0x7a 1042b9def8cSDerek Fang #define RT1308_BQ2_EQ_L_3 0x7b 1052b9def8cSDerek Fang #define RT1308_BQ2_EQ_R_1 0x7c 1062b9def8cSDerek Fang #define RT1308_BQ2_EQ_R_2 0x7d 1072b9def8cSDerek Fang #define RT1308_BQ2_EQ_R_3 0x7e 1082b9def8cSDerek Fang #define RT1308_EFUSE_1 0x7f 1092b9def8cSDerek Fang #define RT1308_EFUSE_2 0x80 1102b9def8cSDerek Fang #define RT1308_EFUSE_PROG_PVDD_L 0x81 1112b9def8cSDerek Fang #define RT1308_EFUSE_PROG_PVDD_R 0x82 1122b9def8cSDerek Fang #define RT1308_EFUSE_PROG_R0_L 0x83 1132b9def8cSDerek Fang #define RT1308_EFUSE_PROG_R0_R 0x84 1142b9def8cSDerek Fang #define RT1308_EFUSE_PROG_DEV 0x85 1152b9def8cSDerek Fang #define RT1308_EFUSE_READ_PVDD_L 0x86 1162b9def8cSDerek Fang #define RT1308_EFUSE_READ_PVDD_R 0x87 1172b9def8cSDerek Fang #define RT1308_EFUSE_READ_PVDD_PTBL 0x88 1182b9def8cSDerek Fang #define RT1308_EFUSE_READ_DEV 0x89 1192b9def8cSDerek Fang #define RT1308_EFUSE_READ_R0 0x8a 1202b9def8cSDerek Fang #define RT1308_EFUSE_READ_ADC_L 0x8b 1212b9def8cSDerek Fang #define RT1308_EFUSE_READ_ADC_R 0x8c 1222b9def8cSDerek Fang #define RT1308_EFUSE_READ_ADC_PBTL 0x8d 1232b9def8cSDerek Fang #define RT1308_EFUSE_RESERVE 0x8e 1242b9def8cSDerek Fang #define RT1308_PADS_1 0x90 1252b9def8cSDerek Fang #define RT1308_PADS_2 0x91 1262b9def8cSDerek Fang #define RT1308_TEST_MODE 0xa0 1272b9def8cSDerek Fang #define RT1308_TEST_1 0xa1 1282b9def8cSDerek Fang #define RT1308_TEST_2 0xa2 1292b9def8cSDerek Fang #define RT1308_TEST_3 0xa3 1302b9def8cSDerek Fang #define RT1308_TEST_4 0xa4 1312b9def8cSDerek Fang #define RT1308_EFUSE_DATA_0_MSB 0xb0 1322b9def8cSDerek Fang #define RT1308_EFUSE_DATA_0_LSB 0xb1 1332b9def8cSDerek Fang #define RT1308_EFUSE_DATA_1_MSB 0xb2 1342b9def8cSDerek Fang #define RT1308_EFUSE_DATA_1_LSB 0xb3 1352b9def8cSDerek Fang #define RT1308_EFUSE_DATA_2_MSB 0xb4 1362b9def8cSDerek Fang #define RT1308_EFUSE_DATA_2_LSB 0xb5 1372b9def8cSDerek Fang #define RT1308_EFUSE_DATA_3_MSB 0xb6 1382b9def8cSDerek Fang #define RT1308_EFUSE_DATA_3_LSB 0xb7 1392b9def8cSDerek Fang #define RT1308_EFUSE_DATA_TEST_MSB 0xb8 1402b9def8cSDerek Fang #define RT1308_EFUSE_DATA_TEST_LSB 0xb9 1412b9def8cSDerek Fang #define RT1308_EFUSE_STATUS_1 0xba 1422b9def8cSDerek Fang #define RT1308_EFUSE_STATUS_2 0xbb 1432b9def8cSDerek Fang #define RT1308_TCON_1 0xc0 1442b9def8cSDerek Fang #define RT1308_TCON_2 0xc1 1452b9def8cSDerek Fang #define RT1308_DUMMY_REG 0xf0 1462b9def8cSDerek Fang #define RT1308_MAX_REG 0xff 1472b9def8cSDerek Fang 1482b9def8cSDerek Fang /* PLL1 M/N/K Code-1 (0x03) */ 1492b9def8cSDerek Fang #define RT1308_PLL1_K_SFT 24 1502b9def8cSDerek Fang #define RT1308_PLL1_K_MASK (0x1f << 24) 1512b9def8cSDerek Fang #define RT1308_PLL1_M_BYPASS_MASK (0x1 << 23) 1522b9def8cSDerek Fang #define RT1308_PLL1_M_BYPASS_SFT 23 1532b9def8cSDerek Fang #define RT1308_PLL1_M_BYPASS (0x1 << 23) 1542b9def8cSDerek Fang #define RT1308_PLL1_M_MASK (0x3f << 16) 1552b9def8cSDerek Fang #define RT1308_PLL1_M_SFT 16 1562b9def8cSDerek Fang #define RT1308_PLL1_N_MASK (0x7f << 8) 1572b9def8cSDerek Fang #define RT1308_PLL1_N_SFT 8 1582b9def8cSDerek Fang 1592b9def8cSDerek Fang /* CLOCK-1 (0x06) */ 1602b9def8cSDerek Fang #define RT1308_DIV_FS_SYS_MASK (0xf << 28) 1612b9def8cSDerek Fang #define RT1308_DIV_FS_SYS_SFT 28 1622b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_MASK (0x7 << 24) 1632b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SFT 24 1642b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_MCLK (0x0 << 24) 1652b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_BCLK (0x1 << 24) 1662b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_PLL (0x2 << 24) 1672b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_RCCLK (0x4 << 24) 1682b9def8cSDerek Fang 1692b9def8cSDerek Fang /* CLOCK-2 (0x08) */ 1702b9def8cSDerek Fang #define RT1308_DIV_PRE_PLL_MASK (0xf << 28) 1712b9def8cSDerek Fang #define RT1308_DIV_PRE_PLL_SFT 28 1722b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_MASK (0x7 << 24) 1732b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_SFT 24 1742b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_MCLK (0x0 << 24) 1752b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_BCLK (0x1 << 24) 1762b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_RCCLK (0x4 << 24) 1772b9def8cSDerek Fang 1782b9def8cSDerek Fang /* Clock Detect (0x0a) */ 1792b9def8cSDerek Fang #define RT1308_MCLK_DET_EN_MASK (0x1 << 25) 1802b9def8cSDerek Fang #define RT1308_MCLK_DET_EN_SFT 25 1812b9def8cSDerek Fang #define RT1308_MCLK_DET_EN (0x1 << 25) 1822b9def8cSDerek Fang #define RT1308_BCLK_DET_EN_MASK (0x1 << 24) 1832b9def8cSDerek Fang #define RT1308_BCLK_DET_EN_SFT 24 1842b9def8cSDerek Fang #define RT1308_BCLK_DET_EN (0x1 << 24) 1852b9def8cSDerek Fang 1862b9def8cSDerek Fang /* DAC Setting (0x10) */ 1872b9def8cSDerek Fang #define RT1308_DVOL_MUTE_R_EN_SFT 7 1882b9def8cSDerek Fang #define RT1308_DVOL_MUTE_L_EN_SFT 6 1892b9def8cSDerek Fang 1902b9def8cSDerek Fang /* I2S Setting-1 (0x15) */ 1912b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_MASK (0x3 << 12) 1922b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_SFT 12 1932b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_I2S (0x0 << 12) 1942b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_LEFT (0x1 << 12) 1952b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_PCM_A (0x2 << 12) 1962b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_PCM_B (0x3 << 12) 1972b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_MASK (0x7 << 4) 1982b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_SFT 4 1992b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_16B (0x0 << 4) 2002b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_20B (0x1 << 4) 2012b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_24B (0x2 << 4) 2022b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_32B (0x3 << 4) 2032b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_8B (0x4 << 4) 2042b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_MASK (0x7 << 0) 2052b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_SFT 0 2062b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_16B (0x0 << 0) 2072b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_20B (0x1 << 0) 2082b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_24B (0x2 << 0) 2092b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_32B (0x3 << 0) 2102b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_8B (0x4 << 0) 2112b9def8cSDerek Fang 2122b9def8cSDerek Fang /* I2S Setting-2 (0x16) */ 2132b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_MASK (0x7 << 24) 2142b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_SFT 24 2152b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_16B (0x0 << 24) 2162b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_20B (0x1 << 24) 2172b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_24B (0x2 << 24) 2182b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_32B (0x3 << 24) 2192b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_8B (0x4 << 24) 2202b9def8cSDerek Fang #define RT1308_I2S_BCLK_MASK (0x1 << 14) 2212b9def8cSDerek Fang #define RT1308_I2S_BCLK_SFT 14 2222b9def8cSDerek Fang #define RT1308_I2S_BCLK_NORMAL (0x0 << 14) 2232b9def8cSDerek Fang #define RT1308_I2S_BCLK_INV (0x1 << 14) 2242b9def8cSDerek Fang 2252b9def8cSDerek Fang /* Power Control-1 (0x32) */ 2262b9def8cSDerek Fang #define RT1308_POW_MBIAS20U (0x1 << 31) 2272b9def8cSDerek Fang #define RT1308_POW_MBIAS20U_BIT 31 2282b9def8cSDerek Fang #define RT1308_POW_ALDO (0x1 << 30) 2292b9def8cSDerek Fang #define RT1308_POW_ALDO_BIT 30 2302b9def8cSDerek Fang #define RT1308_POW_DBG (0x1 << 29) 2312b9def8cSDerek Fang #define RT1308_POW_DBG_BIT 29 2322b9def8cSDerek Fang #define RT1308_POW_DACL (0x1 << 28) 2332b9def8cSDerek Fang #define RT1308_POW_DACL_BIT 28 2342b9def8cSDerek Fang #define RT1308_POW_DAC1 (0x1 << 27) 2352b9def8cSDerek Fang #define RT1308_POW_DAC1_BIT 27 2362b9def8cSDerek Fang #define RT1308_POW_CLK25M (0x1 << 26) 2372b9def8cSDerek Fang #define RT1308_POW_CLK25M_BIT 26 2382b9def8cSDerek Fang #define RT1308_POW_ADC_R (0x1 << 25) 2392b9def8cSDerek Fang #define RT1308_POW_ADC_R_BIT 25 2402b9def8cSDerek Fang #define RT1308_POW_ADC_L (0x1 << 24) 2412b9def8cSDerek Fang #define RT1308_POW_ADC_L_BIT 24 2422b9def8cSDerek Fang #define RT1308_POW_DLDO (0x1 << 21) 2432b9def8cSDerek Fang #define RT1308_POW_DLDO_BIT 21 2442b9def8cSDerek Fang #define RT1308_POW_VREF (0x1 << 20) 2452b9def8cSDerek Fang #define RT1308_POW_VREF_BIT 20 2462b9def8cSDerek Fang #define RT1308_POW_MIXER_R (0x1 << 18) 2472b9def8cSDerek Fang #define RT1308_POW_MIXER_R_BIT 18 2482b9def8cSDerek Fang #define RT1308_POW_MIXER_L (0x1 << 17) 2492b9def8cSDerek Fang #define RT1308_POW_MIXER_L_BIT 17 2502b9def8cSDerek Fang #define RT1308_POW_MBIAS4U (0x1 << 16) 2512b9def8cSDerek Fang #define RT1308_POW_MBIAS4U_BIT 16 2522b9def8cSDerek Fang #define RT1308_POW_PLL2_LDO_EN (0x1 << 12) 2532b9def8cSDerek Fang #define RT1308_POW_PLL2_LDO_EN_BIT 12 2542b9def8cSDerek Fang #define RT1308_POW_PLL2B_EN (0x1 << 11) 2552b9def8cSDerek Fang #define RT1308_POW_PLL2B_EN_BIT 11 2562b9def8cSDerek Fang #define RT1308_POW_PLL2F_EN (0x1 << 10) 2572b9def8cSDerek Fang #define RT1308_POW_PLL2F_EN_BIT 10 2582b9def8cSDerek Fang #define RT1308_POW_PLL2F2_EN (0x1 << 9) 2592b9def8cSDerek Fang #define RT1308_POW_PLL2F2_EN_BIT 9 2602b9def8cSDerek Fang #define RT1308_POW_PLL2B2_EN (0x1 << 8) 2612b9def8cSDerek Fang #define RT1308_POW_PLL2B2_EN_BIT 8 2622b9def8cSDerek Fang 2632b9def8cSDerek Fang /* Power Control-2 (0x36) */ 2642b9def8cSDerek Fang #define RT1308_POW_PDB_SRC_BIT (0x1 << 27) 2652b9def8cSDerek Fang #define RT1308_POW_PDB_MN_BIT (0x1 << 25) 2662b9def8cSDerek Fang #define RT1308_POW_PDB_REG_BIT (0x1 << 24) 2672b9def8cSDerek Fang 2682b9def8cSDerek Fang 2692b9def8cSDerek Fang /* System Clock Source */ 2702b9def8cSDerek Fang enum { 2712b9def8cSDerek Fang RT1308_FS_SYS_S_MCLK, 2722b9def8cSDerek Fang RT1308_FS_SYS_S_BCLK, 2732b9def8cSDerek Fang RT1308_FS_SYS_S_PLL, 2742b9def8cSDerek Fang RT1308_FS_SYS_S_RCCLK, /* 25.0 MHz */ 2752b9def8cSDerek Fang }; 2762b9def8cSDerek Fang 2772b9def8cSDerek Fang /* PLL Source */ 2782b9def8cSDerek Fang enum { 2792b9def8cSDerek Fang RT1308_PLL_S_MCLK, 2802b9def8cSDerek Fang RT1308_PLL_S_BCLK, 2812b9def8cSDerek Fang RT1308_PLL_S_RCCLK, 2822b9def8cSDerek Fang }; 2832b9def8cSDerek Fang 2842b9def8cSDerek Fang enum { 2852b9def8cSDerek Fang RT1308_AIF1, 2862b9def8cSDerek Fang RT1308_AIFS 2872b9def8cSDerek Fang }; 2882b9def8cSDerek Fang 2892b9def8cSDerek Fang #endif /* end of _RT1308_H_ */ 290