1*2b9def8cSDerek Fang /* 2*2b9def8cSDerek Fang * RT1308.h -- RT1308 ALSA SoC amplifier component driver 3*2b9def8cSDerek Fang * 4*2b9def8cSDerek Fang * Copyright 2019 Realtek Semiconductor Corp. 5*2b9def8cSDerek Fang * Author: Derek Fang <derek.fang@realtek.com> 6*2b9def8cSDerek Fang * 7*2b9def8cSDerek Fang * This program is free software; you can redistribute it and/or modify 8*2b9def8cSDerek Fang * it under the terms of the GNU General Public License version 2 as 9*2b9def8cSDerek Fang * published by the Free Software Foundation. 10*2b9def8cSDerek Fang */ 11*2b9def8cSDerek Fang 12*2b9def8cSDerek Fang #ifndef _RT1308_H_ 13*2b9def8cSDerek Fang #define _RT1308_H_ 14*2b9def8cSDerek Fang 15*2b9def8cSDerek Fang #define RT1308_DEVICE_ID_NUM 0x10ec1300 16*2b9def8cSDerek Fang 17*2b9def8cSDerek Fang #define RT1308_RESET 0x00 18*2b9def8cSDerek Fang #define RT1308_RESET_N 0x01 19*2b9def8cSDerek Fang #define RT1308_CLK_GATING 0x02 20*2b9def8cSDerek Fang #define RT1308_PLL_1 0x03 21*2b9def8cSDerek Fang #define RT1308_PLL_2 0x04 22*2b9def8cSDerek Fang #define RT1308_PLL_INT 0x05 23*2b9def8cSDerek Fang #define RT1308_CLK_1 0x06 24*2b9def8cSDerek Fang #define RT1308_DATA_PATH 0x07 25*2b9def8cSDerek Fang #define RT1308_CLK_2 0x08 26*2b9def8cSDerek Fang #define RT1308_SIL_DET 0x09 27*2b9def8cSDerek Fang #define RT1308_CLK_DET 0x0a 28*2b9def8cSDerek Fang #define RT1308_DC_DET 0x0b 29*2b9def8cSDerek Fang #define RT1308_DC_DET_THRES 0x0c 30*2b9def8cSDerek Fang #define RT1308_DAC_SET 0x10 31*2b9def8cSDerek Fang #define RT1308_SRC_SET 0x11 32*2b9def8cSDerek Fang #define RT1308_DAC_BUF 0x12 33*2b9def8cSDerek Fang #define RT1308_ADC_SET 0x13 34*2b9def8cSDerek Fang #define RT1308_ADC_SET_INT 0x14 35*2b9def8cSDerek Fang #define RT1308_I2S_SET_1 0x15 36*2b9def8cSDerek Fang #define RT1308_I2S_SET_2 0x16 37*2b9def8cSDerek Fang #define RT1308_I2C_I2S_SDW_SET 0x17 38*2b9def8cSDerek Fang #define RT1308_SDW_REG_RW 0x18 39*2b9def8cSDerek Fang #define RT1308_SDW_REG_RDATA 0x19 40*2b9def8cSDerek Fang #define RT1308_IV_SENSE 0x1a 41*2b9def8cSDerek Fang #define RT1308_I2S_TX_DAC_SET 0x1b 42*2b9def8cSDerek Fang #define RT1308_AD_FILTER_SET 0x1c 43*2b9def8cSDerek Fang #define RT1308_DC_CAL_1 0x20 44*2b9def8cSDerek Fang #define RT1308_DC_CAL_2 0x21 45*2b9def8cSDerek Fang #define RT1308_DC_CAL_L_OFFSET 0x22 46*2b9def8cSDerek Fang #define RT1308_DC_CAL_R_OFFSET 0x23 47*2b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_CTL 0x24 48*2b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_L 0x25 49*2b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_R 0x26 50*2b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_PBTL 0x27 51*2b9def8cSDerek Fang #define RT1308_PVDD_OFFSET_PVDD 0x28 52*2b9def8cSDerek Fang #define RT1308_CAL_OFFSET_DAC_PBTL 0x29 53*2b9def8cSDerek Fang #define RT1308_CAL_OFFSET_DAC_L 0x2a 54*2b9def8cSDerek Fang #define RT1308_CAL_OFFSET_DAC_R 0x2b 55*2b9def8cSDerek Fang #define RT1308_CAL_OFFSET_PWM_L 0x2c 56*2b9def8cSDerek Fang #define RT1308_CAL_OFFSET_PWM_R 0x2d 57*2b9def8cSDerek Fang #define RT1308_CAL_PWM_VOS_ADC_L 0x2e 58*2b9def8cSDerek Fang #define RT1308_CAL_PWM_VOS_ADC_R 0x2f 59*2b9def8cSDerek Fang #define RT1308_CLASS_D_SET_1 0x30 60*2b9def8cSDerek Fang #define RT1308_CLASS_D_SET_2 0x31 61*2b9def8cSDerek Fang #define RT1308_POWER 0x32 62*2b9def8cSDerek Fang #define RT1308_LDO 0x33 63*2b9def8cSDerek Fang #define RT1308_VREF 0x34 64*2b9def8cSDerek Fang #define RT1308_MBIAS 0x35 65*2b9def8cSDerek Fang #define RT1308_POWER_STATUS 0x36 66*2b9def8cSDerek Fang #define RT1308_POWER_INT 0x37 67*2b9def8cSDerek Fang #define RT1308_SINE_TONE_GEN_1 0x50 68*2b9def8cSDerek Fang #define RT1308_SINE_TONE_GEN_2 0x51 69*2b9def8cSDerek Fang #define RT1308_BQ_SET 0x54 70*2b9def8cSDerek Fang #define RT1308_BQ_PARA_UPDATE 0x55 71*2b9def8cSDerek Fang #define RT1308_BQ_PRE_VOL_L 0x56 72*2b9def8cSDerek Fang #define RT1308_BQ_PRE_VOL_R 0x57 73*2b9def8cSDerek Fang #define RT1308_BQ_POST_VOL_L 0x58 74*2b9def8cSDerek Fang #define RT1308_BQ_POST_VOL_R 0x59 75*2b9def8cSDerek Fang #define RT1308_BQ1_L_H0 0x5b 76*2b9def8cSDerek Fang #define RT1308_BQ1_L_B1 0x5c 77*2b9def8cSDerek Fang #define RT1308_BQ1_L_B2 0x5d 78*2b9def8cSDerek Fang #define RT1308_BQ1_L_A1 0x5e 79*2b9def8cSDerek Fang #define RT1308_BQ1_L_A2 0x5f 80*2b9def8cSDerek Fang #define RT1308_BQ1_R_H0 0x60 81*2b9def8cSDerek Fang #define RT1308_BQ1_R_B1 0x61 82*2b9def8cSDerek Fang #define RT1308_BQ1_R_B2 0x62 83*2b9def8cSDerek Fang #define RT1308_BQ1_R_A1 0x63 84*2b9def8cSDerek Fang #define RT1308_BQ1_R_A2 0x64 85*2b9def8cSDerek Fang #define RT1308_BQ2_L_H0 0x65 86*2b9def8cSDerek Fang #define RT1308_BQ2_L_B1 0x66 87*2b9def8cSDerek Fang #define RT1308_BQ2_L_B2 0x67 88*2b9def8cSDerek Fang #define RT1308_BQ2_L_A1 0x68 89*2b9def8cSDerek Fang #define RT1308_BQ2_L_A2 0x69 90*2b9def8cSDerek Fang #define RT1308_BQ2_R_H0 0x6a 91*2b9def8cSDerek Fang #define RT1308_BQ2_R_B1 0x6b 92*2b9def8cSDerek Fang #define RT1308_BQ2_R_B2 0x6c 93*2b9def8cSDerek Fang #define RT1308_BQ2_R_A1 0x6d 94*2b9def8cSDerek Fang #define RT1308_BQ2_R_A2 0x6e 95*2b9def8cSDerek Fang #define RT1308_VEN_DEV_ID 0x70 96*2b9def8cSDerek Fang #define RT1308_VERSION_ID 0x71 97*2b9def8cSDerek Fang #define RT1308_SPK_BOUND 0x72 98*2b9def8cSDerek Fang #define RT1308_BQ1_EQ_L_1 0x73 99*2b9def8cSDerek Fang #define RT1308_BQ1_EQ_L_2 0x74 100*2b9def8cSDerek Fang #define RT1308_BQ1_EQ_L_3 0x75 101*2b9def8cSDerek Fang #define RT1308_BQ1_EQ_R_1 0x76 102*2b9def8cSDerek Fang #define RT1308_BQ1_EQ_R_2 0x77 103*2b9def8cSDerek Fang #define RT1308_BQ1_EQ_R_3 0x78 104*2b9def8cSDerek Fang #define RT1308_BQ2_EQ_L_1 0x79 105*2b9def8cSDerek Fang #define RT1308_BQ2_EQ_L_2 0x7a 106*2b9def8cSDerek Fang #define RT1308_BQ2_EQ_L_3 0x7b 107*2b9def8cSDerek Fang #define RT1308_BQ2_EQ_R_1 0x7c 108*2b9def8cSDerek Fang #define RT1308_BQ2_EQ_R_2 0x7d 109*2b9def8cSDerek Fang #define RT1308_BQ2_EQ_R_3 0x7e 110*2b9def8cSDerek Fang #define RT1308_EFUSE_1 0x7f 111*2b9def8cSDerek Fang #define RT1308_EFUSE_2 0x80 112*2b9def8cSDerek Fang #define RT1308_EFUSE_PROG_PVDD_L 0x81 113*2b9def8cSDerek Fang #define RT1308_EFUSE_PROG_PVDD_R 0x82 114*2b9def8cSDerek Fang #define RT1308_EFUSE_PROG_R0_L 0x83 115*2b9def8cSDerek Fang #define RT1308_EFUSE_PROG_R0_R 0x84 116*2b9def8cSDerek Fang #define RT1308_EFUSE_PROG_DEV 0x85 117*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_PVDD_L 0x86 118*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_PVDD_R 0x87 119*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_PVDD_PTBL 0x88 120*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_DEV 0x89 121*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_R0 0x8a 122*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_ADC_L 0x8b 123*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_ADC_R 0x8c 124*2b9def8cSDerek Fang #define RT1308_EFUSE_READ_ADC_PBTL 0x8d 125*2b9def8cSDerek Fang #define RT1308_EFUSE_RESERVE 0x8e 126*2b9def8cSDerek Fang #define RT1308_PADS_1 0x90 127*2b9def8cSDerek Fang #define RT1308_PADS_2 0x91 128*2b9def8cSDerek Fang #define RT1308_TEST_MODE 0xa0 129*2b9def8cSDerek Fang #define RT1308_TEST_1 0xa1 130*2b9def8cSDerek Fang #define RT1308_TEST_2 0xa2 131*2b9def8cSDerek Fang #define RT1308_TEST_3 0xa3 132*2b9def8cSDerek Fang #define RT1308_TEST_4 0xa4 133*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_0_MSB 0xb0 134*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_0_LSB 0xb1 135*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_1_MSB 0xb2 136*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_1_LSB 0xb3 137*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_2_MSB 0xb4 138*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_2_LSB 0xb5 139*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_3_MSB 0xb6 140*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_3_LSB 0xb7 141*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_TEST_MSB 0xb8 142*2b9def8cSDerek Fang #define RT1308_EFUSE_DATA_TEST_LSB 0xb9 143*2b9def8cSDerek Fang #define RT1308_EFUSE_STATUS_1 0xba 144*2b9def8cSDerek Fang #define RT1308_EFUSE_STATUS_2 0xbb 145*2b9def8cSDerek Fang #define RT1308_TCON_1 0xc0 146*2b9def8cSDerek Fang #define RT1308_TCON_2 0xc1 147*2b9def8cSDerek Fang #define RT1308_DUMMY_REG 0xf0 148*2b9def8cSDerek Fang #define RT1308_MAX_REG 0xff 149*2b9def8cSDerek Fang 150*2b9def8cSDerek Fang /* PLL1 M/N/K Code-1 (0x03) */ 151*2b9def8cSDerek Fang #define RT1308_PLL1_K_SFT 24 152*2b9def8cSDerek Fang #define RT1308_PLL1_K_MASK (0x1f << 24) 153*2b9def8cSDerek Fang #define RT1308_PLL1_M_BYPASS_MASK (0x1 << 23) 154*2b9def8cSDerek Fang #define RT1308_PLL1_M_BYPASS_SFT 23 155*2b9def8cSDerek Fang #define RT1308_PLL1_M_BYPASS (0x1 << 23) 156*2b9def8cSDerek Fang #define RT1308_PLL1_M_MASK (0x3f << 16) 157*2b9def8cSDerek Fang #define RT1308_PLL1_M_SFT 16 158*2b9def8cSDerek Fang #define RT1308_PLL1_N_MASK (0x7f << 8) 159*2b9def8cSDerek Fang #define RT1308_PLL1_N_SFT 8 160*2b9def8cSDerek Fang 161*2b9def8cSDerek Fang /* CLOCK-1 (0x06) */ 162*2b9def8cSDerek Fang #define RT1308_DIV_FS_SYS_MASK (0xf << 28) 163*2b9def8cSDerek Fang #define RT1308_DIV_FS_SYS_SFT 28 164*2b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_MASK (0x7 << 24) 165*2b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SFT 24 166*2b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_MCLK (0x0 << 24) 167*2b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_BCLK (0x1 << 24) 168*2b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_PLL (0x2 << 24) 169*2b9def8cSDerek Fang #define RT1308_SEL_FS_SYS_SRC_RCCLK (0x4 << 24) 170*2b9def8cSDerek Fang 171*2b9def8cSDerek Fang /* CLOCK-2 (0x08) */ 172*2b9def8cSDerek Fang #define RT1308_DIV_PRE_PLL_MASK (0xf << 28) 173*2b9def8cSDerek Fang #define RT1308_DIV_PRE_PLL_SFT 28 174*2b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_MASK (0x7 << 24) 175*2b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_SFT 24 176*2b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_MCLK (0x0 << 24) 177*2b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_BCLK (0x1 << 24) 178*2b9def8cSDerek Fang #define RT1308_SEL_PLL_SRC_RCCLK (0x4 << 24) 179*2b9def8cSDerek Fang 180*2b9def8cSDerek Fang /* Clock Detect (0x0a) */ 181*2b9def8cSDerek Fang #define RT1308_MCLK_DET_EN_MASK (0x1 << 25) 182*2b9def8cSDerek Fang #define RT1308_MCLK_DET_EN_SFT 25 183*2b9def8cSDerek Fang #define RT1308_MCLK_DET_EN (0x1 << 25) 184*2b9def8cSDerek Fang #define RT1308_BCLK_DET_EN_MASK (0x1 << 24) 185*2b9def8cSDerek Fang #define RT1308_BCLK_DET_EN_SFT 24 186*2b9def8cSDerek Fang #define RT1308_BCLK_DET_EN (0x1 << 24) 187*2b9def8cSDerek Fang 188*2b9def8cSDerek Fang /* DAC Setting (0x10) */ 189*2b9def8cSDerek Fang #define RT1308_DVOL_MUTE_R_EN_SFT 7 190*2b9def8cSDerek Fang #define RT1308_DVOL_MUTE_L_EN_SFT 6 191*2b9def8cSDerek Fang 192*2b9def8cSDerek Fang /* I2S Setting-1 (0x15) */ 193*2b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_MASK (0x3 << 12) 194*2b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_SFT 12 195*2b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_I2S (0x0 << 12) 196*2b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_LEFT (0x1 << 12) 197*2b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_PCM_A (0x2 << 12) 198*2b9def8cSDerek Fang #define RT1308_I2S_DF_SEL_PCM_B (0x3 << 12) 199*2b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_MASK (0x7 << 4) 200*2b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_SFT 4 201*2b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_16B (0x0 << 4) 202*2b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_20B (0x1 << 4) 203*2b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_24B (0x2 << 4) 204*2b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_32B (0x3 << 4) 205*2b9def8cSDerek Fang #define RT1308_I2S_DL_RX_SEL_8B (0x4 << 4) 206*2b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_MASK (0x7 << 0) 207*2b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_SFT 0 208*2b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_16B (0x0 << 0) 209*2b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_20B (0x1 << 0) 210*2b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_24B (0x2 << 0) 211*2b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_32B (0x3 << 0) 212*2b9def8cSDerek Fang #define RT1308_I2S_DL_TX_SEL_8B (0x4 << 0) 213*2b9def8cSDerek Fang 214*2b9def8cSDerek Fang /* I2S Setting-2 (0x16) */ 215*2b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_MASK (0x7 << 24) 216*2b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_SFT 24 217*2b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_16B (0x0 << 24) 218*2b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_20B (0x1 << 24) 219*2b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_24B (0x2 << 24) 220*2b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_32B (0x3 << 24) 221*2b9def8cSDerek Fang #define RT1308_I2S_DL_SEL_8B (0x4 << 24) 222*2b9def8cSDerek Fang #define RT1308_I2S_BCLK_MASK (0x1 << 14) 223*2b9def8cSDerek Fang #define RT1308_I2S_BCLK_SFT 14 224*2b9def8cSDerek Fang #define RT1308_I2S_BCLK_NORMAL (0x0 << 14) 225*2b9def8cSDerek Fang #define RT1308_I2S_BCLK_INV (0x1 << 14) 226*2b9def8cSDerek Fang 227*2b9def8cSDerek Fang /* Power Control-1 (0x32) */ 228*2b9def8cSDerek Fang #define RT1308_POW_MBIAS20U (0x1 << 31) 229*2b9def8cSDerek Fang #define RT1308_POW_MBIAS20U_BIT 31 230*2b9def8cSDerek Fang #define RT1308_POW_ALDO (0x1 << 30) 231*2b9def8cSDerek Fang #define RT1308_POW_ALDO_BIT 30 232*2b9def8cSDerek Fang #define RT1308_POW_DBG (0x1 << 29) 233*2b9def8cSDerek Fang #define RT1308_POW_DBG_BIT 29 234*2b9def8cSDerek Fang #define RT1308_POW_DACL (0x1 << 28) 235*2b9def8cSDerek Fang #define RT1308_POW_DACL_BIT 28 236*2b9def8cSDerek Fang #define RT1308_POW_DAC1 (0x1 << 27) 237*2b9def8cSDerek Fang #define RT1308_POW_DAC1_BIT 27 238*2b9def8cSDerek Fang #define RT1308_POW_CLK25M (0x1 << 26) 239*2b9def8cSDerek Fang #define RT1308_POW_CLK25M_BIT 26 240*2b9def8cSDerek Fang #define RT1308_POW_ADC_R (0x1 << 25) 241*2b9def8cSDerek Fang #define RT1308_POW_ADC_R_BIT 25 242*2b9def8cSDerek Fang #define RT1308_POW_ADC_L (0x1 << 24) 243*2b9def8cSDerek Fang #define RT1308_POW_ADC_L_BIT 24 244*2b9def8cSDerek Fang #define RT1308_POW_DLDO (0x1 << 21) 245*2b9def8cSDerek Fang #define RT1308_POW_DLDO_BIT 21 246*2b9def8cSDerek Fang #define RT1308_POW_VREF (0x1 << 20) 247*2b9def8cSDerek Fang #define RT1308_POW_VREF_BIT 20 248*2b9def8cSDerek Fang #define RT1308_POW_MIXER_R (0x1 << 18) 249*2b9def8cSDerek Fang #define RT1308_POW_MIXER_R_BIT 18 250*2b9def8cSDerek Fang #define RT1308_POW_MIXER_L (0x1 << 17) 251*2b9def8cSDerek Fang #define RT1308_POW_MIXER_L_BIT 17 252*2b9def8cSDerek Fang #define RT1308_POW_MBIAS4U (0x1 << 16) 253*2b9def8cSDerek Fang #define RT1308_POW_MBIAS4U_BIT 16 254*2b9def8cSDerek Fang #define RT1308_POW_PLL2_LDO_EN (0x1 << 12) 255*2b9def8cSDerek Fang #define RT1308_POW_PLL2_LDO_EN_BIT 12 256*2b9def8cSDerek Fang #define RT1308_POW_PLL2B_EN (0x1 << 11) 257*2b9def8cSDerek Fang #define RT1308_POW_PLL2B_EN_BIT 11 258*2b9def8cSDerek Fang #define RT1308_POW_PLL2F_EN (0x1 << 10) 259*2b9def8cSDerek Fang #define RT1308_POW_PLL2F_EN_BIT 10 260*2b9def8cSDerek Fang #define RT1308_POW_PLL2F2_EN (0x1 << 9) 261*2b9def8cSDerek Fang #define RT1308_POW_PLL2F2_EN_BIT 9 262*2b9def8cSDerek Fang #define RT1308_POW_PLL2B2_EN (0x1 << 8) 263*2b9def8cSDerek Fang #define RT1308_POW_PLL2B2_EN_BIT 8 264*2b9def8cSDerek Fang 265*2b9def8cSDerek Fang /* Power Control-2 (0x36) */ 266*2b9def8cSDerek Fang #define RT1308_POW_PDB_SRC_BIT (0x1 << 27) 267*2b9def8cSDerek Fang #define RT1308_POW_PDB_MN_BIT (0x1 << 25) 268*2b9def8cSDerek Fang #define RT1308_POW_PDB_REG_BIT (0x1 << 24) 269*2b9def8cSDerek Fang 270*2b9def8cSDerek Fang 271*2b9def8cSDerek Fang /* System Clock Source */ 272*2b9def8cSDerek Fang enum { 273*2b9def8cSDerek Fang RT1308_FS_SYS_S_MCLK, 274*2b9def8cSDerek Fang RT1308_FS_SYS_S_BCLK, 275*2b9def8cSDerek Fang RT1308_FS_SYS_S_PLL, 276*2b9def8cSDerek Fang RT1308_FS_SYS_S_RCCLK, /* 25.0 MHz */ 277*2b9def8cSDerek Fang }; 278*2b9def8cSDerek Fang 279*2b9def8cSDerek Fang /* PLL Source */ 280*2b9def8cSDerek Fang enum { 281*2b9def8cSDerek Fang RT1308_PLL_S_MCLK, 282*2b9def8cSDerek Fang RT1308_PLL_S_BCLK, 283*2b9def8cSDerek Fang RT1308_PLL_S_RCCLK, 284*2b9def8cSDerek Fang }; 285*2b9def8cSDerek Fang 286*2b9def8cSDerek Fang enum { 287*2b9def8cSDerek Fang RT1308_AIF1, 288*2b9def8cSDerek Fang RT1308_AIFS 289*2b9def8cSDerek Fang }; 290*2b9def8cSDerek Fang 291*2b9def8cSDerek Fang #endif /* end of _RT1308_H_ */ 292