1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver 4 // 5 // Copyright(c) 2019 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <linux/soundwire/sdw_registers.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/initval.h> 23 24 #include "rt1308.h" 25 #include "rt1308-sdw.h" 26 27 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 28 { 29 switch (reg) { 30 case 0x00e0: 31 case 0x00f0: 32 case 0x2f01 ... 0x2f07: 33 case 0x3000 ... 0x3001: 34 case 0x3004 ... 0x3005: 35 case 0x3008: 36 case 0x300a: 37 case 0xc000 ... 0xcff3: 38 return true; 39 default: 40 return false; 41 } 42 } 43 44 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 45 { 46 switch (reg) { 47 case 0x2f01 ... 0x2f07: 48 case 0x3000 ... 0x3001: 49 case 0x3004 ... 0x3005: 50 case 0x3008: 51 case 0x300a: 52 case 0xc000: 53 return true; 54 default: 55 return false; 56 } 57 } 58 59 static const struct regmap_config rt1308_sdw_regmap = { 60 .reg_bits = 32, 61 .val_bits = 8, 62 .readable_reg = rt1308_readable_register, 63 .volatile_reg = rt1308_volatile_register, 64 .max_register = 0xcfff, 65 .reg_defaults = rt1308_reg_defaults, 66 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults), 67 .cache_type = REGCACHE_RBTREE, 68 .use_single_read = true, 69 .use_single_write = true, 70 }; 71 72 /* Bus clock frequency */ 73 #define RT1308_CLK_FREQ_9600000HZ 9600000 74 #define RT1308_CLK_FREQ_12000000HZ 12000000 75 #define RT1308_CLK_FREQ_6000000HZ 6000000 76 #define RT1308_CLK_FREQ_4800000HZ 4800000 77 #define RT1308_CLK_FREQ_2400000HZ 2400000 78 #define RT1308_CLK_FREQ_12288000HZ 12288000 79 80 static int rt1308_clock_config(struct device *dev) 81 { 82 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 83 unsigned int clk_freq, value; 84 85 clk_freq = (rt1308->params.curr_dr_freq >> 1); 86 87 switch (clk_freq) { 88 case RT1308_CLK_FREQ_12000000HZ: 89 value = 0x0; 90 break; 91 case RT1308_CLK_FREQ_6000000HZ: 92 value = 0x1; 93 break; 94 case RT1308_CLK_FREQ_9600000HZ: 95 value = 0x2; 96 break; 97 case RT1308_CLK_FREQ_4800000HZ: 98 value = 0x3; 99 break; 100 case RT1308_CLK_FREQ_2400000HZ: 101 value = 0x4; 102 break; 103 case RT1308_CLK_FREQ_12288000HZ: 104 value = 0x5; 105 break; 106 default: 107 return -EINVAL; 108 } 109 110 regmap_write(rt1308->regmap, 0xe0, value); 111 regmap_write(rt1308->regmap, 0xf0, value); 112 113 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq); 114 115 return 0; 116 } 117 118 static int rt1308_read_prop(struct sdw_slave *slave) 119 { 120 struct sdw_slave_prop *prop = &slave->prop; 121 int nval, i, num_of_ports = 1; 122 u32 bit; 123 unsigned long addr; 124 struct sdw_dpn_prop *dpn; 125 126 prop->paging_support = true; 127 128 /* first we need to allocate memory for set bits in port lists */ 129 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ 130 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 131 132 /* for sink */ 133 nval = hweight32(prop->sink_ports); 134 num_of_ports += nval; 135 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 136 sizeof(*prop->sink_dpn_prop), 137 GFP_KERNEL); 138 if (!prop->sink_dpn_prop) 139 return -ENOMEM; 140 141 i = 0; 142 dpn = prop->sink_dpn_prop; 143 addr = prop->sink_ports; 144 for_each_set_bit(bit, &addr, 32) { 145 dpn[i].num = bit; 146 dpn[i].type = SDW_DPN_FULL; 147 dpn[i].simple_ch_prep_sm = true; 148 dpn[i].ch_prep_timeout = 10; 149 i++; 150 } 151 152 /* Allocate port_ready based on num_of_ports */ 153 slave->port_ready = devm_kcalloc(&slave->dev, num_of_ports, 154 sizeof(*slave->port_ready), 155 GFP_KERNEL); 156 if (!slave->port_ready) 157 return -ENOMEM; 158 159 /* Initialize completion */ 160 for (i = 0; i < num_of_ports; i++) 161 init_completion(&slave->port_ready[i]); 162 163 /* set the timeout values */ 164 prop->clk_stop_timeout = 20; 165 166 dev_dbg(&slave->dev, "%s\n", __func__); 167 168 return 0; 169 } 170 171 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave) 172 { 173 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 174 int ret = 0; 175 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp; 176 unsigned int efuse_c_btl_l, efuse_c_btl_r; 177 178 if (rt1308->hw_init) 179 return 0; 180 181 ret = rt1308_read_prop(slave); 182 if (ret < 0) 183 goto _io_init_err_; 184 185 if (rt1308->first_hw_init) { 186 regcache_cache_only(rt1308->regmap, false); 187 regcache_cache_bypass(rt1308->regmap, true); 188 } 189 190 /* 191 * PM runtime is only enabled when a Slave reports as Attached 192 */ 193 if (!rt1308->first_hw_init) { 194 /* set autosuspend parameters */ 195 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 196 pm_runtime_use_autosuspend(&slave->dev); 197 198 /* update count of parent 'active' children */ 199 pm_runtime_set_active(&slave->dev); 200 201 /* make sure the device does not suspend immediately */ 202 pm_runtime_mark_last_busy(&slave->dev); 203 204 pm_runtime_enable(&slave->dev); 205 } 206 207 pm_runtime_get_noresume(&slave->dev); 208 209 /* sw reset */ 210 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); 211 212 /* read efuse */ 213 regmap_write(rt1308->regmap, 0xc360, 0x01); 214 regmap_write(rt1308->regmap, 0xc361, 0x80); 215 regmap_write(rt1308->regmap, 0xc7f0, 0x04); 216 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); 217 msleep(100); 218 regmap_write(rt1308->regmap, 0xc7f0, 0x44); 219 msleep(20); 220 regmap_write(rt1308->regmap, 0xc240, 0x10); 221 222 regmap_read(rt1308->regmap, 0xc861, &tmp); 223 efuse_m_btl_l = tmp; 224 regmap_read(rt1308->regmap, 0xc860, &tmp); 225 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8); 226 regmap_read(rt1308->regmap, 0xc863, &tmp); 227 efuse_c_btl_l = tmp; 228 regmap_read(rt1308->regmap, 0xc862, &tmp); 229 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8); 230 regmap_read(rt1308->regmap, 0xc871, &tmp); 231 efuse_m_btl_r = tmp; 232 regmap_read(rt1308->regmap, 0xc870, &tmp); 233 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8); 234 regmap_read(rt1308->regmap, 0xc873, &tmp); 235 efuse_c_btl_r = tmp; 236 regmap_read(rt1308->regmap, 0xc872, &tmp); 237 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8); 238 dev_info(&slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, 239 efuse_m_btl_l, efuse_m_btl_r); 240 dev_info(&slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, 241 efuse_c_btl_l, efuse_c_btl_r); 242 243 /* initial settings */ 244 regmap_write(rt1308->regmap, 0xc103, 0xc0); 245 regmap_write(rt1308->regmap, 0xc030, 0x17); 246 regmap_write(rt1308->regmap, 0xc031, 0x81); 247 regmap_write(rt1308->regmap, 0xc032, 0x26); 248 regmap_write(rt1308->regmap, 0xc040, 0x80); 249 regmap_write(rt1308->regmap, 0xc041, 0x80); 250 regmap_write(rt1308->regmap, 0xc042, 0x06); 251 regmap_write(rt1308->regmap, 0xc052, 0x0a); 252 regmap_write(rt1308->regmap, 0xc080, 0x0a); 253 regmap_write(rt1308->regmap, 0xc060, 0x02); 254 regmap_write(rt1308->regmap, 0xc061, 0x75); 255 regmap_write(rt1308->regmap, 0xc062, 0x05); 256 regmap_write(rt1308->regmap, 0xc171, 0x07); 257 regmap_write(rt1308->regmap, 0xc173, 0x0d); 258 regmap_write(rt1308->regmap, 0xc311, 0x7f); 259 regmap_write(rt1308->regmap, 0xc900, 0x90); 260 regmap_write(rt1308->regmap, 0xc1a0, 0x84); 261 regmap_write(rt1308->regmap, 0xc1a1, 0x01); 262 regmap_write(rt1308->regmap, 0xc360, 0x78); 263 regmap_write(rt1308->regmap, 0xc361, 0x87); 264 regmap_write(rt1308->regmap, 0xc0a1, 0x71); 265 regmap_write(rt1308->regmap, 0xc210, 0x00); 266 regmap_write(rt1308->regmap, 0xc070, 0x00); 267 regmap_write(rt1308->regmap, 0xc100, 0xd7); 268 regmap_write(rt1308->regmap, 0xc101, 0xd7); 269 regmap_write(rt1308->regmap, 0xc300, 0x09); 270 271 if (rt1308->first_hw_init) { 272 regcache_cache_bypass(rt1308->regmap, false); 273 regcache_mark_dirty(rt1308->regmap); 274 } else 275 rt1308->first_hw_init = true; 276 277 /* Mark Slave initialization complete */ 278 rt1308->hw_init = true; 279 280 pm_runtime_mark_last_busy(&slave->dev); 281 pm_runtime_put_autosuspend(&slave->dev); 282 283 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 284 285 _io_init_err_: 286 return ret; 287 } 288 289 static int rt1308_update_status(struct sdw_slave *slave, 290 enum sdw_slave_status status) 291 { 292 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 293 294 /* Update the status */ 295 rt1308->status = status; 296 297 if (status == SDW_SLAVE_UNATTACHED) 298 rt1308->hw_init = false; 299 300 /* 301 * Perform initialization only if slave status is present and 302 * hw_init flag is false 303 */ 304 if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED) 305 return 0; 306 307 /* perform I/O transfers required for Slave initialization */ 308 return rt1308_io_init(&slave->dev, slave); 309 } 310 311 static int rt1308_bus_config(struct sdw_slave *slave, 312 struct sdw_bus_params *params) 313 { 314 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 315 int ret; 316 317 memcpy(&rt1308->params, params, sizeof(*params)); 318 319 ret = rt1308_clock_config(&slave->dev); 320 if (ret < 0) 321 dev_err(&slave->dev, "Invalid clk config"); 322 323 return ret; 324 } 325 326 static int rt1308_interrupt_callback(struct sdw_slave *slave, 327 struct sdw_slave_intr_status *status) 328 { 329 dev_dbg(&slave->dev, 330 "%s control_port_stat=%x", __func__, status->control_port); 331 332 return 0; 333 } 334 335 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 336 struct snd_kcontrol *kcontrol, int event) 337 { 338 struct snd_soc_component *component = 339 snd_soc_dapm_to_component(w->dapm); 340 341 switch (event) { 342 case SND_SOC_DAPM_POST_PMU: 343 msleep(30); 344 snd_soc_component_update_bits(component, 345 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 346 0x3, 0x3); 347 msleep(40); 348 break; 349 case SND_SOC_DAPM_PRE_PMD: 350 snd_soc_component_update_bits(component, 351 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 352 0x3, 0); 353 usleep_range(150000, 200000); 354 break; 355 356 default: 357 break; 358 } 359 360 return 0; 361 } 362 363 static const char * const rt1308_rx_data_ch_select[] = { 364 "LR", 365 "LL", 366 "RL", 367 "RR", 368 }; 369 370 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, 371 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0, 372 rt1308_rx_data_ch_select); 373 374 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 375 376 /* I2S Data Channel Selection */ 377 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 378 }; 379 380 static const struct snd_kcontrol_new rt1308_sto_dac_l = 381 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 382 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 383 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 384 385 static const struct snd_kcontrol_new rt1308_sto_dac_r = 386 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 387 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 388 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 389 390 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 391 /* Audio Interface */ 392 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 393 394 /* Supply Widgets */ 395 SND_SOC_DAPM_SUPPLY("MBIAS20U", 396 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0), 397 SND_SOC_DAPM_SUPPLY("ALDO", 398 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0), 399 SND_SOC_DAPM_SUPPLY("DBG", 400 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0), 401 SND_SOC_DAPM_SUPPLY("DACL", 402 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0), 403 SND_SOC_DAPM_SUPPLY("CLK25M", 404 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0), 405 SND_SOC_DAPM_SUPPLY("ADC_R", 406 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0), 407 SND_SOC_DAPM_SUPPLY("ADC_L", 408 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0), 409 SND_SOC_DAPM_SUPPLY("DAC Power", 410 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0), 411 412 SND_SOC_DAPM_SUPPLY("DLDO", 413 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0), 414 SND_SOC_DAPM_SUPPLY("VREF", 415 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0), 416 SND_SOC_DAPM_SUPPLY("MIXER_R", 417 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0), 418 SND_SOC_DAPM_SUPPLY("MIXER_L", 419 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0), 420 SND_SOC_DAPM_SUPPLY("MBIAS4U", 421 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0), 422 423 SND_SOC_DAPM_SUPPLY("PLL2_LDO", 424 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0), 425 SND_SOC_DAPM_SUPPLY("PLL2B", 426 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0), 427 SND_SOC_DAPM_SUPPLY("PLL2F", 428 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0), 429 SND_SOC_DAPM_SUPPLY("PLL2F2", 430 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0), 431 SND_SOC_DAPM_SUPPLY("PLL2B2", 432 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0), 433 434 /* Digital Interface */ 435 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 436 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 437 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 438 439 /* Output Lines */ 440 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 441 rt1308_classd_event, 442 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 443 SND_SOC_DAPM_OUTPUT("SPOL"), 444 SND_SOC_DAPM_OUTPUT("SPOR"), 445 }; 446 447 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 448 449 { "DAC", NULL, "AIF1RX" }, 450 451 { "DAC", NULL, "MBIAS20U" }, 452 { "DAC", NULL, "ALDO" }, 453 { "DAC", NULL, "DBG" }, 454 { "DAC", NULL, "DACL" }, 455 { "DAC", NULL, "CLK25M" }, 456 { "DAC", NULL, "ADC_R" }, 457 { "DAC", NULL, "ADC_L" }, 458 { "DAC", NULL, "DLDO" }, 459 { "DAC", NULL, "VREF" }, 460 { "DAC", NULL, "MIXER_R" }, 461 { "DAC", NULL, "MIXER_L" }, 462 { "DAC", NULL, "MBIAS4U" }, 463 { "DAC", NULL, "PLL2_LDO" }, 464 { "DAC", NULL, "PLL2B" }, 465 { "DAC", NULL, "PLL2F" }, 466 { "DAC", NULL, "PLL2F2" }, 467 { "DAC", NULL, "PLL2B2" }, 468 469 { "DAC L", "Switch", "DAC" }, 470 { "DAC R", "Switch", "DAC" }, 471 { "DAC L", NULL, "DAC Power" }, 472 { "DAC R", NULL, "DAC Power" }, 473 474 { "CLASS D", NULL, "DAC L" }, 475 { "CLASS D", NULL, "DAC R" }, 476 { "SPOL", NULL, "CLASS D" }, 477 { "SPOR", NULL, "CLASS D" }, 478 }; 479 480 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 481 int direction) 482 { 483 struct sdw_stream_data *stream; 484 485 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 486 if (!stream) 487 return -ENOMEM; 488 489 stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream; 490 491 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 492 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 493 dai->playback_dma_data = stream; 494 else 495 dai->capture_dma_data = stream; 496 497 return 0; 498 } 499 500 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream, 501 struct snd_soc_dai *dai) 502 { 503 struct sdw_stream_data *stream; 504 505 stream = snd_soc_dai_get_dma_data(dai, substream); 506 snd_soc_dai_set_dma_data(dai, substream, NULL); 507 kfree(stream); 508 } 509 510 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream, 511 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 512 { 513 struct snd_soc_component *component = dai->component; 514 struct rt1308_sdw_priv *rt1308 = 515 snd_soc_component_get_drvdata(component); 516 struct sdw_stream_config stream_config; 517 struct sdw_port_config port_config; 518 enum sdw_data_direction direction; 519 struct sdw_stream_data *stream; 520 int retval, port, num_channels; 521 522 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 523 stream = snd_soc_dai_get_dma_data(dai, substream); 524 525 if (!stream) 526 return -EINVAL; 527 528 if (!rt1308->sdw_slave) 529 return -EINVAL; 530 531 /* SoundWire specific configuration */ 532 /* port 1 for playback */ 533 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 534 direction = SDW_DATA_DIR_RX; 535 port = 1; 536 } else { 537 return -EINVAL; 538 } 539 540 stream_config.frame_rate = params_rate(params); 541 stream_config.ch_count = params_channels(params); 542 stream_config.bps = snd_pcm_format_width(params_format(params)); 543 stream_config.direction = direction; 544 545 num_channels = params_channels(params); 546 port_config.ch_mask = (1 << (num_channels)) - 1; 547 port_config.num = port; 548 549 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config, 550 &port_config, 1, stream->sdw_stream); 551 if (retval) { 552 dev_err(dai->dev, "Unable to configure port\n"); 553 return retval; 554 } 555 556 return retval; 557 } 558 559 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 560 struct snd_soc_dai *dai) 561 { 562 struct snd_soc_component *component = dai->component; 563 struct rt1308_sdw_priv *rt1308 = 564 snd_soc_component_get_drvdata(component); 565 struct sdw_stream_data *stream = 566 snd_soc_dai_get_dma_data(dai, substream); 567 568 if (!rt1308->sdw_slave) 569 return -EINVAL; 570 571 sdw_stream_remove_slave(rt1308->sdw_slave, stream->sdw_stream); 572 return 0; 573 } 574 575 /* 576 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 577 * port_prep are not defined for now 578 */ 579 static struct sdw_slave_ops rt1308_slave_ops = { 580 .read_prop = rt1308_read_prop, 581 .interrupt_callback = rt1308_interrupt_callback, 582 .update_status = rt1308_update_status, 583 .bus_config = rt1308_bus_config, 584 }; 585 586 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = { 587 .controls = rt1308_snd_controls, 588 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 589 .dapm_widgets = rt1308_dapm_widgets, 590 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 591 .dapm_routes = rt1308_dapm_routes, 592 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 593 }; 594 595 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 596 .hw_params = rt1308_sdw_hw_params, 597 .hw_free = rt1308_sdw_pcm_hw_free, 598 .set_sdw_stream = rt1308_set_sdw_stream, 599 .shutdown = rt1308_sdw_shutdown, 600 }; 601 602 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 603 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 604 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 605 SNDRV_PCM_FMTBIT_S24_LE) 606 607 static struct snd_soc_dai_driver rt1308_sdw_dai[] = { 608 { 609 .name = "rt1308-aif", 610 .playback = { 611 .stream_name = "DP1 Playback", 612 .channels_min = 1, 613 .channels_max = 2, 614 .rates = RT1308_STEREO_RATES, 615 .formats = RT1308_FORMATS, 616 }, 617 .ops = &rt1308_aif_dai_ops, 618 }, 619 }; 620 621 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap, 622 struct sdw_slave *slave) 623 { 624 struct rt1308_sdw_priv *rt1308; 625 int ret; 626 627 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL); 628 if (!rt1308) 629 return -ENOMEM; 630 631 dev_set_drvdata(dev, rt1308); 632 rt1308->sdw_slave = slave; 633 rt1308->regmap = regmap; 634 635 /* 636 * Mark hw_init to false 637 * HW init will be performed when device reports present 638 */ 639 rt1308->hw_init = false; 640 rt1308->first_hw_init = false; 641 642 ret = devm_snd_soc_register_component(dev, 643 &soc_component_sdw_rt1308, 644 rt1308_sdw_dai, 645 ARRAY_SIZE(rt1308_sdw_dai)); 646 647 dev_dbg(&slave->dev, "%s\n", __func__); 648 649 return ret; 650 } 651 652 static int rt1308_sdw_probe(struct sdw_slave *slave, 653 const struct sdw_device_id *id) 654 { 655 struct regmap *regmap; 656 657 /* Assign ops */ 658 slave->ops = &rt1308_slave_ops; 659 660 /* Regmap Initialization */ 661 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 662 if (!regmap) 663 return -EINVAL; 664 665 rt1308_sdw_init(&slave->dev, regmap, slave); 666 667 return 0; 668 } 669 670 static const struct sdw_device_id rt1308_id[] = { 671 SDW_SLAVE_ENTRY(0x025d, 0x1308, 0), 672 {}, 673 }; 674 MODULE_DEVICE_TABLE(sdw, rt1308_id); 675 676 static int rt1308_dev_suspend(struct device *dev) 677 { 678 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 679 680 if (!rt1308->hw_init) 681 return 0; 682 683 regcache_cache_only(rt1308->regmap, true); 684 685 return 0; 686 } 687 688 #define RT1308_PROBE_TIMEOUT 2000 689 690 static int rt1308_dev_resume(struct device *dev) 691 { 692 struct sdw_slave *slave = dev_to_sdw_dev(dev); 693 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 694 unsigned long time; 695 696 if (!rt1308->hw_init) 697 return 0; 698 699 if (!slave->unattach_request) 700 goto regmap_sync; 701 702 time = wait_for_completion_timeout(&slave->initialization_complete, 703 msecs_to_jiffies(RT1308_PROBE_TIMEOUT)); 704 if (!time) { 705 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 706 return -ETIMEDOUT; 707 } 708 709 regmap_sync: 710 slave->unattach_request = 0; 711 regcache_cache_only(rt1308->regmap, false); 712 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); 713 714 return 0; 715 } 716 717 static const struct dev_pm_ops rt1308_pm = { 718 SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume) 719 SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL) 720 }; 721 722 static struct sdw_driver rt1308_sdw_driver = { 723 .driver = { 724 .name = "rt1308", 725 .owner = THIS_MODULE, 726 .pm = &rt1308_pm, 727 }, 728 .probe = rt1308_sdw_probe, 729 .ops = &rt1308_slave_ops, 730 .id_table = rt1308_id, 731 }; 732 module_sdw_driver(rt1308_sdw_driver); 733 734 MODULE_DESCRIPTION("ASoC RT1308 driver SDW"); 735 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 736 MODULE_LICENSE("GPL v2"); 737