1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver 4 // 5 // Copyright(c) 2019 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/soundwire/sdw.h> 12 #include <linux/soundwire/sdw_type.h> 13 #include <linux/soundwire/sdw_registers.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/sdw.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/initval.h> 23 24 #include "rt1308.h" 25 #include "rt1308-sdw.h" 26 27 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 28 { 29 switch (reg) { 30 case 0x00e0: 31 case 0x00f0: 32 case 0x2f01 ... 0x2f07: 33 case 0x3000 ... 0x3001: 34 case 0x3004 ... 0x3005: 35 case 0x3008: 36 case 0x300a: 37 case 0xc000 ... 0xcff3: 38 return true; 39 default: 40 return false; 41 } 42 } 43 44 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 45 { 46 switch (reg) { 47 case 0x2f01 ... 0x2f07: 48 case 0x3000 ... 0x3001: 49 case 0x3004 ... 0x3005: 50 case 0x3008: 51 case 0x300a: 52 case 0xc000: 53 case 0xc710: 54 case 0xcf01: 55 case 0xc860 ... 0xc863: 56 case 0xc870 ... 0xc873: 57 return true; 58 default: 59 return false; 60 } 61 } 62 63 static const struct regmap_config rt1308_sdw_regmap = { 64 .reg_bits = 32, 65 .val_bits = 8, 66 .readable_reg = rt1308_readable_register, 67 .volatile_reg = rt1308_volatile_register, 68 .max_register = 0xcfff, 69 .reg_defaults = rt1308_reg_defaults, 70 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults), 71 .cache_type = REGCACHE_MAPLE, 72 .use_single_read = true, 73 .use_single_write = true, 74 }; 75 76 /* Bus clock frequency */ 77 #define RT1308_CLK_FREQ_9600000HZ 9600000 78 #define RT1308_CLK_FREQ_12000000HZ 12000000 79 #define RT1308_CLK_FREQ_6000000HZ 6000000 80 #define RT1308_CLK_FREQ_4800000HZ 4800000 81 #define RT1308_CLK_FREQ_2400000HZ 2400000 82 #define RT1308_CLK_FREQ_12288000HZ 12288000 83 84 static int rt1308_clock_config(struct device *dev) 85 { 86 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 87 unsigned int clk_freq, value; 88 89 clk_freq = (rt1308->params.curr_dr_freq >> 1); 90 91 switch (clk_freq) { 92 case RT1308_CLK_FREQ_12000000HZ: 93 value = 0x0; 94 break; 95 case RT1308_CLK_FREQ_6000000HZ: 96 value = 0x1; 97 break; 98 case RT1308_CLK_FREQ_9600000HZ: 99 value = 0x2; 100 break; 101 case RT1308_CLK_FREQ_4800000HZ: 102 value = 0x3; 103 break; 104 case RT1308_CLK_FREQ_2400000HZ: 105 value = 0x4; 106 break; 107 case RT1308_CLK_FREQ_12288000HZ: 108 value = 0x5; 109 break; 110 default: 111 return -EINVAL; 112 } 113 114 regmap_write(rt1308->regmap, 0xe0, value); 115 regmap_write(rt1308->regmap, 0xf0, value); 116 117 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq); 118 119 return 0; 120 } 121 122 static int rt1308_read_prop(struct sdw_slave *slave) 123 { 124 struct sdw_slave_prop *prop = &slave->prop; 125 int nval, i; 126 u32 bit; 127 unsigned long addr; 128 struct sdw_dpn_prop *dpn; 129 130 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 131 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 132 133 prop->paging_support = true; 134 135 /* first we need to allocate memory for set bits in port lists */ 136 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ 137 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 138 139 /* for sink */ 140 nval = hweight32(prop->sink_ports); 141 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 142 sizeof(*prop->sink_dpn_prop), 143 GFP_KERNEL); 144 if (!prop->sink_dpn_prop) 145 return -ENOMEM; 146 147 i = 0; 148 dpn = prop->sink_dpn_prop; 149 addr = prop->sink_ports; 150 for_each_set_bit(bit, &addr, 32) { 151 dpn[i].num = bit; 152 dpn[i].type = SDW_DPN_FULL; 153 dpn[i].simple_ch_prep_sm = true; 154 dpn[i].ch_prep_timeout = 10; 155 i++; 156 } 157 158 /* set the timeout values */ 159 prop->clk_stop_timeout = 20; 160 161 dev_dbg(&slave->dev, "%s\n", __func__); 162 163 return 0; 164 } 165 166 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308) 167 { 168 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp; 169 unsigned int efuse_c_btl_l, efuse_c_btl_r; 170 171 /* read efuse to apply calibration parameters */ 172 regmap_write(rt1308->regmap, 0xc7f0, 0x04); 173 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); 174 msleep(100); 175 regmap_write(rt1308->regmap, 0xc7f0, 0x44); 176 msleep(20); 177 regmap_write(rt1308->regmap, 0xc240, 0x10); 178 179 regmap_read(rt1308->regmap, 0xc861, &tmp); 180 efuse_m_btl_l = tmp; 181 regmap_read(rt1308->regmap, 0xc860, &tmp); 182 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8); 183 regmap_read(rt1308->regmap, 0xc863, &tmp); 184 efuse_c_btl_l = tmp; 185 regmap_read(rt1308->regmap, 0xc862, &tmp); 186 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8); 187 regmap_read(rt1308->regmap, 0xc871, &tmp); 188 efuse_m_btl_r = tmp; 189 regmap_read(rt1308->regmap, 0xc870, &tmp); 190 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8); 191 regmap_read(rt1308->regmap, 0xc873, &tmp); 192 efuse_c_btl_r = tmp; 193 regmap_read(rt1308->regmap, 0xc872, &tmp); 194 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8); 195 dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, 196 efuse_m_btl_l, efuse_m_btl_r); 197 dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, 198 efuse_c_btl_l, efuse_c_btl_r); 199 } 200 201 static void rt1308_apply_bq_params(struct rt1308_sdw_priv *rt1308) 202 { 203 unsigned int i, reg, data; 204 205 for (i = 0; i < rt1308->bq_params_cnt; i += 3) { 206 reg = rt1308->bq_params[i] | (rt1308->bq_params[i + 1] << 8); 207 data = rt1308->bq_params[i + 2]; 208 regmap_write(rt1308->regmap, reg, data); 209 } 210 } 211 212 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave) 213 { 214 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 215 int ret = 0; 216 unsigned int tmp, hibernation_flag; 217 218 if (rt1308->hw_init) 219 return 0; 220 221 regcache_cache_only(rt1308->regmap, false); 222 if (rt1308->first_hw_init) 223 regcache_cache_bypass(rt1308->regmap, true); 224 225 /* 226 * PM runtime status is marked as 'active' only when a Slave reports as Attached 227 */ 228 if (!rt1308->first_hw_init) 229 /* update count of parent 'active' children */ 230 pm_runtime_set_active(&slave->dev); 231 232 pm_runtime_get_noresume(&slave->dev); 233 234 regmap_read(rt1308->regmap, 0xcf01, &hibernation_flag); 235 if ((hibernation_flag != 0x00) && rt1308->first_hw_init) 236 goto _preset_ready_; 237 238 /* sw reset */ 239 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); 240 241 regmap_read(rt1308->regmap, 0xc710, &tmp); 242 rt1308->hw_ver = tmp; 243 dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver); 244 245 /* initial settings */ 246 regmap_write(rt1308->regmap, 0xc103, 0xc0); 247 regmap_write(rt1308->regmap, 0xc030, 0x17); 248 regmap_write(rt1308->regmap, 0xc031, 0x81); 249 regmap_write(rt1308->regmap, 0xc032, 0x26); 250 regmap_write(rt1308->regmap, 0xc040, 0x80); 251 regmap_write(rt1308->regmap, 0xc041, 0x80); 252 regmap_write(rt1308->regmap, 0xc042, 0x06); 253 regmap_write(rt1308->regmap, 0xc052, 0x0a); 254 regmap_write(rt1308->regmap, 0xc080, 0x0a); 255 regmap_write(rt1308->regmap, 0xc060, 0x02); 256 regmap_write(rt1308->regmap, 0xc061, 0x75); 257 regmap_write(rt1308->regmap, 0xc062, 0x05); 258 regmap_write(rt1308->regmap, 0xc171, 0x07); 259 regmap_write(rt1308->regmap, 0xc173, 0x0d); 260 if (rt1308->hw_ver == RT1308_VER_C) { 261 regmap_write(rt1308->regmap, 0xc311, 0x7f); 262 regmap_write(rt1308->regmap, 0xc300, 0x09); 263 } else { 264 regmap_write(rt1308->regmap, 0xc311, 0x4f); 265 regmap_write(rt1308->regmap, 0xc300, 0x0b); 266 } 267 regmap_write(rt1308->regmap, 0xc900, 0x5a); 268 regmap_write(rt1308->regmap, 0xc1a0, 0x84); 269 regmap_write(rt1308->regmap, 0xc1a1, 0x01); 270 regmap_write(rt1308->regmap, 0xc360, 0x78); 271 regmap_write(rt1308->regmap, 0xc361, 0x87); 272 regmap_write(rt1308->regmap, 0xc0a1, 0x71); 273 regmap_write(rt1308->regmap, 0xc210, 0x00); 274 regmap_write(rt1308->regmap, 0xc070, 0x00); 275 regmap_write(rt1308->regmap, 0xc100, 0xd7); 276 regmap_write(rt1308->regmap, 0xc101, 0xd7); 277 278 /* apply BQ params */ 279 rt1308_apply_bq_params(rt1308); 280 281 regmap_write(rt1308->regmap, 0xcf01, 0x01); 282 283 _preset_ready_: 284 if (rt1308->first_hw_init) { 285 regcache_cache_bypass(rt1308->regmap, false); 286 regcache_mark_dirty(rt1308->regmap); 287 } else 288 rt1308->first_hw_init = true; 289 290 /* Mark Slave initialization complete */ 291 rt1308->hw_init = true; 292 293 pm_runtime_put_autosuspend(&slave->dev); 294 295 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 296 297 return ret; 298 } 299 300 static int rt1308_update_status(struct sdw_slave *slave, 301 enum sdw_slave_status status) 302 { 303 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 304 305 if (status == SDW_SLAVE_UNATTACHED) 306 rt1308->hw_init = false; 307 308 /* 309 * Perform initialization only if slave status is present and 310 * hw_init flag is false 311 */ 312 if (rt1308->hw_init || status != SDW_SLAVE_ATTACHED) 313 return 0; 314 315 /* perform I/O transfers required for Slave initialization */ 316 return rt1308_io_init(&slave->dev, slave); 317 } 318 319 static int rt1308_bus_config(struct sdw_slave *slave, 320 struct sdw_bus_params *params) 321 { 322 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 323 int ret; 324 325 memcpy(&rt1308->params, params, sizeof(*params)); 326 327 ret = rt1308_clock_config(&slave->dev); 328 if (ret < 0) 329 dev_err(&slave->dev, "Invalid clk config"); 330 331 return ret; 332 } 333 334 static int rt1308_interrupt_callback(struct sdw_slave *slave, 335 struct sdw_slave_intr_status *status) 336 { 337 dev_dbg(&slave->dev, 338 "%s control_port_stat=%x", __func__, status->control_port); 339 340 return 0; 341 } 342 343 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 344 struct snd_kcontrol *kcontrol, int event) 345 { 346 struct snd_soc_component *component = 347 snd_soc_dapm_to_component(w->dapm); 348 struct rt1308_sdw_priv *rt1308 = 349 snd_soc_component_get_drvdata(component); 350 351 switch (event) { 352 case SND_SOC_DAPM_POST_PMU: 353 msleep(30); 354 snd_soc_component_update_bits(component, 355 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 356 0x3, 0x3); 357 msleep(40); 358 rt1308_apply_calib_params(rt1308); 359 break; 360 case SND_SOC_DAPM_PRE_PMD: 361 snd_soc_component_update_bits(component, 362 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 363 0x3, 0); 364 usleep_range(150000, 200000); 365 break; 366 367 default: 368 break; 369 } 370 371 return 0; 372 } 373 374 static const char * const rt1308_rx_data_ch_select[] = { 375 "LR", 376 "LL", 377 "RL", 378 "RR", 379 }; 380 381 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, 382 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0, 383 rt1308_rx_data_ch_select); 384 385 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 386 387 /* I2S Data Channel Selection */ 388 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 389 }; 390 391 static const struct snd_kcontrol_new rt1308_sto_dac_l = 392 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 393 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 394 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 395 396 static const struct snd_kcontrol_new rt1308_sto_dac_r = 397 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 398 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 399 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 400 401 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 402 /* Audio Interface */ 403 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 404 405 /* Supply Widgets */ 406 SND_SOC_DAPM_SUPPLY("MBIAS20U", 407 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0), 408 SND_SOC_DAPM_SUPPLY("ALDO", 409 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0), 410 SND_SOC_DAPM_SUPPLY("DBG", 411 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0), 412 SND_SOC_DAPM_SUPPLY("DACL", 413 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0), 414 SND_SOC_DAPM_SUPPLY("CLK25M", 415 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0), 416 SND_SOC_DAPM_SUPPLY("ADC_R", 417 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0), 418 SND_SOC_DAPM_SUPPLY("ADC_L", 419 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0), 420 SND_SOC_DAPM_SUPPLY("DAC Power", 421 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0), 422 423 SND_SOC_DAPM_SUPPLY("DLDO", 424 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0), 425 SND_SOC_DAPM_SUPPLY("VREF", 426 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0), 427 SND_SOC_DAPM_SUPPLY("MIXER_R", 428 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0), 429 SND_SOC_DAPM_SUPPLY("MIXER_L", 430 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0), 431 SND_SOC_DAPM_SUPPLY("MBIAS4U", 432 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0), 433 434 SND_SOC_DAPM_SUPPLY("PLL2_LDO", 435 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0), 436 SND_SOC_DAPM_SUPPLY("PLL2B", 437 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0), 438 SND_SOC_DAPM_SUPPLY("PLL2F", 439 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0), 440 SND_SOC_DAPM_SUPPLY("PLL2F2", 441 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0), 442 SND_SOC_DAPM_SUPPLY("PLL2B2", 443 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0), 444 445 /* Digital Interface */ 446 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 447 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 448 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 449 450 /* Output Lines */ 451 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 452 rt1308_classd_event, 453 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 454 SND_SOC_DAPM_OUTPUT("SPOL"), 455 SND_SOC_DAPM_OUTPUT("SPOR"), 456 }; 457 458 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 459 460 { "DAC", NULL, "AIF1RX" }, 461 462 { "DAC", NULL, "MBIAS20U" }, 463 { "DAC", NULL, "ALDO" }, 464 { "DAC", NULL, "DBG" }, 465 { "DAC", NULL, "DACL" }, 466 { "DAC", NULL, "CLK25M" }, 467 { "DAC", NULL, "ADC_R" }, 468 { "DAC", NULL, "ADC_L" }, 469 { "DAC", NULL, "DLDO" }, 470 { "DAC", NULL, "VREF" }, 471 { "DAC", NULL, "MIXER_R" }, 472 { "DAC", NULL, "MIXER_L" }, 473 { "DAC", NULL, "MBIAS4U" }, 474 { "DAC", NULL, "PLL2_LDO" }, 475 { "DAC", NULL, "PLL2B" }, 476 { "DAC", NULL, "PLL2F" }, 477 { "DAC", NULL, "PLL2F2" }, 478 { "DAC", NULL, "PLL2B2" }, 479 480 { "DAC L", "Switch", "DAC" }, 481 { "DAC R", "Switch", "DAC" }, 482 { "DAC L", NULL, "DAC Power" }, 483 { "DAC R", NULL, "DAC Power" }, 484 485 { "CLASS D", NULL, "DAC L" }, 486 { "CLASS D", NULL, "DAC R" }, 487 { "SPOL", NULL, "CLASS D" }, 488 { "SPOR", NULL, "CLASS D" }, 489 }; 490 491 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 492 int direction) 493 { 494 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 495 496 return 0; 497 } 498 499 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream, 500 struct snd_soc_dai *dai) 501 { 502 snd_soc_dai_set_dma_data(dai, substream, NULL); 503 } 504 505 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai, 506 unsigned int tx_mask, 507 unsigned int rx_mask, 508 int slots, int slot_width) 509 { 510 struct snd_soc_component *component = dai->component; 511 struct rt1308_sdw_priv *rt1308 = 512 snd_soc_component_get_drvdata(component); 513 514 if (tx_mask) 515 return -EINVAL; 516 517 if (slots > 2) 518 return -EINVAL; 519 520 rt1308->rx_mask = rx_mask; 521 rt1308->slots = slots; 522 /* slot_width is not used since it's irrelevant for SoundWire */ 523 524 return 0; 525 } 526 527 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream, 528 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 529 { 530 struct snd_soc_component *component = dai->component; 531 struct rt1308_sdw_priv *rt1308 = 532 snd_soc_component_get_drvdata(component); 533 struct sdw_stream_config stream_config = {0}; 534 struct sdw_port_config port_config = {0}; 535 struct sdw_stream_runtime *sdw_stream; 536 int retval; 537 538 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 539 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 540 541 if (!sdw_stream) 542 return -EINVAL; 543 544 if (!rt1308->sdw_slave) 545 return -EINVAL; 546 547 /* SoundWire specific configuration */ 548 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 549 550 /* port 1 for playback */ 551 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 552 port_config.num = 1; 553 else 554 return -EINVAL; 555 556 if (rt1308->slots) { 557 stream_config.ch_count = rt1308->slots; 558 port_config.ch_mask = rt1308->rx_mask; 559 } 560 561 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config, 562 &port_config, 1, sdw_stream); 563 if (retval) { 564 dev_err(dai->dev, "Unable to configure port\n"); 565 return retval; 566 } 567 568 return retval; 569 } 570 571 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 572 struct snd_soc_dai *dai) 573 { 574 struct snd_soc_component *component = dai->component; 575 struct rt1308_sdw_priv *rt1308 = 576 snd_soc_component_get_drvdata(component); 577 struct sdw_stream_runtime *sdw_stream = 578 snd_soc_dai_get_dma_data(dai, substream); 579 580 if (!rt1308->sdw_slave) 581 return -EINVAL; 582 583 sdw_stream_remove_slave(rt1308->sdw_slave, sdw_stream); 584 return 0; 585 } 586 587 /* 588 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 589 * port_prep are not defined for now 590 */ 591 static const struct sdw_slave_ops rt1308_slave_ops = { 592 .read_prop = rt1308_read_prop, 593 .interrupt_callback = rt1308_interrupt_callback, 594 .update_status = rt1308_update_status, 595 .bus_config = rt1308_bus_config, 596 }; 597 598 static int rt1308_sdw_parse_dt(struct rt1308_sdw_priv *rt1308, struct device *dev) 599 { 600 int ret = 0; 601 602 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1308->bq_params_cnt); 603 if (rt1308->bq_params_cnt) { 604 rt1308->bq_params = devm_kzalloc(dev, rt1308->bq_params_cnt, GFP_KERNEL); 605 if (!rt1308->bq_params) { 606 dev_err(dev, "Could not allocate bq_params memory\n"); 607 ret = -ENOMEM; 608 } else { 609 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1308->bq_params, rt1308->bq_params_cnt); 610 if (ret < 0) 611 dev_err(dev, "Could not read list of realtek,bq-params\n"); 612 } 613 } 614 615 dev_dbg(dev, "bq_params_cnt=%d\n", rt1308->bq_params_cnt); 616 return ret; 617 } 618 619 static int rt1308_sdw_component_probe(struct snd_soc_component *component) 620 { 621 struct rt1308_sdw_priv *rt1308 = snd_soc_component_get_drvdata(component); 622 int ret; 623 624 rt1308->component = component; 625 rt1308_sdw_parse_dt(rt1308, &rt1308->sdw_slave->dev); 626 627 if (!rt1308->first_hw_init) 628 return 0; 629 630 ret = pm_runtime_resume(component->dev); 631 if (ret < 0 && ret != -EACCES) 632 return ret; 633 634 /* apply BQ params */ 635 rt1308_apply_bq_params(rt1308); 636 637 return 0; 638 } 639 640 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = { 641 .probe = rt1308_sdw_component_probe, 642 .controls = rt1308_snd_controls, 643 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 644 .dapm_widgets = rt1308_dapm_widgets, 645 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 646 .dapm_routes = rt1308_dapm_routes, 647 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 648 .endianness = 1, 649 }; 650 651 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 652 .hw_params = rt1308_sdw_hw_params, 653 .hw_free = rt1308_sdw_pcm_hw_free, 654 .set_stream = rt1308_set_sdw_stream, 655 .shutdown = rt1308_sdw_shutdown, 656 .set_tdm_slot = rt1308_sdw_set_tdm_slot, 657 }; 658 659 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 660 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 661 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 662 SNDRV_PCM_FMTBIT_S24_LE) 663 664 static struct snd_soc_dai_driver rt1308_sdw_dai[] = { 665 { 666 .name = "rt1308-aif", 667 .playback = { 668 .stream_name = "DP1 Playback", 669 .channels_min = 1, 670 .channels_max = 2, 671 .rates = RT1308_STEREO_RATES, 672 .formats = RT1308_FORMATS, 673 }, 674 .ops = &rt1308_aif_dai_ops, 675 }, 676 }; 677 678 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap, 679 struct sdw_slave *slave) 680 { 681 struct rt1308_sdw_priv *rt1308; 682 int ret; 683 684 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL); 685 if (!rt1308) 686 return -ENOMEM; 687 688 dev_set_drvdata(dev, rt1308); 689 rt1308->sdw_slave = slave; 690 rt1308->regmap = regmap; 691 692 regcache_cache_only(rt1308->regmap, true); 693 694 /* 695 * Mark hw_init to false 696 * HW init will be performed when device reports present 697 */ 698 rt1308->hw_init = false; 699 rt1308->first_hw_init = false; 700 701 ret = devm_snd_soc_register_component(dev, 702 &soc_component_sdw_rt1308, 703 rt1308_sdw_dai, 704 ARRAY_SIZE(rt1308_sdw_dai)); 705 if (ret < 0) 706 return ret; 707 708 /* set autosuspend parameters */ 709 pm_runtime_set_autosuspend_delay(dev, 3000); 710 pm_runtime_use_autosuspend(dev); 711 712 /* make sure the device does not suspend immediately */ 713 pm_runtime_mark_last_busy(dev); 714 715 pm_runtime_enable(dev); 716 717 /* important note: the device is NOT tagged as 'active' and will remain 718 * 'suspended' until the hardware is enumerated/initialized. This is required 719 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 720 * fail with -EACCESS because of race conditions between card creation and enumeration 721 */ 722 723 dev_dbg(dev, "%s\n", __func__); 724 725 return 0; 726 } 727 728 static int rt1308_sdw_probe(struct sdw_slave *slave, 729 const struct sdw_device_id *id) 730 { 731 struct regmap *regmap; 732 733 /* Regmap Initialization */ 734 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 735 if (IS_ERR(regmap)) 736 return PTR_ERR(regmap); 737 738 return rt1308_sdw_init(&slave->dev, regmap, slave); 739 } 740 741 static void rt1308_sdw_remove(struct sdw_slave *slave) 742 { 743 pm_runtime_disable(&slave->dev); 744 } 745 746 static const struct sdw_device_id rt1308_id[] = { 747 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0), 748 {}, 749 }; 750 MODULE_DEVICE_TABLE(sdw, rt1308_id); 751 752 static int rt1308_dev_suspend(struct device *dev) 753 { 754 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 755 756 if (!rt1308->hw_init) 757 return 0; 758 759 regcache_cache_only(rt1308->regmap, true); 760 761 return 0; 762 } 763 764 #define RT1308_PROBE_TIMEOUT 5000 765 766 static int rt1308_dev_resume(struct device *dev) 767 { 768 struct sdw_slave *slave = dev_to_sdw_dev(dev); 769 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 770 int ret; 771 772 if (!rt1308->first_hw_init) 773 return 0; 774 775 ret = sdw_slave_wait_for_init(slave, RT1308_PROBE_TIMEOUT); 776 if (ret) { 777 sdw_show_ping_status(slave->bus, true); 778 return ret; 779 } 780 781 regcache_cache_only(rt1308->regmap, false); 782 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); 783 784 return 0; 785 } 786 787 static const struct dev_pm_ops rt1308_pm = { 788 SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume) 789 RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL) 790 }; 791 792 static struct sdw_driver rt1308_sdw_driver = { 793 .driver = { 794 .name = "rt1308", 795 .pm = pm_ptr(&rt1308_pm), 796 }, 797 .probe = rt1308_sdw_probe, 798 .remove = rt1308_sdw_remove, 799 .ops = &rt1308_slave_ops, 800 .id_table = rt1308_id, 801 }; 802 module_sdw_driver(rt1308_sdw_driver); 803 804 MODULE_DESCRIPTION("ASoC RT1308 driver SDW"); 805 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 806 MODULE_LICENSE("GPL v2"); 807