1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver 4 // 5 // Copyright(c) 2019 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <linux/soundwire/sdw_registers.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <sound/initval.h> 23 24 #include "rt1308.h" 25 #include "rt1308-sdw.h" 26 27 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 28 { 29 switch (reg) { 30 case 0x00e0: 31 case 0x00f0: 32 case 0x2f01 ... 0x2f07: 33 case 0x3000 ... 0x3001: 34 case 0x3004 ... 0x3005: 35 case 0x3008: 36 case 0x300a: 37 case 0xc000 ... 0xcff3: 38 return true; 39 default: 40 return false; 41 } 42 } 43 44 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 45 { 46 switch (reg) { 47 case 0x2f01 ... 0x2f07: 48 case 0x3000 ... 0x3001: 49 case 0x3004 ... 0x3005: 50 case 0x3008: 51 case 0x300a: 52 case 0xc000: 53 case 0xc860 ... 0xc863: 54 case 0xc870 ... 0xc873: 55 return true; 56 default: 57 return false; 58 } 59 } 60 61 static const struct regmap_config rt1308_sdw_regmap = { 62 .reg_bits = 32, 63 .val_bits = 8, 64 .readable_reg = rt1308_readable_register, 65 .volatile_reg = rt1308_volatile_register, 66 .max_register = 0xcfff, 67 .reg_defaults = rt1308_reg_defaults, 68 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults), 69 .cache_type = REGCACHE_RBTREE, 70 .use_single_read = true, 71 .use_single_write = true, 72 }; 73 74 /* Bus clock frequency */ 75 #define RT1308_CLK_FREQ_9600000HZ 9600000 76 #define RT1308_CLK_FREQ_12000000HZ 12000000 77 #define RT1308_CLK_FREQ_6000000HZ 6000000 78 #define RT1308_CLK_FREQ_4800000HZ 4800000 79 #define RT1308_CLK_FREQ_2400000HZ 2400000 80 #define RT1308_CLK_FREQ_12288000HZ 12288000 81 82 static int rt1308_clock_config(struct device *dev) 83 { 84 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 85 unsigned int clk_freq, value; 86 87 clk_freq = (rt1308->params.curr_dr_freq >> 1); 88 89 switch (clk_freq) { 90 case RT1308_CLK_FREQ_12000000HZ: 91 value = 0x0; 92 break; 93 case RT1308_CLK_FREQ_6000000HZ: 94 value = 0x1; 95 break; 96 case RT1308_CLK_FREQ_9600000HZ: 97 value = 0x2; 98 break; 99 case RT1308_CLK_FREQ_4800000HZ: 100 value = 0x3; 101 break; 102 case RT1308_CLK_FREQ_2400000HZ: 103 value = 0x4; 104 break; 105 case RT1308_CLK_FREQ_12288000HZ: 106 value = 0x5; 107 break; 108 default: 109 return -EINVAL; 110 } 111 112 regmap_write(rt1308->regmap, 0xe0, value); 113 regmap_write(rt1308->regmap, 0xf0, value); 114 115 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq); 116 117 return 0; 118 } 119 120 static int rt1308_read_prop(struct sdw_slave *slave) 121 { 122 struct sdw_slave_prop *prop = &slave->prop; 123 int nval, i; 124 u32 bit; 125 unsigned long addr; 126 struct sdw_dpn_prop *dpn; 127 128 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 129 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 130 131 prop->paging_support = true; 132 133 /* first we need to allocate memory for set bits in port lists */ 134 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ 135 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 136 137 /* for sink */ 138 nval = hweight32(prop->sink_ports); 139 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 140 sizeof(*prop->sink_dpn_prop), 141 GFP_KERNEL); 142 if (!prop->sink_dpn_prop) 143 return -ENOMEM; 144 145 i = 0; 146 dpn = prop->sink_dpn_prop; 147 addr = prop->sink_ports; 148 for_each_set_bit(bit, &addr, 32) { 149 dpn[i].num = bit; 150 dpn[i].type = SDW_DPN_FULL; 151 dpn[i].simple_ch_prep_sm = true; 152 dpn[i].ch_prep_timeout = 10; 153 i++; 154 } 155 156 /* set the timeout values */ 157 prop->clk_stop_timeout = 20; 158 159 dev_dbg(&slave->dev, "%s\n", __func__); 160 161 return 0; 162 } 163 164 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308) 165 { 166 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp; 167 unsigned int efuse_c_btl_l, efuse_c_btl_r; 168 169 /* read efuse to apply calibration parameters */ 170 regmap_write(rt1308->regmap, 0xc7f0, 0x04); 171 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); 172 msleep(100); 173 regmap_write(rt1308->regmap, 0xc7f0, 0x44); 174 msleep(20); 175 regmap_write(rt1308->regmap, 0xc240, 0x10); 176 177 regmap_read(rt1308->regmap, 0xc861, &tmp); 178 efuse_m_btl_l = tmp; 179 regmap_read(rt1308->regmap, 0xc860, &tmp); 180 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8); 181 regmap_read(rt1308->regmap, 0xc863, &tmp); 182 efuse_c_btl_l = tmp; 183 regmap_read(rt1308->regmap, 0xc862, &tmp); 184 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8); 185 regmap_read(rt1308->regmap, 0xc871, &tmp); 186 efuse_m_btl_r = tmp; 187 regmap_read(rt1308->regmap, 0xc870, &tmp); 188 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8); 189 regmap_read(rt1308->regmap, 0xc873, &tmp); 190 efuse_c_btl_r = tmp; 191 regmap_read(rt1308->regmap, 0xc872, &tmp); 192 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8); 193 dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, 194 efuse_m_btl_l, efuse_m_btl_r); 195 dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, 196 efuse_c_btl_l, efuse_c_btl_r); 197 } 198 199 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave) 200 { 201 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 202 int ret = 0; 203 204 if (rt1308->hw_init) 205 return 0; 206 207 if (rt1308->first_hw_init) { 208 regcache_cache_only(rt1308->regmap, false); 209 regcache_cache_bypass(rt1308->regmap, true); 210 } 211 212 /* 213 * PM runtime is only enabled when a Slave reports as Attached 214 */ 215 if (!rt1308->first_hw_init) { 216 /* set autosuspend parameters */ 217 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 218 pm_runtime_use_autosuspend(&slave->dev); 219 220 /* update count of parent 'active' children */ 221 pm_runtime_set_active(&slave->dev); 222 223 /* make sure the device does not suspend immediately */ 224 pm_runtime_mark_last_busy(&slave->dev); 225 226 pm_runtime_enable(&slave->dev); 227 } 228 229 pm_runtime_get_noresume(&slave->dev); 230 231 /* sw reset */ 232 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); 233 234 /* initial settings */ 235 regmap_write(rt1308->regmap, 0xc103, 0xc0); 236 regmap_write(rt1308->regmap, 0xc030, 0x17); 237 regmap_write(rt1308->regmap, 0xc031, 0x81); 238 regmap_write(rt1308->regmap, 0xc032, 0x26); 239 regmap_write(rt1308->regmap, 0xc040, 0x80); 240 regmap_write(rt1308->regmap, 0xc041, 0x80); 241 regmap_write(rt1308->regmap, 0xc042, 0x06); 242 regmap_write(rt1308->regmap, 0xc052, 0x0a); 243 regmap_write(rt1308->regmap, 0xc080, 0x0a); 244 regmap_write(rt1308->regmap, 0xc060, 0x02); 245 regmap_write(rt1308->regmap, 0xc061, 0x75); 246 regmap_write(rt1308->regmap, 0xc062, 0x05); 247 regmap_write(rt1308->regmap, 0xc171, 0x07); 248 regmap_write(rt1308->regmap, 0xc173, 0x0d); 249 regmap_write(rt1308->regmap, 0xc311, 0x7f); 250 regmap_write(rt1308->regmap, 0xc900, 0x90); 251 regmap_write(rt1308->regmap, 0xc1a0, 0x84); 252 regmap_write(rt1308->regmap, 0xc1a1, 0x01); 253 regmap_write(rt1308->regmap, 0xc360, 0x78); 254 regmap_write(rt1308->regmap, 0xc361, 0x87); 255 regmap_write(rt1308->regmap, 0xc0a1, 0x71); 256 regmap_write(rt1308->regmap, 0xc210, 0x00); 257 regmap_write(rt1308->regmap, 0xc070, 0x00); 258 regmap_write(rt1308->regmap, 0xc100, 0xd7); 259 regmap_write(rt1308->regmap, 0xc101, 0xd7); 260 regmap_write(rt1308->regmap, 0xc300, 0x09); 261 262 if (rt1308->first_hw_init) { 263 regcache_cache_bypass(rt1308->regmap, false); 264 regcache_mark_dirty(rt1308->regmap); 265 } else 266 rt1308->first_hw_init = true; 267 268 /* Mark Slave initialization complete */ 269 rt1308->hw_init = true; 270 271 pm_runtime_mark_last_busy(&slave->dev); 272 pm_runtime_put_autosuspend(&slave->dev); 273 274 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 275 276 return ret; 277 } 278 279 static int rt1308_update_status(struct sdw_slave *slave, 280 enum sdw_slave_status status) 281 { 282 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 283 284 /* Update the status */ 285 rt1308->status = status; 286 287 if (status == SDW_SLAVE_UNATTACHED) 288 rt1308->hw_init = false; 289 290 /* 291 * Perform initialization only if slave status is present and 292 * hw_init flag is false 293 */ 294 if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED) 295 return 0; 296 297 /* perform I/O transfers required for Slave initialization */ 298 return rt1308_io_init(&slave->dev, slave); 299 } 300 301 static int rt1308_bus_config(struct sdw_slave *slave, 302 struct sdw_bus_params *params) 303 { 304 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 305 int ret; 306 307 memcpy(&rt1308->params, params, sizeof(*params)); 308 309 ret = rt1308_clock_config(&slave->dev); 310 if (ret < 0) 311 dev_err(&slave->dev, "Invalid clk config"); 312 313 return ret; 314 } 315 316 static int rt1308_interrupt_callback(struct sdw_slave *slave, 317 struct sdw_slave_intr_status *status) 318 { 319 dev_dbg(&slave->dev, 320 "%s control_port_stat=%x", __func__, status->control_port); 321 322 return 0; 323 } 324 325 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 326 struct snd_kcontrol *kcontrol, int event) 327 { 328 struct snd_soc_component *component = 329 snd_soc_dapm_to_component(w->dapm); 330 struct rt1308_sdw_priv *rt1308 = 331 snd_soc_component_get_drvdata(component); 332 333 switch (event) { 334 case SND_SOC_DAPM_POST_PMU: 335 msleep(30); 336 snd_soc_component_update_bits(component, 337 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 338 0x3, 0x3); 339 msleep(40); 340 rt1308_apply_calib_params(rt1308); 341 break; 342 case SND_SOC_DAPM_PRE_PMD: 343 snd_soc_component_update_bits(component, 344 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 345 0x3, 0); 346 usleep_range(150000, 200000); 347 break; 348 349 default: 350 break; 351 } 352 353 return 0; 354 } 355 356 static const char * const rt1308_rx_data_ch_select[] = { 357 "LR", 358 "LL", 359 "RL", 360 "RR", 361 }; 362 363 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, 364 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0, 365 rt1308_rx_data_ch_select); 366 367 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 368 369 /* I2S Data Channel Selection */ 370 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 371 }; 372 373 static const struct snd_kcontrol_new rt1308_sto_dac_l = 374 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 375 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 376 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 377 378 static const struct snd_kcontrol_new rt1308_sto_dac_r = 379 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 380 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 381 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 382 383 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 384 /* Audio Interface */ 385 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 386 387 /* Supply Widgets */ 388 SND_SOC_DAPM_SUPPLY("MBIAS20U", 389 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0), 390 SND_SOC_DAPM_SUPPLY("ALDO", 391 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0), 392 SND_SOC_DAPM_SUPPLY("DBG", 393 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0), 394 SND_SOC_DAPM_SUPPLY("DACL", 395 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0), 396 SND_SOC_DAPM_SUPPLY("CLK25M", 397 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0), 398 SND_SOC_DAPM_SUPPLY("ADC_R", 399 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0), 400 SND_SOC_DAPM_SUPPLY("ADC_L", 401 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0), 402 SND_SOC_DAPM_SUPPLY("DAC Power", 403 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0), 404 405 SND_SOC_DAPM_SUPPLY("DLDO", 406 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0), 407 SND_SOC_DAPM_SUPPLY("VREF", 408 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0), 409 SND_SOC_DAPM_SUPPLY("MIXER_R", 410 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0), 411 SND_SOC_DAPM_SUPPLY("MIXER_L", 412 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0), 413 SND_SOC_DAPM_SUPPLY("MBIAS4U", 414 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0), 415 416 SND_SOC_DAPM_SUPPLY("PLL2_LDO", 417 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0), 418 SND_SOC_DAPM_SUPPLY("PLL2B", 419 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0), 420 SND_SOC_DAPM_SUPPLY("PLL2F", 421 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0), 422 SND_SOC_DAPM_SUPPLY("PLL2F2", 423 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0), 424 SND_SOC_DAPM_SUPPLY("PLL2B2", 425 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0), 426 427 /* Digital Interface */ 428 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 429 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 430 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 431 432 /* Output Lines */ 433 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 434 rt1308_classd_event, 435 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 436 SND_SOC_DAPM_OUTPUT("SPOL"), 437 SND_SOC_DAPM_OUTPUT("SPOR"), 438 }; 439 440 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 441 442 { "DAC", NULL, "AIF1RX" }, 443 444 { "DAC", NULL, "MBIAS20U" }, 445 { "DAC", NULL, "ALDO" }, 446 { "DAC", NULL, "DBG" }, 447 { "DAC", NULL, "DACL" }, 448 { "DAC", NULL, "CLK25M" }, 449 { "DAC", NULL, "ADC_R" }, 450 { "DAC", NULL, "ADC_L" }, 451 { "DAC", NULL, "DLDO" }, 452 { "DAC", NULL, "VREF" }, 453 { "DAC", NULL, "MIXER_R" }, 454 { "DAC", NULL, "MIXER_L" }, 455 { "DAC", NULL, "MBIAS4U" }, 456 { "DAC", NULL, "PLL2_LDO" }, 457 { "DAC", NULL, "PLL2B" }, 458 { "DAC", NULL, "PLL2F" }, 459 { "DAC", NULL, "PLL2F2" }, 460 { "DAC", NULL, "PLL2B2" }, 461 462 { "DAC L", "Switch", "DAC" }, 463 { "DAC R", "Switch", "DAC" }, 464 { "DAC L", NULL, "DAC Power" }, 465 { "DAC R", NULL, "DAC Power" }, 466 467 { "CLASS D", NULL, "DAC L" }, 468 { "CLASS D", NULL, "DAC R" }, 469 { "SPOL", NULL, "CLASS D" }, 470 { "SPOR", NULL, "CLASS D" }, 471 }; 472 473 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 474 int direction) 475 { 476 struct sdw_stream_data *stream; 477 478 if (!sdw_stream) 479 return 0; 480 481 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 482 if (!stream) 483 return -ENOMEM; 484 485 stream->sdw_stream = sdw_stream; 486 487 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 488 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 489 dai->playback_dma_data = stream; 490 else 491 dai->capture_dma_data = stream; 492 493 return 0; 494 } 495 496 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream, 497 struct snd_soc_dai *dai) 498 { 499 struct sdw_stream_data *stream; 500 501 stream = snd_soc_dai_get_dma_data(dai, substream); 502 snd_soc_dai_set_dma_data(dai, substream, NULL); 503 kfree(stream); 504 } 505 506 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai, 507 unsigned int tx_mask, 508 unsigned int rx_mask, 509 int slots, int slot_width) 510 { 511 struct snd_soc_component *component = dai->component; 512 struct rt1308_sdw_priv *rt1308 = 513 snd_soc_component_get_drvdata(component); 514 515 if (tx_mask) 516 return -EINVAL; 517 518 if (slots > 2) 519 return -EINVAL; 520 521 rt1308->rx_mask = rx_mask; 522 rt1308->slots = slots; 523 /* slot_width is not used since it's irrelevant for SoundWire */ 524 525 return 0; 526 } 527 528 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream, 529 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 530 { 531 struct snd_soc_component *component = dai->component; 532 struct rt1308_sdw_priv *rt1308 = 533 snd_soc_component_get_drvdata(component); 534 struct sdw_stream_config stream_config; 535 struct sdw_port_config port_config; 536 enum sdw_data_direction direction; 537 struct sdw_stream_data *stream; 538 int retval, port, num_channels, ch_mask; 539 540 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 541 stream = snd_soc_dai_get_dma_data(dai, substream); 542 543 if (!stream) 544 return -EINVAL; 545 546 if (!rt1308->sdw_slave) 547 return -EINVAL; 548 549 /* SoundWire specific configuration */ 550 /* port 1 for playback */ 551 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 552 direction = SDW_DATA_DIR_RX; 553 port = 1; 554 } else { 555 return -EINVAL; 556 } 557 558 if (rt1308->slots) { 559 num_channels = rt1308->slots; 560 ch_mask = rt1308->rx_mask; 561 } else { 562 num_channels = params_channels(params); 563 ch_mask = (1 << num_channels) - 1; 564 } 565 566 stream_config.frame_rate = params_rate(params); 567 stream_config.ch_count = num_channels; 568 stream_config.bps = snd_pcm_format_width(params_format(params)); 569 stream_config.direction = direction; 570 571 port_config.ch_mask = ch_mask; 572 port_config.num = port; 573 574 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config, 575 &port_config, 1, stream->sdw_stream); 576 if (retval) { 577 dev_err(dai->dev, "Unable to configure port\n"); 578 return retval; 579 } 580 581 return retval; 582 } 583 584 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 585 struct snd_soc_dai *dai) 586 { 587 struct snd_soc_component *component = dai->component; 588 struct rt1308_sdw_priv *rt1308 = 589 snd_soc_component_get_drvdata(component); 590 struct sdw_stream_data *stream = 591 snd_soc_dai_get_dma_data(dai, substream); 592 593 if (!rt1308->sdw_slave) 594 return -EINVAL; 595 596 sdw_stream_remove_slave(rt1308->sdw_slave, stream->sdw_stream); 597 return 0; 598 } 599 600 /* 601 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 602 * port_prep are not defined for now 603 */ 604 static const struct sdw_slave_ops rt1308_slave_ops = { 605 .read_prop = rt1308_read_prop, 606 .interrupt_callback = rt1308_interrupt_callback, 607 .update_status = rt1308_update_status, 608 .bus_config = rt1308_bus_config, 609 }; 610 611 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = { 612 .controls = rt1308_snd_controls, 613 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 614 .dapm_widgets = rt1308_dapm_widgets, 615 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 616 .dapm_routes = rt1308_dapm_routes, 617 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 618 .endianness = 1, 619 }; 620 621 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 622 .hw_params = rt1308_sdw_hw_params, 623 .hw_free = rt1308_sdw_pcm_hw_free, 624 .set_stream = rt1308_set_sdw_stream, 625 .shutdown = rt1308_sdw_shutdown, 626 .set_tdm_slot = rt1308_sdw_set_tdm_slot, 627 }; 628 629 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 630 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 631 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 632 SNDRV_PCM_FMTBIT_S24_LE) 633 634 static struct snd_soc_dai_driver rt1308_sdw_dai[] = { 635 { 636 .name = "rt1308-aif", 637 .playback = { 638 .stream_name = "DP1 Playback", 639 .channels_min = 1, 640 .channels_max = 2, 641 .rates = RT1308_STEREO_RATES, 642 .formats = RT1308_FORMATS, 643 }, 644 .ops = &rt1308_aif_dai_ops, 645 }, 646 }; 647 648 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap, 649 struct sdw_slave *slave) 650 { 651 struct rt1308_sdw_priv *rt1308; 652 int ret; 653 654 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL); 655 if (!rt1308) 656 return -ENOMEM; 657 658 dev_set_drvdata(dev, rt1308); 659 rt1308->sdw_slave = slave; 660 rt1308->regmap = regmap; 661 662 /* 663 * Mark hw_init to false 664 * HW init will be performed when device reports present 665 */ 666 rt1308->hw_init = false; 667 rt1308->first_hw_init = false; 668 669 ret = devm_snd_soc_register_component(dev, 670 &soc_component_sdw_rt1308, 671 rt1308_sdw_dai, 672 ARRAY_SIZE(rt1308_sdw_dai)); 673 674 dev_dbg(&slave->dev, "%s\n", __func__); 675 676 return ret; 677 } 678 679 static int rt1308_sdw_probe(struct sdw_slave *slave, 680 const struct sdw_device_id *id) 681 { 682 struct regmap *regmap; 683 684 /* Regmap Initialization */ 685 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 686 if (IS_ERR(regmap)) 687 return PTR_ERR(regmap); 688 689 rt1308_sdw_init(&slave->dev, regmap, slave); 690 691 return 0; 692 } 693 694 static int rt1308_sdw_remove(struct sdw_slave *slave) 695 { 696 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 697 698 if (rt1308->first_hw_init) 699 pm_runtime_disable(&slave->dev); 700 701 return 0; 702 } 703 704 static const struct sdw_device_id rt1308_id[] = { 705 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0), 706 {}, 707 }; 708 MODULE_DEVICE_TABLE(sdw, rt1308_id); 709 710 static int __maybe_unused rt1308_dev_suspend(struct device *dev) 711 { 712 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 713 714 if (!rt1308->hw_init) 715 return 0; 716 717 regcache_cache_only(rt1308->regmap, true); 718 719 return 0; 720 } 721 722 #define RT1308_PROBE_TIMEOUT 5000 723 724 static int __maybe_unused rt1308_dev_resume(struct device *dev) 725 { 726 struct sdw_slave *slave = dev_to_sdw_dev(dev); 727 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 728 unsigned long time; 729 730 if (!rt1308->first_hw_init) 731 return 0; 732 733 if (!slave->unattach_request) 734 goto regmap_sync; 735 736 time = wait_for_completion_timeout(&slave->initialization_complete, 737 msecs_to_jiffies(RT1308_PROBE_TIMEOUT)); 738 if (!time) { 739 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 740 return -ETIMEDOUT; 741 } 742 743 regmap_sync: 744 slave->unattach_request = 0; 745 regcache_cache_only(rt1308->regmap, false); 746 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); 747 748 return 0; 749 } 750 751 static const struct dev_pm_ops rt1308_pm = { 752 SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume) 753 SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL) 754 }; 755 756 static struct sdw_driver rt1308_sdw_driver = { 757 .driver = { 758 .name = "rt1308", 759 .owner = THIS_MODULE, 760 .pm = &rt1308_pm, 761 }, 762 .probe = rt1308_sdw_probe, 763 .remove = rt1308_sdw_remove, 764 .ops = &rt1308_slave_ops, 765 .id_table = rt1308_id, 766 }; 767 module_sdw_driver(rt1308_sdw_driver); 768 769 MODULE_DESCRIPTION("ASoC RT1308 driver SDW"); 770 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 771 MODULE_LICENSE("GPL v2"); 772