1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver 4 // 5 // Copyright(c) 2019 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <linux/soundwire/sdw_registers.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/sdw.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dapm.h> 23 #include <sound/initval.h> 24 25 #include "rt1308.h" 26 #include "rt1308-sdw.h" 27 28 static bool rt1308_readable_register(struct device *dev, unsigned int reg) 29 { 30 switch (reg) { 31 case 0x00e0: 32 case 0x00f0: 33 case 0x2f01 ... 0x2f07: 34 case 0x3000 ... 0x3001: 35 case 0x3004 ... 0x3005: 36 case 0x3008: 37 case 0x300a: 38 case 0xc000 ... 0xcff3: 39 return true; 40 default: 41 return false; 42 } 43 } 44 45 static bool rt1308_volatile_register(struct device *dev, unsigned int reg) 46 { 47 switch (reg) { 48 case 0x2f01 ... 0x2f07: 49 case 0x3000 ... 0x3001: 50 case 0x3004 ... 0x3005: 51 case 0x3008: 52 case 0x300a: 53 case 0xc000: 54 case 0xc710: 55 case 0xc860 ... 0xc863: 56 case 0xc870 ... 0xc873: 57 return true; 58 default: 59 return false; 60 } 61 } 62 63 static const struct regmap_config rt1308_sdw_regmap = { 64 .reg_bits = 32, 65 .val_bits = 8, 66 .readable_reg = rt1308_readable_register, 67 .volatile_reg = rt1308_volatile_register, 68 .max_register = 0xcfff, 69 .reg_defaults = rt1308_reg_defaults, 70 .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults), 71 .cache_type = REGCACHE_MAPLE, 72 .use_single_read = true, 73 .use_single_write = true, 74 }; 75 76 /* Bus clock frequency */ 77 #define RT1308_CLK_FREQ_9600000HZ 9600000 78 #define RT1308_CLK_FREQ_12000000HZ 12000000 79 #define RT1308_CLK_FREQ_6000000HZ 6000000 80 #define RT1308_CLK_FREQ_4800000HZ 4800000 81 #define RT1308_CLK_FREQ_2400000HZ 2400000 82 #define RT1308_CLK_FREQ_12288000HZ 12288000 83 84 static int rt1308_clock_config(struct device *dev) 85 { 86 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 87 unsigned int clk_freq, value; 88 89 clk_freq = (rt1308->params.curr_dr_freq >> 1); 90 91 switch (clk_freq) { 92 case RT1308_CLK_FREQ_12000000HZ: 93 value = 0x0; 94 break; 95 case RT1308_CLK_FREQ_6000000HZ: 96 value = 0x1; 97 break; 98 case RT1308_CLK_FREQ_9600000HZ: 99 value = 0x2; 100 break; 101 case RT1308_CLK_FREQ_4800000HZ: 102 value = 0x3; 103 break; 104 case RT1308_CLK_FREQ_2400000HZ: 105 value = 0x4; 106 break; 107 case RT1308_CLK_FREQ_12288000HZ: 108 value = 0x5; 109 break; 110 default: 111 return -EINVAL; 112 } 113 114 regmap_write(rt1308->regmap, 0xe0, value); 115 regmap_write(rt1308->regmap, 0xf0, value); 116 117 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq); 118 119 return 0; 120 } 121 122 static int rt1308_read_prop(struct sdw_slave *slave) 123 { 124 struct sdw_slave_prop *prop = &slave->prop; 125 int nval, i; 126 u32 bit; 127 unsigned long addr; 128 struct sdw_dpn_prop *dpn; 129 130 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 131 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 132 133 prop->paging_support = true; 134 135 /* first we need to allocate memory for set bits in port lists */ 136 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ 137 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ 138 139 /* for sink */ 140 nval = hweight32(prop->sink_ports); 141 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 142 sizeof(*prop->sink_dpn_prop), 143 GFP_KERNEL); 144 if (!prop->sink_dpn_prop) 145 return -ENOMEM; 146 147 i = 0; 148 dpn = prop->sink_dpn_prop; 149 addr = prop->sink_ports; 150 for_each_set_bit(bit, &addr, 32) { 151 dpn[i].num = bit; 152 dpn[i].type = SDW_DPN_FULL; 153 dpn[i].simple_ch_prep_sm = true; 154 dpn[i].ch_prep_timeout = 10; 155 i++; 156 } 157 158 /* set the timeout values */ 159 prop->clk_stop_timeout = 20; 160 161 dev_dbg(&slave->dev, "%s\n", __func__); 162 163 return 0; 164 } 165 166 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308) 167 { 168 unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp; 169 unsigned int efuse_c_btl_l, efuse_c_btl_r; 170 171 /* read efuse to apply calibration parameters */ 172 regmap_write(rt1308->regmap, 0xc7f0, 0x04); 173 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); 174 msleep(100); 175 regmap_write(rt1308->regmap, 0xc7f0, 0x44); 176 msleep(20); 177 regmap_write(rt1308->regmap, 0xc240, 0x10); 178 179 regmap_read(rt1308->regmap, 0xc861, &tmp); 180 efuse_m_btl_l = tmp; 181 regmap_read(rt1308->regmap, 0xc860, &tmp); 182 efuse_m_btl_l = efuse_m_btl_l | (tmp << 8); 183 regmap_read(rt1308->regmap, 0xc863, &tmp); 184 efuse_c_btl_l = tmp; 185 regmap_read(rt1308->regmap, 0xc862, &tmp); 186 efuse_c_btl_l = efuse_c_btl_l | (tmp << 8); 187 regmap_read(rt1308->regmap, 0xc871, &tmp); 188 efuse_m_btl_r = tmp; 189 regmap_read(rt1308->regmap, 0xc870, &tmp); 190 efuse_m_btl_r = efuse_m_btl_r | (tmp << 8); 191 regmap_read(rt1308->regmap, 0xc873, &tmp); 192 efuse_c_btl_r = tmp; 193 regmap_read(rt1308->regmap, 0xc872, &tmp); 194 efuse_c_btl_r = efuse_c_btl_r | (tmp << 8); 195 dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, 196 efuse_m_btl_l, efuse_m_btl_r); 197 dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, 198 efuse_c_btl_l, efuse_c_btl_r); 199 } 200 201 static void rt1308_apply_bq_params(struct rt1308_sdw_priv *rt1308) 202 { 203 unsigned int i, reg, data; 204 205 for (i = 0; i < rt1308->bq_params_cnt; i += 3) { 206 reg = rt1308->bq_params[i] | (rt1308->bq_params[i + 1] << 8); 207 data = rt1308->bq_params[i + 2]; 208 regmap_write(rt1308->regmap, reg, data); 209 } 210 } 211 212 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave) 213 { 214 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 215 int ret = 0; 216 unsigned int tmp; 217 218 if (rt1308->hw_init) 219 return 0; 220 221 regcache_cache_only(rt1308->regmap, false); 222 if (rt1308->first_hw_init) 223 regcache_cache_bypass(rt1308->regmap, true); 224 225 /* 226 * PM runtime status is marked as 'active' only when a Slave reports as Attached 227 */ 228 if (!rt1308->first_hw_init) 229 /* update count of parent 'active' children */ 230 pm_runtime_set_active(&slave->dev); 231 232 pm_runtime_get_noresume(&slave->dev); 233 234 /* sw reset */ 235 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); 236 237 regmap_read(rt1308->regmap, 0xc710, &tmp); 238 rt1308->hw_ver = tmp; 239 dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver); 240 241 /* initial settings */ 242 regmap_write(rt1308->regmap, 0xc103, 0xc0); 243 regmap_write(rt1308->regmap, 0xc030, 0x17); 244 regmap_write(rt1308->regmap, 0xc031, 0x81); 245 regmap_write(rt1308->regmap, 0xc032, 0x26); 246 regmap_write(rt1308->regmap, 0xc040, 0x80); 247 regmap_write(rt1308->regmap, 0xc041, 0x80); 248 regmap_write(rt1308->regmap, 0xc042, 0x06); 249 regmap_write(rt1308->regmap, 0xc052, 0x0a); 250 regmap_write(rt1308->regmap, 0xc080, 0x0a); 251 regmap_write(rt1308->regmap, 0xc060, 0x02); 252 regmap_write(rt1308->regmap, 0xc061, 0x75); 253 regmap_write(rt1308->regmap, 0xc062, 0x05); 254 regmap_write(rt1308->regmap, 0xc171, 0x07); 255 regmap_write(rt1308->regmap, 0xc173, 0x0d); 256 if (rt1308->hw_ver == RT1308_VER_C) { 257 regmap_write(rt1308->regmap, 0xc311, 0x7f); 258 regmap_write(rt1308->regmap, 0xc300, 0x09); 259 } else { 260 regmap_write(rt1308->regmap, 0xc311, 0x4f); 261 regmap_write(rt1308->regmap, 0xc300, 0x0b); 262 } 263 regmap_write(rt1308->regmap, 0xc900, 0x5a); 264 regmap_write(rt1308->regmap, 0xc1a0, 0x84); 265 regmap_write(rt1308->regmap, 0xc1a1, 0x01); 266 regmap_write(rt1308->regmap, 0xc360, 0x78); 267 regmap_write(rt1308->regmap, 0xc361, 0x87); 268 regmap_write(rt1308->regmap, 0xc0a1, 0x71); 269 regmap_write(rt1308->regmap, 0xc210, 0x00); 270 regmap_write(rt1308->regmap, 0xc070, 0x00); 271 regmap_write(rt1308->regmap, 0xc100, 0xd7); 272 regmap_write(rt1308->regmap, 0xc101, 0xd7); 273 274 if (rt1308->first_hw_init) { 275 regcache_cache_bypass(rt1308->regmap, false); 276 regcache_mark_dirty(rt1308->regmap); 277 } else 278 rt1308->first_hw_init = true; 279 280 /* Mark Slave initialization complete */ 281 rt1308->hw_init = true; 282 283 pm_runtime_mark_last_busy(&slave->dev); 284 pm_runtime_put_autosuspend(&slave->dev); 285 286 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 287 288 return ret; 289 } 290 291 static int rt1308_update_status(struct sdw_slave *slave, 292 enum sdw_slave_status status) 293 { 294 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 295 296 if (status == SDW_SLAVE_UNATTACHED) 297 rt1308->hw_init = false; 298 299 /* 300 * Perform initialization only if slave status is present and 301 * hw_init flag is false 302 */ 303 if (rt1308->hw_init || status != SDW_SLAVE_ATTACHED) 304 return 0; 305 306 /* perform I/O transfers required for Slave initialization */ 307 return rt1308_io_init(&slave->dev, slave); 308 } 309 310 static int rt1308_bus_config(struct sdw_slave *slave, 311 struct sdw_bus_params *params) 312 { 313 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev); 314 int ret; 315 316 memcpy(&rt1308->params, params, sizeof(*params)); 317 318 ret = rt1308_clock_config(&slave->dev); 319 if (ret < 0) 320 dev_err(&slave->dev, "Invalid clk config"); 321 322 return ret; 323 } 324 325 static int rt1308_interrupt_callback(struct sdw_slave *slave, 326 struct sdw_slave_intr_status *status) 327 { 328 dev_dbg(&slave->dev, 329 "%s control_port_stat=%x", __func__, status->control_port); 330 331 return 0; 332 } 333 334 static int rt1308_classd_event(struct snd_soc_dapm_widget *w, 335 struct snd_kcontrol *kcontrol, int event) 336 { 337 struct snd_soc_component *component = 338 snd_soc_dapm_to_component(w->dapm); 339 struct rt1308_sdw_priv *rt1308 = 340 snd_soc_component_get_drvdata(component); 341 342 switch (event) { 343 case SND_SOC_DAPM_POST_PMU: 344 msleep(30); 345 snd_soc_component_update_bits(component, 346 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 347 0x3, 0x3); 348 msleep(40); 349 rt1308_apply_calib_params(rt1308); 350 break; 351 case SND_SOC_DAPM_PRE_PMD: 352 snd_soc_component_update_bits(component, 353 RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4), 354 0x3, 0); 355 usleep_range(150000, 200000); 356 break; 357 358 default: 359 break; 360 } 361 362 return 0; 363 } 364 365 static const char * const rt1308_rx_data_ch_select[] = { 366 "LR", 367 "LL", 368 "RL", 369 "RR", 370 }; 371 372 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, 373 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0, 374 rt1308_rx_data_ch_select); 375 376 static const struct snd_kcontrol_new rt1308_snd_controls[] = { 377 378 /* I2S Data Channel Selection */ 379 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum), 380 }; 381 382 static const struct snd_kcontrol_new rt1308_sto_dac_l = 383 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 384 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 385 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1); 386 387 static const struct snd_kcontrol_new rt1308_sto_dac_r = 388 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 389 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4), 390 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1); 391 392 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = { 393 /* Audio Interface */ 394 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 395 396 /* Supply Widgets */ 397 SND_SOC_DAPM_SUPPLY("MBIAS20U", 398 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0), 399 SND_SOC_DAPM_SUPPLY("ALDO", 400 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0), 401 SND_SOC_DAPM_SUPPLY("DBG", 402 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0), 403 SND_SOC_DAPM_SUPPLY("DACL", 404 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0), 405 SND_SOC_DAPM_SUPPLY("CLK25M", 406 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0), 407 SND_SOC_DAPM_SUPPLY("ADC_R", 408 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0), 409 SND_SOC_DAPM_SUPPLY("ADC_L", 410 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0), 411 SND_SOC_DAPM_SUPPLY("DAC Power", 412 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0), 413 414 SND_SOC_DAPM_SUPPLY("DLDO", 415 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0), 416 SND_SOC_DAPM_SUPPLY("VREF", 417 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0), 418 SND_SOC_DAPM_SUPPLY("MIXER_R", 419 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0), 420 SND_SOC_DAPM_SUPPLY("MIXER_L", 421 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0), 422 SND_SOC_DAPM_SUPPLY("MBIAS4U", 423 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0), 424 425 SND_SOC_DAPM_SUPPLY("PLL2_LDO", 426 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0), 427 SND_SOC_DAPM_SUPPLY("PLL2B", 428 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0), 429 SND_SOC_DAPM_SUPPLY("PLL2F", 430 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0), 431 SND_SOC_DAPM_SUPPLY("PLL2F2", 432 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0), 433 SND_SOC_DAPM_SUPPLY("PLL2B2", 434 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0), 435 436 /* Digital Interface */ 437 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 438 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l), 439 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r), 440 441 /* Output Lines */ 442 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 443 rt1308_classd_event, 444 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 445 SND_SOC_DAPM_OUTPUT("SPOL"), 446 SND_SOC_DAPM_OUTPUT("SPOR"), 447 }; 448 449 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = { 450 451 { "DAC", NULL, "AIF1RX" }, 452 453 { "DAC", NULL, "MBIAS20U" }, 454 { "DAC", NULL, "ALDO" }, 455 { "DAC", NULL, "DBG" }, 456 { "DAC", NULL, "DACL" }, 457 { "DAC", NULL, "CLK25M" }, 458 { "DAC", NULL, "ADC_R" }, 459 { "DAC", NULL, "ADC_L" }, 460 { "DAC", NULL, "DLDO" }, 461 { "DAC", NULL, "VREF" }, 462 { "DAC", NULL, "MIXER_R" }, 463 { "DAC", NULL, "MIXER_L" }, 464 { "DAC", NULL, "MBIAS4U" }, 465 { "DAC", NULL, "PLL2_LDO" }, 466 { "DAC", NULL, "PLL2B" }, 467 { "DAC", NULL, "PLL2F" }, 468 { "DAC", NULL, "PLL2F2" }, 469 { "DAC", NULL, "PLL2B2" }, 470 471 { "DAC L", "Switch", "DAC" }, 472 { "DAC R", "Switch", "DAC" }, 473 { "DAC L", NULL, "DAC Power" }, 474 { "DAC R", NULL, "DAC Power" }, 475 476 { "CLASS D", NULL, "DAC L" }, 477 { "CLASS D", NULL, "DAC R" }, 478 { "SPOL", NULL, "CLASS D" }, 479 { "SPOR", NULL, "CLASS D" }, 480 }; 481 482 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 483 int direction) 484 { 485 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 486 487 return 0; 488 } 489 490 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream, 491 struct snd_soc_dai *dai) 492 { 493 snd_soc_dai_set_dma_data(dai, substream, NULL); 494 } 495 496 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai, 497 unsigned int tx_mask, 498 unsigned int rx_mask, 499 int slots, int slot_width) 500 { 501 struct snd_soc_component *component = dai->component; 502 struct rt1308_sdw_priv *rt1308 = 503 snd_soc_component_get_drvdata(component); 504 505 if (tx_mask) 506 return -EINVAL; 507 508 if (slots > 2) 509 return -EINVAL; 510 511 rt1308->rx_mask = rx_mask; 512 rt1308->slots = slots; 513 /* slot_width is not used since it's irrelevant for SoundWire */ 514 515 return 0; 516 } 517 518 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream, 519 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 520 { 521 struct snd_soc_component *component = dai->component; 522 struct rt1308_sdw_priv *rt1308 = 523 snd_soc_component_get_drvdata(component); 524 struct sdw_stream_config stream_config = {0}; 525 struct sdw_port_config port_config = {0}; 526 struct sdw_stream_runtime *sdw_stream; 527 int retval; 528 529 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 530 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 531 532 if (!sdw_stream) 533 return -EINVAL; 534 535 if (!rt1308->sdw_slave) 536 return -EINVAL; 537 538 /* SoundWire specific configuration */ 539 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 540 541 /* port 1 for playback */ 542 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 543 port_config.num = 1; 544 else 545 return -EINVAL; 546 547 if (rt1308->slots) { 548 stream_config.ch_count = rt1308->slots; 549 port_config.ch_mask = rt1308->rx_mask; 550 } 551 552 retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config, 553 &port_config, 1, sdw_stream); 554 if (retval) { 555 dev_err(dai->dev, "Unable to configure port\n"); 556 return retval; 557 } 558 559 return retval; 560 } 561 562 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 563 struct snd_soc_dai *dai) 564 { 565 struct snd_soc_component *component = dai->component; 566 struct rt1308_sdw_priv *rt1308 = 567 snd_soc_component_get_drvdata(component); 568 struct sdw_stream_runtime *sdw_stream = 569 snd_soc_dai_get_dma_data(dai, substream); 570 571 if (!rt1308->sdw_slave) 572 return -EINVAL; 573 574 sdw_stream_remove_slave(rt1308->sdw_slave, sdw_stream); 575 return 0; 576 } 577 578 /* 579 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 580 * port_prep are not defined for now 581 */ 582 static const struct sdw_slave_ops rt1308_slave_ops = { 583 .read_prop = rt1308_read_prop, 584 .interrupt_callback = rt1308_interrupt_callback, 585 .update_status = rt1308_update_status, 586 .bus_config = rt1308_bus_config, 587 }; 588 589 static int rt1308_sdw_parse_dt(struct rt1308_sdw_priv *rt1308, struct device *dev) 590 { 591 int ret = 0; 592 593 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1308->bq_params_cnt); 594 if (rt1308->bq_params_cnt) { 595 rt1308->bq_params = devm_kzalloc(dev, rt1308->bq_params_cnt, GFP_KERNEL); 596 if (!rt1308->bq_params) { 597 dev_err(dev, "Could not allocate bq_params memory\n"); 598 ret = -ENOMEM; 599 } else { 600 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1308->bq_params, rt1308->bq_params_cnt); 601 if (ret < 0) 602 dev_err(dev, "Could not read list of realtek,bq-params\n"); 603 } 604 } 605 606 dev_dbg(dev, "bq_params_cnt=%d\n", rt1308->bq_params_cnt); 607 return ret; 608 } 609 610 static int rt1308_sdw_component_probe(struct snd_soc_component *component) 611 { 612 struct rt1308_sdw_priv *rt1308 = snd_soc_component_get_drvdata(component); 613 int ret; 614 615 rt1308->component = component; 616 rt1308_sdw_parse_dt(rt1308, &rt1308->sdw_slave->dev); 617 618 if (!rt1308->first_hw_init) 619 return 0; 620 621 ret = pm_runtime_resume(component->dev); 622 if (ret < 0 && ret != -EACCES) 623 return ret; 624 625 /* apply BQ params */ 626 rt1308_apply_bq_params(rt1308); 627 628 return 0; 629 } 630 631 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = { 632 .probe = rt1308_sdw_component_probe, 633 .controls = rt1308_snd_controls, 634 .num_controls = ARRAY_SIZE(rt1308_snd_controls), 635 .dapm_widgets = rt1308_dapm_widgets, 636 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets), 637 .dapm_routes = rt1308_dapm_routes, 638 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes), 639 .endianness = 1, 640 }; 641 642 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = { 643 .hw_params = rt1308_sdw_hw_params, 644 .hw_free = rt1308_sdw_pcm_hw_free, 645 .set_stream = rt1308_set_sdw_stream, 646 .shutdown = rt1308_sdw_shutdown, 647 .set_tdm_slot = rt1308_sdw_set_tdm_slot, 648 }; 649 650 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000 651 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 652 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 653 SNDRV_PCM_FMTBIT_S24_LE) 654 655 static struct snd_soc_dai_driver rt1308_sdw_dai[] = { 656 { 657 .name = "rt1308-aif", 658 .playback = { 659 .stream_name = "DP1 Playback", 660 .channels_min = 1, 661 .channels_max = 2, 662 .rates = RT1308_STEREO_RATES, 663 .formats = RT1308_FORMATS, 664 }, 665 .ops = &rt1308_aif_dai_ops, 666 }, 667 }; 668 669 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap, 670 struct sdw_slave *slave) 671 { 672 struct rt1308_sdw_priv *rt1308; 673 int ret; 674 675 rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL); 676 if (!rt1308) 677 return -ENOMEM; 678 679 dev_set_drvdata(dev, rt1308); 680 rt1308->sdw_slave = slave; 681 rt1308->regmap = regmap; 682 683 regcache_cache_only(rt1308->regmap, true); 684 685 /* 686 * Mark hw_init to false 687 * HW init will be performed when device reports present 688 */ 689 rt1308->hw_init = false; 690 rt1308->first_hw_init = false; 691 692 ret = devm_snd_soc_register_component(dev, 693 &soc_component_sdw_rt1308, 694 rt1308_sdw_dai, 695 ARRAY_SIZE(rt1308_sdw_dai)); 696 if (ret < 0) 697 return ret; 698 699 /* set autosuspend parameters */ 700 pm_runtime_set_autosuspend_delay(dev, 3000); 701 pm_runtime_use_autosuspend(dev); 702 703 /* make sure the device does not suspend immediately */ 704 pm_runtime_mark_last_busy(dev); 705 706 pm_runtime_enable(dev); 707 708 /* important note: the device is NOT tagged as 'active' and will remain 709 * 'suspended' until the hardware is enumerated/initialized. This is required 710 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 711 * fail with -EACCESS because of race conditions between card creation and enumeration 712 */ 713 714 dev_dbg(dev, "%s\n", __func__); 715 716 return 0; 717 } 718 719 static int rt1308_sdw_probe(struct sdw_slave *slave, 720 const struct sdw_device_id *id) 721 { 722 struct regmap *regmap; 723 724 /* Regmap Initialization */ 725 regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap); 726 if (IS_ERR(regmap)) 727 return PTR_ERR(regmap); 728 729 return rt1308_sdw_init(&slave->dev, regmap, slave); 730 } 731 732 static int rt1308_sdw_remove(struct sdw_slave *slave) 733 { 734 pm_runtime_disable(&slave->dev); 735 736 return 0; 737 } 738 739 static const struct sdw_device_id rt1308_id[] = { 740 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0), 741 {}, 742 }; 743 MODULE_DEVICE_TABLE(sdw, rt1308_id); 744 745 static int __maybe_unused rt1308_dev_suspend(struct device *dev) 746 { 747 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 748 749 if (!rt1308->hw_init) 750 return 0; 751 752 regcache_cache_only(rt1308->regmap, true); 753 754 return 0; 755 } 756 757 #define RT1308_PROBE_TIMEOUT 5000 758 759 static int __maybe_unused rt1308_dev_resume(struct device *dev) 760 { 761 struct sdw_slave *slave = dev_to_sdw_dev(dev); 762 struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev); 763 unsigned long time; 764 765 if (!rt1308->first_hw_init) 766 return 0; 767 768 if (!slave->unattach_request) 769 goto regmap_sync; 770 771 time = wait_for_completion_timeout(&slave->initialization_complete, 772 msecs_to_jiffies(RT1308_PROBE_TIMEOUT)); 773 if (!time) { 774 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 775 sdw_show_ping_status(slave->bus, true); 776 777 return -ETIMEDOUT; 778 } 779 780 regmap_sync: 781 slave->unattach_request = 0; 782 regcache_cache_only(rt1308->regmap, false); 783 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); 784 785 return 0; 786 } 787 788 static const struct dev_pm_ops rt1308_pm = { 789 SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume) 790 SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL) 791 }; 792 793 static struct sdw_driver rt1308_sdw_driver = { 794 .driver = { 795 .name = "rt1308", 796 .owner = THIS_MODULE, 797 .pm = &rt1308_pm, 798 }, 799 .probe = rt1308_sdw_probe, 800 .remove = rt1308_sdw_remove, 801 .ops = &rt1308_slave_ops, 802 .id_table = rt1308_id, 803 }; 804 module_sdw_driver(rt1308_sdw_driver); 805 806 MODULE_DESCRIPTION("ASoC RT1308 driver SDW"); 807 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 808 MODULE_LICENSE("GPL v2"); 809