1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1019.c -- RT1019 ALSA SoC audio amplifier driver 4 // Author: Jack Yu <jack.yu@realtek.com> 5 // 6 // Copyright(c) 2021 Realtek Semiconductor Corp. 7 // 8 // 9 10 #include <linux/acpi.h> 11 #include <linux/fs.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/regmap.h> 18 #include <linux/i2c.h> 19 #include <linux/platform_device.h> 20 #include <linux/firmware.h> 21 #include <linux/gpio.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt1019.h" 32 33 static const struct reg_default rt1019_reg[] = { 34 { 0x0000, 0x00 }, 35 { 0x0002, 0x55 }, 36 { 0x0003, 0x55 }, 37 { 0x0005, 0x54 }, 38 { 0x0006, 0x05 }, 39 { 0x0007, 0x01 }, 40 { 0x0008, 0x70 }, 41 { 0x0009, 0x28 }, 42 { 0x000a, 0x7f }, 43 { 0x0011, 0x04 }, 44 { 0x0013, 0x00 }, 45 { 0x0015, 0x00 }, 46 { 0x0017, 0x00 }, 47 { 0x0019, 0x30 }, 48 { 0x001b, 0x01 }, 49 { 0x001d, 0x18 }, 50 { 0x001f, 0x29 }, 51 { 0x0021, 0x09 }, 52 { 0x0023, 0x02 }, 53 { 0x0025, 0x00 }, 54 { 0x0026, 0x00 }, 55 { 0x0028, 0x03 }, 56 { 0x0053, 0x00 }, 57 { 0x0055, 0x00 }, 58 { 0x0056, 0x00 }, 59 { 0x0057, 0x00 }, 60 { 0x0058, 0x00 }, 61 { 0x005a, 0x00 }, 62 { 0x005c, 0x00 }, 63 { 0x005d, 0x00 }, 64 { 0x005e, 0x10 }, 65 { 0x005f, 0xec }, 66 { 0x0061, 0x10 }, 67 { 0x0062, 0x19 }, 68 { 0x0064, 0x00 }, 69 { 0x0066, 0x08 }, 70 { 0x0068, 0x00 }, 71 { 0x006a, 0x00 }, 72 { 0x006c, 0x00 }, 73 { 0x006e, 0x00 }, 74 { 0x0100, 0x80 }, 75 { 0x0100, 0x51 }, 76 { 0x0102, 0x23 }, 77 { 0x0102, 0x0f }, 78 { 0x0104, 0x6c }, 79 { 0x0105, 0xec }, 80 { 0x0106, 0x00 }, 81 { 0x0107, 0x00 }, 82 { 0x0108, 0x00 }, 83 { 0x0200, 0x40 }, 84 { 0x0201, 0x00 }, 85 { 0x0202, 0x00 }, 86 { 0x0203, 0x00 }, 87 { 0x0301, 0x02 }, 88 { 0x0302, 0xaa }, 89 { 0x0303, 0x2a }, 90 { 0x0304, 0x6a }, 91 { 0x0306, 0xb0 }, 92 { 0x0308, 0x48 }, 93 { 0x030a, 0x0a }, 94 { 0x030b, 0x4b }, 95 { 0x030d, 0x7d }, 96 { 0x030e, 0xef }, 97 { 0x030f, 0x5a }, 98 { 0x0311, 0x00 }, 99 { 0x0312, 0x3e }, 100 { 0x0313, 0x86 }, 101 { 0x0315, 0xa8 }, 102 { 0x0318, 0x1b }, 103 { 0x031a, 0x3d }, 104 { 0x031c, 0x40 }, 105 { 0x031d, 0x40 }, 106 { 0x031e, 0x30 }, 107 { 0x031f, 0xbb }, 108 { 0x0320, 0xa5 }, 109 { 0x0321, 0xa5 }, 110 { 0x0323, 0x5a }, 111 { 0x0324, 0xaa }, 112 { 0x0325, 0x80 }, 113 { 0x0326, 0xaa }, 114 { 0x0327, 0x66 }, 115 { 0x0328, 0x94 }, 116 { 0x0329, 0x00 }, 117 { 0x0330, 0x00 }, 118 { 0x0331, 0x30 }, 119 { 0x0332, 0x05 }, 120 { 0x0400, 0x03 }, 121 { 0x0401, 0x02 }, 122 { 0x0402, 0x01 }, 123 { 0x0403, 0x23 }, 124 { 0x0404, 0x45 }, 125 { 0x0405, 0x67 }, 126 { 0x0500, 0x80 }, 127 { 0x0501, 0x00 }, 128 { 0x0502, 0x00 }, 129 { 0x0503, 0x00 }, 130 { 0x0504, 0xff }, 131 { 0x0505, 0x24 }, 132 { 0x0600, 0x75 }, 133 { 0x0601, 0x41 }, 134 { 0x0602, 0x60 }, 135 { 0x0603, 0x7f }, 136 { 0x0604, 0x65 }, 137 { 0x0605, 0x43 }, 138 { 0x0606, 0x00 }, 139 { 0x0607, 0x00 }, 140 { 0x0608, 0x00 }, 141 { 0x0609, 0x00 }, 142 { 0x060a, 0x00 }, 143 { 0x060b, 0x00 }, 144 { 0x060c, 0x00 }, 145 { 0x060d, 0x00 }, 146 { 0x060e, 0x00 }, 147 { 0x060f, 0x00 }, 148 { 0x0700, 0x15 }, 149 { 0x0701, 0xc8 }, 150 { 0x0704, 0x02 }, 151 { 0x0705, 0x00 }, 152 { 0x0706, 0x00 }, 153 { 0x0707, 0x80 }, 154 { 0x0708, 0x08 }, 155 { 0x0709, 0x00 }, 156 { 0x0800, 0x00 }, 157 { 0x0801, 0x00 }, 158 { 0x0802, 0x09 }, 159 { 0x0803, 0x00 }, 160 { 0x0900, 0x87 }, 161 { 0x0a01, 0x99 }, 162 { 0x0a02, 0x40 }, 163 { 0x0a03, 0x10 }, 164 { 0x0b00, 0x50 }, 165 { 0x0b01, 0xc3 }, 166 { 0x0c00, 0x84 }, 167 { 0x0c01, 0x00 }, 168 { 0x0c02, 0xbb }, 169 { 0x0c03, 0x80 }, 170 { 0x0c04, 0x10 }, 171 { 0x0c05, 0x30 }, 172 { 0x0c06, 0x00 }, 173 { 0x0d00, 0x80 }, 174 { 0x0d01, 0xbb }, 175 { 0x0d02, 0x80 }, 176 { 0x0d03, 0x00 }, 177 { 0x0d04, 0x00 }, 178 { 0x0d05, 0x00 }, 179 { 0x0e00, 0x80 }, 180 { 0x0e01, 0xbb }, 181 { 0x0e02, 0x80 }, 182 { 0x0e03, 0x00 }, 183 { 0x0e04, 0x10 }, 184 { 0x0e05, 0x30 }, 185 { 0x0f00, 0x80 }, 186 { 0x0f01, 0xbb }, 187 { 0x0f02, 0x80 }, 188 { 0x0f03, 0x00 }, 189 { 0x0f04, 0x10 }, 190 { 0x0f05, 0x30 }, 191 { 0x0f06, 0x88 }, 192 { 0x0f07, 0x88 }, 193 { 0x0f08, 0x00 }, 194 { 0x0f09, 0x00 }, 195 }; 196 197 static bool rt1019_volatile_register(struct device *dev, unsigned int reg) 198 { 199 switch (reg) { 200 case RT1019_PWR_STRP_1: 201 case RT1019_PWR_STRP_2: 202 case RT1019_SIL_DET_GAT: 203 case RT1019_PHASE_SYNC: 204 case RT1019_STAT_MACH_2: 205 case RT1019_FS_DET_1: 206 case RT1019_FS_DET_2: 207 case RT1019_FS_DET_3: 208 case RT1019_FS_DET_4: 209 case RT1019_FS_DET_5: 210 case RT1019_FS_DET_6: 211 case RT1019_FS_DET_7: 212 case RT1019_ANA_READ: 213 case RT1019_VER_ID: 214 case RT1019_CUSTOM_ID: 215 case RT1019_VEND_ID_1: 216 case RT1019_VEND_ID_2: 217 case RT1019_DEV_ID_1: 218 case RT1019_DEV_ID_2: 219 case RT1019_CAL_TOP_3: 220 case RT1019_CAL_TOP_7: 221 case RT1019_CAL_TOP_17: 222 case RT1019_CAL_TOP_18: 223 case RT1019_CAL_TOP_19: 224 case RT1019_CAL_TOP_20: 225 case RT1019_CAL_TOP_21: 226 case RT1019_CAL_TOP_22: 227 case RT1019_MDRE_CTRL_2: 228 case RT1019_MDRE_CTRL_3: 229 case RT1019_MDRE_CTRL_4: 230 case RT1019_SIL_DET_2: 231 case RT1019_PWM_DC_DET_1: 232 case RT1019_PMC_8: 233 case RT1019_PMC_9: 234 case RT1019_SPKDRC_7: 235 case RT1019_HALF_FREQ_7: 236 case RT1019_CUR_CTRL_11: 237 case RT1019_CUR_CTRL_12: 238 case RT1019_CUR_CTRL_13: 239 return true; 240 241 default: 242 return false; 243 } 244 } 245 246 static bool rt1019_readable_register(struct device *dev, unsigned int reg) 247 { 248 switch (reg) { 249 case RT1019_RESET: 250 case RT1019_PAD_DRV_1: 251 case RT1019_PAD_DRV_2: 252 case RT1019_PAD_PULL_1: 253 case RT1019_PAD_PULL_2: 254 case RT1019_PAD_PULL_3: 255 case RT1019_I2C_CTRL_1: 256 case RT1019_I2C_CTRL_2: 257 case RT1019_I2C_CTRL_3: 258 case RT1019_IDS_CTRL: 259 case RT1019_ASEL_CTRL: 260 case RT1019_PLL_RESET: 261 case RT1019_PWR_STRP_1: 262 case RT1019_PWR_STRP_2: 263 case RT1019_BEEP_TONE: 264 case RT1019_SIL_DET_GAT: 265 case RT1019_CLASSD_TIME: 266 case RT1019_CLASSD_OCP: 267 case RT1019_PHASE_SYNC: 268 case RT1019_STAT_MACH_1: 269 case RT1019_STAT_MACH_2: 270 case RT1019_EFF_CTRL: 271 case RT1019_FS_DET_1: 272 case RT1019_FS_DET_2: 273 case RT1019_FS_DET_3: 274 case RT1019_FS_DET_4: 275 case RT1019_FS_DET_5: 276 case RT1019_FS_DET_6: 277 case RT1019_FS_DET_7: 278 case RT1019_ANA_CTRL: 279 case RT1019_DUMMY_A: 280 case RT1019_DUMMY_B: 281 case RT1019_DUMMY_C: 282 case RT1019_DUMMY_D: 283 case RT1019_ANA_READ: 284 case RT1019_VER_ID: 285 case RT1019_CUSTOM_ID: 286 case RT1019_VEND_ID_1: 287 case RT1019_VEND_ID_2: 288 case RT1019_DEV_ID_1: 289 case RT1019_DEV_ID_2: 290 case RT1019_TEST_PAD: 291 case RT1019_SDB_CTRL: 292 case RT1019_TEST_CTRL_1: 293 case RT1019_TEST_CTRL_2: 294 case RT1019_TEST_CTRL_3: 295 case RT1019_SCAN_MODE: 296 case RT1019_CLK_TREE_1: 297 case RT1019_CLK_TREE_2: 298 case RT1019_CLK_TREE_3: 299 case RT1019_CLK_TREE_4: 300 case RT1019_CLK_TREE_5: 301 case RT1019_CLK_TREE_6: 302 case RT1019_CLK_TREE_7: 303 case RT1019_CLK_TREE_8: 304 case RT1019_CLK_TREE_9: 305 case RT1019_ASRC_1: 306 case RT1019_ASRC_2: 307 case RT1019_ASRC_3: 308 case RT1019_ASRC_4: 309 case RT1019_SYS_CLK: 310 case RT1019_BIAS_CUR_1: 311 case RT1019_BIAS_CUR_2: 312 case RT1019_BIAS_CUR_3: 313 case RT1019_BIAS_CUR_4: 314 case RT1019_CHOP_CLK_DAC: 315 case RT1019_CHOP_CLK_ADC: 316 case RT1019_LDO_CTRL_1: 317 case RT1019_LDO_CTRL_2: 318 case RT1019_PM_ANA_1: 319 case RT1019_PM_ANA_2: 320 case RT1019_PM_ANA_3: 321 case RT1019_PLL_1: 322 case RT1019_PLL_2: 323 case RT1019_PLL_3: 324 case RT1019_PLL_INT_1: 325 case RT1019_PLL_INT_3: 326 case RT1019_MIXER: 327 case RT1019_CLD_OUT_1: 328 case RT1019_CLD_OUT_2: 329 case RT1019_CLD_OUT_3: 330 case RT1019_CLD_OUT_4: 331 case RT1019_CLD_OUT_5: 332 case RT1019_CLD_OUT_6: 333 case RT1019_CLS_INT_REG_1: 334 case RT1019_CLS_INT_REG_2: 335 case RT1019_CLS_INT_REG_3: 336 case RT1019_CLS_INT_REG_4: 337 case RT1019_CLS_INT_REG_5: 338 case RT1019_CLS_INT_REG_6: 339 case RT1019_CLS_INT_REG_7: 340 case RT1019_CLS_INT_REG_8: 341 case RT1019_CLS_INT_REG_9: 342 case RT1019_CLS_INT_REG_10: 343 case RT1019_TDM_1: 344 case RT1019_TDM_2: 345 case RT1019_TDM_3: 346 case RT1019_TDM_4: 347 case RT1019_TDM_5: 348 case RT1019_TDM_6: 349 case RT1019_DVOL_1: 350 case RT1019_DVOL_2: 351 case RT1019_DVOL_3: 352 case RT1019_DVOL_4: 353 case RT1019_DMIX_MONO_1: 354 case RT1019_DMIX_MONO_2: 355 case RT1019_CAL_TOP_1: 356 case RT1019_CAL_TOP_2: 357 case RT1019_CAL_TOP_3: 358 case RT1019_CAL_TOP_4: 359 case RT1019_CAL_TOP_5: 360 case RT1019_CAL_TOP_6: 361 case RT1019_CAL_TOP_7: 362 case RT1019_CAL_TOP_8: 363 case RT1019_CAL_TOP_9: 364 case RT1019_CAL_TOP_10: 365 case RT1019_CAL_TOP_11: 366 case RT1019_CAL_TOP_12: 367 case RT1019_CAL_TOP_13: 368 case RT1019_CAL_TOP_14: 369 case RT1019_CAL_TOP_15: 370 case RT1019_CAL_TOP_16: 371 case RT1019_CAL_TOP_17: 372 case RT1019_CAL_TOP_18: 373 case RT1019_CAL_TOP_19: 374 case RT1019_CAL_TOP_20: 375 case RT1019_CAL_TOP_21: 376 case RT1019_CAL_TOP_22: 377 case RT1019_MDRE_CTRL_1: 378 case RT1019_MDRE_CTRL_2: 379 case RT1019_MDRE_CTRL_3: 380 case RT1019_MDRE_CTRL_4: 381 case RT1019_MDRE_CTRL_5: 382 case RT1019_MDRE_CTRL_6: 383 case RT1019_MDRE_CTRL_7: 384 case RT1019_MDRE_CTRL_8: 385 case RT1019_MDRE_CTRL_9: 386 case RT1019_MDRE_CTRL_10: 387 case RT1019_SCC_CTRL_1: 388 case RT1019_SCC_CTRL_2: 389 case RT1019_SCC_CTRL_3: 390 case RT1019_SCC_DUMMY: 391 case RT1019_SIL_DET_1: 392 case RT1019_SIL_DET_2: 393 case RT1019_PWM_DC_DET_1: 394 case RT1019_PWM_DC_DET_2: 395 case RT1019_PWM_DC_DET_3: 396 case RT1019_PWM_DC_DET_4: 397 case RT1019_BEEP_1: 398 case RT1019_BEEP_2: 399 case RT1019_PMC_1: 400 case RT1019_PMC_2: 401 case RT1019_PMC_3: 402 case RT1019_PMC_4: 403 case RT1019_PMC_5: 404 case RT1019_PMC_6: 405 case RT1019_PMC_7: 406 case RT1019_PMC_8: 407 case RT1019_PMC_9: 408 case RT1019_SPKDRC_1: 409 case RT1019_SPKDRC_2: 410 case RT1019_SPKDRC_3: 411 case RT1019_SPKDRC_4: 412 case RT1019_SPKDRC_5: 413 case RT1019_SPKDRC_6: 414 case RT1019_SPKDRC_7: 415 case RT1019_HALF_FREQ_1: 416 case RT1019_HALF_FREQ_2: 417 case RT1019_HALF_FREQ_3: 418 case RT1019_HALF_FREQ_4: 419 case RT1019_HALF_FREQ_5: 420 case RT1019_HALF_FREQ_6: 421 case RT1019_HALF_FREQ_7: 422 case RT1019_CUR_CTRL_1: 423 case RT1019_CUR_CTRL_2: 424 case RT1019_CUR_CTRL_3: 425 case RT1019_CUR_CTRL_4: 426 case RT1019_CUR_CTRL_5: 427 case RT1019_CUR_CTRL_6: 428 case RT1019_CUR_CTRL_7: 429 case RT1019_CUR_CTRL_8: 430 case RT1019_CUR_CTRL_9: 431 case RT1019_CUR_CTRL_10: 432 case RT1019_CUR_CTRL_11: 433 case RT1019_CUR_CTRL_12: 434 case RT1019_CUR_CTRL_13: 435 return true; 436 default: 437 return false; 438 } 439 } 440 441 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0); 442 443 static const char * const rt1019_din_source_select[] = { 444 "Left", 445 "Right", 446 "Left + Right average", 447 }; 448 449 static SOC_ENUM_SINGLE_DECL(rt1019_mono_lr_sel, RT1019_IDS_CTRL, 0, 450 rt1019_din_source_select); 451 452 static const struct snd_kcontrol_new rt1019_snd_controls[] = { 453 SOC_SINGLE_TLV("DAC Playback Volume", RT1019_DMIX_MONO_1, 0, 454 127, 0, dac_vol_tlv), 455 SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel), 456 }; 457 458 static int r1019_dac_event(struct snd_soc_dapm_widget *w, 459 struct snd_kcontrol *kcontrol, int event) 460 { 461 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 462 463 switch (event) { 464 case SND_SOC_DAPM_PRE_PMU: 465 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xb); 466 break; 467 case SND_SOC_DAPM_POST_PMD: 468 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa); 469 break; 470 default: 471 break; 472 } 473 474 return 0; 475 } 476 477 static const struct snd_soc_dapm_widget rt1019_dapm_widgets[] = { 478 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 479 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, 480 r1019_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 481 SND_SOC_DAPM_OUTPUT("SPO"), 482 }; 483 484 static const struct snd_soc_dapm_route rt1019_dapm_routes[] = { 485 { "DAC", NULL, "AIFRX" }, 486 { "SPO", NULL, "DAC" }, 487 }; 488 489 static int rt1019_hw_params(struct snd_pcm_substream *substream, 490 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 491 { 492 struct snd_soc_component *component = dai->component; 493 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 494 int pre_div, bclk_ms, frame_size; 495 unsigned int val_len = 0, sys_div_da_filter = 0; 496 unsigned int sys_dac_osr = 0, sys_fifo_clk = 0; 497 unsigned int sys_clk_cal = 0, sys_asrc_in = 0; 498 499 rt1019->lrck = params_rate(params); 500 pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck); 501 if (pre_div < 0) { 502 dev_err(component->dev, "Unsupported clock setting\n"); 503 return -EINVAL; 504 } 505 506 frame_size = snd_soc_params_to_frame_size(params); 507 if (frame_size < 0) { 508 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 509 return -EINVAL; 510 } 511 512 bclk_ms = frame_size > 32; 513 rt1019->bclk = rt1019->lrck * (32 << bclk_ms); 514 515 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 516 rt1019->bclk, rt1019->lrck); 517 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 518 bclk_ms, pre_div, dai->id); 519 520 switch (pre_div) { 521 case 0: 522 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV1; 523 sys_dac_osr = RT1019_SYS_DA_OSR_DIV1; 524 sys_asrc_in = RT1019_ASRC_256FS_DIV1; 525 sys_fifo_clk = RT1019_SEL_FIFO_DIV1; 526 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV1; 527 break; 528 case 1: 529 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV2; 530 sys_dac_osr = RT1019_SYS_DA_OSR_DIV2; 531 sys_asrc_in = RT1019_ASRC_256FS_DIV2; 532 sys_fifo_clk = RT1019_SEL_FIFO_DIV2; 533 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV2; 534 break; 535 case 3: 536 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV4; 537 sys_dac_osr = RT1019_SYS_DA_OSR_DIV4; 538 sys_asrc_in = RT1019_ASRC_256FS_DIV4; 539 sys_fifo_clk = RT1019_SEL_FIFO_DIV4; 540 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV4; 541 break; 542 default: 543 return -EINVAL; 544 } 545 546 switch (params_width(params)) { 547 case 16: 548 break; 549 case 20: 550 val_len = RT1019_I2S_DL_20; 551 break; 552 case 24: 553 val_len = RT1019_I2S_DL_24; 554 break; 555 case 32: 556 val_len = RT1019_I2S_DL_32; 557 break; 558 case 8: 559 val_len = RT1019_I2S_DL_8; 560 break; 561 default: 562 return -EINVAL; 563 } 564 565 snd_soc_component_update_bits(component, RT1019_TDM_2, RT1019_I2S_DL_MASK, 566 val_len); 567 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 568 RT1019_SEL_FIFO_MASK, sys_fifo_clk); 569 snd_soc_component_update_bits(component, RT1019_CLK_TREE_2, 570 RT1019_SYS_DIV_DA_FIL_MASK | RT1019_SYS_DA_OSR_MASK | 571 RT1019_ASRC_256FS_MASK, sys_div_da_filter | sys_dac_osr | 572 sys_asrc_in); 573 snd_soc_component_update_bits(component, RT1019_CLK_TREE_3, 574 RT1019_SEL_CLK_CAL_MASK, sys_clk_cal); 575 576 return 0; 577 } 578 579 static int rt1019_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 580 { 581 struct snd_soc_component *component = dai->component; 582 unsigned int reg_val = 0, reg_val2 = 0; 583 584 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 585 case SND_SOC_DAIFMT_NB_NF: 586 break; 587 case SND_SOC_DAIFMT_IB_NF: 588 reg_val2 |= RT1019_TDM_BCLK_INV; 589 break; 590 default: 591 return -EINVAL; 592 } 593 594 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 595 case SND_SOC_DAIFMT_I2S: 596 break; 597 598 case SND_SOC_DAIFMT_LEFT_J: 599 reg_val |= RT1019_I2S_DF_LEFT; 600 break; 601 602 case SND_SOC_DAIFMT_DSP_A: 603 reg_val |= RT1019_I2S_DF_PCM_A_R; 604 break; 605 606 case SND_SOC_DAIFMT_DSP_B: 607 reg_val |= RT1019_I2S_DF_PCM_B_R; 608 break; 609 610 default: 611 return -EINVAL; 612 } 613 614 snd_soc_component_update_bits(component, RT1019_TDM_2, 615 RT1019_I2S_DF_MASK, reg_val); 616 snd_soc_component_update_bits(component, RT1019_TDM_1, 617 RT1019_TDM_BCLK_MASK, reg_val2); 618 619 return 0; 620 } 621 622 static int rt1019_set_dai_sysclk(struct snd_soc_dai *dai, 623 int clk_id, unsigned int freq, int dir) 624 { 625 struct snd_soc_component *component = dai->component; 626 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 627 unsigned int reg_val = 0; 628 629 if (freq == rt1019->sysclk && clk_id == rt1019->sysclk_src) 630 return 0; 631 632 switch (clk_id) { 633 case RT1019_SCLK_S_BCLK: 634 reg_val |= RT1019_CLK_SYS_PRE_SEL_BCLK; 635 break; 636 637 case RT1019_SCLK_S_PLL: 638 reg_val |= RT1019_CLK_SYS_PRE_SEL_PLL; 639 break; 640 641 default: 642 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 643 return -EINVAL; 644 } 645 646 rt1019->sysclk = freq; 647 rt1019->sysclk_src = clk_id; 648 649 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 650 651 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 652 RT1019_CLK_SYS_PRE_SEL_MASK, reg_val); 653 654 return 0; 655 } 656 657 static int rt1019_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 658 unsigned int freq_in, unsigned int freq_out) 659 { 660 struct snd_soc_component *component = dai->component; 661 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 662 struct rl6231_pll_code pll_code; 663 int ret; 664 665 if (!freq_in || !freq_out) { 666 dev_dbg(component->dev, "PLL disabled\n"); 667 rt1019->pll_in = 0; 668 rt1019->pll_out = 0; 669 return 0; 670 } 671 672 if (source == rt1019->pll_src && freq_in == rt1019->pll_in && 673 freq_out == rt1019->pll_out) 674 return 0; 675 676 switch (source) { 677 case RT1019_PLL_S_BCLK: 678 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 679 RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_BCLK); 680 break; 681 682 case RT1019_PLL_S_RC25M: 683 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1, 684 RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_RC); 685 break; 686 687 default: 688 dev_err(component->dev, "Unknown PLL source %d\n", source); 689 return -EINVAL; 690 } 691 692 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 693 if (ret < 0) { 694 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 695 return ret; 696 } 697 698 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 699 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 700 pll_code.n_code, pll_code.k_code); 701 702 snd_soc_component_update_bits(component, RT1019_PWR_STRP_2, 703 RT1019_AUTO_BITS_SEL_MASK | RT1019_AUTO_CLK_SEL_MASK, 704 RT1019_AUTO_BITS_SEL_MANU | RT1019_AUTO_CLK_SEL_MANU); 705 snd_soc_component_update_bits(component, RT1019_PLL_1, 706 RT1019_PLL_M_MASK | RT1019_PLL_M_BP_MASK | RT1019_PLL_Q_8_8_MASK, 707 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1019_PLL_M_SFT | 708 pll_code.m_bp << RT1019_PLL_M_BP_SFT | 709 ((pll_code.n_code >> 8) & RT1019_PLL_Q_8_8_MASK)); 710 snd_soc_component_update_bits(component, RT1019_PLL_2, 711 RT1019_PLL_Q_7_0_MASK, pll_code.n_code & RT1019_PLL_Q_7_0_MASK); 712 snd_soc_component_update_bits(component, RT1019_PLL_3, 713 RT1019_PLL_K_MASK, pll_code.k_code); 714 715 rt1019->pll_in = freq_in; 716 rt1019->pll_out = freq_out; 717 rt1019->pll_src = source; 718 719 return 0; 720 } 721 722 static int rt1019_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 723 unsigned int rx_mask, int slots, int slot_width) 724 { 725 struct snd_soc_component *component = dai->component; 726 unsigned int val = 0, rx_slotnum; 727 int ret = 0, first_bit; 728 729 switch (slots) { 730 case 4: 731 val |= RT1019_I2S_TX_4CH; 732 break; 733 case 6: 734 val |= RT1019_I2S_TX_6CH; 735 break; 736 case 8: 737 val |= RT1019_I2S_TX_8CH; 738 break; 739 case 2: 740 break; 741 default: 742 return -EINVAL; 743 } 744 745 switch (slot_width) { 746 case 20: 747 val |= RT1019_I2S_DL_20; 748 break; 749 case 24: 750 val |= RT1019_I2S_DL_24; 751 break; 752 case 32: 753 val |= RT1019_I2S_DL_32; 754 break; 755 case 8: 756 val |= RT1019_I2S_DL_8; 757 break; 758 case 16: 759 break; 760 default: 761 return -EINVAL; 762 } 763 764 /* Rx slot configuration */ 765 rx_slotnum = hweight_long(rx_mask); 766 if (rx_slotnum != 1) { 767 ret = -EINVAL; 768 dev_err(component->dev, "too many rx slots or zero slot\n"); 769 goto _set_tdm_err_; 770 } 771 /* This is an assumption that the system sends stereo audio to the 772 * amplifier typically. And the stereo audio is placed in slot 0/2/4/6 773 * as the starting slot. The users could select the channel from 774 * L/R/L+R by "Mono LR Select" control. 775 */ 776 first_bit = __ffs(rx_mask); 777 switch (first_bit) { 778 case 0: 779 case 2: 780 case 4: 781 case 6: 782 snd_soc_component_update_bits(component, 783 RT1019_TDM_3, 784 RT1019_TDM_I2S_TX_L_DAC1_1_MASK | 785 RT1019_TDM_I2S_TX_R_DAC1_1_MASK, 786 (first_bit << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) | 787 ((first_bit + 1) << RT1019_TDM_I2S_TX_R_DAC1_1_SFT)); 788 break; 789 case 1: 790 case 3: 791 case 5: 792 case 7: 793 snd_soc_component_update_bits(component, 794 RT1019_TDM_3, 795 RT1019_TDM_I2S_TX_L_DAC1_1_MASK | 796 RT1019_TDM_I2S_TX_R_DAC1_1_MASK, 797 ((first_bit - 1) << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) | 798 (first_bit << RT1019_TDM_I2S_TX_R_DAC1_1_SFT)); 799 break; 800 default: 801 ret = -EINVAL; 802 goto _set_tdm_err_; 803 } 804 805 snd_soc_component_update_bits(component, RT1019_TDM_2, 806 RT1019_I2S_CH_TX_MASK | RT1019_I2S_DF_MASK, val); 807 808 _set_tdm_err_: 809 return ret; 810 } 811 812 static int rt1019_probe(struct snd_soc_component *component) 813 { 814 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component); 815 816 rt1019->component = component; 817 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa); 818 819 return 0; 820 } 821 822 #define RT1019_STEREO_RATES SNDRV_PCM_RATE_8000_192000 823 #define RT1019_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 824 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 825 826 static const struct snd_soc_dai_ops rt1019_aif_dai_ops = { 827 .hw_params = rt1019_hw_params, 828 .set_fmt = rt1019_set_dai_fmt, 829 .set_sysclk = rt1019_set_dai_sysclk, 830 .set_pll = rt1019_set_dai_pll, 831 .set_tdm_slot = rt1019_set_tdm_slot, 832 }; 833 834 static struct snd_soc_dai_driver rt1019_dai[] = { 835 { 836 .name = "rt1019-aif", 837 .id = 0, 838 .playback = { 839 .stream_name = "AIF Playback", 840 .channels_min = 1, 841 .channels_max = 2, 842 .rates = RT1019_STEREO_RATES, 843 .formats = RT1019_FORMATS, 844 }, 845 .ops = &rt1019_aif_dai_ops, 846 } 847 }; 848 849 static const struct snd_soc_component_driver soc_component_dev_rt1019 = { 850 .probe = rt1019_probe, 851 .controls = rt1019_snd_controls, 852 .num_controls = ARRAY_SIZE(rt1019_snd_controls), 853 .dapm_widgets = rt1019_dapm_widgets, 854 .num_dapm_widgets = ARRAY_SIZE(rt1019_dapm_widgets), 855 .dapm_routes = rt1019_dapm_routes, 856 .num_dapm_routes = ARRAY_SIZE(rt1019_dapm_routes), 857 }; 858 859 static const struct regmap_config rt1019_regmap = { 860 .reg_bits = 16, 861 .val_bits = 8, 862 .use_single_read = true, 863 .use_single_write = true, 864 .max_register = RT1019_CUR_CTRL_13, 865 .volatile_reg = rt1019_volatile_register, 866 .readable_reg = rt1019_readable_register, 867 .cache_type = REGCACHE_RBTREE, 868 .reg_defaults = rt1019_reg, 869 .num_reg_defaults = ARRAY_SIZE(rt1019_reg), 870 }; 871 872 static const struct i2c_device_id rt1019_i2c_id[] = { 873 { "rt1019", 0 }, 874 { } 875 }; 876 MODULE_DEVICE_TABLE(i2c, rt1019_i2c_id); 877 878 static const struct of_device_id rt1019_of_match[] = { 879 { .compatible = "realtek,rt1019", }, 880 {}, 881 }; 882 MODULE_DEVICE_TABLE(of, rt1019_of_match); 883 884 #ifdef CONFIG_ACPI 885 static const struct acpi_device_id rt1019_acpi_match[] = { 886 { "10EC1019", 0}, 887 { }, 888 }; 889 MODULE_DEVICE_TABLE(acpi, rt1019_acpi_match); 890 #endif 891 892 static int rt1019_i2c_probe(struct i2c_client *i2c, 893 const struct i2c_device_id *id) 894 { 895 struct rt1019_priv *rt1019; 896 int ret; 897 unsigned int val, val2, dev_id; 898 899 rt1019 = devm_kzalloc(&i2c->dev, sizeof(struct rt1019_priv), 900 GFP_KERNEL); 901 if (!rt1019) 902 return -ENOMEM; 903 904 i2c_set_clientdata(i2c, rt1019); 905 906 rt1019->regmap = devm_regmap_init_i2c(i2c, &rt1019_regmap); 907 if (IS_ERR(rt1019->regmap)) { 908 ret = PTR_ERR(rt1019->regmap); 909 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 910 ret); 911 return ret; 912 } 913 914 regmap_read(rt1019->regmap, RT1019_DEV_ID_1, &val); 915 regmap_read(rt1019->regmap, RT1019_DEV_ID_2, &val2); 916 dev_id = val << 8 | val2; 917 if (dev_id != RT1019_DEVICE_ID_VAL && dev_id != RT1019_DEVICE_ID_VAL2) { 918 dev_err(&i2c->dev, 919 "Device with ID register 0x%x is not rt1019\n", dev_id); 920 return -ENODEV; 921 } 922 923 return devm_snd_soc_register_component(&i2c->dev, 924 &soc_component_dev_rt1019, rt1019_dai, ARRAY_SIZE(rt1019_dai)); 925 } 926 927 static struct i2c_driver rt1019_i2c_driver = { 928 .driver = { 929 .name = "rt1019", 930 .of_match_table = of_match_ptr(rt1019_of_match), 931 .acpi_match_table = ACPI_PTR(rt1019_acpi_match), 932 }, 933 .probe = rt1019_i2c_probe, 934 .id_table = rt1019_i2c_id, 935 }; 936 module_i2c_driver(rt1019_i2c_driver); 937 938 MODULE_DESCRIPTION("ASoC RT1019 driver"); 939 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 940 MODULE_LICENSE("GPL v2"); 941