1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1017-sdca-sdw.c -- rt1017 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2023 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <sound/core.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <sound/soc.h> 17 #include <sound/soc-dapm.h> 18 #include <sound/initval.h> 19 #include <sound/tlv.h> 20 21 #include "rt1017-sdca-sdw.h" 22 23 static bool rt1017_sdca_readable_register(struct device *dev, unsigned int reg) 24 { 25 switch (reg) { 26 case 0x2f55: 27 case 0x3206: 28 case 0xc000: 29 case 0xc001: 30 case 0xc022: 31 case 0xc030: 32 case 0xc104: 33 case 0xc10b: 34 case 0xc10c: 35 case 0xc110: 36 case 0xc112: 37 case 0xc300: 38 case 0xc301: 39 case 0xc318: 40 case 0xc325 ... 0xc328: 41 case 0xc331: 42 case 0xc340: 43 case 0xc350 ... 0xc351: 44 case 0xc500: 45 case 0xc502: 46 case 0xc504: 47 case 0xc507: 48 case 0xc509: 49 case 0xc510: 50 case 0xc512: 51 case 0xc518: 52 case 0xc51b: 53 case 0xc51d: 54 case 0xc520: 55 case 0xc540 ... 0xc542: 56 case 0xc550 ... 0xc552: 57 case 0xc600: 58 case 0xc602: 59 case 0xc612: 60 case 0xc622: 61 case 0xc632: 62 case 0xc642: 63 case 0xc651: 64 case 0xca00: 65 case 0xca09 ... 0xca0c: 66 case 0xca0e ... 0xca0f: 67 case 0xca10 ... 0xca11: 68 case 0xca16 ... 0xca17: 69 case 0xcb00: 70 case 0xcc00: 71 case 0xcc02: 72 case 0xd017: 73 case 0xd01a ... 0xd01c: 74 case 0xd101: 75 case 0xd20c: 76 case 0xd300: 77 case 0xd370: 78 case 0xd500: 79 case 0xd545 ... 0xd548: 80 case 0xd5a5 ... 0xd5a8: 81 case 0xd5aa ... 0xd5ad: 82 case 0xda04 ... 0xda07: 83 case 0xda09 ... 0xda0a: 84 case 0xda0c ... 0xda0f: 85 case 0xda11 ... 0xda14: 86 case 0xda16 ... 0xda19: 87 case 0xdab6 ... 0xdabb: 88 case 0xdb09 ... 0xdb0a: 89 case 0xdb14: 90 91 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_UDMPU21, 92 RT1017_SDCA_CTL_UDMPU_CLUSTER, 0): 93 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_FU, 94 RT1017_SDCA_CTL_FU_MUTE, 0x01): 95 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_XU22, 96 RT1017_SDCA_CTL_BYPASS, 0): 97 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_SAPU29, 98 RT1017_SDCA_CTL_PROT_STAT, 0): 99 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_CS21, 100 RT1017_SDCA_CTL_FS_INDEX, 0): 101 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23, 102 RT1017_SDCA_CTL_REQ_POWER_STATE, 0): 103 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE22, 104 RT1017_SDCA_CTL_REQ_POWER_STATE, 0): 105 return true; 106 default: 107 return false; 108 } 109 } 110 111 static bool rt1017_sdca_volatile_register(struct device *dev, unsigned int reg) 112 { 113 switch (reg) { 114 case 0x2f55: 115 case 0xc000: 116 case 0xc022: 117 case 0xc351: 118 case 0xc518: 119 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_SAPU29, 120 RT1017_SDCA_CTL_PROT_STAT, 0): 121 return true; 122 default: 123 return false; 124 } 125 } 126 127 static const struct reg_sequence rt1017_blind_write[] = { 128 { 0xc001, 0x43 }, 129 { 0x2f55, 0x02 }, 130 { 0x3206, 0x80 }, 131 { 0x005f, 0x7f }, 132 { 0xd101, 0xa0 }, 133 { 0xc112, 0xc0 }, 134 { 0xc104, 0xaa }, 135 { 0xc110, 0x59 }, 136 { 0xc112, 0xc0 }, 137 { 0xc340, 0x80 }, 138 { 0xd017, 0x2c }, 139 { 0xd01a, 0xc8 }, 140 { 0xd01b, 0xcf }, 141 { 0xd01c, 0x0c }, 142 { 0xd20c, 0x14 }, 143 { 0xdb09, 0x0f }, 144 { 0xdb0a, 0x7f }, 145 { 0xdb14, 0x03 }, 146 { 0xcb00, 0x31 }, 147 { 0xc318, 0x44 }, 148 { 0xc325, 0xce }, 149 { 0xc326, 0x13 }, 150 { 0xc327, 0x5f }, 151 { 0xc328, 0xf3 }, 152 { 0xc350, 0xe1 }, 153 { 0xc351, 0x88 }, 154 { 0xc030, 0x14 }, 155 { 0xc331, 0xf2 }, 156 { 0xc551, 0x0f }, 157 { 0xc552, 0xff }, 158 { 0xc651, 0xc0 }, 159 { 0xc550, 0xd0 }, 160 { 0xc612, 0x00 }, 161 { 0xc622, 0x00 }, 162 { 0xc632, 0x00 }, 163 { 0xc642, 0x00 }, 164 { 0xc602, 0xf0 }, 165 { 0xc600, 0xd0 }, 166 { 0xcc02, 0x78 }, 167 { 0xcc00, 0x90 }, 168 { 0xc300, 0x3f }, 169 { 0xc301, 0x1d }, 170 { 0xc10b, 0x2e }, 171 { 0xc10c, 0x36 }, 172 173 { 0xd5a5, 0x00 }, 174 { 0xd5a6, 0x6a }, 175 { 0xd5a7, 0xaa }, 176 { 0xd5a8, 0xaa }, 177 { 0xd5aa, 0x00 }, 178 { 0xd5ab, 0x16 }, 179 { 0xd5ac, 0xdb }, 180 { 0xd5ad, 0x6d }, 181 { 0xd545, 0x09 }, 182 { 0xd546, 0x30 }, 183 { 0xd547, 0xf0 }, 184 { 0xd548, 0xf0 }, 185 { 0xd500, 0x20 }, 186 { 0xc504, 0x3f }, 187 { 0xc540, 0x00 }, 188 { 0xc541, 0x0a }, 189 { 0xc542, 0x1a }, 190 { 0xc512, 0x00 }, 191 { 0xc520, 0x40 }, 192 { 0xc51b, 0x7f }, 193 { 0xc51d, 0x0f }, 194 { 0xc500, 0x40 }, 195 { 0xc502, 0xde }, 196 { 0xc507, 0x05 }, 197 { 0xc509, 0x05 }, 198 { 0xc510, 0x40 }, 199 { 0xc518, 0xc0 }, 200 { 0xc500, 0xc0 }, 201 202 { 0xda0c, 0x00 }, 203 { 0xda0d, 0x0b }, 204 { 0xda0e, 0x55 }, 205 { 0xda0f, 0x55 }, 206 { 0xda04, 0x00 }, 207 { 0xda05, 0x51 }, 208 { 0xda06, 0xeb }, 209 { 0xda07, 0x85 }, 210 { 0xca16, 0x0f }, 211 { 0xca17, 0x00 }, 212 { 0xda09, 0x5d }, 213 { 0xda0a, 0xc0 }, 214 { 0xda11, 0x26 }, 215 { 0xda12, 0x66 }, 216 { 0xda13, 0x66 }, 217 { 0xda14, 0x66 }, 218 { 0xda16, 0x79 }, 219 { 0xda17, 0x99 }, 220 { 0xda18, 0x99 }, 221 { 0xda19, 0x99 }, 222 { 0xca09, 0x00 }, 223 { 0xca0a, 0x07 }, 224 { 0xca0b, 0x89 }, 225 { 0xca0c, 0x61 }, 226 { 0xca0e, 0x00 }, 227 { 0xca0f, 0x03 }, 228 { 0xca10, 0xc4 }, 229 { 0xca11, 0xb0 }, 230 { 0xdab6, 0x00 }, 231 { 0xdab7, 0x01 }, 232 { 0xdab8, 0x00 }, 233 { 0xdab9, 0x00 }, 234 { 0xdaba, 0x00 }, 235 { 0xdabb, 0x00 }, 236 { 0xd017, 0x0e }, 237 { 0xca00, 0xcd }, 238 { 0xc022, 0x84 }, 239 }; 240 241 #define RT1017_MAX_REG_NUM 0x4108ffff 242 243 static const struct regmap_config rt1017_sdca_regmap = { 244 .reg_bits = 32, 245 .val_bits = 8, 246 .readable_reg = rt1017_sdca_readable_register, 247 .volatile_reg = rt1017_sdca_volatile_register, 248 .max_register = RT1017_MAX_REG_NUM, 249 .reg_defaults = rt1017_sdca_reg_defaults, 250 .num_reg_defaults = ARRAY_SIZE(rt1017_sdca_reg_defaults), 251 .cache_type = REGCACHE_MAPLE, 252 .use_single_read = true, 253 .use_single_write = true, 254 }; 255 256 static int rt1017_sdca_read_prop(struct sdw_slave *slave) 257 { 258 struct sdw_slave_prop *prop = &slave->prop; 259 int nval; 260 int i, j; 261 u32 bit; 262 unsigned long addr; 263 struct sdw_dpn_prop *dpn; 264 265 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 266 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 267 268 prop->paging_support = true; 269 270 /* first we need to allocate memory for set bits in port lists 271 * port = 1 for AMP playback 272 * port = 2 for IV capture 273 */ 274 prop->source_ports = BIT(2); /* BITMAP: 00000100 */ 275 prop->sink_ports = BIT(1); /* BITMAP: 00000010 */ 276 277 nval = hweight32(prop->source_ports); 278 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 279 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 280 if (!prop->src_dpn_prop) 281 return -ENOMEM; 282 283 i = 0; 284 dpn = prop->src_dpn_prop; 285 addr = prop->source_ports; 286 for_each_set_bit(bit, &addr, 32) { 287 dpn[i].num = bit; 288 dpn[i].type = SDW_DPN_FULL; 289 dpn[i].simple_ch_prep_sm = true; 290 dpn[i].ch_prep_timeout = 10; 291 i++; 292 } 293 294 /* do this again for sink now */ 295 nval = hweight32(prop->sink_ports); 296 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 297 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 298 if (!prop->sink_dpn_prop) 299 return -ENOMEM; 300 301 j = 0; 302 dpn = prop->sink_dpn_prop; 303 addr = prop->sink_ports; 304 for_each_set_bit(bit, &addr, 32) { 305 dpn[j].num = bit; 306 dpn[j].type = SDW_DPN_FULL; 307 dpn[j].simple_ch_prep_sm = true; 308 dpn[j].ch_prep_timeout = 10; 309 j++; 310 } 311 312 /* set the timeout values */ 313 prop->clk_stop_timeout = 64; 314 315 return 0; 316 } 317 318 static int rt1017_sdca_io_init(struct device *dev, struct sdw_slave *slave) 319 { 320 struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(dev); 321 322 if (rt1017->hw_init) 323 return 0; 324 325 if (rt1017->first_hw_init) { 326 regcache_cache_only(rt1017->regmap, false); 327 regcache_cache_bypass(rt1017->regmap, true); 328 } else { 329 /* 330 * PM runtime is only enabled when a Slave reports as Attached 331 */ 332 333 /* set autosuspend parameters */ 334 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 335 pm_runtime_use_autosuspend(&slave->dev); 336 337 /* update count of parent 'active' children */ 338 pm_runtime_set_active(&slave->dev); 339 340 /* make sure the device does not suspend immediately */ 341 pm_runtime_mark_last_busy(&slave->dev); 342 343 pm_runtime_enable(&slave->dev); 344 } 345 346 pm_runtime_get_noresume(&slave->dev); 347 348 /* sw reset */ 349 regmap_write(rt1017->regmap, 0xc000, 0x02); 350 351 /* initial settings - blind write */ 352 regmap_multi_reg_write(rt1017->regmap, rt1017_blind_write, 353 ARRAY_SIZE(rt1017_blind_write)); 354 355 if (rt1017->first_hw_init) { 356 regcache_cache_bypass(rt1017->regmap, false); 357 regcache_mark_dirty(rt1017->regmap); 358 } else 359 rt1017->first_hw_init = true; 360 361 /* Mark Slave initialization complete */ 362 rt1017->hw_init = true; 363 364 pm_runtime_put_autosuspend(&slave->dev); 365 366 dev_dbg(&slave->dev, "hw_init complete\n"); 367 return 0; 368 } 369 370 static int rt1017_sdca_update_status(struct sdw_slave *slave, 371 enum sdw_slave_status status) 372 { 373 struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(&slave->dev); 374 375 if (status == SDW_SLAVE_UNATTACHED) 376 rt1017->hw_init = false; 377 378 /* 379 * Perform initialization only if slave status is present and 380 * hw_init flag is false 381 */ 382 if (rt1017->hw_init || status != SDW_SLAVE_ATTACHED) 383 return 0; 384 385 /* perform I/O transfers required for Slave initialization */ 386 return rt1017_sdca_io_init(&slave->dev, slave); 387 } 388 389 static const char * const rt1017_rx_data_ch_select[] = { 390 "Bypass", 391 "CN1", 392 "CN2", 393 "CN3", 394 "CN4", 395 "(1+2)/2", 396 "(1+3)/2", 397 "(1+4)/2", 398 "(2+3)/2", 399 "(2+4)/2", 400 "(3+4)/2", 401 }; 402 403 static SOC_ENUM_SINGLE_DECL(rt1017_rx_data_ch_enum, 404 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_UDMPU21, 405 RT1017_SDCA_CTL_UDMPU_CLUSTER, 0), 406 0, rt1017_rx_data_ch_select); 407 408 static const struct snd_kcontrol_new rt1017_sdca_controls[] = { 409 /* UDMPU Cluster Selection */ 410 SOC_ENUM("RX Channel Select", rt1017_rx_data_ch_enum), 411 }; 412 413 static const struct snd_kcontrol_new rt1017_sto_dac = 414 SOC_DAPM_SINGLE("Switch", 415 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_FU, RT1017_SDCA_CTL_FU_MUTE, 0x1), 416 0, 1, 1); 417 418 static int rt1017_sdca_pde23_event(struct snd_soc_dapm_widget *w, 419 struct snd_kcontrol *kcontrol, int event) 420 { 421 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 422 struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component); 423 unsigned char ps0 = 0x0, ps3 = 0x3; 424 425 switch (event) { 426 case SND_SOC_DAPM_POST_PMU: 427 regmap_write(rt1017->regmap, 428 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23, 429 RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 430 ps0); 431 break; 432 case SND_SOC_DAPM_PRE_PMD: 433 regmap_write(rt1017->regmap, 434 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23, 435 RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 436 ps3); 437 break; 438 default: 439 break; 440 } 441 return 0; 442 } 443 444 static int rt1017_sdca_classd_event(struct snd_soc_dapm_widget *w, 445 struct snd_kcontrol *kcontrol, int event) 446 { 447 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 448 struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component); 449 450 switch (event) { 451 case SND_SOC_DAPM_POST_PMU: 452 regmap_update_bits(rt1017->regmap, RT1017_PWM_TRIM_1, 453 RT1017_PWM_FREQ_CTL_SRC_SEL_MASK, RT1017_PWM_FREQ_CTL_SRC_SEL_REG); 454 regmap_write(rt1017->regmap, RT1017_CLASSD_INT_1, 0x10); 455 break; 456 default: 457 break; 458 } 459 460 return 0; 461 } 462 463 static int rt1017_sdca_feedback_event(struct snd_soc_dapm_widget *w, 464 struct snd_kcontrol *kcontrol, int event) 465 { 466 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 467 struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component); 468 469 switch (event) { 470 case SND_SOC_DAPM_PRE_PMU: 471 regmap_update_bits(rt1017->regmap, 0xd017, 0x1f, 0x08); 472 break; 473 case SND_SOC_DAPM_POST_PMD: 474 regmap_update_bits(rt1017->regmap, 0xd017, 0x1f, 0x09); 475 break; 476 default: 477 break; 478 } 479 480 return 0; 481 } 482 483 static const struct snd_soc_dapm_widget rt1017_sdca_dapm_widgets[] = { 484 /* Audio Interface */ 485 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 486 SND_SOC_DAPM_AIF_OUT_E("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0, 487 rt1017_sdca_feedback_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 488 489 /* Digital Interface */ 490 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1017_sto_dac), 491 492 /* Output Lines */ 493 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0, 494 rt1017_sdca_classd_event, SND_SOC_DAPM_POST_PMU), 495 SND_SOC_DAPM_OUTPUT("SPO"), 496 497 SND_SOC_DAPM_SUPPLY("PDE23", SND_SOC_NOPM, 0, 0, 498 rt1017_sdca_pde23_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 499 500 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 501 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0), 502 SND_SOC_DAPM_SIGGEN("I Gen"), 503 SND_SOC_DAPM_SIGGEN("V Gen"), 504 }; 505 506 static const struct snd_soc_dapm_route rt1017_sdca_dapm_routes[] = { 507 508 { "DAC", "Switch", "DP1RX" }, 509 { "CLASS D", NULL, "DAC" }, 510 { "CLASS D", NULL, "PDE23" }, 511 { "SPO", NULL, "CLASS D" }, 512 513 { "I Sense", NULL, "I Gen" }, 514 { "V Sense", NULL, "V Gen" }, 515 { "I Sense", NULL, "PDE23" }, 516 { "V Sense", NULL, "PDE23" }, 517 { "DP2TX", NULL, "I Sense" }, 518 { "DP2TX", NULL, "V Sense" }, 519 }; 520 521 static const struct sdw_slave_ops rt1017_sdca_slave_ops = { 522 .read_prop = rt1017_sdca_read_prop, 523 .update_status = rt1017_sdca_update_status, 524 }; 525 526 static int rt1017_sdca_component_probe(struct snd_soc_component *component) 527 { 528 int ret; 529 530 ret = pm_runtime_resume(component->dev); 531 if (ret < 0 && ret != -EACCES) 532 return ret; 533 534 return 0; 535 } 536 537 static void rt1017_sdca_component_remove(struct snd_soc_component *component) 538 { 539 struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component); 540 541 regcache_cache_only(rt1017->regmap, true); 542 } 543 544 static const struct snd_soc_component_driver soc_sdca_component_rt1017 = { 545 .probe = rt1017_sdca_component_probe, 546 .remove = rt1017_sdca_component_remove, 547 .controls = rt1017_sdca_controls, 548 .num_controls = ARRAY_SIZE(rt1017_sdca_controls), 549 .dapm_widgets = rt1017_sdca_dapm_widgets, 550 .num_dapm_widgets = ARRAY_SIZE(rt1017_sdca_dapm_widgets), 551 .dapm_routes = rt1017_sdca_dapm_routes, 552 .num_dapm_routes = ARRAY_SIZE(rt1017_sdca_dapm_routes), 553 .endianness = 1, 554 }; 555 556 static int rt1017_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 557 int direction) 558 { 559 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 560 561 return 0; 562 } 563 564 static void rt1017_sdca_shutdown(struct snd_pcm_substream *substream, 565 struct snd_soc_dai *dai) 566 { 567 snd_soc_dai_set_dma_data(dai, substream, NULL); 568 } 569 570 static int rt1017_sdca_pcm_hw_params(struct snd_pcm_substream *substream, 571 struct snd_pcm_hw_params *params, 572 struct snd_soc_dai *dai) 573 { 574 struct snd_soc_component *component = dai->component; 575 struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component); 576 struct sdw_stream_config stream_config; 577 struct sdw_port_config port_config; 578 enum sdw_data_direction direction; 579 struct sdw_stream_runtime *sdw_stream; 580 int retval, port, num_channels, ch_mask; 581 unsigned int sampling_rate; 582 583 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 584 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 585 586 if (!sdw_stream) 587 return -EINVAL; 588 589 if (!rt1017->sdw_slave) 590 return -EINVAL; 591 592 /* SoundWire specific configuration */ 593 /* port 1 for playback */ 594 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 595 direction = SDW_DATA_DIR_RX; 596 port = 1; 597 } else { 598 direction = SDW_DATA_DIR_TX; 599 port = 2; 600 } 601 602 num_channels = params_channels(params); 603 ch_mask = (1 << num_channels) - 1; 604 605 stream_config.frame_rate = params_rate(params); 606 stream_config.ch_count = num_channels; 607 stream_config.bps = snd_pcm_format_width(params_format(params)); 608 stream_config.direction = direction; 609 610 port_config.ch_mask = ch_mask; 611 port_config.num = port; 612 613 dev_dbg(dai->dev, "frame_rate %d, ch_count %d, bps %d, direction %d, ch_mask %d, port: %d\n", 614 params_rate(params), num_channels, snd_pcm_format_width(params_format(params)), 615 direction, ch_mask, port); 616 617 retval = sdw_stream_add_slave(rt1017->sdw_slave, &stream_config, 618 &port_config, 1, sdw_stream); 619 if (retval) { 620 dev_err(dai->dev, "Unable to configure port\n"); 621 return retval; 622 } 623 624 /* sampling rate configuration */ 625 switch (params_rate(params)) { 626 case 44100: 627 sampling_rate = RT1017_SDCA_RATE_44100HZ; 628 break; 629 case 48000: 630 sampling_rate = RT1017_SDCA_RATE_48000HZ; 631 break; 632 case 96000: 633 sampling_rate = RT1017_SDCA_RATE_96000HZ; 634 break; 635 case 192000: 636 sampling_rate = RT1017_SDCA_RATE_192000HZ; 637 break; 638 default: 639 dev_err(component->dev, "Rate %d is not supported\n", 640 params_rate(params)); 641 return -EINVAL; 642 } 643 644 /* set sampling frequency */ 645 regmap_write(rt1017->regmap, 646 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_CS21, 647 RT1017_SDCA_CTL_FS_INDEX, 0), 648 sampling_rate); 649 650 return 0; 651 } 652 653 static int rt1017_sdca_pcm_hw_free(struct snd_pcm_substream *substream, 654 struct snd_soc_dai *dai) 655 { 656 struct snd_soc_component *component = dai->component; 657 struct rt1017_sdca_priv *rt1017 = snd_soc_component_get_drvdata(component); 658 struct sdw_stream_runtime *sdw_stream = 659 snd_soc_dai_get_dma_data(dai, substream); 660 661 if (!rt1017->sdw_slave) 662 return -EINVAL; 663 664 sdw_stream_remove_slave(rt1017->sdw_slave, sdw_stream); 665 return 0; 666 } 667 668 static const struct snd_soc_dai_ops rt1017_sdca_ops = { 669 .hw_params = rt1017_sdca_pcm_hw_params, 670 .hw_free = rt1017_sdca_pcm_hw_free, 671 .set_stream = rt1017_sdca_set_sdw_stream, 672 .shutdown = rt1017_sdca_shutdown, 673 }; 674 675 #define RT1017_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 676 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 677 #define RT1017_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ 678 SNDRV_PCM_FMTBIT_S24_LE) 679 680 static struct snd_soc_dai_driver rt1017_sdca_dai[] = { 681 { 682 .name = "rt1017-aif", 683 .playback = { 684 .stream_name = "DP1 Playback", 685 .channels_min = 1, 686 .channels_max = 1, 687 .rates = RT1017_STEREO_RATES, 688 .formats = RT1017_FORMATS, 689 }, 690 .capture = { 691 .stream_name = "DP2 Capture", 692 .channels_min = 1, 693 .channels_max = 1, 694 .rates = RT1017_STEREO_RATES, 695 .formats = RT1017_FORMATS, 696 }, 697 .ops = &rt1017_sdca_ops, 698 }, 699 }; 700 701 static int rt1017_sdca_init(struct device *dev, struct regmap *regmap, 702 struct sdw_slave *slave) 703 { 704 struct rt1017_sdca_priv *rt1017; 705 int ret; 706 707 rt1017 = devm_kzalloc(dev, sizeof(*rt1017), GFP_KERNEL); 708 if (!rt1017) 709 return -ENOMEM; 710 711 dev_set_drvdata(dev, rt1017); 712 rt1017->sdw_slave = slave; 713 rt1017->regmap = regmap; 714 715 /* 716 * Mark hw_init to false 717 * HW init will be performed when device reports present 718 */ 719 rt1017->hw_init = false; 720 rt1017->first_hw_init = false; 721 722 ret = devm_snd_soc_register_component(dev, 723 &soc_sdca_component_rt1017, 724 rt1017_sdca_dai, 725 ARRAY_SIZE(rt1017_sdca_dai)); 726 727 return ret; 728 } 729 730 static int rt1017_sdca_sdw_probe(struct sdw_slave *slave, 731 const struct sdw_device_id *id) 732 { 733 struct regmap *regmap; 734 735 /* Regmap Initialization */ 736 regmap = devm_regmap_init_sdw(slave, &rt1017_sdca_regmap); 737 if (IS_ERR(regmap)) 738 return PTR_ERR(regmap); 739 740 return rt1017_sdca_init(&slave->dev, regmap, slave); 741 } 742 743 static void rt1017_sdca_sdw_remove(struct sdw_slave *slave) 744 { 745 struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(&slave->dev); 746 747 if (rt1017->first_hw_init) 748 pm_runtime_disable(&slave->dev); 749 } 750 751 static const struct sdw_device_id rt1017_sdca_id[] = { 752 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1017, 0x3, 0x1, 0), 753 {}, 754 }; 755 MODULE_DEVICE_TABLE(sdw, rt1017_sdca_id); 756 757 static int rt1017_sdca_dev_suspend(struct device *dev) 758 { 759 struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(dev); 760 761 if (!rt1017->hw_init) 762 return 0; 763 764 regcache_cache_only(rt1017->regmap, true); 765 766 return 0; 767 } 768 769 #define RT1017_PROBE_TIMEOUT 5000 770 771 static int rt1017_sdca_dev_resume(struct device *dev) 772 { 773 struct sdw_slave *slave = dev_to_sdw_dev(dev); 774 struct rt1017_sdca_priv *rt1017 = dev_get_drvdata(dev); 775 int ret; 776 777 if (!rt1017->first_hw_init) 778 return 0; 779 780 ret = sdw_slave_wait_for_init(slave, RT1017_PROBE_TIMEOUT); 781 if (ret) { 782 sdw_show_ping_status(slave->bus, true); 783 return ret; 784 } 785 786 regcache_cache_only(rt1017->regmap, false); 787 ret = regcache_sync(rt1017->regmap); 788 if (ret) { 789 regcache_cache_only(rt1017->regmap, true); 790 regcache_mark_dirty(rt1017->regmap); 791 return ret; 792 } 793 794 return 0; 795 } 796 797 static const struct dev_pm_ops rt1017_sdca_pm = { 798 SYSTEM_SLEEP_PM_OPS(rt1017_sdca_dev_suspend, rt1017_sdca_dev_resume) 799 RUNTIME_PM_OPS(rt1017_sdca_dev_suspend, rt1017_sdca_dev_resume, NULL) 800 }; 801 802 static struct sdw_driver rt1017_sdca_sdw_driver = { 803 .driver = { 804 .name = "rt1017-sdca", 805 .pm = pm_ptr(&rt1017_sdca_pm), 806 }, 807 .probe = rt1017_sdca_sdw_probe, 808 .remove = rt1017_sdca_sdw_remove, 809 .ops = &rt1017_sdca_slave_ops, 810 .id_table = rt1017_sdca_id, 811 }; 812 module_sdw_driver(rt1017_sdca_sdw_driver); 813 814 MODULE_DESCRIPTION("ASoC RT1017 driver SDCA SDW"); 815 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>"); 816 MODULE_LICENSE("GPL"); 817