1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 249ef7925SOder Chiou /* 349ef7925SOder Chiou * rl6231.h - RL6231 class device shared support 449ef7925SOder Chiou * 549ef7925SOder Chiou * Copyright 2014 Realtek Semiconductor Corp. 649ef7925SOder Chiou * 749ef7925SOder Chiou * Author: Oder Chiou <oder_chiou@realtek.com> 849ef7925SOder Chiou */ 949ef7925SOder Chiou 1049ef7925SOder Chiou #ifndef __RL6231_H__ 1149ef7925SOder Chiou #define __RL6231_H__ 1249ef7925SOder Chiou 13bbf53b95SDerek Fang #define RL6231_PLL_INP_MAX 50000000 1471c7a2d6SOder Chiou #define RL6231_PLL_INP_MIN 256000 1571c7a2d6SOder Chiou #define RL6231_PLL_N_MAX 0x1ff 1671c7a2d6SOder Chiou #define RL6231_PLL_K_MAX 0x1f 1771c7a2d6SOder Chiou #define RL6231_PLL_M_MAX 0xf 1871c7a2d6SOder Chiou 1971c7a2d6SOder Chiou struct rl6231_pll_code { 2071c7a2d6SOder Chiou bool m_bp; /* Indicates bypass m code or not. */ 21*c25504adSOder Chiou bool k_bp; /* Indicates bypass k code or not. */ 2271c7a2d6SOder Chiou int m_code; 2371c7a2d6SOder Chiou int n_code; 2471c7a2d6SOder Chiou int k_code; 2571c7a2d6SOder Chiou }; 2671c7a2d6SOder Chiou 2749ef7925SOder Chiou int rl6231_calc_dmic_clk(int rate); 2871c7a2d6SOder Chiou int rl6231_pll_calc(const unsigned int freq_in, 2971c7a2d6SOder Chiou const unsigned int freq_out, struct rl6231_pll_code *pll_code); 30d92950e7SOder Chiou int rl6231_get_clk_info(int sclk, int rate); 3100a6d6e5SOder Chiou int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft); 3249ef7925SOder Chiou 3349ef7925SOder Chiou #endif /* __RL6231_H__ */ 34