1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 */ 4 5 #ifndef _PM4125_REGISTERS_H 6 #define _PM4125_REGISTERS_H 7 8 #include <linux/soundwire/sdw.h> 9 #include <linux/soundwire/sdw_type.h> 10 #include "wcd-common.h" 11 12 #define PM4125_ANA_BASE_ADDR 0x3000 13 #define PM4125_DIG_BASE_ADDR 0x3400 14 15 #define PM4125_ANA_MICBIAS_MICB_1_2_EN (PM4125_ANA_BASE_ADDR+0x040) 16 #define PM4125_ANA_MICBIAS_MICB1_PULL_UP_MASK BIT(5) 17 #define PM4125_ANA_MICBIAS_MICB2_PULL_UP_MASK BIT(1) 18 #define PM4125_ANA_MICBIAS_MICB2_PULL_DN_MASK BIT(0) 19 #define PM4125_ANA_MICBIAS_MICB_PULL_ENABLE 1 20 #define PM4125_ANA_MICBIAS_MICB_PULL_DISABLE 0 21 #define PM4125_ANA_MICBIAS_MICB_3_EN (PM4125_ANA_BASE_ADDR+0x041) 22 #define PM4125_ANA_MICBIAS_LDO_1_SETTING (PM4125_ANA_BASE_ADDR+0x042) 23 #define PM4125_ANA_MICBIAS_MICB_OUT_VAL_MASK GENMASK(7, 3) 24 #define PM4125_ANA_MICBIAS_LDO_1_CTRL (PM4125_ANA_BASE_ADDR+0x043) 25 #define PM4125_ANA_TX_AMIC1 (PM4125_ANA_BASE_ADDR+0x047) 26 #define PM4125_ANA_TX_AMIC2 (PM4125_ANA_BASE_ADDR+0x048) 27 #define PM4125_ANA_MBHC_MECH (PM4125_ANA_BASE_ADDR+0x05A) 28 #define PM4125_ANA_MBHC_ELECT (PM4125_ANA_BASE_ADDR+0x05B) 29 #define PM4125_ANA_MBHC_ELECT_BIAS_EN_MASK BIT(0) 30 #define PM4125_ANA_MBHC_ELECT_BIAS_ENABLE 1 31 #define PM4125_ANA_MBHC_ELECT_BIAS_DISABLE 0 32 #define PM4125_ANA_MBHC_ZDET (PM4125_ANA_BASE_ADDR+0x05C) 33 #define PM4125_ANA_MBHC_RESULT_1 (PM4125_ANA_BASE_ADDR+0x05D) 34 #define PM4125_ANA_MBHC_RESULT_2 (PM4125_ANA_BASE_ADDR+0x05E) 35 #define PM4125_ANA_MBHC_RESULT_3 (PM4125_ANA_BASE_ADDR+0x05F) 36 #define PM4125_ANA_MBHC_BTN0_ZDET_VREF1 (PM4125_ANA_BASE_ADDR+0x060) 37 #define PM4125_ANA_MBHC_BTN0_THRESHOLD_MASK GENMASK(7, 2) 38 #define PM4125_ANA_MBHC_BTN1_ZDET_VREF2 (PM4125_ANA_BASE_ADDR+0x061) 39 #define PM4125_ANA_MBHC_BTN2_ZDET_VREF3 (PM4125_ANA_BASE_ADDR+0x062) 40 #define PM4125_ANA_MBHC_BTN3_ZDET_DBG_400 (PM4125_ANA_BASE_ADDR+0x063) 41 #define PM4125_ANA_MBHC_BTN4_ZDET_DBG_1400 (PM4125_ANA_BASE_ADDR+0x064) 42 #define PM4125_ANA_MBHC_MICB2_RAMP (PM4125_ANA_BASE_ADDR+0x065) 43 #define PM4125_ANA_MBHC_CTL_1 (PM4125_ANA_BASE_ADDR+0x066) 44 #define PM4125_ANA_MBHC_CTL_2 (PM4125_ANA_BASE_ADDR+0x067) 45 #define PM4125_ANA_MBHC_PLUG_DETECT_CTL (PM4125_ANA_BASE_ADDR+0x068) 46 #define PM4125_ANA_MBHC_ZDET_ANA_CTL (PM4125_ANA_BASE_ADDR+0x069) 47 #define PM4125_ANA_MBHC_ZDET_RAMP_CTL (PM4125_ANA_BASE_ADDR+0x06A) 48 #define PM4125_ANA_MBHC_FSM_STATUS (PM4125_ANA_BASE_ADDR+0x06B) 49 #define PM4125_ANA_MBHC_ADC_RESULT (PM4125_ANA_BASE_ADDR+0x06C) 50 #define PM4125_ANA_MBHC_CTL_CLK (PM4125_ANA_BASE_ADDR+0x06D) 51 #define PM4125_ANA_MBHC_ZDET_CALIB_RESULT (PM4125_ANA_BASE_ADDR+0x072) 52 #define PM4125_ANA_NCP_EN (PM4125_ANA_BASE_ADDR+0x077) 53 #define PM4125_ANA_NCP_ENABLE_MASK BIT(0) 54 #define PM4125_ANA_NCP_ENABLE 1 55 #define PM4125_ANA_NCP_DISABLE 0 56 #define PM4125_ANA_NCP_VCTRL (PM4125_ANA_BASE_ADDR+0x07C) 57 #define PM4125_ANA_HPHPA_CNP_CTL_1 (PM4125_ANA_BASE_ADDR+0x083) 58 #define PM4125_ANA_HPHPA_CNP_CTL_1_EN_MASK BIT(1) 59 #define PM4125_ANA_HPHPA_CNP_CTL_1_EN 1 60 #define PM4125_ANA_HPHPA_CNP_CTL_2 (PM4125_ANA_BASE_ADDR+0x084) 61 #define PM4125_ANA_HPHPA_CNP_OCP_EN_L_MASK BIT(1) 62 #define PM4125_ANA_HPHPA_CNP_OCP_EN_R_MASK BIT(0) 63 #define PM4125_ANA_HPHPA_CNP_OCP_ENABLE 1 64 #define PM4125_ANA_HPHPA_CNP_OCP_DISABLE 0 65 #define PM4125_ANA_HPHPA_PA_STATUS (PM4125_ANA_BASE_ADDR+0x087) 66 #define PM4125_ANA_HPHPA_FSM_CLK (PM4125_ANA_BASE_ADDR+0x088) 67 #define PM4125_ANA_HPHPA_FSM_CLK_DIV_EN_MASK BIT(7) 68 #define PM4125_ANA_HPHPA_FSM_CLK_DIV_ENABLE 1 69 #define PM4125_ANA_HPHPA_FSM_CLK_DIV_DISABLE 0 70 #define PM4125_ANA_HPHPA_FSM_DIV_RATIO_MASK GENMASK(6, 0) 71 #define PM4125_ANA_HPHPA_FSM_DIV_RATIO_68 (0x11) 72 #define PM4125_ANA_HPHPA_L_GAIN (PM4125_ANA_BASE_ADDR+0x08B) 73 #define PM4125_ANA_HPHPA_R_GAIN (PM4125_ANA_BASE_ADDR+0x08C) 74 #define PM4125_ANA_HPHPA_SPARE_CTL (PM4125_ANA_BASE_ADDR+0x08E) 75 #define PM4125_SWR_HPHPA_HD2 (PM4125_ANA_BASE_ADDR+0x090) 76 #define PM4125_SWR_HPHPA_HD2_LEFT_MASK GENMASK(5, 3) 77 #define PM4125_SWR_HPHPA_HD2_RIGHT_MASK GENMASK(2, 0) 78 #define PM4125_SWR_HPHPA_HD2_ENABLE (BIT(2) | BIT(1) | BIT(0)) 79 #define PM4125_ANA_SURGE_EN (PM4125_ANA_BASE_ADDR+0x097) 80 #define PM4125_ANA_SURGE_PROTECTION_HPHL_MASK BIT(7) 81 #define PM4125_ANA_SURGE_PROTECTION_HPHR_MASK BIT(6) 82 #define PM4125_ANA_SURGE_PROTECTION_ENABLE 1 83 #define PM4125_ANA_SURGE_PROTECTION_DISABLE 0 84 #define PM4125_ANA_COMBOPA_CTL (PM4125_ANA_BASE_ADDR+0x09B) 85 #define PM4125_ANA_COMBO_PA_SELECT_MASK BIT(6) 86 #define PM4125_ANA_COMBO_PA_SELECT_EAR 0 87 #define PM4125_ANA_COMBO_PA_SELECT_LO 1 88 #define PM4125_ANA_COMBOPA_CTL_4 (PM4125_ANA_BASE_ADDR+0x09F) 89 #define PM4125_ANA_COMBOPA_CTL_5 (PM4125_ANA_BASE_ADDR+0x0A0) 90 #define PM4125_ANA_RXLDO_CTL (PM4125_ANA_BASE_ADDR+0x0B2) 91 #define PM4125_ANA_MBIAS_EN (PM4125_ANA_BASE_ADDR+0x0B4) 92 #define PM4125_ANA_MBIAS_EN_GLOBAL_MASK BIT(5) 93 #define PM4125_ANA_MBIAS_EN_V2I_MASK BIT(4) 94 #define PM4125_ANA_MBIAS_EN_ENABLE 1 95 #define PM4125_ANA_MBIAS_EN_DISABLE 0 96 97 #define PM4125_DIG_SWR_CHIP_ID0 (PM4125_DIG_BASE_ADDR+0x001) 98 #define PM4125_DIG_SWR_CHIP_ID1 (PM4125_DIG_BASE_ADDR+0x002) 99 #define PM4125_DIG_SWR_CHIP_ID2 (PM4125_DIG_BASE_ADDR+0x003) 100 #define PM4125_DIG_SWR_CHIP_ID3 (PM4125_DIG_BASE_ADDR+0x004) 101 #define PM4125_DIG_SWR_SWR_TX_CLK_RATE (PM4125_DIG_BASE_ADDR+0x040) 102 #define PM4125_DIG_SWR_CDC_RST_CTL (PM4125_DIG_BASE_ADDR+0x041) 103 #define PM4125_DIG_SWR_TOP_CLK_CFG (PM4125_DIG_BASE_ADDR+0x042) 104 #define PM4125_DIG_SWR_CDC_RX_CLK_CTL (PM4125_DIG_BASE_ADDR+0x043) 105 #define PM4125_DIG_SWR_ANA_RX_DIV2_CLK_EN_MASK BIT(5) 106 #define PM4125_DIG_SWR_ANA_RX_CLK_EN_MASK BIT(4) 107 #define PM4125_DIG_SWR_RX1_CLK_EN_MASK BIT(1) 108 #define PM4125_DIG_SWR_RX0_CLK_EN_MASK BIT(0) 109 #define PM4125_DIG_SWR_RX_CLK_ENABLE 1 110 #define PM4125_DIG_SWR_RX_CLK_DISABLE 0 111 #define PM4125_DIG_SWR_CDC_TX_CLK_CTL (PM4125_DIG_BASE_ADDR+0x044) 112 #define PM4125_DIG_SWR_SWR_RST_EN (PM4125_DIG_BASE_ADDR+0x045) 113 #define PM4125_DIG_SWR_CDC_RX_RST (PM4125_DIG_BASE_ADDR+0x047) 114 #define PM4125_DIG_SWR_CDC_RX0_CTL (PM4125_DIG_BASE_ADDR+0x048) 115 #define PM4125_DIG_SWR_DSM_DITHER_EN_MASK BIT(7) 116 #define PM4125_DIG_SWR_DSM_DITHER_DISABLE 0 117 #define PM4125_DIG_SWR_DSM_DITHER_ENABLE 1 118 #define PM4125_DIG_SWR_CDC_RX1_CTL (PM4125_DIG_BASE_ADDR+0x049) 119 #define PM4125_DIG_SWR_CDC_TX_ANA_MODE_0_1 (PM4125_DIG_BASE_ADDR+0x04B) 120 #define PM4125_DIG_SWR_TX_ANA_TXD1_MODE_MASK GENMASK(7, 4) 121 #define PM4125_DIG_SWR_TX_ANA_TXD0_MODE_MASK GENMASK(3, 0) 122 #define PM4125_DIG_SWR_TXD_MODE_ULPI (0x9) 123 #define PM4125_DIG_SWR_TXD_MODE_NORMAL (0x3) 124 #define PM4125_DIG_SWR_CDC_COMP_CTL_0 (PM4125_DIG_BASE_ADDR+0x04F) 125 #define PM4125_DIG_SWR_COMP_HPHL_EN_MASK BIT(1) 126 #define PM4125_DIG_SWR_COMP_HPHR_EN_MASK BIT(0) 127 #define PM4125_DIG_SWR_COMP_ENABLE 1 128 #define PM4125_DIG_SWR_COMP_DISABLE 0 129 #define PM4125_DIG_SWR_CDC_RX_DELAY_CTL (PM4125_DIG_BASE_ADDR+0x052) 130 #define PM4125_DIG_SWR_CDC_RX_GAIN_0 (PM4125_DIG_BASE_ADDR+0x053) 131 #define PM4125_DIG_SWR_CDC_RX_GAIN_1 (PM4125_DIG_BASE_ADDR+0x054) 132 #define PM4125_DIG_SWR_CDC_RX_GAIN_CTL (PM4125_DIG_BASE_ADDR+0x057) 133 #define PM4125_DIG_SWR_RX1_EN_MASK BIT(3) 134 #define PM4125_DIG_SWR_RX0_EN_MASK BIT(2) 135 #define PM4125_DIG_SWR_RX_INPUT_DISABLE 0 136 #define PM4125_DIG_SWR_RX_INPUT_ENABLE 1 137 #define PM4125_DIG_SWR_CDC_TX0_CTL (PM4125_DIG_BASE_ADDR+0x060) 138 #define PM4125_DIG_SWR_CDC_TX1_CTL (PM4125_DIG_BASE_ADDR+0x061) 139 #define PM4125_DIG_SWR_CDC_TX_RST (PM4125_DIG_BASE_ADDR+0x063) 140 #define PM4125_DIG_SWR_CDC_REQ0_CTL (PM4125_DIG_BASE_ADDR+0x064) 141 #define PM4125_DIG_SWR_CDC_REQ1_CTL (PM4125_DIG_BASE_ADDR+0x065) 142 #define PM4125_DIG_SWR_CDC_RST (PM4125_DIG_BASE_ADDR+0x067) 143 #define PM4125_DIG_SWR_CDC_AMIC_CTL (PM4125_DIG_BASE_ADDR+0x06A) 144 #define PM4125_DIG_SWR_AMIC_SELECT_MASK BIT(1) 145 #define PM4125_DIG_SWR_AMIC_SELECT_DMIC1 0 146 #define PM4125_DIG_SWR_AMIC_SELECT_AMIC3 1 147 #define PM4125_DIG_SWR_CDC_DMIC_CTL (PM4125_DIG_BASE_ADDR+0x06B) 148 #define PM4125_DIG_SWR_CDC_DMIC1_CTL (PM4125_DIG_BASE_ADDR+0x06C) 149 #define PM4125_DIG_SWR_DMIC1_CLK_EN_MASK BIT(3) 150 #define PM4125_DIG_SWR_DMIC1_CLK_ENABLE 1 151 #define PM4125_DIG_SWR_DMIC1_CLK_DISABLE 0 152 #define PM4125_DIG_SWR_CDC_DMIC1_RATE (PM4125_DIG_BASE_ADDR+0x06D) 153 #define PM4125_DIG_SWR_PDM_WD_CTL0 (PM4125_DIG_BASE_ADDR+0x070) 154 #define PM4125_WDT_ENABLE_MASK GENMASK(1, 0) 155 #define PM4125_WDT_ENABLE_RX0_L BIT(0) 156 #define PM4125_WDT_ENABLE_RX0_M BIT(1) 157 #define PM4125_DIG_SWR_PDM_WD_CTL1 (PM4125_DIG_BASE_ADDR+0x071) 158 #define PM4125_WDT_ENABLE_RX1_L BIT(0) 159 #define PM4125_WDT_ENABLE_RX1_M BIT(1) 160 #define PM4125_DIG_SWR_INTR_MODE (PM4125_DIG_BASE_ADDR+0x080) 161 #define PM4125_DIG_SWR_INTR_MASK_0 (PM4125_DIG_BASE_ADDR+0x081) 162 #define PM4125_DIG_SWR_INTR_MASK_1 (PM4125_DIG_BASE_ADDR+0x082) 163 #define PM4125_DIG_SWR_INTR_MASK_2 (PM4125_DIG_BASE_ADDR+0x083) 164 #define PM4125_DIG_SWR_INTR_STATUS_0 (PM4125_DIG_BASE_ADDR+0x084) 165 #define PM4125_DIG_SWR_INTR_STATUS_1 (PM4125_DIG_BASE_ADDR+0x085) 166 #define PM4125_DIG_SWR_INTR_STATUS_2 (PM4125_DIG_BASE_ADDR+0x086) 167 #define PM4125_DIG_SWR_INTR_CLEAR_0 (PM4125_DIG_BASE_ADDR+0x087) 168 #define PM4125_DIG_SWR_INTR_CLEAR_1 (PM4125_DIG_BASE_ADDR+0x088) 169 #define PM4125_DIG_SWR_INTR_CLEAR_2 (PM4125_DIG_BASE_ADDR+0x089) 170 #define PM4125_DIG_SWR_INTR_LEVEL_0 (PM4125_DIG_BASE_ADDR+0x08A) 171 #define PM4125_DIG_SWR_INTR_LEVEL_1 (PM4125_DIG_BASE_ADDR+0x08B) 172 #define PM4125_DIG_SWR_INTR_LEVEL_2 (PM4125_DIG_BASE_ADDR+0x08C) 173 #define PM4125_DIG_SWR_CDC_CONN_RX0_CTL (PM4125_DIG_BASE_ADDR+0x093) 174 #define PM4125_DIG_SWR_CDC_CONN_RX1_CTL (PM4125_DIG_BASE_ADDR+0x094) 175 #define PM4125_DIG_SWR_LOOP_BACK_MODE (PM4125_DIG_BASE_ADDR+0x097) 176 #define PM4125_DIG_SWR_DRIVE_STRENGTH_0 (PM4125_DIG_BASE_ADDR+0x0A0) 177 #define PM4125_DIG_SWR_DIG_DEBUG_CTL (PM4125_DIG_BASE_ADDR+0x0AB) 178 #define PM4125_DIG_SWR_DIG_DEBUG_EN (PM4125_DIG_BASE_ADDR+0x0AC) 179 #define PM4125_DIG_SWR_DEM_BYPASS_DATA0 (PM4125_DIG_BASE_ADDR+0x0B0) 180 #define PM4125_DIG_SWR_DEM_BYPASS_DATA1 (PM4125_DIG_BASE_ADDR+0x0B1) 181 #define PM4125_DIG_SWR_DEM_BYPASS_DATA2 (PM4125_DIG_BASE_ADDR+0x0B2) 182 #define PM4125_DIG_SWR_DEM_BYPASS_DATA3 (PM4125_DIG_BASE_ADDR+0x0B3) 183 184 #define PM4125_ANALOG_REGISTERS_MAX_SIZE (PM4125_ANA_BASE_ADDR+0x0B5) 185 #define PM4125_DIGITAL_REGISTERS_MAX_SIZE (PM4125_DIG_BASE_ADDR+0x0B4) 186 #define PM4125_ANALOG_MAX_REGISTER (PM4125_ANALOG_REGISTERS_MAX_SIZE - 1) 187 #define PM4125_DIGITAL_MAX_REGISTER (PM4125_DIGITAL_REGISTERS_MAX_SIZE - 1) 188 #define PM4125_MAX_REGISTER PM4125_DIGITAL_MAX_REGISTER 189 190 #define PM4125_MAX_MICBIAS 3 191 #define PM4125_MAX_SWR_CH_IDS 15 192 #define PM4125_SWRM_CH_MASK(ch_idx) BIT(ch_idx - 1) 193 194 enum pm4125_tx_sdw_ports { 195 PM4125_ADC_1_2_DMIC1L_BCS_PORT = 1, 196 PM4125_DMIC_1L_1R_ADC1_BCS_PORT, 197 PM4125_MAX_TX_SWR_PORTS = PM4125_DMIC_1L_1R_ADC1_BCS_PORT, 198 }; 199 200 enum pm4125_rx_sdw_ports { 201 PM4125_HPH_PORT = 1, 202 PM4125_COMP_PORT, 203 PM4125_MAX_SWR_PORTS = PM4125_COMP_PORT, 204 }; 205 206 struct pm4125_priv; 207 struct pm4125_sdw_priv { 208 struct sdw_slave *sdev; 209 struct sdw_stream_config sconfig; 210 struct sdw_stream_runtime *sruntime; 211 struct sdw_port_config port_config[PM4125_MAX_SWR_PORTS]; 212 struct wcd_sdw_ch_info *ch_info; 213 bool port_enable[PM4125_MAX_SWR_CH_IDS]; 214 unsigned int master_channel_map[SDW_MAX_PORTS]; 215 int active_ports; 216 int num_ports; 217 bool is_tx; 218 struct pm4125_priv *pm4125; 219 struct irq_domain *slave_irq; 220 struct regmap *regmap; 221 }; 222 223 #if IS_ENABLED(CONFIG_SND_SOC_PM4125_SDW) 224 int pm4125_sdw_free(struct pm4125_sdw_priv *pm4125, struct snd_pcm_substream *substream, 225 struct snd_soc_dai *dai); 226 int pm4125_sdw_set_sdw_stream(struct pm4125_sdw_priv *pm4125, struct snd_soc_dai *dai, void *stream, 227 int direction); 228 int pm4125_sdw_hw_params(struct pm4125_sdw_priv *pm4125, struct snd_pcm_substream *substream, 229 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai); 230 231 #else 232 static inline int pm4125_sdw_free(struct pm4125_sdw_priv *pm4125, 233 struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 234 { 235 return -EOPNOTSUPP; 236 } 237 238 static inline int pm4125_sdw_set_sdw_stream(struct pm4125_sdw_priv *pm4125, 239 struct snd_soc_dai *dai, void *stream, int direction) 240 { 241 return -EOPNOTSUPP; 242 } 243 244 static inline int pm4125_sdw_hw_params(struct pm4125_sdw_priv *pm4125, 245 struct snd_pcm_substream *substream, 246 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 247 { 248 return -EOPNOTSUPP; 249 } 250 #endif 251 252 enum { 253 /* INTR_CTRL_INT_MASK_0 */ 254 PM4125_IRQ_MBHC_BUTTON_PRESS_DET = 0, 255 PM4125_IRQ_MBHC_BUTTON_RELEASE_DET, 256 PM4125_IRQ_MBHC_ELECT_INS_REM_DET, 257 PM4125_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 258 PM4125_IRQ_MBHC_SW_DET, 259 PM4125_IRQ_HPHR_OCP_INT, 260 PM4125_IRQ_HPHR_CNP_INT, 261 PM4125_IRQ_HPHL_OCP_INT, 262 263 /* INTR_CTRL_INT_MASK_1 */ 264 PM4125_IRQ_HPHL_CNP_INT, 265 PM4125_IRQ_EAR_CNP_INT, 266 PM4125_IRQ_EAR_SCD_INT, 267 PM4125_IRQ_AUX_CNP_INT, 268 PM4125_IRQ_AUX_SCD_INT, 269 PM4125_IRQ_HPHL_PDM_WD_INT, 270 PM4125_IRQ_HPHR_PDM_WD_INT, 271 PM4125_IRQ_AUX_PDM_WD_INT, 272 273 /* INTR_CTRL_INT_MASK_2 */ 274 PM4125_IRQ_LDORT_SCD_INT, 275 PM4125_IRQ_MBHC_MOISTURE_INT, 276 PM4125_IRQ_HPHL_SURGE_DET_INT, 277 PM4125_IRQ_HPHR_SURGE_DET_INT, 278 PM4125_NUM_IRQS, 279 }; 280 281 enum pm4125_tx_sdw_channels { 282 PM4125_ADC1, 283 PM4125_ADC2, 284 }; 285 286 enum pm4125_rx_sdw_channels { 287 PM4125_HPH_L, 288 PM4125_HPH_R, 289 PM4125_COMP_L, 290 PM4125_COMP_R, 291 }; 292 293 #endif /* _PM4125_REGISTERS_H */ 294