1 /* SPDX-License-Identifier: GPL-2.0-only 2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 */ 4 5 #ifndef _PM4125_REGISTERS_H 6 #define _PM4125_REGISTERS_H 7 8 #include <linux/soundwire/sdw.h> 9 #include <linux/soundwire/sdw_type.h> 10 11 #define PM4125_ANA_BASE_ADDR 0x3000 12 #define PM4125_DIG_BASE_ADDR 0x3400 13 14 #define PM4125_ANA_MICBIAS_MICB_1_2_EN (PM4125_ANA_BASE_ADDR+0x040) 15 #define PM4125_ANA_MICBIAS_MICB1_PULL_UP_MASK BIT(5) 16 #define PM4125_ANA_MICBIAS_MICB2_PULL_UP_MASK BIT(1) 17 #define PM4125_ANA_MICBIAS_MICB2_PULL_DN_MASK BIT(0) 18 #define PM4125_ANA_MICBIAS_MICB_PULL_ENABLE 1 19 #define PM4125_ANA_MICBIAS_MICB_PULL_DISABLE 0 20 #define PM4125_ANA_MICBIAS_MICB_3_EN (PM4125_ANA_BASE_ADDR+0x041) 21 #define PM4125_ANA_MICBIAS_LDO_1_SETTING (PM4125_ANA_BASE_ADDR+0x042) 22 #define PM4125_ANA_MICBIAS_MICB_OUT_VAL_MASK GENMASK(7, 3) 23 #define PM4125_ANA_MICBIAS_LDO_1_CTRL (PM4125_ANA_BASE_ADDR+0x043) 24 #define PM4125_ANA_TX_AMIC1 (PM4125_ANA_BASE_ADDR+0x047) 25 #define PM4125_ANA_TX_AMIC2 (PM4125_ANA_BASE_ADDR+0x048) 26 #define PM4125_ANA_MBHC_MECH (PM4125_ANA_BASE_ADDR+0x05A) 27 #define PM4125_ANA_MBHC_ELECT (PM4125_ANA_BASE_ADDR+0x05B) 28 #define PM4125_ANA_MBHC_ELECT_BIAS_EN_MASK BIT(0) 29 #define PM4125_ANA_MBHC_ELECT_BIAS_ENABLE 1 30 #define PM4125_ANA_MBHC_ELECT_BIAS_DISABLE 0 31 #define PM4125_ANA_MBHC_ZDET (PM4125_ANA_BASE_ADDR+0x05C) 32 #define PM4125_ANA_MBHC_RESULT_1 (PM4125_ANA_BASE_ADDR+0x05D) 33 #define PM4125_ANA_MBHC_RESULT_2 (PM4125_ANA_BASE_ADDR+0x05E) 34 #define PM4125_ANA_MBHC_RESULT_3 (PM4125_ANA_BASE_ADDR+0x05F) 35 #define PM4125_ANA_MBHC_BTN0_ZDET_VREF1 (PM4125_ANA_BASE_ADDR+0x060) 36 #define PM4125_ANA_MBHC_BTN0_THRESHOLD_MASK GENMASK(7, 2) 37 #define PM4125_ANA_MBHC_BTN1_ZDET_VREF2 (PM4125_ANA_BASE_ADDR+0x061) 38 #define PM4125_ANA_MBHC_BTN2_ZDET_VREF3 (PM4125_ANA_BASE_ADDR+0x062) 39 #define PM4125_ANA_MBHC_BTN3_ZDET_DBG_400 (PM4125_ANA_BASE_ADDR+0x063) 40 #define PM4125_ANA_MBHC_BTN4_ZDET_DBG_1400 (PM4125_ANA_BASE_ADDR+0x064) 41 #define PM4125_ANA_MBHC_MICB2_RAMP (PM4125_ANA_BASE_ADDR+0x065) 42 #define PM4125_ANA_MBHC_CTL_1 (PM4125_ANA_BASE_ADDR+0x066) 43 #define PM4125_ANA_MBHC_CTL_2 (PM4125_ANA_BASE_ADDR+0x067) 44 #define PM4125_ANA_MBHC_PLUG_DETECT_CTL (PM4125_ANA_BASE_ADDR+0x068) 45 #define PM4125_ANA_MBHC_ZDET_ANA_CTL (PM4125_ANA_BASE_ADDR+0x069) 46 #define PM4125_ANA_MBHC_ZDET_RAMP_CTL (PM4125_ANA_BASE_ADDR+0x06A) 47 #define PM4125_ANA_MBHC_FSM_STATUS (PM4125_ANA_BASE_ADDR+0x06B) 48 #define PM4125_ANA_MBHC_ADC_RESULT (PM4125_ANA_BASE_ADDR+0x06C) 49 #define PM4125_ANA_MBHC_CTL_CLK (PM4125_ANA_BASE_ADDR+0x06D) 50 #define PM4125_ANA_MBHC_ZDET_CALIB_RESULT (PM4125_ANA_BASE_ADDR+0x072) 51 #define PM4125_ANA_NCP_EN (PM4125_ANA_BASE_ADDR+0x077) 52 #define PM4125_ANA_NCP_ENABLE_MASK BIT(0) 53 #define PM4125_ANA_NCP_ENABLE 1 54 #define PM4125_ANA_NCP_DISABLE 0 55 #define PM4125_ANA_NCP_VCTRL (PM4125_ANA_BASE_ADDR+0x07C) 56 #define PM4125_ANA_HPHPA_CNP_CTL_1 (PM4125_ANA_BASE_ADDR+0x083) 57 #define PM4125_ANA_HPHPA_CNP_CTL_1_EN_MASK BIT(1) 58 #define PM4125_ANA_HPHPA_CNP_CTL_1_EN 1 59 #define PM4125_ANA_HPHPA_CNP_CTL_2 (PM4125_ANA_BASE_ADDR+0x084) 60 #define PM4125_ANA_HPHPA_CNP_OCP_EN_L_MASK BIT(1) 61 #define PM4125_ANA_HPHPA_CNP_OCP_EN_R_MASK BIT(0) 62 #define PM4125_ANA_HPHPA_CNP_OCP_ENABLE 1 63 #define PM4125_ANA_HPHPA_CNP_OCP_DISABLE 0 64 #define PM4125_ANA_HPHPA_PA_STATUS (PM4125_ANA_BASE_ADDR+0x087) 65 #define PM4125_ANA_HPHPA_FSM_CLK (PM4125_ANA_BASE_ADDR+0x088) 66 #define PM4125_ANA_HPHPA_FSM_CLK_DIV_EN_MASK BIT(7) 67 #define PM4125_ANA_HPHPA_FSM_CLK_DIV_ENABLE 1 68 #define PM4125_ANA_HPHPA_FSM_CLK_DIV_DISABLE 0 69 #define PM4125_ANA_HPHPA_FSM_DIV_RATIO_MASK GENMASK(6, 0) 70 #define PM4125_ANA_HPHPA_FSM_DIV_RATIO_68 (0x11) 71 #define PM4125_ANA_HPHPA_L_GAIN (PM4125_ANA_BASE_ADDR+0x08B) 72 #define PM4125_ANA_HPHPA_R_GAIN (PM4125_ANA_BASE_ADDR+0x08C) 73 #define PM4125_ANA_HPHPA_SPARE_CTL (PM4125_ANA_BASE_ADDR+0x08E) 74 #define PM4125_SWR_HPHPA_HD2 (PM4125_ANA_BASE_ADDR+0x090) 75 #define PM4125_SWR_HPHPA_HD2_LEFT_MASK GENMASK(5, 3) 76 #define PM4125_SWR_HPHPA_HD2_RIGHT_MASK GENMASK(2, 0) 77 #define PM4125_SWR_HPHPA_HD2_ENABLE (BIT(2) | BIT(1) | BIT(0)) 78 #define PM4125_ANA_SURGE_EN (PM4125_ANA_BASE_ADDR+0x097) 79 #define PM4125_ANA_SURGE_PROTECTION_HPHL_MASK BIT(7) 80 #define PM4125_ANA_SURGE_PROTECTION_HPHR_MASK BIT(6) 81 #define PM4125_ANA_SURGE_PROTECTION_ENABLE 1 82 #define PM4125_ANA_SURGE_PROTECTION_DISABLE 0 83 #define PM4125_ANA_COMBOPA_CTL (PM4125_ANA_BASE_ADDR+0x09B) 84 #define PM4125_ANA_COMBO_PA_SELECT_MASK BIT(6) 85 #define PM4125_ANA_COMBO_PA_SELECT_EAR 0 86 #define PM4125_ANA_COMBO_PA_SELECT_LO 1 87 #define PM4125_ANA_COMBOPA_CTL_4 (PM4125_ANA_BASE_ADDR+0x09F) 88 #define PM4125_ANA_COMBOPA_CTL_5 (PM4125_ANA_BASE_ADDR+0x0A0) 89 #define PM4125_ANA_RXLDO_CTL (PM4125_ANA_BASE_ADDR+0x0B2) 90 #define PM4125_ANA_MBIAS_EN (PM4125_ANA_BASE_ADDR+0x0B4) 91 #define PM4125_ANA_MBIAS_EN_GLOBAL_MASK BIT(5) 92 #define PM4125_ANA_MBIAS_EN_V2I_MASK BIT(4) 93 #define PM4125_ANA_MBIAS_EN_ENABLE 1 94 #define PM4125_ANA_MBIAS_EN_DISABLE 0 95 96 #define PM4125_DIG_SWR_CHIP_ID0 (PM4125_DIG_BASE_ADDR+0x001) 97 #define PM4125_DIG_SWR_CHIP_ID1 (PM4125_DIG_BASE_ADDR+0x002) 98 #define PM4125_DIG_SWR_CHIP_ID2 (PM4125_DIG_BASE_ADDR+0x003) 99 #define PM4125_DIG_SWR_CHIP_ID3 (PM4125_DIG_BASE_ADDR+0x004) 100 #define PM4125_DIG_SWR_SWR_TX_CLK_RATE (PM4125_DIG_BASE_ADDR+0x040) 101 #define PM4125_DIG_SWR_CDC_RST_CTL (PM4125_DIG_BASE_ADDR+0x041) 102 #define PM4125_DIG_SWR_TOP_CLK_CFG (PM4125_DIG_BASE_ADDR+0x042) 103 #define PM4125_DIG_SWR_CDC_RX_CLK_CTL (PM4125_DIG_BASE_ADDR+0x043) 104 #define PM4125_DIG_SWR_ANA_RX_DIV2_CLK_EN_MASK BIT(5) 105 #define PM4125_DIG_SWR_ANA_RX_CLK_EN_MASK BIT(4) 106 #define PM4125_DIG_SWR_RX1_CLK_EN_MASK BIT(1) 107 #define PM4125_DIG_SWR_RX0_CLK_EN_MASK BIT(0) 108 #define PM4125_DIG_SWR_RX_CLK_ENABLE 1 109 #define PM4125_DIG_SWR_RX_CLK_DISABLE 0 110 #define PM4125_DIG_SWR_CDC_TX_CLK_CTL (PM4125_DIG_BASE_ADDR+0x044) 111 #define PM4125_DIG_SWR_SWR_RST_EN (PM4125_DIG_BASE_ADDR+0x045) 112 #define PM4125_DIG_SWR_CDC_RX_RST (PM4125_DIG_BASE_ADDR+0x047) 113 #define PM4125_DIG_SWR_CDC_RX0_CTL (PM4125_DIG_BASE_ADDR+0x048) 114 #define PM4125_DIG_SWR_DSM_DITHER_EN_MASK BIT(7) 115 #define PM4125_DIG_SWR_DSM_DITHER_DISABLE 0 116 #define PM4125_DIG_SWR_DSM_DITHER_ENABLE 1 117 #define PM4125_DIG_SWR_CDC_RX1_CTL (PM4125_DIG_BASE_ADDR+0x049) 118 #define PM4125_DIG_SWR_CDC_TX_ANA_MODE_0_1 (PM4125_DIG_BASE_ADDR+0x04B) 119 #define PM4125_DIG_SWR_TX_ANA_TXD1_MODE_MASK GENMASK(7, 4) 120 #define PM4125_DIG_SWR_TX_ANA_TXD0_MODE_MASK GENMASK(3, 0) 121 #define PM4125_DIG_SWR_TXD_MODE_ULPI (0x9) 122 #define PM4125_DIG_SWR_TXD_MODE_NORMAL (0x3) 123 #define PM4125_DIG_SWR_CDC_COMP_CTL_0 (PM4125_DIG_BASE_ADDR+0x04F) 124 #define PM4125_DIG_SWR_COMP_HPHL_EN_MASK BIT(1) 125 #define PM4125_DIG_SWR_COMP_HPHR_EN_MASK BIT(0) 126 #define PM4125_DIG_SWR_COMP_ENABLE 1 127 #define PM4125_DIG_SWR_COMP_DISABLE 0 128 #define PM4125_DIG_SWR_CDC_RX_DELAY_CTL (PM4125_DIG_BASE_ADDR+0x052) 129 #define PM4125_DIG_SWR_CDC_RX_GAIN_0 (PM4125_DIG_BASE_ADDR+0x053) 130 #define PM4125_DIG_SWR_CDC_RX_GAIN_1 (PM4125_DIG_BASE_ADDR+0x054) 131 #define PM4125_DIG_SWR_CDC_RX_GAIN_CTL (PM4125_DIG_BASE_ADDR+0x057) 132 #define PM4125_DIG_SWR_RX1_EN_MASK BIT(3) 133 #define PM4125_DIG_SWR_RX0_EN_MASK BIT(2) 134 #define PM4125_DIG_SWR_RX_INPUT_DISABLE 0 135 #define PM4125_DIG_SWR_RX_INPUT_ENABLE 1 136 #define PM4125_DIG_SWR_CDC_TX0_CTL (PM4125_DIG_BASE_ADDR+0x060) 137 #define PM4125_DIG_SWR_CDC_TX1_CTL (PM4125_DIG_BASE_ADDR+0x061) 138 #define PM4125_DIG_SWR_CDC_TX_RST (PM4125_DIG_BASE_ADDR+0x063) 139 #define PM4125_DIG_SWR_CDC_REQ0_CTL (PM4125_DIG_BASE_ADDR+0x064) 140 #define PM4125_DIG_SWR_CDC_REQ1_CTL (PM4125_DIG_BASE_ADDR+0x065) 141 #define PM4125_DIG_SWR_CDC_RST (PM4125_DIG_BASE_ADDR+0x067) 142 #define PM4125_DIG_SWR_CDC_AMIC_CTL (PM4125_DIG_BASE_ADDR+0x06A) 143 #define PM4125_DIG_SWR_AMIC_SELECT_MASK BIT(1) 144 #define PM4125_DIG_SWR_AMIC_SELECT_DMIC1 0 145 #define PM4125_DIG_SWR_AMIC_SELECT_AMIC3 1 146 #define PM4125_DIG_SWR_CDC_DMIC_CTL (PM4125_DIG_BASE_ADDR+0x06B) 147 #define PM4125_DIG_SWR_CDC_DMIC1_CTL (PM4125_DIG_BASE_ADDR+0x06C) 148 #define PM4125_DIG_SWR_DMIC1_CLK_EN_MASK BIT(3) 149 #define PM4125_DIG_SWR_DMIC1_CLK_ENABLE 1 150 #define PM4125_DIG_SWR_DMIC1_CLK_DISABLE 0 151 #define PM4125_DIG_SWR_CDC_DMIC1_RATE (PM4125_DIG_BASE_ADDR+0x06D) 152 #define PM4125_DIG_SWR_PDM_WD_CTL0 (PM4125_DIG_BASE_ADDR+0x070) 153 #define PM4125_WDT_ENABLE_MASK GENMASK(1, 0) 154 #define PM4125_WDT_ENABLE_RX0_L BIT(0) 155 #define PM4125_WDT_ENABLE_RX0_M BIT(1) 156 #define PM4125_DIG_SWR_PDM_WD_CTL1 (PM4125_DIG_BASE_ADDR+0x071) 157 #define PM4125_WDT_ENABLE_RX1_L BIT(0) 158 #define PM4125_WDT_ENABLE_RX1_M BIT(1) 159 #define PM4125_DIG_SWR_INTR_MODE (PM4125_DIG_BASE_ADDR+0x080) 160 #define PM4125_DIG_SWR_INTR_MASK_0 (PM4125_DIG_BASE_ADDR+0x081) 161 #define PM4125_DIG_SWR_INTR_MASK_1 (PM4125_DIG_BASE_ADDR+0x082) 162 #define PM4125_DIG_SWR_INTR_MASK_2 (PM4125_DIG_BASE_ADDR+0x083) 163 #define PM4125_DIG_SWR_INTR_STATUS_0 (PM4125_DIG_BASE_ADDR+0x084) 164 #define PM4125_DIG_SWR_INTR_STATUS_1 (PM4125_DIG_BASE_ADDR+0x085) 165 #define PM4125_DIG_SWR_INTR_STATUS_2 (PM4125_DIG_BASE_ADDR+0x086) 166 #define PM4125_DIG_SWR_INTR_CLEAR_0 (PM4125_DIG_BASE_ADDR+0x087) 167 #define PM4125_DIG_SWR_INTR_CLEAR_1 (PM4125_DIG_BASE_ADDR+0x088) 168 #define PM4125_DIG_SWR_INTR_CLEAR_2 (PM4125_DIG_BASE_ADDR+0x089) 169 #define PM4125_DIG_SWR_INTR_LEVEL_0 (PM4125_DIG_BASE_ADDR+0x08A) 170 #define PM4125_DIG_SWR_INTR_LEVEL_1 (PM4125_DIG_BASE_ADDR+0x08B) 171 #define PM4125_DIG_SWR_INTR_LEVEL_2 (PM4125_DIG_BASE_ADDR+0x08C) 172 #define PM4125_DIG_SWR_CDC_CONN_RX0_CTL (PM4125_DIG_BASE_ADDR+0x093) 173 #define PM4125_DIG_SWR_CDC_CONN_RX1_CTL (PM4125_DIG_BASE_ADDR+0x094) 174 #define PM4125_DIG_SWR_LOOP_BACK_MODE (PM4125_DIG_BASE_ADDR+0x097) 175 #define PM4125_DIG_SWR_DRIVE_STRENGTH_0 (PM4125_DIG_BASE_ADDR+0x0A0) 176 #define PM4125_DIG_SWR_DIG_DEBUG_CTL (PM4125_DIG_BASE_ADDR+0x0AB) 177 #define PM4125_DIG_SWR_DIG_DEBUG_EN (PM4125_DIG_BASE_ADDR+0x0AC) 178 #define PM4125_DIG_SWR_DEM_BYPASS_DATA0 (PM4125_DIG_BASE_ADDR+0x0B0) 179 #define PM4125_DIG_SWR_DEM_BYPASS_DATA1 (PM4125_DIG_BASE_ADDR+0x0B1) 180 #define PM4125_DIG_SWR_DEM_BYPASS_DATA2 (PM4125_DIG_BASE_ADDR+0x0B2) 181 #define PM4125_DIG_SWR_DEM_BYPASS_DATA3 (PM4125_DIG_BASE_ADDR+0x0B3) 182 183 #define PM4125_ANALOG_REGISTERS_MAX_SIZE (PM4125_ANA_BASE_ADDR+0x0B5) 184 #define PM4125_DIGITAL_REGISTERS_MAX_SIZE (PM4125_DIG_BASE_ADDR+0x0B4) 185 #define PM4125_ANALOG_MAX_REGISTER (PM4125_ANALOG_REGISTERS_MAX_SIZE - 1) 186 #define PM4125_DIGITAL_MAX_REGISTER (PM4125_DIGITAL_REGISTERS_MAX_SIZE - 1) 187 #define PM4125_MAX_REGISTER PM4125_DIGITAL_MAX_REGISTER 188 189 #define PM4125_MAX_MICBIAS 3 190 #define PM4125_MAX_SWR_CH_IDS 15 191 #define PM4125_SWRM_CH_MASK(ch_idx) BIT(ch_idx - 1) 192 193 enum pm4125_tx_sdw_ports { 194 PM4125_ADC_1_2_DMIC1L_BCS_PORT = 1, 195 PM4125_DMIC_1L_1R_ADC1_BCS_PORT, 196 PM4125_MAX_TX_SWR_PORTS = PM4125_DMIC_1L_1R_ADC1_BCS_PORT, 197 }; 198 199 enum pm4125_rx_sdw_ports { 200 PM4125_HPH_PORT = 1, 201 PM4125_COMP_PORT, 202 PM4125_MAX_SWR_PORTS = PM4125_COMP_PORT, 203 }; 204 205 struct pm4125_sdw_ch_info { 206 int port_num; 207 unsigned int ch_mask; 208 unsigned int master_ch_mask; 209 }; 210 211 #define WCD_SDW_CH(id, pn, cmask) \ 212 [id] = { \ 213 .port_num = pn, \ 214 .ch_mask = cmask, \ 215 .master_ch_mask = cmask, \ 216 } 217 218 struct pm4125_priv; 219 struct pm4125_sdw_priv { 220 struct sdw_slave *sdev; 221 struct sdw_stream_config sconfig; 222 struct sdw_stream_runtime *sruntime; 223 struct sdw_port_config port_config[PM4125_MAX_SWR_PORTS]; 224 struct pm4125_sdw_ch_info *ch_info; 225 bool port_enable[PM4125_MAX_SWR_CH_IDS]; 226 unsigned int master_channel_map[SDW_MAX_PORTS]; 227 int active_ports; 228 int num_ports; 229 bool is_tx; 230 struct pm4125_priv *pm4125; 231 struct irq_domain *slave_irq; 232 struct regmap *regmap; 233 }; 234 235 #if IS_ENABLED(CONFIG_SND_SOC_PM4125_SDW) 236 int pm4125_sdw_free(struct pm4125_sdw_priv *pm4125, struct snd_pcm_substream *substream, 237 struct snd_soc_dai *dai); 238 int pm4125_sdw_set_sdw_stream(struct pm4125_sdw_priv *pm4125, struct snd_soc_dai *dai, void *stream, 239 int direction); 240 int pm4125_sdw_hw_params(struct pm4125_sdw_priv *pm4125, struct snd_pcm_substream *substream, 241 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai); 242 243 struct device *pm4125_sdw_device_get(struct device_node *np); 244 245 #else 246 static inline int pm4125_sdw_free(struct pm4125_sdw_priv *pm4125, 247 struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 248 { 249 return -EOPNOTSUPP; 250 } 251 252 static inline int pm4125_sdw_set_sdw_stream(struct pm4125_sdw_priv *pm4125, 253 struct snd_soc_dai *dai, void *stream, int direction) 254 { 255 return -EOPNOTSUPP; 256 } 257 258 static inline int pm4125_sdw_hw_params(struct pm4125_sdw_priv *pm4125, 259 struct snd_pcm_substream *substream, 260 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 261 { 262 return -EOPNOTSUPP; 263 } 264 #endif 265 266 enum { 267 /* INTR_CTRL_INT_MASK_0 */ 268 PM4125_IRQ_MBHC_BUTTON_PRESS_DET = 0, 269 PM4125_IRQ_MBHC_BUTTON_RELEASE_DET, 270 PM4125_IRQ_MBHC_ELECT_INS_REM_DET, 271 PM4125_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 272 PM4125_IRQ_MBHC_SW_DET, 273 PM4125_IRQ_HPHR_OCP_INT, 274 PM4125_IRQ_HPHR_CNP_INT, 275 PM4125_IRQ_HPHL_OCP_INT, 276 277 /* INTR_CTRL_INT_MASK_1 */ 278 PM4125_IRQ_HPHL_CNP_INT, 279 PM4125_IRQ_EAR_CNP_INT, 280 PM4125_IRQ_EAR_SCD_INT, 281 PM4125_IRQ_AUX_CNP_INT, 282 PM4125_IRQ_AUX_SCD_INT, 283 PM4125_IRQ_HPHL_PDM_WD_INT, 284 PM4125_IRQ_HPHR_PDM_WD_INT, 285 PM4125_IRQ_AUX_PDM_WD_INT, 286 287 /* INTR_CTRL_INT_MASK_2 */ 288 PM4125_IRQ_LDORT_SCD_INT, 289 PM4125_IRQ_MBHC_MOISTURE_INT, 290 PM4125_IRQ_HPHL_SURGE_DET_INT, 291 PM4125_IRQ_HPHR_SURGE_DET_INT, 292 PM4125_NUM_IRQS, 293 }; 294 295 enum pm4125_tx_sdw_channels { 296 PM4125_ADC1, 297 PM4125_ADC2, 298 }; 299 300 enum pm4125_rx_sdw_channels { 301 PM4125_HPH_L, 302 PM4125_HPH_R, 303 PM4125_COMP_L, 304 PM4125_COMP_R, 305 }; 306 307 #endif /* _PM4125_REGISTERS_H */ 308