1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 // Copyright, 2025 Linaro Ltd 4 5 #include <linux/component.h> 6 #include <linux/device.h> 7 #include <linux/irq.h> 8 #include <linux/irqdomain.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/soundwire/sdw.h> 17 #include <linux/soundwire/sdw_registers.h> 18 #include <linux/soundwire/sdw_type.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/soc.h> 21 #include "pm4125.h" 22 23 static struct pm4125_sdw_ch_info pm4125_sdw_rx_ch_info[] = { 24 WCD_SDW_CH(PM4125_HPH_L, PM4125_HPH_PORT, BIT(0)), 25 WCD_SDW_CH(PM4125_HPH_R, PM4125_HPH_PORT, BIT(1)), 26 }; 27 28 static struct pm4125_sdw_ch_info pm4125_sdw_tx_ch_info[] = { 29 WCD_SDW_CH(PM4125_ADC1, PM4125_ADC_1_2_DMIC1L_BCS_PORT, BIT(0)), 30 WCD_SDW_CH(PM4125_ADC2, PM4125_ADC_1_2_DMIC1L_BCS_PORT, BIT(1)), 31 }; 32 33 static struct sdw_dpn_prop pm4125_dpn_prop[PM4125_MAX_SWR_PORTS] = { 34 { 35 .num = 1, 36 .type = SDW_DPN_SIMPLE, 37 .min_ch = 1, 38 .max_ch = 8, 39 .simple_ch_prep_sm = true, 40 }, { 41 .num = 2, 42 .type = SDW_DPN_SIMPLE, 43 .min_ch = 1, 44 .max_ch = 4, 45 .simple_ch_prep_sm = true, 46 } 47 }; 48 49 struct device *pm4125_sdw_device_get(struct device_node *np) 50 { 51 return bus_find_device_by_of_node(&sdw_bus_type, np); 52 } 53 EXPORT_SYMBOL_GPL(pm4125_sdw_device_get); 54 55 int pm4125_sdw_hw_params(struct pm4125_sdw_priv *priv, struct snd_pcm_substream *substream, 56 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 57 { 58 struct sdw_port_config port_config[PM4125_MAX_SWR_PORTS]; 59 unsigned long ch_mask; 60 int i, j; 61 62 priv->sconfig.ch_count = 1; 63 priv->active_ports = 0; 64 for (i = 0; i < PM4125_MAX_SWR_PORTS; i++) { 65 ch_mask = priv->port_config[i].ch_mask; 66 if (!ch_mask) 67 continue; 68 69 for_each_set_bit(j, &ch_mask, 4) 70 priv->sconfig.ch_count++; 71 72 port_config[priv->active_ports] = priv->port_config[i]; 73 priv->active_ports++; 74 } 75 76 priv->sconfig.bps = 1; 77 priv->sconfig.frame_rate = params_rate(params); 78 priv->sconfig.direction = priv->is_tx ? SDW_DATA_DIR_TX : SDW_DATA_DIR_RX; 79 priv->sconfig.type = SDW_STREAM_PCM; 80 81 return sdw_stream_add_slave(priv->sdev, &priv->sconfig, &port_config[0], priv->active_ports, 82 priv->sruntime); 83 } 84 EXPORT_SYMBOL_GPL(pm4125_sdw_hw_params); 85 86 static int pm4125_update_status(struct sdw_slave *slave, enum sdw_slave_status status) 87 { 88 struct pm4125_sdw_priv *priv = dev_get_drvdata(&slave->dev); 89 90 if (priv->regmap && status == SDW_SLAVE_ATTACHED) { 91 /* Write out any cached changes that happened between probe and attach */ 92 regcache_cache_only(priv->regmap, false); 93 return regcache_sync(priv->regmap); 94 } 95 96 return 0; 97 } 98 99 /* 100 * Handle Soundwire out-of-band interrupt event by triggering the first irq of the slave_irq 101 * irq domain, which then will be handled by the regmap_irq threaded irq. 102 * Looping is to ensure no interrupts were missed in the process. 103 */ 104 static int pm4125_interrupt_callback(struct sdw_slave *slave, struct sdw_slave_intr_status *status) 105 { 106 struct pm4125_sdw_priv *priv = dev_get_drvdata(&slave->dev); 107 struct irq_domain *slave_irq = priv->slave_irq; 108 u32 sts1, sts2, sts3; 109 110 do { 111 handle_nested_irq(irq_find_mapping(slave_irq, 0)); 112 regmap_read(priv->regmap, PM4125_DIG_SWR_INTR_STATUS_0, &sts1); 113 regmap_read(priv->regmap, PM4125_DIG_SWR_INTR_STATUS_1, &sts2); 114 regmap_read(priv->regmap, PM4125_DIG_SWR_INTR_STATUS_2, &sts3); 115 116 } while (sts1 || sts2 || sts3); 117 118 return IRQ_HANDLED; 119 } 120 121 static const struct reg_default pm4125_defaults[] = { 122 { PM4125_ANA_MICBIAS_MICB_1_2_EN, 0x01 }, 123 { PM4125_ANA_MICBIAS_MICB_3_EN, 0x00 }, 124 { PM4125_ANA_MICBIAS_LDO_1_SETTING, 0x21 }, 125 { PM4125_ANA_MICBIAS_LDO_1_CTRL, 0x01 }, 126 { PM4125_ANA_TX_AMIC1, 0x00 }, 127 { PM4125_ANA_TX_AMIC2, 0x00 }, 128 { PM4125_ANA_MBHC_MECH, 0x39 }, 129 { PM4125_ANA_MBHC_ELECT, 0x08 }, 130 { PM4125_ANA_MBHC_ZDET, 0x10 }, 131 { PM4125_ANA_MBHC_RESULT_1, 0x00 }, 132 { PM4125_ANA_MBHC_RESULT_2, 0x00 }, 133 { PM4125_ANA_MBHC_RESULT_3, 0x00 }, 134 { PM4125_ANA_MBHC_BTN0_ZDET_VREF1, 0x00 }, 135 { PM4125_ANA_MBHC_BTN1_ZDET_VREF2, 0x10 }, 136 { PM4125_ANA_MBHC_BTN2_ZDET_VREF3, 0x20 }, 137 { PM4125_ANA_MBHC_BTN3_ZDET_DBG_400, 0x30 }, 138 { PM4125_ANA_MBHC_BTN4_ZDET_DBG_1400, 0x40 }, 139 { PM4125_ANA_MBHC_MICB2_RAMP, 0x00 }, 140 { PM4125_ANA_MBHC_CTL_1, 0x02 }, 141 { PM4125_ANA_MBHC_CTL_2, 0x05 }, 142 { PM4125_ANA_MBHC_PLUG_DETECT_CTL, 0xE9 }, 143 { PM4125_ANA_MBHC_ZDET_ANA_CTL, 0x0F }, 144 { PM4125_ANA_MBHC_ZDET_RAMP_CTL, 0x00 }, 145 { PM4125_ANA_MBHC_FSM_STATUS, 0x00 }, 146 { PM4125_ANA_MBHC_ADC_RESULT, 0x00 }, 147 { PM4125_ANA_MBHC_CTL_CLK, 0x30 }, 148 { PM4125_ANA_MBHC_ZDET_CALIB_RESULT, 0x00 }, 149 { PM4125_ANA_NCP_EN, 0x00 }, 150 { PM4125_ANA_NCP_VCTRL, 0xA7 }, 151 { PM4125_ANA_HPHPA_CNP_CTL_1, 0x54 }, 152 { PM4125_ANA_HPHPA_CNP_CTL_2, 0x2B }, 153 { PM4125_ANA_HPHPA_PA_STATUS, 0x00 }, 154 { PM4125_ANA_HPHPA_FSM_CLK, 0x12 }, 155 { PM4125_ANA_HPHPA_L_GAIN, 0x00 }, 156 { PM4125_ANA_HPHPA_R_GAIN, 0x00 }, 157 { PM4125_SWR_HPHPA_HD2, 0x1B }, 158 { PM4125_ANA_HPHPA_SPARE_CTL, 0x02 }, 159 { PM4125_ANA_SURGE_EN, 0x38 }, 160 { PM4125_ANA_COMBOPA_CTL, 0x35 }, 161 { PM4125_ANA_COMBOPA_CTL_4, 0x84 }, 162 { PM4125_ANA_COMBOPA_CTL_5, 0x05 }, 163 { PM4125_ANA_RXLDO_CTL, 0x86 }, 164 { PM4125_ANA_MBIAS_EN, 0x00 }, 165 { PM4125_DIG_SWR_CHIP_ID0, 0x00 }, 166 { PM4125_DIG_SWR_CHIP_ID1, 0x00 }, 167 { PM4125_DIG_SWR_CHIP_ID2, 0x0C }, 168 { PM4125_DIG_SWR_CHIP_ID3, 0x01 }, 169 { PM4125_DIG_SWR_SWR_TX_CLK_RATE, 0x00 }, 170 { PM4125_DIG_SWR_CDC_RST_CTL, 0x03 }, 171 { PM4125_DIG_SWR_TOP_CLK_CFG, 0x00 }, 172 { PM4125_DIG_SWR_CDC_RX_CLK_CTL, 0x00 }, 173 { PM4125_DIG_SWR_CDC_TX_CLK_CTL, 0x33 }, 174 { PM4125_DIG_SWR_SWR_RST_EN, 0x00 }, 175 { PM4125_DIG_SWR_CDC_RX_RST, 0x00 }, 176 { PM4125_DIG_SWR_CDC_RX0_CTL, 0xFC }, 177 { PM4125_DIG_SWR_CDC_RX1_CTL, 0xFC }, 178 { PM4125_DIG_SWR_CDC_TX_ANA_MODE_0_1, 0x00 }, 179 { PM4125_DIG_SWR_CDC_COMP_CTL_0, 0x00 }, 180 { PM4125_DIG_SWR_CDC_RX_DELAY_CTL, 0x66 }, 181 { PM4125_DIG_SWR_CDC_RX_GAIN_0, 0x55 }, 182 { PM4125_DIG_SWR_CDC_RX_GAIN_1, 0xA9 }, 183 { PM4125_DIG_SWR_CDC_RX_GAIN_CTL, 0x00 }, 184 { PM4125_DIG_SWR_CDC_TX0_CTL, 0x68 }, 185 { PM4125_DIG_SWR_CDC_TX1_CTL, 0x68 }, 186 { PM4125_DIG_SWR_CDC_TX_RST, 0x00 }, 187 { PM4125_DIG_SWR_CDC_REQ0_CTL, 0x01 }, 188 { PM4125_DIG_SWR_CDC_REQ1_CTL, 0x01 }, 189 { PM4125_DIG_SWR_CDC_RST, 0x00 }, 190 { PM4125_DIG_SWR_CDC_AMIC_CTL, 0x02 }, 191 { PM4125_DIG_SWR_CDC_DMIC_CTL, 0x00 }, 192 { PM4125_DIG_SWR_CDC_DMIC1_CTL, 0x00 }, 193 { PM4125_DIG_SWR_CDC_DMIC1_RATE, 0x01 }, 194 { PM4125_DIG_SWR_PDM_WD_CTL0, 0x00 }, 195 { PM4125_DIG_SWR_PDM_WD_CTL1, 0x00 }, 196 { PM4125_DIG_SWR_INTR_MODE, 0x00 }, 197 { PM4125_DIG_SWR_INTR_MASK_0, 0xFF }, 198 { PM4125_DIG_SWR_INTR_MASK_1, 0x7F }, 199 { PM4125_DIG_SWR_INTR_MASK_2, 0x0C }, 200 { PM4125_DIG_SWR_INTR_STATUS_0, 0x00 }, 201 { PM4125_DIG_SWR_INTR_STATUS_1, 0x00 }, 202 { PM4125_DIG_SWR_INTR_STATUS_2, 0x00 }, 203 { PM4125_DIG_SWR_INTR_CLEAR_0, 0x00 }, 204 { PM4125_DIG_SWR_INTR_CLEAR_1, 0x00 }, 205 { PM4125_DIG_SWR_INTR_CLEAR_2, 0x00 }, 206 { PM4125_DIG_SWR_INTR_LEVEL_0, 0x00 }, 207 { PM4125_DIG_SWR_INTR_LEVEL_1, 0x2A }, 208 { PM4125_DIG_SWR_INTR_LEVEL_2, 0x00 }, 209 { PM4125_DIG_SWR_CDC_CONN_RX0_CTL, 0x00 }, 210 { PM4125_DIG_SWR_CDC_CONN_RX1_CTL, 0x00 }, 211 { PM4125_DIG_SWR_LOOP_BACK_MODE, 0x00 }, 212 { PM4125_DIG_SWR_DRIVE_STRENGTH_0, 0x00 }, 213 { PM4125_DIG_SWR_DIG_DEBUG_CTL, 0x00 }, 214 { PM4125_DIG_SWR_DIG_DEBUG_EN, 0x00 }, 215 { PM4125_DIG_SWR_DEM_BYPASS_DATA0, 0x55 }, 216 { PM4125_DIG_SWR_DEM_BYPASS_DATA1, 0x55 }, 217 { PM4125_DIG_SWR_DEM_BYPASS_DATA2, 0x55 }, 218 { PM4125_DIG_SWR_DEM_BYPASS_DATA3, 0x01 }, 219 }; 220 221 static bool pm4125_rdwr_register(struct device *dev, unsigned int reg) 222 { 223 switch (reg) { 224 case PM4125_ANA_MICBIAS_MICB_1_2_EN: 225 case PM4125_ANA_MICBIAS_MICB_3_EN: 226 case PM4125_ANA_MICBIAS_LDO_1_SETTING: 227 case PM4125_ANA_MICBIAS_LDO_1_CTRL: 228 case PM4125_ANA_TX_AMIC1: 229 case PM4125_ANA_TX_AMIC2: 230 case PM4125_ANA_MBHC_MECH: 231 case PM4125_ANA_MBHC_ELECT: 232 case PM4125_ANA_MBHC_ZDET: 233 case PM4125_ANA_MBHC_BTN0_ZDET_VREF1: 234 case PM4125_ANA_MBHC_BTN1_ZDET_VREF2: 235 case PM4125_ANA_MBHC_BTN2_ZDET_VREF3: 236 case PM4125_ANA_MBHC_BTN3_ZDET_DBG_400: 237 case PM4125_ANA_MBHC_BTN4_ZDET_DBG_1400: 238 case PM4125_ANA_MBHC_MICB2_RAMP: 239 case PM4125_ANA_MBHC_CTL_1: 240 case PM4125_ANA_MBHC_CTL_2: 241 case PM4125_ANA_MBHC_PLUG_DETECT_CTL: 242 case PM4125_ANA_MBHC_ZDET_ANA_CTL: 243 case PM4125_ANA_MBHC_ZDET_RAMP_CTL: 244 case PM4125_ANA_MBHC_CTL_CLK: 245 case PM4125_ANA_NCP_EN: 246 case PM4125_ANA_NCP_VCTRL: 247 case PM4125_ANA_HPHPA_CNP_CTL_1: 248 case PM4125_ANA_HPHPA_CNP_CTL_2: 249 case PM4125_ANA_HPHPA_FSM_CLK: 250 case PM4125_ANA_HPHPA_L_GAIN: 251 case PM4125_ANA_HPHPA_R_GAIN: 252 case PM4125_ANA_HPHPA_SPARE_CTL: 253 case PM4125_SWR_HPHPA_HD2: 254 case PM4125_ANA_SURGE_EN: 255 case PM4125_ANA_COMBOPA_CTL: 256 case PM4125_ANA_COMBOPA_CTL_4: 257 case PM4125_ANA_COMBOPA_CTL_5: 258 case PM4125_ANA_RXLDO_CTL: 259 case PM4125_ANA_MBIAS_EN: 260 case PM4125_DIG_SWR_SWR_TX_CLK_RATE: 261 case PM4125_DIG_SWR_CDC_RST_CTL: 262 case PM4125_DIG_SWR_TOP_CLK_CFG: 263 case PM4125_DIG_SWR_CDC_RX_CLK_CTL: 264 case PM4125_DIG_SWR_CDC_TX_CLK_CTL: 265 case PM4125_DIG_SWR_SWR_RST_EN: 266 case PM4125_DIG_SWR_CDC_RX_RST: 267 case PM4125_DIG_SWR_CDC_RX0_CTL: 268 case PM4125_DIG_SWR_CDC_RX1_CTL: 269 case PM4125_DIG_SWR_CDC_TX_ANA_MODE_0_1: 270 case PM4125_DIG_SWR_CDC_COMP_CTL_0: 271 case PM4125_DIG_SWR_CDC_RX_DELAY_CTL: 272 case PM4125_DIG_SWR_CDC_RX_GAIN_0: 273 case PM4125_DIG_SWR_CDC_RX_GAIN_1: 274 case PM4125_DIG_SWR_CDC_RX_GAIN_CTL: 275 case PM4125_DIG_SWR_CDC_TX0_CTL: 276 case PM4125_DIG_SWR_CDC_TX1_CTL: 277 case PM4125_DIG_SWR_CDC_TX_RST: 278 case PM4125_DIG_SWR_CDC_REQ0_CTL: 279 case PM4125_DIG_SWR_CDC_REQ1_CTL: 280 case PM4125_DIG_SWR_CDC_RST: 281 case PM4125_DIG_SWR_CDC_AMIC_CTL: 282 case PM4125_DIG_SWR_CDC_DMIC_CTL: 283 case PM4125_DIG_SWR_CDC_DMIC1_CTL: 284 case PM4125_DIG_SWR_CDC_DMIC1_RATE: 285 case PM4125_DIG_SWR_PDM_WD_CTL0: 286 case PM4125_DIG_SWR_PDM_WD_CTL1: 287 case PM4125_DIG_SWR_INTR_MODE: 288 case PM4125_DIG_SWR_INTR_MASK_0: 289 case PM4125_DIG_SWR_INTR_MASK_1: 290 case PM4125_DIG_SWR_INTR_MASK_2: 291 case PM4125_DIG_SWR_INTR_CLEAR_0: 292 case PM4125_DIG_SWR_INTR_CLEAR_1: 293 case PM4125_DIG_SWR_INTR_CLEAR_2: 294 case PM4125_DIG_SWR_INTR_LEVEL_0: 295 case PM4125_DIG_SWR_INTR_LEVEL_1: 296 case PM4125_DIG_SWR_INTR_LEVEL_2: 297 case PM4125_DIG_SWR_CDC_CONN_RX0_CTL: 298 case PM4125_DIG_SWR_CDC_CONN_RX1_CTL: 299 case PM4125_DIG_SWR_LOOP_BACK_MODE: 300 case PM4125_DIG_SWR_DRIVE_STRENGTH_0: 301 case PM4125_DIG_SWR_DIG_DEBUG_CTL: 302 case PM4125_DIG_SWR_DIG_DEBUG_EN: 303 case PM4125_DIG_SWR_DEM_BYPASS_DATA0: 304 case PM4125_DIG_SWR_DEM_BYPASS_DATA1: 305 case PM4125_DIG_SWR_DEM_BYPASS_DATA2: 306 case PM4125_DIG_SWR_DEM_BYPASS_DATA3: 307 return true; 308 } 309 310 return false; 311 } 312 313 static bool pm4125_readable_register(struct device *dev, unsigned int reg) 314 { 315 switch (reg) { 316 case PM4125_ANA_MBHC_RESULT_1: 317 case PM4125_ANA_MBHC_RESULT_2: 318 case PM4125_ANA_MBHC_RESULT_3: 319 case PM4125_ANA_MBHC_FSM_STATUS: 320 case PM4125_ANA_MBHC_ADC_RESULT: 321 case PM4125_ANA_MBHC_ZDET_CALIB_RESULT: 322 case PM4125_ANA_HPHPA_PA_STATUS: 323 case PM4125_DIG_SWR_CHIP_ID0: 324 case PM4125_DIG_SWR_CHIP_ID1: 325 case PM4125_DIG_SWR_CHIP_ID2: 326 case PM4125_DIG_SWR_CHIP_ID3: 327 case PM4125_DIG_SWR_INTR_STATUS_0: 328 case PM4125_DIG_SWR_INTR_STATUS_1: 329 case PM4125_DIG_SWR_INTR_STATUS_2: 330 return true; 331 } 332 return pm4125_rdwr_register(dev, reg); 333 } 334 335 static bool pm4125_volatile_register(struct device *dev, unsigned int reg) 336 { 337 switch (reg) { 338 case PM4125_ANA_MBHC_RESULT_1: 339 case PM4125_ANA_MBHC_RESULT_2: 340 case PM4125_ANA_MBHC_RESULT_3: 341 case PM4125_ANA_MBHC_FSM_STATUS: 342 case PM4125_ANA_MBHC_ADC_RESULT: 343 case PM4125_ANA_MBHC_ZDET_CALIB_RESULT: 344 case PM4125_ANA_HPHPA_PA_STATUS: 345 case PM4125_DIG_SWR_CHIP_ID0: 346 case PM4125_DIG_SWR_CHIP_ID1: 347 case PM4125_DIG_SWR_CHIP_ID2: 348 case PM4125_DIG_SWR_CHIP_ID3: 349 case PM4125_DIG_SWR_INTR_STATUS_0: 350 case PM4125_DIG_SWR_INTR_STATUS_1: 351 case PM4125_DIG_SWR_INTR_STATUS_2: 352 return true; 353 } 354 355 return false; 356 } 357 358 static const struct regmap_config pm4125_regmap_config = { 359 .name = "pm4125_csr", 360 .reg_bits = 32, 361 .val_bits = 8, 362 .cache_type = REGCACHE_MAPLE, 363 .reg_defaults = pm4125_defaults, 364 .num_reg_defaults = ARRAY_SIZE(pm4125_defaults), 365 .max_register = PM4125_MAX_REGISTER, 366 .readable_reg = pm4125_readable_register, 367 .writeable_reg = pm4125_rdwr_register, 368 .volatile_reg = pm4125_volatile_register, 369 }; 370 371 static const struct sdw_slave_ops pm4125_slave_ops = { 372 .update_status = pm4125_update_status, 373 .interrupt_callback = pm4125_interrupt_callback, 374 }; 375 376 static int pm4125_sdw_component_bind(struct device *dev, struct device *master, void *data) 377 { 378 pm_runtime_set_autosuspend_delay(dev, 3000); 379 pm_runtime_use_autosuspend(dev); 380 pm_runtime_set_active(dev); 381 pm_runtime_enable(dev); 382 383 return 0; 384 } 385 386 static void pm4125_sdw_component_unbind(struct device *dev, struct device *master, void *data) 387 { 388 pm_runtime_disable(dev); 389 pm_runtime_set_suspended(dev); 390 pm_runtime_dont_use_autosuspend(dev); 391 } 392 393 static const struct component_ops pm4125_sdw_component_ops = { 394 .bind = pm4125_sdw_component_bind, 395 .unbind = pm4125_sdw_component_unbind, 396 }; 397 398 static int pm4125_probe(struct sdw_slave *pdev, const struct sdw_device_id *id) 399 { 400 struct device *dev = &pdev->dev; 401 struct pm4125_sdw_priv *priv; 402 u8 master_ch_mask[PM4125_MAX_SWR_CH_IDS]; 403 int master_ch_mask_size = 0; 404 int ret, i; 405 406 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 407 if (!priv) 408 return -ENOMEM; 409 410 /* Port map index starts at 0, however the data port for this codec starts at index 1 */ 411 if (of_property_present(dev->of_node, "qcom,tx-port-mapping")) { 412 priv->is_tx = true; 413 ret = of_property_read_u32_array(dev->of_node, "qcom,tx-port-mapping", 414 &pdev->m_port_map[1], PM4125_MAX_TX_SWR_PORTS); 415 } else { 416 ret = of_property_read_u32_array(dev->of_node, "qcom,rx-port-mapping", 417 &pdev->m_port_map[1], PM4125_MAX_SWR_PORTS); 418 } 419 420 if (ret < 0) 421 dev_info(dev, "Error getting static port mapping for %s (%d)\n", 422 priv->is_tx ? "TX" : "RX", ret); 423 424 priv->sdev = pdev; 425 dev_set_drvdata(dev, priv); 426 427 pdev->prop.scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | 428 SDW_SCP_INT1_BUS_CLASH | 429 SDW_SCP_INT1_PARITY; 430 pdev->prop.lane_control_support = true; 431 pdev->prop.simple_clk_stop_capable = true; 432 433 memset(master_ch_mask, 0, PM4125_MAX_SWR_CH_IDS); 434 435 if (priv->is_tx) { 436 master_ch_mask_size = of_property_count_u8_elems(dev->of_node, 437 "qcom,tx-channel-mapping"); 438 439 if (master_ch_mask_size) 440 ret = of_property_read_u8_array(dev->of_node, "qcom,tx-channel-mapping", 441 master_ch_mask, master_ch_mask_size); 442 } else { 443 master_ch_mask_size = of_property_count_u8_elems(dev->of_node, 444 "qcom,rx-channel-mapping"); 445 446 if (master_ch_mask_size) 447 ret = of_property_read_u8_array(dev->of_node, "qcom,rx-channel-mapping", 448 master_ch_mask, master_ch_mask_size); 449 } 450 451 if (ret < 0) 452 dev_info(dev, "Static channel mapping not specified using device channel maps\n"); 453 454 if (priv->is_tx) { 455 pdev->prop.source_ports = GENMASK(PM4125_MAX_TX_SWR_PORTS, 0); 456 pdev->prop.src_dpn_prop = pm4125_dpn_prop; 457 priv->ch_info = &pm4125_sdw_tx_ch_info[0]; 458 459 for (i = 0; i < master_ch_mask_size; i++) 460 priv->ch_info[i].master_ch_mask = PM4125_SWRM_CH_MASK(master_ch_mask[i]); 461 462 pdev->prop.wake_capable = true; 463 464 priv->regmap = devm_regmap_init_sdw(pdev, &pm4125_regmap_config); 465 if (IS_ERR(priv->regmap)) 466 return dev_err_probe(dev, PTR_ERR(priv->regmap), "regmap init failed\n"); 467 468 /* Start in cache-only until device is enumerated */ 469 regcache_cache_only(priv->regmap, true); 470 } else { 471 pdev->prop.sink_ports = GENMASK(PM4125_MAX_SWR_PORTS - 1, 0); 472 pdev->prop.sink_dpn_prop = pm4125_dpn_prop; 473 priv->ch_info = &pm4125_sdw_rx_ch_info[0]; 474 475 for (i = 0; i < master_ch_mask_size; i++) 476 priv->ch_info[i].master_ch_mask = PM4125_SWRM_CH_MASK(master_ch_mask[i]); 477 } 478 479 ret = component_add(dev, &pm4125_sdw_component_ops); 480 if (ret) 481 return ret; 482 483 /* Set suspended until aggregate device is bind */ 484 pm_runtime_set_suspended(dev); 485 486 return 0; 487 } 488 489 static int pm4125_remove(struct sdw_slave *pdev) 490 { 491 struct device *dev = &pdev->dev; 492 493 component_del(dev, &pm4125_sdw_component_ops); 494 495 return 0; 496 } 497 498 static const struct sdw_device_id pm4125_slave_id[] = { 499 SDW_SLAVE_ENTRY(0x0217, 0x10c, 0), /* Soundwire pm4125 RX/TX Device ID */ 500 { } 501 }; 502 MODULE_DEVICE_TABLE(sdw, pm4125_slave_id); 503 504 static int __maybe_unused pm4125_sdw_runtime_suspend(struct device *dev) 505 { 506 struct pm4125_sdw_priv *priv = dev_get_drvdata(dev); 507 508 if (priv->regmap) { 509 regcache_cache_only(priv->regmap, true); 510 regcache_mark_dirty(priv->regmap); 511 } 512 513 return 0; 514 } 515 516 static int __maybe_unused pm4125_sdw_runtime_resume(struct device *dev) 517 { 518 struct pm4125_sdw_priv *priv = dev_get_drvdata(dev); 519 520 if (priv->regmap) { 521 regcache_cache_only(priv->regmap, false); 522 regcache_sync(priv->regmap); 523 } 524 525 return 0; 526 } 527 528 static const struct dev_pm_ops pm4125_sdw_pm_ops = { 529 SET_RUNTIME_PM_OPS(pm4125_sdw_runtime_suspend, pm4125_sdw_runtime_resume, NULL) 530 }; 531 532 static struct sdw_driver pm4125_codec_driver = { 533 .probe = pm4125_probe, 534 .remove = pm4125_remove, 535 .ops = &pm4125_slave_ops, 536 .id_table = pm4125_slave_id, 537 .driver = { 538 .name = "pm4125-codec", 539 .pm = &pm4125_sdw_pm_ops, 540 } 541 }; 542 module_sdw_driver(pm4125_codec_driver); 543 544 MODULE_DESCRIPTION("PM4125 SDW codec driver"); 545 MODULE_LICENSE("GPL"); 546