1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the PCM512x CODECs 4 * 5 * Author: Mark Brown <broonie@kernel.org> 6 * Copyright 2014 Linaro Ltd 7 */ 8 9 10 #include <linux/init.h> 11 #include <linux/module.h> 12 #include <linux/clk.h> 13 #include <linux/kernel.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/gcd.h> 18 #include <sound/soc.h> 19 #include <sound/soc-dapm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/tlv.h> 22 23 #include "pcm512x.h" 24 25 #define PCM512x_NUM_SUPPLIES 3 26 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { 27 "AVDD", 28 "DVDD", 29 "CPVDD", 30 }; 31 32 struct pcm512x_priv { 33 struct regmap *regmap; 34 struct clk *sclk; 35 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; 36 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; 37 int fmt; 38 int pll_in; 39 int pll_out; 40 int pll_r; 41 int pll_j; 42 int pll_d; 43 int pll_p; 44 unsigned long real_pll; 45 unsigned long overclock_pll; 46 unsigned long overclock_dac; 47 unsigned long overclock_dsp; 48 int mute; 49 struct mutex mutex; 50 unsigned int bclk_ratio; 51 int force_pll_on; 52 }; 53 54 /* 55 * We can't use the same notifier block for more than one supply and 56 * there's no way I can see to get from a callback to the caller 57 * except container_of(). 58 */ 59 #define PCM512x_REGULATOR_EVENT(n) \ 60 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ 61 unsigned long event, void *data) \ 62 { \ 63 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ 64 supply_nb[n]); \ 65 if (event & REGULATOR_EVENT_DISABLE) { \ 66 regcache_mark_dirty(pcm512x->regmap); \ 67 regcache_cache_only(pcm512x->regmap, true); \ 68 } \ 69 return 0; \ 70 } 71 72 PCM512x_REGULATOR_EVENT(0) 73 PCM512x_REGULATOR_EVENT(1) 74 PCM512x_REGULATOR_EVENT(2) 75 76 static const struct reg_default pcm512x_reg_defaults[] = { 77 { PCM512x_RESET, 0x00 }, 78 { PCM512x_POWER, 0x00 }, 79 { PCM512x_MUTE, 0x00 }, 80 { PCM512x_DSP, 0x00 }, 81 { PCM512x_PLL_REF, 0x00 }, 82 { PCM512x_DAC_REF, 0x00 }, 83 { PCM512x_DAC_ROUTING, 0x11 }, 84 { PCM512x_DSP_PROGRAM, 0x01 }, 85 { PCM512x_CLKDET, 0x00 }, 86 { PCM512x_AUTO_MUTE, 0x00 }, 87 { PCM512x_ERROR_DETECT, 0x00 }, 88 { PCM512x_DIGITAL_VOLUME_1, 0x00 }, 89 { PCM512x_DIGITAL_VOLUME_2, 0x30 }, 90 { PCM512x_DIGITAL_VOLUME_3, 0x30 }, 91 { PCM512x_DIGITAL_MUTE_1, 0x22 }, 92 { PCM512x_DIGITAL_MUTE_2, 0x00 }, 93 { PCM512x_DIGITAL_MUTE_3, 0x07 }, 94 { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, 95 { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, 96 { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, 97 { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, 98 { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, 99 { PCM512x_VCOM_CTRL_1, 0x00 }, 100 { PCM512x_VCOM_CTRL_2, 0x01 }, 101 { PCM512x_BCLK_LRCLK_CFG, 0x00 }, 102 { PCM512x_MASTER_MODE, 0x7c }, 103 { PCM512x_GPIO_DACIN, 0x00 }, 104 { PCM512x_GPIO_PLLIN, 0x00 }, 105 { PCM512x_SYNCHRONIZE, 0x10 }, 106 { PCM512x_PLL_COEFF_0, 0x00 }, 107 { PCM512x_PLL_COEFF_1, 0x00 }, 108 { PCM512x_PLL_COEFF_2, 0x00 }, 109 { PCM512x_PLL_COEFF_3, 0x00 }, 110 { PCM512x_PLL_COEFF_4, 0x00 }, 111 { PCM512x_DSP_CLKDIV, 0x00 }, 112 { PCM512x_DAC_CLKDIV, 0x00 }, 113 { PCM512x_NCP_CLKDIV, 0x00 }, 114 { PCM512x_OSR_CLKDIV, 0x00 }, 115 { PCM512x_MASTER_CLKDIV_1, 0x00 }, 116 { PCM512x_MASTER_CLKDIV_2, 0x00 }, 117 { PCM512x_FS_SPEED_MODE, 0x00 }, 118 { PCM512x_IDAC_1, 0x01 }, 119 { PCM512x_IDAC_2, 0x00 }, 120 { PCM512x_I2S_1, 0x02 }, 121 { PCM512x_I2S_2, 0x00 }, 122 }; 123 124 static bool pcm512x_readable(struct device *dev, unsigned int reg) 125 { 126 switch (reg) { 127 case PCM512x_RESET: 128 case PCM512x_POWER: 129 case PCM512x_MUTE: 130 case PCM512x_PLL_EN: 131 case PCM512x_SPI_MISO_FUNCTION: 132 case PCM512x_DSP: 133 case PCM512x_GPIO_EN: 134 case PCM512x_BCLK_LRCLK_CFG: 135 case PCM512x_DSP_GPIO_INPUT: 136 case PCM512x_MASTER_MODE: 137 case PCM512x_PLL_REF: 138 case PCM512x_DAC_REF: 139 case PCM512x_GPIO_DACIN: 140 case PCM512x_GPIO_PLLIN: 141 case PCM512x_SYNCHRONIZE: 142 case PCM512x_PLL_COEFF_0: 143 case PCM512x_PLL_COEFF_1: 144 case PCM512x_PLL_COEFF_2: 145 case PCM512x_PLL_COEFF_3: 146 case PCM512x_PLL_COEFF_4: 147 case PCM512x_DSP_CLKDIV: 148 case PCM512x_DAC_CLKDIV: 149 case PCM512x_NCP_CLKDIV: 150 case PCM512x_OSR_CLKDIV: 151 case PCM512x_MASTER_CLKDIV_1: 152 case PCM512x_MASTER_CLKDIV_2: 153 case PCM512x_FS_SPEED_MODE: 154 case PCM512x_IDAC_1: 155 case PCM512x_IDAC_2: 156 case PCM512x_ERROR_DETECT: 157 case PCM512x_I2S_1: 158 case PCM512x_I2S_2: 159 case PCM512x_DAC_ROUTING: 160 case PCM512x_DSP_PROGRAM: 161 case PCM512x_CLKDET: 162 case PCM512x_AUTO_MUTE: 163 case PCM512x_DIGITAL_VOLUME_1: 164 case PCM512x_DIGITAL_VOLUME_2: 165 case PCM512x_DIGITAL_VOLUME_3: 166 case PCM512x_DIGITAL_MUTE_1: 167 case PCM512x_DIGITAL_MUTE_2: 168 case PCM512x_DIGITAL_MUTE_3: 169 case PCM512x_GPIO_OUTPUT_1: 170 case PCM512x_GPIO_OUTPUT_2: 171 case PCM512x_GPIO_OUTPUT_3: 172 case PCM512x_GPIO_OUTPUT_4: 173 case PCM512x_GPIO_OUTPUT_5: 174 case PCM512x_GPIO_OUTPUT_6: 175 case PCM512x_GPIO_CONTROL_1: 176 case PCM512x_GPIO_CONTROL_2: 177 case PCM512x_OVERFLOW: 178 case PCM512x_RATE_DET_1: 179 case PCM512x_RATE_DET_2: 180 case PCM512x_RATE_DET_3: 181 case PCM512x_RATE_DET_4: 182 case PCM512x_CLOCK_STATUS: 183 case PCM512x_ANALOG_MUTE_DET: 184 case PCM512x_GPIN: 185 case PCM512x_DIGITAL_MUTE_DET: 186 case PCM512x_OUTPUT_AMPLITUDE: 187 case PCM512x_ANALOG_GAIN_CTRL: 188 case PCM512x_UNDERVOLTAGE_PROT: 189 case PCM512x_ANALOG_MUTE_CTRL: 190 case PCM512x_ANALOG_GAIN_BOOST: 191 case PCM512x_VCOM_CTRL_1: 192 case PCM512x_VCOM_CTRL_2: 193 case PCM512x_CRAM_CTRL: 194 case PCM512x_FLEX_A: 195 case PCM512x_FLEX_B: 196 return true; 197 default: 198 /* There are 256 raw register addresses */ 199 return reg < 0xff; 200 } 201 } 202 203 static bool pcm512x_volatile(struct device *dev, unsigned int reg) 204 { 205 switch (reg) { 206 case PCM512x_PLL_EN: 207 case PCM512x_OVERFLOW: 208 case PCM512x_RATE_DET_1: 209 case PCM512x_RATE_DET_2: 210 case PCM512x_RATE_DET_3: 211 case PCM512x_RATE_DET_4: 212 case PCM512x_CLOCK_STATUS: 213 case PCM512x_ANALOG_MUTE_DET: 214 case PCM512x_GPIN: 215 case PCM512x_DIGITAL_MUTE_DET: 216 case PCM512x_CRAM_CTRL: 217 return true; 218 default: 219 /* There are 256 raw register addresses */ 220 return reg < 0xff; 221 } 222 } 223 224 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, 225 struct snd_ctl_elem_value *ucontrol) 226 { 227 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 228 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 229 230 ucontrol->value.integer.value[0] = pcm512x->overclock_pll; 231 return 0; 232 } 233 234 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, 235 struct snd_ctl_elem_value *ucontrol) 236 { 237 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 238 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 239 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 240 241 switch (snd_soc_dapm_get_bias_level(dapm)) { 242 case SND_SOC_BIAS_OFF: 243 case SND_SOC_BIAS_STANDBY: 244 break; 245 default: 246 return -EBUSY; 247 } 248 249 pcm512x->overclock_pll = ucontrol->value.integer.value[0]; 250 return 0; 251 } 252 253 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, 254 struct snd_ctl_elem_value *ucontrol) 255 { 256 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 257 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 258 259 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; 260 return 0; 261 } 262 263 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, 264 struct snd_ctl_elem_value *ucontrol) 265 { 266 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 267 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 268 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 269 270 switch (snd_soc_dapm_get_bias_level(dapm)) { 271 case SND_SOC_BIAS_OFF: 272 case SND_SOC_BIAS_STANDBY: 273 break; 274 default: 275 return -EBUSY; 276 } 277 278 pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; 279 return 0; 280 } 281 282 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, 283 struct snd_ctl_elem_value *ucontrol) 284 { 285 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 286 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 287 288 ucontrol->value.integer.value[0] = pcm512x->overclock_dac; 289 return 0; 290 } 291 292 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, 293 struct snd_ctl_elem_value *ucontrol) 294 { 295 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 296 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 297 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 298 299 switch (snd_soc_dapm_get_bias_level(dapm)) { 300 case SND_SOC_BIAS_OFF: 301 case SND_SOC_BIAS_STANDBY: 302 break; 303 default: 304 return -EBUSY; 305 } 306 307 pcm512x->overclock_dac = ucontrol->value.integer.value[0]; 308 return 0; 309 } 310 311 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); 312 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); 313 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); 314 315 static const char * const pcm512x_dsp_program_texts[] = { 316 "FIR interpolation with de-emphasis", 317 "Low latency IIR with de-emphasis", 318 "High attenuation with de-emphasis", 319 "Fixed process flow", 320 "Ringing-less low latency FIR", 321 }; 322 323 static const unsigned int pcm512x_dsp_program_values[] = { 324 1, 325 2, 326 3, 327 5, 328 7, 329 }; 330 331 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, 332 PCM512x_DSP_PROGRAM, 0, 0x1f, 333 pcm512x_dsp_program_texts, 334 pcm512x_dsp_program_values); 335 336 static const char * const pcm512x_clk_missing_text[] = { 337 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" 338 }; 339 340 static const struct soc_enum pcm512x_clk_missing = 341 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); 342 343 static const char * const pcm512x_autom_text[] = { 344 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" 345 }; 346 347 static const struct soc_enum pcm512x_autom_l = 348 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, 349 pcm512x_autom_text); 350 351 static const struct soc_enum pcm512x_autom_r = 352 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, 353 pcm512x_autom_text); 354 355 static const char * const pcm512x_ramp_rate_text[] = { 356 "1 sample/update", "2 samples/update", "4 samples/update", 357 "Immediate" 358 }; 359 360 static const struct soc_enum pcm512x_vndf = 361 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, 362 pcm512x_ramp_rate_text); 363 364 static const struct soc_enum pcm512x_vnuf = 365 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, 366 pcm512x_ramp_rate_text); 367 368 static const struct soc_enum pcm512x_vedf = 369 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, 370 pcm512x_ramp_rate_text); 371 372 static const char * const pcm512x_ramp_step_text[] = { 373 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" 374 }; 375 376 static const struct soc_enum pcm512x_vnds = 377 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, 378 pcm512x_ramp_step_text); 379 380 static const struct soc_enum pcm512x_vnus = 381 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, 382 pcm512x_ramp_step_text); 383 384 static const struct soc_enum pcm512x_veds = 385 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, 386 pcm512x_ramp_step_text); 387 388 static int pcm512x_update_mute(struct pcm512x_priv *pcm512x) 389 { 390 return regmap_update_bits( 391 pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR, 392 (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT) 393 | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT)); 394 } 395 396 static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol, 397 struct snd_ctl_elem_value *ucontrol) 398 { 399 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 400 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 401 402 mutex_lock(&pcm512x->mutex); 403 ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4); 404 ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2); 405 mutex_unlock(&pcm512x->mutex); 406 407 return 0; 408 } 409 410 static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol, 411 struct snd_ctl_elem_value *ucontrol) 412 { 413 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 414 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 415 int ret, changed = 0; 416 417 mutex_lock(&pcm512x->mutex); 418 419 if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) { 420 pcm512x->mute ^= 0x4; 421 changed = 1; 422 } 423 if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) { 424 pcm512x->mute ^= 0x2; 425 changed = 1; 426 } 427 428 if (changed) { 429 ret = pcm512x_update_mute(pcm512x); 430 if (ret != 0) { 431 dev_err(component->dev, 432 "Failed to update digital mute: %d\n", ret); 433 mutex_unlock(&pcm512x->mutex); 434 return ret; 435 } 436 } 437 438 mutex_unlock(&pcm512x->mutex); 439 440 return changed; 441 } 442 443 static const struct snd_kcontrol_new pcm512x_controls[] = { 444 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, 445 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), 446 SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL, 447 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), 448 SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, 449 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), 450 { 451 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 452 .name = "Digital Playback Switch", 453 .index = 0, 454 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 455 .info = snd_ctl_boolean_stereo_info, 456 .get = pcm512x_digital_playback_switch_get, 457 .put = pcm512x_digital_playback_switch_put 458 }, 459 460 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), 461 SOC_ENUM("DSP Program", pcm512x_dsp_program), 462 463 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), 464 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), 465 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), 466 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, 467 PCM512x_ACTL_SHIFT, 1, 0), 468 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, 469 PCM512x_AMRE_SHIFT, 1, 0), 470 471 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), 472 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), 473 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), 474 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), 475 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), 476 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), 477 478 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, 479 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), 480 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, 481 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), 482 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, 483 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), 484 }; 485 486 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { 487 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 488 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 489 490 SND_SOC_DAPM_OUTPUT("OUTL"), 491 SND_SOC_DAPM_OUTPUT("OUTR"), 492 }; 493 494 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { 495 { "DACL", NULL, "Playback" }, 496 { "DACR", NULL, "Playback" }, 497 498 { "OUTL", NULL, "DACL" }, 499 { "OUTR", NULL, "DACR" }, 500 }; 501 502 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) 503 { 504 return 25000000 + 25000000 * pcm512x->overclock_pll / 100; 505 } 506 507 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) 508 { 509 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; 510 } 511 512 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, 513 unsigned long rate) 514 { 515 return rate + rate * pcm512x->overclock_dac / 100; 516 } 517 518 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) 519 { 520 if (!pcm512x->pll_out) 521 return 25000000; 522 return pcm512x_pll_max(pcm512x); 523 } 524 525 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, 526 unsigned long dac_rate) 527 { 528 /* 529 * If the DAC is not actually overclocked, use the good old 530 * NCP target rate... 531 */ 532 if (dac_rate <= 6144000) 533 return 1536000; 534 /* 535 * ...but if the DAC is in fact overclocked, bump the NCP target 536 * rate to get the recommended dividers even when overclocking. 537 */ 538 return pcm512x_dac_max(pcm512x, 1536000); 539 } 540 541 static const u32 pcm512x_dai_rates[] = { 542 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 543 88200, 96000, 176400, 192000, 384000, 544 }; 545 546 static const struct snd_pcm_hw_constraint_list constraints_slave = { 547 .count = ARRAY_SIZE(pcm512x_dai_rates), 548 .list = pcm512x_dai_rates, 549 }; 550 551 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, 552 struct snd_pcm_hw_rule *rule) 553 { 554 struct pcm512x_priv *pcm512x = rule->private; 555 struct snd_interval ranges[2]; 556 int frame_size; 557 558 frame_size = snd_soc_params_to_frame_size(params); 559 if (frame_size < 0) 560 return frame_size; 561 562 switch (frame_size) { 563 case 32: 564 /* No hole when the frame size is 32. */ 565 return 0; 566 case 48: 567 case 64: 568 /* There is only one hole in the range of supported 569 * rates, but it moves with the frame size. 570 */ 571 memset(ranges, 0, sizeof(ranges)); 572 ranges[0].min = 8000; 573 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; 574 ranges[1].min = DIV_ROUND_UP(16000000, frame_size); 575 ranges[1].max = 384000; 576 break; 577 default: 578 return -EINVAL; 579 } 580 581 return snd_interval_ranges(hw_param_interval(params, rule->var), 582 ARRAY_SIZE(ranges), ranges, 0); 583 } 584 585 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, 586 struct snd_soc_dai *dai) 587 { 588 struct snd_soc_component *component = dai->component; 589 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 590 struct device *dev = dai->dev; 591 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; 592 struct snd_ratnum *rats_no_pll; 593 594 if (IS_ERR(pcm512x->sclk)) { 595 dev_err(dev, "Need SCLK for master mode: %ld\n", 596 PTR_ERR(pcm512x->sclk)); 597 return PTR_ERR(pcm512x->sclk); 598 } 599 600 if (pcm512x->pll_out) 601 return snd_pcm_hw_rule_add(substream->runtime, 0, 602 SNDRV_PCM_HW_PARAM_RATE, 603 pcm512x_hw_rule_rate, 604 pcm512x, 605 SNDRV_PCM_HW_PARAM_FRAME_BITS, 606 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 607 608 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), 609 GFP_KERNEL); 610 if (!constraints_no_pll) 611 return -ENOMEM; 612 constraints_no_pll->nrats = 1; 613 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); 614 if (!rats_no_pll) 615 return -ENOMEM; 616 constraints_no_pll->rats = rats_no_pll; 617 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; 618 rats_no_pll->den_min = 1; 619 rats_no_pll->den_max = 128; 620 rats_no_pll->den_step = 1; 621 622 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, 623 SNDRV_PCM_HW_PARAM_RATE, 624 constraints_no_pll); 625 } 626 627 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, 628 struct snd_soc_dai *dai) 629 { 630 struct snd_soc_component *component = dai->component; 631 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 632 struct device *dev = dai->dev; 633 struct regmap *regmap = pcm512x->regmap; 634 635 if (IS_ERR(pcm512x->sclk)) { 636 dev_info(dev, "No SCLK, using BCLK: %ld\n", 637 PTR_ERR(pcm512x->sclk)); 638 639 /* Disable reporting of missing SCLK as an error */ 640 regmap_update_bits(regmap, PCM512x_ERROR_DETECT, 641 PCM512x_IDCH, PCM512x_IDCH); 642 643 /* Switch PLL input to BCLK */ 644 regmap_update_bits(regmap, PCM512x_PLL_REF, 645 PCM512x_SREF, PCM512x_SREF_BCK); 646 } 647 648 return snd_pcm_hw_constraint_list(substream->runtime, 0, 649 SNDRV_PCM_HW_PARAM_RATE, 650 &constraints_slave); 651 } 652 653 static int pcm512x_dai_startup(struct snd_pcm_substream *substream, 654 struct snd_soc_dai *dai) 655 { 656 struct snd_soc_component *component = dai->component; 657 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 658 659 switch (pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 660 case SND_SOC_DAIFMT_CBP_CFP: 661 case SND_SOC_DAIFMT_CBP_CFC: 662 return pcm512x_dai_startup_master(substream, dai); 663 664 case SND_SOC_DAIFMT_CBC_CFC: 665 return pcm512x_dai_startup_slave(substream, dai); 666 667 default: 668 return -EINVAL; 669 } 670 } 671 672 static int pcm512x_set_bias_level(struct snd_soc_component *component, 673 enum snd_soc_bias_level level) 674 { 675 struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev); 676 int ret; 677 678 switch (level) { 679 case SND_SOC_BIAS_ON: 680 case SND_SOC_BIAS_PREPARE: 681 break; 682 683 case SND_SOC_BIAS_STANDBY: 684 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 685 PCM512x_RQST, 0); 686 if (ret != 0) { 687 dev_err(component->dev, "Failed to remove standby: %d\n", 688 ret); 689 return ret; 690 } 691 break; 692 693 case SND_SOC_BIAS_OFF: 694 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 695 PCM512x_RQST, PCM512x_RQST); 696 if (ret != 0) { 697 dev_err(component->dev, "Failed to request standby: %d\n", 698 ret); 699 return ret; 700 } 701 break; 702 } 703 704 return 0; 705 } 706 707 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, 708 unsigned long bclk_rate) 709 { 710 struct device *dev = dai->dev; 711 struct snd_soc_component *component = dai->component; 712 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 713 unsigned long sck_rate; 714 int pow2; 715 716 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ 717 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ 718 719 /* select sck_rate as a multiple of bclk_rate but still with 720 * as many factors of 2 as possible, as that makes it easier 721 * to find a fast DAC rate 722 */ 723 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); 724 for (; pow2; pow2 >>= 1) { 725 sck_rate = rounddown(pcm512x_pll_max(pcm512x), 726 bclk_rate * pow2); 727 if (sck_rate >= 16000000) 728 break; 729 } 730 if (!pow2) { 731 dev_err(dev, "Impossible to generate a suitable SCK\n"); 732 return 0; 733 } 734 735 dev_dbg(dev, "sck_rate %lu\n", sck_rate); 736 return sck_rate; 737 } 738 739 /* pll_rate = pllin_rate * R * J.D / P 740 * 1 <= R <= 16 741 * 1 <= J <= 63 742 * 0 <= D <= 9999 743 * 1 <= P <= 15 744 * 64 MHz <= pll_rate <= 100 MHz 745 * if D == 0 746 * 1 MHz <= pllin_rate / P <= 20 MHz 747 * else if D > 0 748 * 6.667 MHz <= pllin_rate / P <= 20 MHz 749 * 4 <= J <= 11 750 * R = 1 751 */ 752 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, 753 unsigned long pllin_rate, 754 unsigned long pll_rate) 755 { 756 struct device *dev = dai->dev; 757 struct snd_soc_component *component = dai->component; 758 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 759 unsigned long common; 760 int R, J, D, P; 761 unsigned long K; /* 10000 * J.D */ 762 unsigned long num; 763 unsigned long den; 764 765 common = gcd(pll_rate, pllin_rate); 766 dev_dbg(dev, "pll %lu pllin %lu common %lu\n", 767 pll_rate, pllin_rate, common); 768 num = pll_rate / common; 769 den = pllin_rate / common; 770 771 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ 772 if (pllin_rate / den > 20000000 && num < 8) { 773 num *= DIV_ROUND_UP(pllin_rate / den, 20000000); 774 den *= DIV_ROUND_UP(pllin_rate / den, 20000000); 775 } 776 dev_dbg(dev, "num / den = %lu / %lu\n", num, den); 777 778 P = den; 779 if (den <= 15 && num <= 16 * 63 780 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { 781 /* Try the case with D = 0 */ 782 D = 0; 783 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ 784 for (R = 16; R; R--) { 785 if (num % R) 786 continue; 787 J = num / R; 788 if (J == 0 || J > 63) 789 continue; 790 791 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); 792 pcm512x->real_pll = pll_rate; 793 goto done; 794 } 795 /* no luck */ 796 } 797 798 R = 1; 799 800 if (num > 0xffffffffUL / 10000) 801 goto fallback; 802 803 /* Try to find an exact pll_rate using the D > 0 case */ 804 common = gcd(10000 * num, den); 805 num = 10000 * num / common; 806 den /= common; 807 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); 808 809 for (P = den; P <= 15; P++) { 810 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) 811 continue; 812 if (num * P % den) 813 continue; 814 K = num * P / den; 815 /* J == 12 is ok if D == 0 */ 816 if (K < 40000 || K > 120000) 817 continue; 818 819 J = K / 10000; 820 D = K % 10000; 821 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); 822 pcm512x->real_pll = pll_rate; 823 goto done; 824 } 825 826 /* Fall back to an approximate pll_rate */ 827 828 fallback: 829 /* find smallest possible P */ 830 P = DIV_ROUND_UP(pllin_rate, 20000000); 831 if (!P) 832 P = 1; 833 else if (P > 15) { 834 dev_err(dev, "Need a slower clock as pll-input\n"); 835 return -EINVAL; 836 } 837 if (pllin_rate / P < 6667000) { 838 dev_err(dev, "Need a faster clock as pll-input\n"); 839 return -EINVAL; 840 } 841 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); 842 if (K < 40000) 843 K = 40000; 844 /* J == 12 is ok if D == 0 */ 845 if (K > 120000) 846 K = 120000; 847 J = K / 10000; 848 D = K % 10000; 849 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); 850 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); 851 852 done: 853 pcm512x->pll_r = R; 854 pcm512x->pll_j = J; 855 pcm512x->pll_d = D; 856 pcm512x->pll_p = P; 857 return 0; 858 } 859 860 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, 861 unsigned long osr_rate, 862 unsigned long pllin_rate) 863 { 864 struct snd_soc_component *component = dai->component; 865 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 866 unsigned long dac_rate; 867 868 if (!pcm512x->pll_out) 869 return 0; /* no PLL to bypass, force SCK as DAC input */ 870 871 if (pllin_rate % osr_rate) 872 return 0; /* futile, quit early */ 873 874 /* run DAC no faster than 6144000 Hz */ 875 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); 876 dac_rate; 877 dac_rate -= osr_rate) { 878 879 if (pllin_rate / dac_rate > 128) 880 return 0; /* DAC divider would be too big */ 881 882 if (!(pllin_rate % dac_rate)) 883 return dac_rate; 884 885 dac_rate -= osr_rate; 886 } 887 888 return 0; 889 } 890 891 static int pcm512x_set_dividers(struct snd_soc_dai *dai, 892 struct snd_pcm_hw_params *params) 893 { 894 struct device *dev = dai->dev; 895 struct snd_soc_component *component = dai->component; 896 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 897 unsigned long pllin_rate = 0; 898 unsigned long pll_rate; 899 unsigned long sck_rate; 900 unsigned long mck_rate; 901 unsigned long bclk_rate; 902 unsigned long sample_rate; 903 unsigned long osr_rate; 904 unsigned long dacsrc_rate; 905 int bclk_div; 906 int lrclk_div; 907 int dsp_div; 908 int dac_div; 909 unsigned long dac_rate; 910 int ncp_div; 911 int osr_div; 912 int ret; 913 int idac; 914 int fssp; 915 int gpio; 916 917 if (pcm512x->bclk_ratio > 0) { 918 lrclk_div = pcm512x->bclk_ratio; 919 } else { 920 lrclk_div = snd_soc_params_to_frame_size(params); 921 922 if (lrclk_div == 0) { 923 dev_err(dev, "No LRCLK?\n"); 924 return -EINVAL; 925 } 926 } 927 928 if (!pcm512x->pll_out) { 929 sck_rate = clk_get_rate(pcm512x->sclk); 930 bclk_rate = params_rate(params) * lrclk_div; 931 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 932 933 mck_rate = sck_rate; 934 } else { 935 ret = snd_soc_params_to_bclk(params); 936 if (ret < 0) { 937 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); 938 return ret; 939 } 940 if (ret == 0) { 941 dev_err(dev, "No BCLK?\n"); 942 return -EINVAL; 943 } 944 bclk_rate = ret; 945 946 pllin_rate = clk_get_rate(pcm512x->sclk); 947 948 sck_rate = pcm512x_find_sck(dai, bclk_rate); 949 if (!sck_rate) 950 return -EINVAL; 951 pll_rate = 4 * sck_rate; 952 953 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); 954 if (ret != 0) 955 return ret; 956 957 ret = regmap_write(pcm512x->regmap, 958 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); 959 if (ret != 0) { 960 dev_err(dev, "Failed to write PLL P: %d\n", ret); 961 return ret; 962 } 963 964 ret = regmap_write(pcm512x->regmap, 965 PCM512x_PLL_COEFF_1, pcm512x->pll_j); 966 if (ret != 0) { 967 dev_err(dev, "Failed to write PLL J: %d\n", ret); 968 return ret; 969 } 970 971 ret = regmap_write(pcm512x->regmap, 972 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); 973 if (ret != 0) { 974 dev_err(dev, "Failed to write PLL D msb: %d\n", ret); 975 return ret; 976 } 977 978 ret = regmap_write(pcm512x->regmap, 979 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); 980 if (ret != 0) { 981 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); 982 return ret; 983 } 984 985 ret = regmap_write(pcm512x->regmap, 986 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); 987 if (ret != 0) { 988 dev_err(dev, "Failed to write PLL R: %d\n", ret); 989 return ret; 990 } 991 992 mck_rate = pcm512x->real_pll; 993 994 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); 995 } 996 997 if (bclk_div > 128) { 998 dev_err(dev, "Failed to find BCLK divider\n"); 999 return -EINVAL; 1000 } 1001 1002 /* the actual rate */ 1003 sample_rate = sck_rate / bclk_div / lrclk_div; 1004 osr_rate = 16 * sample_rate; 1005 1006 /* run DSP no faster than 50 MHz */ 1007 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; 1008 1009 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); 1010 if (dac_rate) { 1011 /* the desired clock rate is "compatible" with the pll input 1012 * clock, so use that clock as dac input instead of the pll 1013 * output clock since the pll will introduce jitter and thus 1014 * noise. 1015 */ 1016 dev_dbg(dev, "using pll input as dac input\n"); 1017 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1018 PCM512x_SDAC, PCM512x_SDAC_GPIO); 1019 if (ret != 0) { 1020 dev_err(component->dev, 1021 "Failed to set gpio as dacref: %d\n", ret); 1022 return ret; 1023 } 1024 1025 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1026 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, 1027 PCM512x_GREF, gpio); 1028 if (ret != 0) { 1029 dev_err(component->dev, 1030 "Failed to set gpio %d as dacin: %d\n", 1031 pcm512x->pll_in, ret); 1032 return ret; 1033 } 1034 1035 dacsrc_rate = pllin_rate; 1036 } else { 1037 /* run DAC no faster than 6144000 Hz */ 1038 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) 1039 / osr_rate; 1040 unsigned long sck_mul = sck_rate / osr_rate; 1041 1042 for (; dac_mul; dac_mul--) { 1043 if (!(sck_mul % dac_mul)) 1044 break; 1045 } 1046 if (!dac_mul) { 1047 dev_err(dev, "Failed to find DAC rate\n"); 1048 return -EINVAL; 1049 } 1050 1051 dac_rate = dac_mul * osr_rate; 1052 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", 1053 dac_rate, sample_rate); 1054 1055 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, 1056 PCM512x_SDAC, PCM512x_SDAC_SCK); 1057 if (ret != 0) { 1058 dev_err(component->dev, 1059 "Failed to set sck as dacref: %d\n", ret); 1060 return ret; 1061 } 1062 1063 dacsrc_rate = sck_rate; 1064 } 1065 1066 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); 1067 if (osr_div > 128) { 1068 dev_err(dev, "Failed to find OSR divider\n"); 1069 return -EINVAL; 1070 } 1071 1072 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); 1073 if (dac_div > 128) { 1074 dev_err(dev, "Failed to find DAC divider\n"); 1075 return -EINVAL; 1076 } 1077 dac_rate = dacsrc_rate / dac_div; 1078 1079 ncp_div = DIV_ROUND_CLOSEST(dac_rate, 1080 pcm512x_ncp_target(pcm512x, dac_rate)); 1081 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { 1082 /* run NCP no faster than 2048000 Hz, but why? */ 1083 ncp_div = DIV_ROUND_UP(dac_rate, 2048000); 1084 if (ncp_div > 128) { 1085 dev_err(dev, "Failed to find NCP divider\n"); 1086 return -EINVAL; 1087 } 1088 } 1089 1090 idac = mck_rate / (dsp_div * sample_rate); 1091 1092 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); 1093 if (ret != 0) { 1094 dev_err(dev, "Failed to write DSP divider: %d\n", ret); 1095 return ret; 1096 } 1097 1098 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); 1099 if (ret != 0) { 1100 dev_err(dev, "Failed to write DAC divider: %d\n", ret); 1101 return ret; 1102 } 1103 1104 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); 1105 if (ret != 0) { 1106 dev_err(dev, "Failed to write NCP divider: %d\n", ret); 1107 return ret; 1108 } 1109 1110 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); 1111 if (ret != 0) { 1112 dev_err(dev, "Failed to write OSR divider: %d\n", ret); 1113 return ret; 1114 } 1115 1116 ret = regmap_write(pcm512x->regmap, 1117 PCM512x_MASTER_CLKDIV_1, bclk_div - 1); 1118 if (ret != 0) { 1119 dev_err(dev, "Failed to write BCLK divider: %d\n", ret); 1120 return ret; 1121 } 1122 1123 ret = regmap_write(pcm512x->regmap, 1124 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); 1125 if (ret != 0) { 1126 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); 1127 return ret; 1128 } 1129 1130 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); 1131 if (ret != 0) { 1132 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); 1133 return ret; 1134 } 1135 1136 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); 1137 if (ret != 0) { 1138 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); 1139 return ret; 1140 } 1141 1142 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) 1143 fssp = PCM512x_FSSP_48KHZ; 1144 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) 1145 fssp = PCM512x_FSSP_96KHZ; 1146 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) 1147 fssp = PCM512x_FSSP_192KHZ; 1148 else 1149 fssp = PCM512x_FSSP_384KHZ; 1150 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, 1151 PCM512x_FSSP, fssp); 1152 if (ret != 0) { 1153 dev_err(component->dev, "Failed to set fs speed: %d\n", ret); 1154 return ret; 1155 } 1156 1157 dev_dbg(component->dev, "DSP divider %d\n", dsp_div); 1158 dev_dbg(component->dev, "DAC divider %d\n", dac_div); 1159 dev_dbg(component->dev, "NCP divider %d\n", ncp_div); 1160 dev_dbg(component->dev, "OSR divider %d\n", osr_div); 1161 dev_dbg(component->dev, "BCK divider %d\n", bclk_div); 1162 dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div); 1163 dev_dbg(component->dev, "IDAC %d\n", idac); 1164 dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp); 1165 1166 return 0; 1167 } 1168 1169 static int pcm512x_hw_params(struct snd_pcm_substream *substream, 1170 struct snd_pcm_hw_params *params, 1171 struct snd_soc_dai *dai) 1172 { 1173 struct snd_soc_component *component = dai->component; 1174 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1175 int alen; 1176 int gpio; 1177 int ret; 1178 1179 dev_dbg(component->dev, "hw_params %u Hz, %u channels\n", 1180 params_rate(params), 1181 params_channels(params)); 1182 1183 switch (params_width(params)) { 1184 case 16: 1185 alen = PCM512x_ALEN_16; 1186 break; 1187 case 20: 1188 alen = PCM512x_ALEN_20; 1189 break; 1190 case 24: 1191 alen = PCM512x_ALEN_24; 1192 break; 1193 case 32: 1194 alen = PCM512x_ALEN_32; 1195 break; 1196 default: 1197 dev_err(component->dev, "Bad frame size: %d\n", 1198 params_width(params)); 1199 return -EINVAL; 1200 } 1201 1202 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, 1203 PCM512x_ALEN, alen); 1204 if (ret != 0) { 1205 dev_err(component->dev, "Failed to set frame size: %d\n", ret); 1206 return ret; 1207 } 1208 1209 if ((pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == 1210 SND_SOC_DAIFMT_CBC_CFC) { 1211 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1212 PCM512x_DCAS, 0); 1213 if (ret != 0) { 1214 dev_err(component->dev, 1215 "Failed to enable clock divider autoset: %d\n", 1216 ret); 1217 return ret; 1218 } 1219 goto skip_pll; 1220 } 1221 1222 if (pcm512x->pll_out) { 1223 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); 1224 if (ret != 0) { 1225 dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret); 1226 return ret; 1227 } 1228 1229 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); 1230 if (ret != 0) { 1231 dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret); 1232 return ret; 1233 } 1234 1235 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1236 PCM512x_IDFS | PCM512x_IDBK 1237 | PCM512x_IDSK | PCM512x_IDCH 1238 | PCM512x_IDCM | PCM512x_DCAS 1239 | PCM512x_IPLK, 1240 PCM512x_IDFS | PCM512x_IDBK 1241 | PCM512x_IDSK | PCM512x_IDCH 1242 | PCM512x_DCAS); 1243 if (ret != 0) { 1244 dev_err(component->dev, 1245 "Failed to ignore auto-clock failures: %d\n", 1246 ret); 1247 return ret; 1248 } 1249 } else { 1250 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, 1251 PCM512x_IDFS | PCM512x_IDBK 1252 | PCM512x_IDSK | PCM512x_IDCH 1253 | PCM512x_IDCM | PCM512x_DCAS 1254 | PCM512x_IPLK, 1255 PCM512x_IDFS | PCM512x_IDBK 1256 | PCM512x_IDSK | PCM512x_IDCH 1257 | PCM512x_DCAS | PCM512x_IPLK); 1258 if (ret != 0) { 1259 dev_err(component->dev, 1260 "Failed to ignore auto-clock failures: %d\n", 1261 ret); 1262 return ret; 1263 } 1264 1265 if (!pcm512x->force_pll_on) { 1266 ret = regmap_update_bits(pcm512x->regmap, 1267 PCM512x_PLL_EN, PCM512x_PLLE, 0); 1268 } else { 1269 /* provide minimum PLL config for TAS575x clocking 1270 * and leave PLL enabled 1271 */ 1272 ret = regmap_write(pcm512x->regmap, 1273 PCM512x_PLL_COEFF_0, 0x01); 1274 if (ret != 0) { 1275 dev_err(component->dev, 1276 "Failed to set pll coefficient: %d\n", ret); 1277 return ret; 1278 } 1279 ret = regmap_write(pcm512x->regmap, 1280 PCM512x_PLL_COEFF_1, 0x04); 1281 if (ret != 0) { 1282 dev_err(component->dev, 1283 "Failed to set pll coefficient: %d\n", ret); 1284 return ret; 1285 } 1286 ret = regmap_write(pcm512x->regmap, 1287 PCM512x_PLL_EN, 0x01); 1288 dev_dbg(component->dev, "Enabling PLL for TAS575x\n"); 1289 } 1290 1291 if (ret != 0) { 1292 dev_err(component->dev, "Failed to set pll mode: %d\n", ret); 1293 return ret; 1294 } 1295 } 1296 1297 ret = pcm512x_set_dividers(dai, params); 1298 if (ret != 0) 1299 return ret; 1300 1301 if (pcm512x->pll_out) { 1302 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, 1303 PCM512x_SREF, PCM512x_SREF_GPIO); 1304 if (ret != 0) { 1305 dev_err(component->dev, 1306 "Failed to set gpio as pllref: %d\n", ret); 1307 return ret; 1308 } 1309 1310 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; 1311 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, 1312 PCM512x_GREF, gpio); 1313 if (ret != 0) { 1314 dev_err(component->dev, 1315 "Failed to set gpio %d as pllin: %d\n", 1316 pcm512x->pll_in, ret); 1317 return ret; 1318 } 1319 1320 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, 1321 PCM512x_PLLE, PCM512x_PLLE); 1322 if (ret != 0) { 1323 dev_err(component->dev, "Failed to enable pll: %d\n", ret); 1324 return ret; 1325 } 1326 1327 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); 1328 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, 1329 gpio, gpio); 1330 if (ret != 0) { 1331 dev_err(component->dev, "Failed to enable gpio %d: %d\n", 1332 pcm512x->pll_out, ret); 1333 return ret; 1334 } 1335 1336 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; 1337 ret = regmap_update_bits(pcm512x->regmap, gpio, 1338 PCM512x_GxSL, PCM512x_GxSL_PLLCK); 1339 if (ret != 0) { 1340 dev_err(component->dev, "Failed to output pll on %d: %d\n", 1341 ret, pcm512x->pll_out); 1342 return ret; 1343 } 1344 } 1345 1346 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1347 PCM512x_RQSY, PCM512x_RQSY_HALT); 1348 if (ret != 0) { 1349 dev_err(component->dev, "Failed to halt clocks: %d\n", ret); 1350 return ret; 1351 } 1352 1353 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, 1354 PCM512x_RQSY, PCM512x_RQSY_RESUME); 1355 if (ret != 0) { 1356 dev_err(component->dev, "Failed to resume clocks: %d\n", ret); 1357 return ret; 1358 } 1359 1360 skip_pll: 1361 return 0; 1362 } 1363 1364 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1365 { 1366 struct snd_soc_component *component = dai->component; 1367 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1368 int afmt; 1369 int offset = 0; 1370 int clock_output; 1371 int provider_mode; 1372 int ret; 1373 1374 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1375 case SND_SOC_DAIFMT_CBC_CFC: 1376 clock_output = 0; 1377 provider_mode = 0; 1378 break; 1379 case SND_SOC_DAIFMT_CBP_CFP: 1380 clock_output = PCM512x_BCKO | PCM512x_LRKO; 1381 provider_mode = PCM512x_RLRK | PCM512x_RBCK; 1382 break; 1383 case SND_SOC_DAIFMT_CBP_CFC: 1384 clock_output = PCM512x_BCKO; 1385 provider_mode = PCM512x_RBCK; 1386 break; 1387 default: 1388 return -EINVAL; 1389 } 1390 1391 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, 1392 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, 1393 clock_output); 1394 if (ret != 0) { 1395 dev_err(component->dev, "Failed to enable clock output: %d\n", ret); 1396 return ret; 1397 } 1398 1399 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, 1400 PCM512x_RLRK | PCM512x_RBCK, 1401 provider_mode); 1402 if (ret != 0) { 1403 dev_err(component->dev, "Failed to enable provider mode: %d\n", ret); 1404 return ret; 1405 } 1406 1407 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1408 case SND_SOC_DAIFMT_I2S: 1409 afmt = PCM512x_AFMT_I2S; 1410 break; 1411 case SND_SOC_DAIFMT_RIGHT_J: 1412 afmt = PCM512x_AFMT_RTJ; 1413 break; 1414 case SND_SOC_DAIFMT_LEFT_J: 1415 afmt = PCM512x_AFMT_LTJ; 1416 break; 1417 case SND_SOC_DAIFMT_DSP_A: 1418 offset = 1; 1419 fallthrough; 1420 case SND_SOC_DAIFMT_DSP_B: 1421 afmt = PCM512x_AFMT_DSP; 1422 break; 1423 default: 1424 dev_err(component->dev, "unsupported DAI format: 0x%x\n", 1425 pcm512x->fmt); 1426 return -EINVAL; 1427 } 1428 1429 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, 1430 PCM512x_AFMT, afmt); 1431 if (ret != 0) { 1432 dev_err(component->dev, "Failed to set data format: %d\n", ret); 1433 return ret; 1434 } 1435 1436 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_2, 1437 0xFF, offset); 1438 if (ret != 0) { 1439 dev_err(component->dev, "Failed to set data offset: %d\n", ret); 1440 return ret; 1441 } 1442 1443 pcm512x->fmt = fmt; 1444 1445 return 0; 1446 } 1447 1448 static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 1449 { 1450 struct snd_soc_component *component = dai->component; 1451 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1452 1453 if (ratio > 256) 1454 return -EINVAL; 1455 1456 pcm512x->bclk_ratio = ratio; 1457 1458 return 0; 1459 } 1460 1461 static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction) 1462 { 1463 struct snd_soc_component *component = dai->component; 1464 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); 1465 int ret; 1466 unsigned int mute_det; 1467 1468 mutex_lock(&pcm512x->mutex); 1469 1470 if (mute) { 1471 pcm512x->mute |= 0x1; 1472 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE, 1473 PCM512x_RQML | PCM512x_RQMR, 1474 PCM512x_RQML | PCM512x_RQMR); 1475 if (ret != 0) { 1476 dev_err(component->dev, 1477 "Failed to set digital mute: %d\n", ret); 1478 goto unlock; 1479 } 1480 1481 regmap_read_poll_timeout(pcm512x->regmap, 1482 PCM512x_ANALOG_MUTE_DET, 1483 mute_det, (mute_det & 0x3) == 0, 1484 200, 10000); 1485 } else { 1486 pcm512x->mute &= ~0x1; 1487 ret = pcm512x_update_mute(pcm512x); 1488 if (ret != 0) { 1489 dev_err(component->dev, 1490 "Failed to update digital mute: %d\n", ret); 1491 goto unlock; 1492 } 1493 1494 regmap_read_poll_timeout(pcm512x->regmap, 1495 PCM512x_ANALOG_MUTE_DET, 1496 mute_det, 1497 (mute_det & 0x3) 1498 == ((~pcm512x->mute >> 1) & 0x3), 1499 200, 10000); 1500 } 1501 1502 unlock: 1503 mutex_unlock(&pcm512x->mutex); 1504 1505 return ret; 1506 } 1507 1508 static const struct snd_soc_dai_ops pcm512x_dai_ops = { 1509 .startup = pcm512x_dai_startup, 1510 .hw_params = pcm512x_hw_params, 1511 .set_fmt = pcm512x_set_fmt, 1512 .mute_stream = pcm512x_mute, 1513 .set_bclk_ratio = pcm512x_set_bclk_ratio, 1514 .no_capture_mute = 1, 1515 }; 1516 1517 static struct snd_soc_dai_driver pcm512x_dai = { 1518 .name = "pcm512x-hifi", 1519 .playback = { 1520 .stream_name = "Playback", 1521 .channels_min = 2, 1522 .channels_max = 2, 1523 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1524 .rate_min = 8000, 1525 .rate_max = 384000, 1526 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1527 SNDRV_PCM_FMTBIT_S24_LE | 1528 SNDRV_PCM_FMTBIT_S32_LE 1529 }, 1530 .ops = &pcm512x_dai_ops, 1531 }; 1532 1533 static const struct snd_soc_component_driver pcm512x_component_driver = { 1534 .set_bias_level = pcm512x_set_bias_level, 1535 .controls = pcm512x_controls, 1536 .num_controls = ARRAY_SIZE(pcm512x_controls), 1537 .dapm_widgets = pcm512x_dapm_widgets, 1538 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), 1539 .dapm_routes = pcm512x_dapm_routes, 1540 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), 1541 .use_pmdown_time = 1, 1542 .endianness = 1, 1543 }; 1544 1545 static const struct regmap_range_cfg pcm512x_range = { 1546 .name = "Pages", .range_min = PCM512x_VIRT_BASE, 1547 .range_max = PCM512x_MAX_REGISTER, 1548 .selector_reg = PCM512x_PAGE, 1549 .selector_mask = 0xff, 1550 .window_start = 0, .window_len = 0x100, 1551 }; 1552 1553 const struct regmap_config pcm512x_regmap = { 1554 .reg_bits = 8, 1555 .val_bits = 8, 1556 1557 .readable_reg = pcm512x_readable, 1558 .volatile_reg = pcm512x_volatile, 1559 1560 .ranges = &pcm512x_range, 1561 .num_ranges = 1, 1562 1563 .max_register = PCM512x_MAX_REGISTER, 1564 .reg_defaults = pcm512x_reg_defaults, 1565 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), 1566 .cache_type = REGCACHE_RBTREE, 1567 }; 1568 EXPORT_SYMBOL_GPL(pcm512x_regmap); 1569 1570 int pcm512x_probe(struct device *dev, struct regmap *regmap) 1571 { 1572 struct pcm512x_priv *pcm512x; 1573 int i, ret; 1574 1575 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); 1576 if (!pcm512x) 1577 return -ENOMEM; 1578 1579 mutex_init(&pcm512x->mutex); 1580 1581 dev_set_drvdata(dev, pcm512x); 1582 pcm512x->regmap = regmap; 1583 1584 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) 1585 pcm512x->supplies[i].supply = pcm512x_supply_names[i]; 1586 1587 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), 1588 pcm512x->supplies); 1589 if (ret != 0) { 1590 dev_err(dev, "Failed to get supplies: %d\n", ret); 1591 return ret; 1592 } 1593 1594 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; 1595 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; 1596 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; 1597 1598 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { 1599 ret = devm_regulator_register_notifier( 1600 pcm512x->supplies[i].consumer, 1601 &pcm512x->supply_nb[i]); 1602 if (ret != 0) { 1603 dev_err(dev, 1604 "Failed to register regulator notifier: %d\n", 1605 ret); 1606 } 1607 } 1608 1609 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1610 pcm512x->supplies); 1611 if (ret != 0) { 1612 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1613 return ret; 1614 } 1615 1616 /* Reset the device, verifying I/O in the process for I2C */ 1617 ret = regmap_write(regmap, PCM512x_RESET, 1618 PCM512x_RSTM | PCM512x_RSTR); 1619 if (ret != 0) { 1620 dev_err(dev, "Failed to reset device: %d\n", ret); 1621 goto err; 1622 } 1623 1624 ret = regmap_write(regmap, PCM512x_RESET, 0); 1625 if (ret != 0) { 1626 dev_err(dev, "Failed to reset device: %d\n", ret); 1627 goto err; 1628 } 1629 1630 pcm512x->sclk = devm_clk_get(dev, NULL); 1631 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) { 1632 ret = -EPROBE_DEFER; 1633 goto err; 1634 } 1635 if (!IS_ERR(pcm512x->sclk)) { 1636 ret = clk_prepare_enable(pcm512x->sclk); 1637 if (ret != 0) { 1638 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1639 goto err; 1640 } 1641 } 1642 1643 /* Default to standby mode */ 1644 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1645 PCM512x_RQST, PCM512x_RQST); 1646 if (ret != 0) { 1647 dev_err(dev, "Failed to request standby: %d\n", 1648 ret); 1649 goto err_clk; 1650 } 1651 1652 pm_runtime_set_active(dev); 1653 pm_runtime_enable(dev); 1654 pm_runtime_idle(dev); 1655 1656 #ifdef CONFIG_OF 1657 if (dev->of_node) { 1658 const struct device_node *np = dev->of_node; 1659 u32 val; 1660 1661 if (of_property_read_u32(np, "pll-in", &val) >= 0) { 1662 if (val > 6) { 1663 dev_err(dev, "Invalid pll-in\n"); 1664 ret = -EINVAL; 1665 goto err_pm; 1666 } 1667 pcm512x->pll_in = val; 1668 } 1669 1670 if (of_property_read_u32(np, "pll-out", &val) >= 0) { 1671 if (val > 6) { 1672 dev_err(dev, "Invalid pll-out\n"); 1673 ret = -EINVAL; 1674 goto err_pm; 1675 } 1676 pcm512x->pll_out = val; 1677 } 1678 1679 if (!pcm512x->pll_in != !pcm512x->pll_out) { 1680 dev_err(dev, 1681 "Error: both pll-in and pll-out, or none\n"); 1682 ret = -EINVAL; 1683 goto err_pm; 1684 } 1685 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { 1686 dev_err(dev, "Error: pll-in == pll-out\n"); 1687 ret = -EINVAL; 1688 goto err_pm; 1689 } 1690 1691 if (!strcmp(np->name, "tas5756") || 1692 !strcmp(np->name, "tas5754")) 1693 pcm512x->force_pll_on = 1; 1694 dev_dbg(dev, "Device ID: %s\n", np->name); 1695 } 1696 #endif 1697 1698 ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver, 1699 &pcm512x_dai, 1); 1700 if (ret != 0) { 1701 dev_err(dev, "Failed to register CODEC: %d\n", ret); 1702 goto err_pm; 1703 } 1704 1705 return 0; 1706 1707 err_pm: 1708 pm_runtime_disable(dev); 1709 err_clk: 1710 if (!IS_ERR(pcm512x->sclk)) 1711 clk_disable_unprepare(pcm512x->sclk); 1712 err: 1713 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1714 pcm512x->supplies); 1715 return ret; 1716 } 1717 EXPORT_SYMBOL_GPL(pcm512x_probe); 1718 1719 void pcm512x_remove(struct device *dev) 1720 { 1721 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1722 1723 pm_runtime_disable(dev); 1724 if (!IS_ERR(pcm512x->sclk)) 1725 clk_disable_unprepare(pcm512x->sclk); 1726 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1727 pcm512x->supplies); 1728 } 1729 EXPORT_SYMBOL_GPL(pcm512x_remove); 1730 1731 static int pcm512x_suspend(struct device *dev) 1732 { 1733 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1734 int ret; 1735 1736 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1737 PCM512x_RQPD, PCM512x_RQPD); 1738 if (ret != 0) { 1739 dev_err(dev, "Failed to request power down: %d\n", ret); 1740 return ret; 1741 } 1742 1743 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), 1744 pcm512x->supplies); 1745 if (ret != 0) { 1746 dev_err(dev, "Failed to disable supplies: %d\n", ret); 1747 return ret; 1748 } 1749 1750 if (!IS_ERR(pcm512x->sclk)) 1751 clk_disable_unprepare(pcm512x->sclk); 1752 1753 return 0; 1754 } 1755 1756 static int pcm512x_resume(struct device *dev) 1757 { 1758 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 1759 int ret; 1760 1761 if (!IS_ERR(pcm512x->sclk)) { 1762 ret = clk_prepare_enable(pcm512x->sclk); 1763 if (ret != 0) { 1764 dev_err(dev, "Failed to enable SCLK: %d\n", ret); 1765 return ret; 1766 } 1767 } 1768 1769 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), 1770 pcm512x->supplies); 1771 if (ret != 0) { 1772 dev_err(dev, "Failed to enable supplies: %d\n", ret); 1773 return ret; 1774 } 1775 1776 regcache_cache_only(pcm512x->regmap, false); 1777 ret = regcache_sync(pcm512x->regmap); 1778 if (ret != 0) { 1779 dev_err(dev, "Failed to sync cache: %d\n", ret); 1780 return ret; 1781 } 1782 1783 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, 1784 PCM512x_RQPD, 0); 1785 if (ret != 0) { 1786 dev_err(dev, "Failed to remove power down: %d\n", ret); 1787 return ret; 1788 } 1789 1790 return 0; 1791 } 1792 1793 EXPORT_GPL_DEV_PM_OPS(pcm512x_pm_ops) = { 1794 RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) 1795 }; 1796 1797 MODULE_DESCRIPTION("ASoC PCM512x codec driver"); 1798 MODULE_AUTHOR("Mark Brown <broonie@kernel.org>"); 1799 MODULE_LICENSE("GPL v2"); 1800