1 /* 2 * PCM3168A codec driver 3 * 4 * Copyright (C) 2015 Imagination Technologies Ltd. 5 * 6 * Author: Damien Horsley <Damien.Horsley@imgtec.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #include "pcm3168a.h" 24 25 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 26 SNDRV_PCM_FMTBIT_S24_3LE | \ 27 SNDRV_PCM_FMTBIT_S24_LE | \ 28 SNDRV_PCM_FMTBIT_S32_LE) 29 30 #define PCM3168A_FMT_I2S 0x0 31 #define PCM3168A_FMT_LEFT_J 0x1 32 #define PCM3168A_FMT_RIGHT_J 0x2 33 #define PCM3168A_FMT_RIGHT_J_16 0x3 34 #define PCM3168A_FMT_DSP_A 0x4 35 #define PCM3168A_FMT_DSP_B 0x5 36 #define PCM3168A_FMT_I2S_TDM 0x6 37 #define PCM3168A_FMT_LEFT_J_TDM 0x7 38 #define PCM3168A_FMT_DSP_MASK 0x4 39 40 #define PCM3168A_NUM_SUPPLIES 6 41 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = { 42 "VDD1", 43 "VDD2", 44 "VCCAD1", 45 "VCCAD2", 46 "VCCDA1", 47 "VCCDA2" 48 }; 49 50 struct pcm3168a_priv { 51 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES]; 52 struct regmap *regmap; 53 struct clk *scki; 54 bool adc_master_mode; 55 bool dac_master_mode; 56 unsigned long sysclk; 57 unsigned int adc_fmt; 58 unsigned int dac_fmt; 59 }; 60 61 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" }; 62 63 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT, 64 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off); 65 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT, 66 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off); 67 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT, 68 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off); 69 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT, 70 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off); 71 72 static const char *const pcm3168a_volume_type[] = { 73 "Individual", "Master + Individual" }; 74 75 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF, 76 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type); 77 78 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" }; 79 80 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF, 81 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult); 82 83 static const char *const pcm3168a_demp[] = { 84 "Disabled", "48khz", "44.1khz", "32khz" }; 85 86 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF, 87 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp); 88 89 static const char *const pcm3168a_zf_func[] = { 90 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND", 91 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" }; 92 93 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF, 94 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func); 95 96 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" }; 97 98 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF, 99 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol); 100 101 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" }; 102 103 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD, 104 0, 1, pcm3168a_con); 105 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD, 106 2, 3, pcm3168a_con); 107 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD, 108 4, 5, pcm3168a_con); 109 110 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF, 111 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type); 112 113 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF, 114 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult); 115 116 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF, 117 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol); 118 119 /* -100db to 0db, register values 0-54 cause mute */ 120 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1); 121 122 /* -100db to 20db, register values 0-14 cause mute */ 123 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1); 124 125 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = { 126 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT, 127 PCM3168A_DAC_PSMDA_SHIFT, 1, 1), 128 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off), 129 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off), 130 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off), 131 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off), 132 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0), 133 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0), 134 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0), 135 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0), 136 SOC_DOUBLE_STS("DAC1 Zero Flag", PCM3168A_DAC_ZERO, 0, 1, 1, 0), 137 SOC_DOUBLE_STS("DAC2 Zero Flag", PCM3168A_DAC_ZERO, 2, 3, 1, 0), 138 SOC_DOUBLE_STS("DAC3 Zero Flag", PCM3168A_DAC_ZERO, 4, 5, 1, 0), 139 SOC_DOUBLE_STS("DAC4 Zero Flag", PCM3168A_DAC_ZERO, 6, 7, 1, 0), 140 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type), 141 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult), 142 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp), 143 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func), 144 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol), 145 SOC_SINGLE_RANGE_TLV("Master Playback Volume", 146 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0, 147 pcm3168a_dac_tlv), 148 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume", 149 PCM3168A_DAC_VOL_CHAN_START, 150 PCM3168A_DAC_VOL_CHAN_START + 1, 151 0, 54, 255, 0, pcm3168a_dac_tlv), 152 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume", 153 PCM3168A_DAC_VOL_CHAN_START + 2, 154 PCM3168A_DAC_VOL_CHAN_START + 3, 155 0, 54, 255, 0, pcm3168a_dac_tlv), 156 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume", 157 PCM3168A_DAC_VOL_CHAN_START + 4, 158 PCM3168A_DAC_VOL_CHAN_START + 5, 159 0, 54, 255, 0, pcm3168a_dac_tlv), 160 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume", 161 PCM3168A_DAC_VOL_CHAN_START + 6, 162 PCM3168A_DAC_VOL_CHAN_START + 7, 163 0, 54, 255, 0, pcm3168a_dac_tlv), 164 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 165 PCM3168A_ADC_BYP_SHIFT, 1, 1), 166 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 167 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1), 168 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, 169 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1), 170 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con), 171 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con), 172 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con), 173 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0), 174 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0), 175 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0), 176 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0), 177 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0), 178 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0), 179 SOC_DOUBLE_STS("ADC1 Overflow Flag", PCM3168A_ADC_OV, 0, 1, 1, 0), 180 SOC_DOUBLE_STS("ADC2 Overflow Flag", PCM3168A_ADC_OV, 2, 3, 1, 0), 181 SOC_DOUBLE_STS("ADC3 Overflow Flag", PCM3168A_ADC_OV, 4, 5, 1, 0), 182 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type), 183 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult), 184 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol), 185 SOC_SINGLE_RANGE_TLV("Master Capture Volume", 186 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0, 187 pcm3168a_adc_tlv), 188 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume", 189 PCM3168A_ADC_VOL_CHAN_START, 190 PCM3168A_ADC_VOL_CHAN_START + 1, 191 0, 14, 255, 0, pcm3168a_adc_tlv), 192 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume", 193 PCM3168A_ADC_VOL_CHAN_START + 2, 194 PCM3168A_ADC_VOL_CHAN_START + 3, 195 0, 14, 255, 0, pcm3168a_adc_tlv), 196 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume", 197 PCM3168A_ADC_VOL_CHAN_START + 4, 198 PCM3168A_ADC_VOL_CHAN_START + 5, 199 0, 14, 255, 0, pcm3168a_adc_tlv) 200 }; 201 202 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = { 203 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT, 204 PCM3168A_DAC_OPEDA_SHIFT, 1), 205 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT, 206 PCM3168A_DAC_OPEDA_SHIFT + 1, 1), 207 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT, 208 PCM3168A_DAC_OPEDA_SHIFT + 2, 1), 209 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT, 210 PCM3168A_DAC_OPEDA_SHIFT + 3, 1), 211 212 SND_SOC_DAPM_OUTPUT("AOUT1L"), 213 SND_SOC_DAPM_OUTPUT("AOUT1R"), 214 SND_SOC_DAPM_OUTPUT("AOUT2L"), 215 SND_SOC_DAPM_OUTPUT("AOUT2R"), 216 SND_SOC_DAPM_OUTPUT("AOUT3L"), 217 SND_SOC_DAPM_OUTPUT("AOUT3R"), 218 SND_SOC_DAPM_OUTPUT("AOUT4L"), 219 SND_SOC_DAPM_OUTPUT("AOUT4R"), 220 221 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB, 222 PCM3168A_ADC_PSVAD_SHIFT, 1), 223 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB, 224 PCM3168A_ADC_PSVAD_SHIFT + 1, 1), 225 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB, 226 PCM3168A_ADC_PSVAD_SHIFT + 2, 1), 227 228 SND_SOC_DAPM_INPUT("AIN1L"), 229 SND_SOC_DAPM_INPUT("AIN1R"), 230 SND_SOC_DAPM_INPUT("AIN2L"), 231 SND_SOC_DAPM_INPUT("AIN2R"), 232 SND_SOC_DAPM_INPUT("AIN3L"), 233 SND_SOC_DAPM_INPUT("AIN3R") 234 }; 235 236 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = { 237 /* Playback */ 238 { "AOUT1L", NULL, "DAC1" }, 239 { "AOUT1R", NULL, "DAC1" }, 240 241 { "AOUT2L", NULL, "DAC2" }, 242 { "AOUT2R", NULL, "DAC2" }, 243 244 { "AOUT3L", NULL, "DAC3" }, 245 { "AOUT3R", NULL, "DAC3" }, 246 247 { "AOUT4L", NULL, "DAC4" }, 248 { "AOUT4R", NULL, "DAC4" }, 249 250 /* Capture */ 251 { "ADC1", NULL, "AIN1L" }, 252 { "ADC1", NULL, "AIN1R" }, 253 254 { "ADC2", NULL, "AIN2L" }, 255 { "ADC2", NULL, "AIN2R" }, 256 257 { "ADC3", NULL, "AIN3L" }, 258 { "ADC3", NULL, "AIN3R" } 259 }; 260 261 static unsigned int pcm3168a_scki_ratios[] = { 262 768, 263 512, 264 384, 265 256, 266 192, 267 128 268 }; 269 270 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios) 271 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2) 272 273 #define PCM1368A_MAX_SYSCLK 36864000 274 275 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a) 276 { 277 int ret; 278 279 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0); 280 if (ret) 281 return ret; 282 283 /* Internal reset is de-asserted after 3846 SCKI cycles */ 284 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); 285 286 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 287 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK); 288 } 289 290 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute) 291 { 292 struct snd_soc_component *component = dai->component; 293 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 294 295 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0); 296 297 return 0; 298 } 299 300 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai, 301 int clk_id, unsigned int freq, int dir) 302 { 303 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component); 304 int ret; 305 306 if (freq > PCM1368A_MAX_SYSCLK) 307 return -EINVAL; 308 309 ret = clk_set_rate(pcm3168a->scki, freq); 310 if (ret) 311 return ret; 312 313 pcm3168a->sysclk = freq; 314 315 return 0; 316 } 317 318 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, 319 unsigned int format, bool dac) 320 { 321 struct snd_soc_component *component = dai->component; 322 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 323 u32 fmt, reg, mask, shift; 324 bool master_mode; 325 326 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 327 case SND_SOC_DAIFMT_LEFT_J: 328 fmt = PCM3168A_FMT_LEFT_J; 329 break; 330 case SND_SOC_DAIFMT_I2S: 331 fmt = PCM3168A_FMT_I2S; 332 break; 333 case SND_SOC_DAIFMT_RIGHT_J: 334 fmt = PCM3168A_FMT_RIGHT_J; 335 break; 336 case SND_SOC_DAIFMT_DSP_A: 337 fmt = PCM3168A_FMT_DSP_A; 338 break; 339 case SND_SOC_DAIFMT_DSP_B: 340 fmt = PCM3168A_FMT_DSP_B; 341 break; 342 default: 343 dev_err(component->dev, "unsupported dai format\n"); 344 return -EINVAL; 345 } 346 347 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 348 case SND_SOC_DAIFMT_CBS_CFS: 349 master_mode = false; 350 break; 351 case SND_SOC_DAIFMT_CBM_CFM: 352 master_mode = true; 353 break; 354 default: 355 dev_err(component->dev, "unsupported master/slave mode\n"); 356 return -EINVAL; 357 } 358 359 switch (format & SND_SOC_DAIFMT_INV_MASK) { 360 case SND_SOC_DAIFMT_NB_NF: 361 break; 362 default: 363 return -EINVAL; 364 } 365 366 if (dac) { 367 reg = PCM3168A_DAC_PWR_MST_FMT; 368 mask = PCM3168A_DAC_FMT_MASK; 369 shift = PCM3168A_DAC_FMT_SHIFT; 370 pcm3168a->dac_master_mode = master_mode; 371 pcm3168a->dac_fmt = fmt; 372 } else { 373 reg = PCM3168A_ADC_MST_FMT; 374 mask = PCM3168A_ADC_FMTAD_MASK; 375 shift = PCM3168A_ADC_FMTAD_SHIFT; 376 pcm3168a->adc_master_mode = master_mode; 377 pcm3168a->adc_fmt = fmt; 378 } 379 380 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 381 382 return 0; 383 } 384 385 static int pcm3168a_set_dai_fmt_dac(struct snd_soc_dai *dai, 386 unsigned int format) 387 { 388 return pcm3168a_set_dai_fmt(dai, format, true); 389 } 390 391 static int pcm3168a_set_dai_fmt_adc(struct snd_soc_dai *dai, 392 unsigned int format) 393 { 394 return pcm3168a_set_dai_fmt(dai, format, false); 395 } 396 397 static int pcm3168a_hw_params(struct snd_pcm_substream *substream, 398 struct snd_pcm_hw_params *params, 399 struct snd_soc_dai *dai) 400 { 401 struct snd_soc_component *component = dai->component; 402 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 403 bool tx, master_mode; 404 u32 val, mask, shift, reg; 405 unsigned int rate, fmt, ratio, max_ratio; 406 unsigned int chan; 407 int i, min_frame_size; 408 409 rate = params_rate(params); 410 chan = params_channels(params); 411 412 ratio = pcm3168a->sysclk / rate; 413 414 tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 415 if (tx) { 416 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC; 417 reg = PCM3168A_DAC_PWR_MST_FMT; 418 mask = PCM3168A_DAC_MSDA_MASK; 419 shift = PCM3168A_DAC_MSDA_SHIFT; 420 master_mode = pcm3168a->dac_master_mode; 421 fmt = pcm3168a->dac_fmt; 422 } else { 423 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC; 424 reg = PCM3168A_ADC_MST_FMT; 425 mask = PCM3168A_ADC_MSAD_MASK; 426 shift = PCM3168A_ADC_MSAD_SHIFT; 427 master_mode = pcm3168a->adc_master_mode; 428 fmt = pcm3168a->adc_fmt; 429 } 430 431 for (i = 0; i < max_ratio; i++) { 432 if (pcm3168a_scki_ratios[i] == ratio) 433 break; 434 } 435 436 if (i == max_ratio) { 437 dev_err(component->dev, "unsupported sysclk ratio\n"); 438 return -EINVAL; 439 } 440 441 min_frame_size = params_width(params) * 2; 442 switch (min_frame_size) { 443 case 32: 444 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) { 445 dev_err(component->dev, "32-bit frames are supported only for slave mode using right justified\n"); 446 return -EINVAL; 447 } 448 fmt = PCM3168A_FMT_RIGHT_J_16; 449 break; 450 case 48: 451 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) { 452 dev_err(component->dev, "48-bit frames not supported in master mode, or slave mode using DSP\n"); 453 return -EINVAL; 454 } 455 break; 456 case 64: 457 break; 458 default: 459 dev_err(component->dev, "unsupported frame size: %d\n", min_frame_size); 460 return -EINVAL; 461 } 462 463 /* for TDM */ 464 if (chan > 2) { 465 switch (fmt) { 466 case PCM3168A_FMT_I2S: 467 fmt = PCM3168A_FMT_I2S_TDM; 468 break; 469 case PCM3168A_FMT_LEFT_J: 470 fmt = PCM3168A_FMT_LEFT_J_TDM; 471 break; 472 default: 473 dev_err(component->dev, "TDM is supported under I2S/Left_J only\n"); 474 return -EINVAL; 475 } 476 } 477 478 if (master_mode) 479 val = ((i + 1) << shift); 480 else 481 val = 0; 482 483 regmap_update_bits(pcm3168a->regmap, reg, mask, val); 484 485 if (tx) { 486 mask = PCM3168A_DAC_FMT_MASK; 487 shift = PCM3168A_DAC_FMT_SHIFT; 488 } else { 489 mask = PCM3168A_ADC_FMTAD_MASK; 490 shift = PCM3168A_ADC_FMTAD_SHIFT; 491 } 492 493 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); 494 495 return 0; 496 } 497 498 static int pcm3168a_startup(struct snd_pcm_substream *substream, 499 struct snd_soc_dai *dai) 500 { 501 struct snd_soc_component *component = dai->component; 502 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component); 503 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 504 unsigned int fmt; 505 unsigned int sample_min; 506 unsigned int channel_max; 507 508 if (tx) 509 fmt = pcm3168a->dac_fmt; 510 else 511 fmt = pcm3168a->adc_fmt; 512 513 /* 514 * Available Data Bits 515 * 516 * RIGHT_J : 24 / 16 517 * LEFT_J : 24 518 * I2S : 24 519 * 520 * TDM available 521 * 522 * I2S 523 * LEFT_J 524 */ 525 switch (fmt) { 526 case PCM3168A_FMT_RIGHT_J: 527 sample_min = 16; 528 channel_max = 2; 529 break; 530 case PCM3168A_FMT_LEFT_J: 531 sample_min = 24; 532 if (tx) 533 channel_max = 8; 534 else 535 channel_max = 6; 536 break; 537 case PCM3168A_FMT_I2S: 538 sample_min = 24; 539 if (tx) 540 channel_max = 8; 541 else 542 channel_max = 6; 543 break; 544 default: 545 sample_min = 24; 546 channel_max = 2; 547 } 548 549 snd_pcm_hw_constraint_minmax(substream->runtime, 550 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 551 sample_min, 32); 552 553 snd_pcm_hw_constraint_minmax(substream->runtime, 554 SNDRV_PCM_HW_PARAM_CHANNELS, 555 2, channel_max); 556 557 return 0; 558 } 559 static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = { 560 .startup = pcm3168a_startup, 561 .set_fmt = pcm3168a_set_dai_fmt_dac, 562 .set_sysclk = pcm3168a_set_dai_sysclk, 563 .hw_params = pcm3168a_hw_params, 564 .digital_mute = pcm3168a_digital_mute 565 }; 566 567 static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = { 568 .startup = pcm3168a_startup, 569 .set_fmt = pcm3168a_set_dai_fmt_adc, 570 .set_sysclk = pcm3168a_set_dai_sysclk, 571 .hw_params = pcm3168a_hw_params 572 }; 573 574 static struct snd_soc_dai_driver pcm3168a_dais[] = { 575 { 576 .name = "pcm3168a-dac", 577 .playback = { 578 .stream_name = "Playback", 579 .channels_min = 1, 580 .channels_max = 8, 581 .rates = SNDRV_PCM_RATE_8000_192000, 582 .formats = PCM3168A_FORMATS 583 }, 584 .ops = &pcm3168a_dac_dai_ops 585 }, 586 { 587 .name = "pcm3168a-adc", 588 .capture = { 589 .stream_name = "Capture", 590 .channels_min = 1, 591 .channels_max = 6, 592 .rates = SNDRV_PCM_RATE_8000_96000, 593 .formats = PCM3168A_FORMATS 594 }, 595 .ops = &pcm3168a_adc_dai_ops 596 }, 597 }; 598 599 static const struct reg_default pcm3168a_reg_default[] = { 600 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK }, 601 { PCM3168A_DAC_PWR_MST_FMT, 0x00 }, 602 { PCM3168A_DAC_OP_FLT, 0x00 }, 603 { PCM3168A_DAC_INV, 0x00 }, 604 { PCM3168A_DAC_MUTE, 0x00 }, 605 { PCM3168A_DAC_ZERO, 0x00 }, 606 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 }, 607 { PCM3168A_DAC_VOL_MASTER, 0xff }, 608 { PCM3168A_DAC_VOL_CHAN_START, 0xff }, 609 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff }, 610 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff }, 611 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff }, 612 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff }, 613 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff }, 614 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff }, 615 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff }, 616 { PCM3168A_ADC_SMODE, 0x00 }, 617 { PCM3168A_ADC_MST_FMT, 0x00 }, 618 { PCM3168A_ADC_PWR_HPFB, 0x00 }, 619 { PCM3168A_ADC_SEAD, 0x00 }, 620 { PCM3168A_ADC_INV, 0x00 }, 621 { PCM3168A_ADC_MUTE, 0x00 }, 622 { PCM3168A_ADC_OV, 0x00 }, 623 { PCM3168A_ADC_ATT_OVF, 0x00 }, 624 { PCM3168A_ADC_VOL_MASTER, 0xd3 }, 625 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 }, 626 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 }, 627 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 }, 628 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 }, 629 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 }, 630 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 } 631 }; 632 633 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) 634 { 635 if (reg >= PCM3168A_RST_SMODE) 636 return true; 637 else 638 return false; 639 } 640 641 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) 642 { 643 switch (reg) { 644 case PCM3168A_DAC_ZERO: 645 case PCM3168A_ADC_OV: 646 return true; 647 default: 648 return false; 649 } 650 } 651 652 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) 653 { 654 if (reg < PCM3168A_RST_SMODE) 655 return false; 656 657 switch (reg) { 658 case PCM3168A_DAC_ZERO: 659 case PCM3168A_ADC_OV: 660 return false; 661 default: 662 return true; 663 } 664 } 665 666 const struct regmap_config pcm3168a_regmap = { 667 .reg_bits = 8, 668 .val_bits = 8, 669 670 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5, 671 .reg_defaults = pcm3168a_reg_default, 672 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default), 673 .readable_reg = pcm3168a_readable_register, 674 .volatile_reg = pcm3168a_volatile_register, 675 .writeable_reg = pcm3168a_writeable_register, 676 .cache_type = REGCACHE_FLAT 677 }; 678 EXPORT_SYMBOL_GPL(pcm3168a_regmap); 679 680 static const struct snd_soc_component_driver pcm3168a_driver = { 681 .controls = pcm3168a_snd_controls, 682 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls), 683 .dapm_widgets = pcm3168a_dapm_widgets, 684 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets), 685 .dapm_routes = pcm3168a_dapm_routes, 686 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes), 687 .use_pmdown_time = 1, 688 .endianness = 1, 689 .non_legacy_dai_naming = 1, 690 }; 691 692 int pcm3168a_probe(struct device *dev, struct regmap *regmap) 693 { 694 struct pcm3168a_priv *pcm3168a; 695 int ret, i; 696 697 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL); 698 if (pcm3168a == NULL) 699 return -ENOMEM; 700 701 dev_set_drvdata(dev, pcm3168a); 702 703 pcm3168a->scki = devm_clk_get(dev, "scki"); 704 if (IS_ERR(pcm3168a->scki)) { 705 ret = PTR_ERR(pcm3168a->scki); 706 if (ret != -EPROBE_DEFER) 707 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret); 708 return ret; 709 } 710 711 ret = clk_prepare_enable(pcm3168a->scki); 712 if (ret) { 713 dev_err(dev, "Failed to enable mclk: %d\n", ret); 714 return ret; 715 } 716 717 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki); 718 719 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++) 720 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i]; 721 722 ret = devm_regulator_bulk_get(dev, 723 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies); 724 if (ret) { 725 if (ret != -EPROBE_DEFER) 726 dev_err(dev, "failed to request supplies: %d\n", ret); 727 goto err_clk; 728 } 729 730 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 731 pcm3168a->supplies); 732 if (ret) { 733 dev_err(dev, "failed to enable supplies: %d\n", ret); 734 goto err_clk; 735 } 736 737 pcm3168a->regmap = regmap; 738 if (IS_ERR(pcm3168a->regmap)) { 739 ret = PTR_ERR(pcm3168a->regmap); 740 dev_err(dev, "failed to allocate regmap: %d\n", ret); 741 goto err_regulator; 742 } 743 744 ret = pcm3168a_reset(pcm3168a); 745 if (ret) { 746 dev_err(dev, "Failed to reset device: %d\n", ret); 747 goto err_regulator; 748 } 749 750 pm_runtime_set_active(dev); 751 pm_runtime_enable(dev); 752 pm_runtime_idle(dev); 753 754 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais, 755 ARRAY_SIZE(pcm3168a_dais)); 756 if (ret) { 757 dev_err(dev, "failed to register component: %d\n", ret); 758 goto err_regulator; 759 } 760 761 return 0; 762 763 err_regulator: 764 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 765 pcm3168a->supplies); 766 err_clk: 767 clk_disable_unprepare(pcm3168a->scki); 768 769 return ret; 770 } 771 EXPORT_SYMBOL_GPL(pcm3168a_probe); 772 773 void pcm3168a_remove(struct device *dev) 774 { 775 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 776 777 pm_runtime_disable(dev); 778 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 779 pcm3168a->supplies); 780 clk_disable_unprepare(pcm3168a->scki); 781 } 782 EXPORT_SYMBOL_GPL(pcm3168a_remove); 783 784 #ifdef CONFIG_PM 785 static int pcm3168a_rt_resume(struct device *dev) 786 { 787 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 788 int ret; 789 790 ret = clk_prepare_enable(pcm3168a->scki); 791 if (ret) { 792 dev_err(dev, "Failed to enable mclk: %d\n", ret); 793 return ret; 794 } 795 796 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), 797 pcm3168a->supplies); 798 if (ret) { 799 dev_err(dev, "Failed to enable supplies: %d\n", ret); 800 goto err_clk; 801 } 802 803 ret = pcm3168a_reset(pcm3168a); 804 if (ret) { 805 dev_err(dev, "Failed to reset device: %d\n", ret); 806 goto err_regulator; 807 } 808 809 regcache_cache_only(pcm3168a->regmap, false); 810 811 regcache_mark_dirty(pcm3168a->regmap); 812 813 ret = regcache_sync(pcm3168a->regmap); 814 if (ret) { 815 dev_err(dev, "Failed to sync regmap: %d\n", ret); 816 goto err_regulator; 817 } 818 819 return 0; 820 821 err_regulator: 822 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 823 pcm3168a->supplies); 824 err_clk: 825 clk_disable_unprepare(pcm3168a->scki); 826 827 return ret; 828 } 829 830 static int pcm3168a_rt_suspend(struct device *dev) 831 { 832 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); 833 834 regcache_cache_only(pcm3168a->regmap, true); 835 836 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), 837 pcm3168a->supplies); 838 839 clk_disable_unprepare(pcm3168a->scki); 840 841 return 0; 842 } 843 #endif 844 845 const struct dev_pm_ops pcm3168a_pm_ops = { 846 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL) 847 }; 848 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops); 849 850 MODULE_DESCRIPTION("PCM3168A codec driver"); 851 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); 852 MODULE_LICENSE("GPL v2"); 853