1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Nuvoton NAU8825 audio codec driver 4 * 5 * Copyright 2015 Google Chromium project. 6 * Author: Anatol Pomozov <anatol@chromium.org> 7 * Copyright 2015 Nuvoton Technology Corp. 8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com> 9 */ 10 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/i2c.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/clk.h> 18 #include <linux/acpi.h> 19 #include <linux/math64.h> 20 #include <linux/semaphore.h> 21 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/jack.h> 29 30 31 #include "nau8825.h" 32 33 34 #define NUVOTON_CODEC_DAI "nau8825-hifi" 35 36 #define NAU_FREF_MAX 13500000 37 #define NAU_FVCO_MAX 124000000 38 #define NAU_FVCO_MIN 90000000 39 40 /* cross talk suppression detection */ 41 #define LOG10_MAGIC 646456993 42 #define GAIN_AUGMENT 22500 43 #define SIDETONE_BASE 207000 44 45 /* the maximum frequency of CLK_ADC and CLK_DAC */ 46 #define CLK_DA_AD_MAX 6144000 47 48 static int nau8825_configure_sysclk(struct nau8825 *nau8825, 49 int clk_id, unsigned int freq); 50 static bool nau8825_is_jack_inserted(struct regmap *regmap); 51 52 struct nau8825_fll { 53 int mclk_src; 54 int ratio; 55 int fll_frac; 56 int fll_int; 57 int clk_ref_div; 58 }; 59 60 struct nau8825_fll_attr { 61 unsigned int param; 62 unsigned int val; 63 }; 64 65 /* scaling for mclk from sysclk_src output */ 66 static const struct nau8825_fll_attr mclk_src_scaling[] = { 67 { 1, 0x0 }, 68 { 2, 0x2 }, 69 { 4, 0x3 }, 70 { 8, 0x4 }, 71 { 16, 0x5 }, 72 { 32, 0x6 }, 73 { 3, 0x7 }, 74 { 6, 0xa }, 75 { 12, 0xb }, 76 { 24, 0xc }, 77 { 48, 0xd }, 78 { 96, 0xe }, 79 { 5, 0xf }, 80 }; 81 82 /* ratio for input clk freq */ 83 static const struct nau8825_fll_attr fll_ratio[] = { 84 { 512000, 0x01 }, 85 { 256000, 0x02 }, 86 { 128000, 0x04 }, 87 { 64000, 0x08 }, 88 { 32000, 0x10 }, 89 { 8000, 0x20 }, 90 { 4000, 0x40 }, 91 }; 92 93 static const struct nau8825_fll_attr fll_pre_scalar[] = { 94 { 1, 0x0 }, 95 { 2, 0x1 }, 96 { 4, 0x2 }, 97 { 8, 0x3 }, 98 }; 99 100 /* over sampling rate */ 101 struct nau8825_osr_attr { 102 unsigned int osr; 103 unsigned int clk_src; 104 }; 105 106 static const struct nau8825_osr_attr osr_dac_sel[] = { 107 { 64, 2 }, /* OSR 64, SRC 1/4 */ 108 { 256, 0 }, /* OSR 256, SRC 1 */ 109 { 128, 1 }, /* OSR 128, SRC 1/2 */ 110 { 0, 0 }, 111 { 32, 3 }, /* OSR 32, SRC 1/8 */ 112 }; 113 114 static const struct nau8825_osr_attr osr_adc_sel[] = { 115 { 32, 3 }, /* OSR 32, SRC 1/8 */ 116 { 64, 2 }, /* OSR 64, SRC 1/4 */ 117 { 128, 1 }, /* OSR 128, SRC 1/2 */ 118 { 256, 0 }, /* OSR 256, SRC 1 */ 119 }; 120 121 static const struct reg_default nau8825_reg_defaults[] = { 122 { NAU8825_REG_ENA_CTRL, 0x00ff }, 123 { NAU8825_REG_IIC_ADDR_SET, 0x0 }, 124 { NAU8825_REG_CLK_DIVIDER, 0x0050 }, 125 { NAU8825_REG_FLL1, 0x0 }, 126 { NAU8825_REG_FLL2, 0x3126 }, 127 { NAU8825_REG_FLL3, 0x0008 }, 128 { NAU8825_REG_FLL4, 0x0010 }, 129 { NAU8825_REG_FLL5, 0x0 }, 130 { NAU8825_REG_FLL6, 0x6000 }, 131 { NAU8825_REG_FLL_VCO_RSV, 0xf13c }, 132 { NAU8825_REG_HSD_CTRL, 0x000c }, 133 { NAU8825_REG_JACK_DET_CTRL, 0x0 }, 134 { NAU8825_REG_INTERRUPT_MASK, 0x0 }, 135 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff }, 136 { NAU8825_REG_SAR_CTRL, 0x0015 }, 137 { NAU8825_REG_KEYDET_CTRL, 0x0110 }, 138 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 }, 139 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 }, 140 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 }, 141 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 }, 142 { NAU8825_REG_GPIO34_CTRL, 0x0 }, 143 { NAU8825_REG_GPIO12_CTRL, 0x0 }, 144 { NAU8825_REG_TDM_CTRL, 0x0 }, 145 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b }, 146 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 }, 147 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 }, 148 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 }, 149 { NAU8825_REG_BIQ_CTRL, 0x0 }, 150 { NAU8825_REG_BIQ_COF1, 0x0 }, 151 { NAU8825_REG_BIQ_COF2, 0x0 }, 152 { NAU8825_REG_BIQ_COF3, 0x0 }, 153 { NAU8825_REG_BIQ_COF4, 0x0 }, 154 { NAU8825_REG_BIQ_COF5, 0x0 }, 155 { NAU8825_REG_BIQ_COF6, 0x0 }, 156 { NAU8825_REG_BIQ_COF7, 0x0 }, 157 { NAU8825_REG_BIQ_COF8, 0x0 }, 158 { NAU8825_REG_BIQ_COF9, 0x0 }, 159 { NAU8825_REG_BIQ_COF10, 0x0 }, 160 { NAU8825_REG_ADC_RATE, 0x0010 }, 161 { NAU8825_REG_DAC_CTRL1, 0x0001 }, 162 { NAU8825_REG_DAC_CTRL2, 0x0 }, 163 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 }, 164 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 165 { NAU8825_REG_MUTE_CTRL, 0x0 }, 166 { NAU8825_REG_HSVOL_CTRL, 0x0 }, 167 { NAU8825_REG_DACL_CTRL, 0x02cf }, 168 { NAU8825_REG_DACR_CTRL, 0x00cf }, 169 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 }, 170 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 }, 171 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff }, 172 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 }, 173 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 }, 174 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 }, 175 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 }, 176 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 }, 177 { NAU8825_REG_IMM_MODE_CTRL, 0x0 }, 178 { NAU8825_REG_CLASSG_CTRL, 0x0 }, 179 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 }, 180 { NAU8825_REG_MISC_CTRL, 0x0 }, 181 { NAU8825_REG_BIAS_ADJ, 0x0 }, 182 { NAU8825_REG_TRIM_SETTINGS, 0x0 }, 183 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 }, 184 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 }, 185 { NAU8825_REG_ANALOG_ADC_1, 0x0011 }, 186 { NAU8825_REG_ANALOG_ADC_2, 0x0020 }, 187 { NAU8825_REG_RDAC, 0x0008 }, 188 { NAU8825_REG_MIC_BIAS, 0x0006 }, 189 { NAU8825_REG_BOOST, 0x0 }, 190 { NAU8825_REG_FEPGA, 0x0 }, 191 { NAU8825_REG_POWER_UP_CONTROL, 0x0 }, 192 { NAU8825_REG_CHARGE_PUMP, 0x0 }, 193 }; 194 195 /* register backup table when cross talk detection */ 196 static struct reg_default nau8825_xtalk_baktab[] = { 197 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 198 { NAU8825_REG_HSVOL_CTRL, 0 }, 199 { NAU8825_REG_DACL_CTRL, 0x00cf }, 200 { NAU8825_REG_DACR_CTRL, 0x02cf }, 201 }; 202 203 static const unsigned short logtable[256] = { 204 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7, 205 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508, 206 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6, 207 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37, 208 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f, 209 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41, 210 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1, 211 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142, 212 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68, 213 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355, 214 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c, 215 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490, 216 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3, 217 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507, 218 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe, 219 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca, 220 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c, 221 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7, 222 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c, 223 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c, 224 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a, 225 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065, 226 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730, 227 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc, 228 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469, 229 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9, 230 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c, 231 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765, 232 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83, 233 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387, 234 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973, 235 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47 236 }; 237 238 /** 239 * nau8825_sema_acquire - acquire the semaphore of nau88l25 240 * @nau8825: component to register the codec private data with 241 * @timeout: how long in jiffies to wait before failure or zero to wait 242 * until release 243 * 244 * Attempts to acquire the semaphore with number of jiffies. If no more 245 * tasks are allowed to acquire the semaphore, calling this function will 246 * put the task to sleep. If the semaphore is not released within the 247 * specified number of jiffies, this function returns. 248 * If the semaphore is not released within the specified number of jiffies, 249 * this function returns -ETIME. If the sleep is interrupted by a signal, 250 * this function will return -EINTR. It returns 0 if the semaphore was 251 * acquired successfully. 252 * 253 * Acquires the semaphore without jiffies. Try to acquire the semaphore 254 * atomically. Returns 0 if the semaphore has been acquired successfully 255 * or 1 if it cannot be acquired. 256 */ 257 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout) 258 { 259 int ret; 260 261 if (timeout) { 262 ret = down_timeout(&nau8825->xtalk_sem, timeout); 263 if (ret < 0) 264 dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); 265 } else { 266 ret = down_trylock(&nau8825->xtalk_sem); 267 if (ret) 268 dev_warn(nau8825->dev, "Acquire semaphore fail\n"); 269 } 270 271 return ret; 272 } 273 274 /** 275 * nau8825_sema_release - release the semaphore of nau88l25 276 * @nau8825: component to register the codec private data with 277 * 278 * Release the semaphore which may be called from any context and 279 * even by tasks which have never called down(). 280 */ 281 static inline void nau8825_sema_release(struct nau8825 *nau8825) 282 { 283 up(&nau8825->xtalk_sem); 284 } 285 286 /** 287 * nau8825_sema_reset - reset the semaphore for nau88l25 288 * @nau8825: component to register the codec private data with 289 * 290 * Reset the counter of the semaphore. Call this function to restart 291 * a new round task management. 292 */ 293 static inline void nau8825_sema_reset(struct nau8825 *nau8825) 294 { 295 nau8825->xtalk_sem.count = 1; 296 } 297 298 /** 299 * nau8825_hpvol_ramp - Ramp up the headphone volume change gradually to target level. 300 * 301 * @nau8825: component to register the codec private data with 302 * @vol_from: the volume to start up 303 * @vol_to: the target volume 304 * @step: the volume span to move on 305 * 306 * The headphone volume is from 0dB to minimum -54dB and -1dB per step. 307 * If the volume changes sharp, there is a pop noise heard in headphone. We 308 * provide the function to ramp up the volume up or down by delaying 10ms 309 * per step. 310 */ 311 static void nau8825_hpvol_ramp(struct nau8825 *nau8825, 312 unsigned int vol_from, unsigned int vol_to, unsigned int step) 313 { 314 unsigned int value, volume, ramp_up, from, to; 315 316 if (vol_from == vol_to || step == 0) { 317 return; 318 } else if (vol_from < vol_to) { 319 ramp_up = true; 320 from = vol_from; 321 to = vol_to; 322 } else { 323 ramp_up = false; 324 from = vol_to; 325 to = vol_from; 326 } 327 /* only handle volume from 0dB to minimum -54dB */ 328 if (to > NAU8825_HP_VOL_MIN) 329 to = NAU8825_HP_VOL_MIN; 330 331 for (volume = from; volume < to; volume += step) { 332 if (ramp_up) 333 value = volume; 334 else 335 value = to - volume + from; 336 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 337 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 338 (value << NAU8825_HPL_VOL_SFT) | value); 339 usleep_range(10000, 10500); 340 } 341 if (ramp_up) 342 value = to; 343 else 344 value = from; 345 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 346 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 347 (value << NAU8825_HPL_VOL_SFT) | value); 348 } 349 350 /** 351 * nau8825_intlog10_dec3 - Computes log10 of a value 352 * the result is round off to 3 decimal. This function takes reference to 353 * dvb-math. The source code locates as the following. 354 * Linux/drivers/media/dvb-core/dvb_math.c 355 * @value: input for log10 356 * 357 * return log10(value) * 1000 358 */ 359 static u32 nau8825_intlog10_dec3(u32 value) 360 { 361 u32 msb, logentry, significand, interpolation, log10val; 362 u64 log2val; 363 364 /* first detect the msb (count begins at 0) */ 365 msb = fls(value) - 1; 366 /** 367 * now we use a logtable after the following method: 368 * 369 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24 370 * where x = msb and therefore 1 <= y < 2 371 * first y is determined by shifting the value left 372 * so that msb is bit 31 373 * 0x00231f56 -> 0x8C7D5800 374 * the result is y * 2^31 -> "significand" 375 * then the highest 9 bits are used for a table lookup 376 * the highest bit is discarded because it's always set 377 * the highest nine bits in our example are 100011000 378 * so we would use the entry 0x18 379 */ 380 significand = value << (31 - msb); 381 logentry = (significand >> 23) & 0xff; 382 /** 383 * last step we do is interpolation because of the 384 * limitations of the log table the error is that part of 385 * the significand which isn't used for lookup then we 386 * compute the ratio between the error and the next table entry 387 * and interpolate it between the log table entry used and the 388 * next one the biggest error possible is 0x7fffff 389 * (in our example it's 0x7D5800) 390 * needed value for next table entry is 0x800000 391 * so the interpolation is 392 * (error / 0x800000) * (logtable_next - logtable_current) 393 * in the implementation the division is moved to the end for 394 * better accuracy there is also an overflow correction if 395 * logtable_next is 256 396 */ 397 interpolation = ((significand & 0x7fffff) * 398 ((logtable[(logentry + 1) & 0xff] - 399 logtable[logentry]) & 0xffff)) >> 15; 400 401 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation); 402 /** 403 * log10(x) = log2(x) * log10(2) 404 */ 405 log10val = (log2val * LOG10_MAGIC) >> 31; 406 /** 407 * the result is round off to 3 decimal 408 */ 409 return log10val / ((1 << 24) / 1000); 410 } 411 412 /** 413 * nau8825_xtalk_sidetone - computes cross talk suppression sidetone gain. 414 * 415 * @sig_org: orignal signal level 416 * @sig_cros: cross talk signal level 417 * 418 * The orignal and cross talk signal vlues need to be characterized. 419 * Once these values have been characterized, this sidetone value 420 * can be converted to decibel with the equation below. 421 * sidetone = 20 * log (original signal level / crosstalk signal level) 422 * 423 * return cross talk sidetone gain 424 */ 425 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros) 426 { 427 u32 gain, sidetone; 428 429 if (WARN_ON(sig_org == 0 || sig_cros == 0)) 430 return 0; 431 432 sig_org = nau8825_intlog10_dec3(sig_org); 433 sig_cros = nau8825_intlog10_dec3(sig_cros); 434 if (sig_org >= sig_cros) 435 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT; 436 else 437 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT; 438 sidetone = SIDETONE_BASE - gain * 2; 439 sidetone /= 1000; 440 441 return sidetone; 442 } 443 444 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg) 445 { 446 int index; 447 448 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++) 449 if (nau8825_xtalk_baktab[index].reg == reg) 450 return index; 451 return -EINVAL; 452 } 453 454 static void nau8825_xtalk_backup(struct nau8825 *nau8825) 455 { 456 int i; 457 458 if (nau8825->xtalk_baktab_initialized) 459 return; 460 461 /* Backup some register values to backup table */ 462 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) 463 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 464 &nau8825_xtalk_baktab[i].def); 465 466 nau8825->xtalk_baktab_initialized = true; 467 } 468 469 static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel) 470 { 471 int i, volume; 472 473 if (!nau8825->xtalk_baktab_initialized) 474 return; 475 476 /* Restore register values from backup table; When the driver restores 477 * the headphone volume in XTALK_DONE state, it needs recover to 478 * original level gradually with 3dB per step for less pop noise. 479 * Otherwise, the restore should do ASAP. 480 */ 481 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) { 482 if (!cause_cancel && nau8825_xtalk_baktab[i].reg == 483 NAU8825_REG_HSVOL_CTRL) { 484 /* Ramping up the volume change to reduce pop noise */ 485 volume = nau8825_xtalk_baktab[i].def & 486 NAU8825_HPR_VOL_MASK; 487 nau8825_hpvol_ramp(nau8825, 0, volume, 3); 488 continue; 489 } 490 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 491 nau8825_xtalk_baktab[i].def); 492 } 493 494 nau8825->xtalk_baktab_initialized = false; 495 } 496 497 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825) 498 { 499 /* Enable power of DAC path */ 500 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 501 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 502 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK | 503 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR | 504 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC | 505 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK); 506 /* Prevent startup click by letting charge pump to ramp up and 507 * change bump enable 508 */ 509 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 510 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 511 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN); 512 /* Enable clock sync of DAC and DAC clock */ 513 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 514 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN | 515 NAU8825_RDAC_FS_BCLK_ENB, 516 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN); 517 /* Power up output driver with 2 stage */ 518 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 519 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 520 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 521 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 522 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L); 523 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 524 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 525 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L); 526 /* HP outputs not shouted to ground */ 527 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 528 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0); 529 /* Enable HP boost driver */ 530 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 531 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS); 532 /* Enable class G compare path to supply 1.8V or 0.9V. */ 533 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL, 534 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN, 535 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN); 536 } 537 538 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825) 539 { 540 /* Power up left ADC and raise 5dB than Vmid for Vref */ 541 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 542 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 543 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB); 544 } 545 546 static void nau8825_xtalk_clock(struct nau8825 *nau8825) 547 { 548 /* Recover FLL default value */ 549 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0); 550 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126); 551 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008); 552 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010); 553 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0); 554 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000); 555 /* Enable internal VCO clock for detection signal generated */ 556 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 557 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 558 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 559 NAU8825_DCO_EN); 560 /* Given specific clock frequency of internal clock to 561 * generate signal. 562 */ 563 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 564 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 565 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 566 NAU8825_FLL_RATIO_MASK, 0x10); 567 } 568 569 static void nau8825_xtalk_prepare(struct nau8825 *nau8825) 570 { 571 int volume, index; 572 573 /* Backup those registers changed by cross talk detection */ 574 nau8825_xtalk_backup(nau8825); 575 /* Config IIS as master to output signal by codec */ 576 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 577 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 578 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER | 579 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1); 580 /* Ramp up headphone volume to 0dB to get better performance and 581 * avoid pop noise in headphone. 582 */ 583 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL); 584 if (index != -EINVAL) { 585 volume = nau8825_xtalk_baktab[index].def & 586 NAU8825_HPR_VOL_MASK; 587 nau8825_hpvol_ramp(nau8825, volume, 0, 3); 588 } 589 nau8825_xtalk_clock(nau8825); 590 nau8825_xtalk_prepare_dac(nau8825); 591 nau8825_xtalk_prepare_adc(nau8825); 592 /* Config channel path and digital gain */ 593 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 594 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK, 595 NAU8825_DACL_CH_SEL_L | 0xab); 596 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 597 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK, 598 NAU8825_DACR_CH_SEL_R | 0xab); 599 /* Config cross talk parameters and generate the 23Hz sine wave with 600 * 1/16 full scale of signal level for impedance measurement. 601 */ 602 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 603 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK | 604 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK, 605 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th | 606 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN); 607 /* RMS intrruption enable */ 608 regmap_update_bits(nau8825->regmap, 609 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0); 610 /* Power up left and right DAC */ 611 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 612 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); 613 } 614 615 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825) 616 { 617 /* Disable HP boost driver */ 618 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 619 NAU8825_HP_BOOST_DIS, 0); 620 /* HP outputs shouted to ground */ 621 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 622 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 623 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 624 /* Power down left and right DAC */ 625 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 626 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 627 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 628 /* Enable the TESTDAC and disable L/R HP impedance */ 629 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 630 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP | 631 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 632 /* Power down output driver with 2 stage */ 633 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 634 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0); 635 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 636 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 637 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0); 638 /* Disable clock sync of DAC and DAC clock */ 639 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 640 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0); 641 /* Disable charge pump ramp up function and change bump */ 642 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 643 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0); 644 /* Disable power of DAC path */ 645 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 646 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 647 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0); 648 if (!nau8825->irq) 649 regmap_update_bits(nau8825->regmap, 650 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 651 } 652 653 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825) 654 { 655 /* Power down left ADC and restore voltage to Vmid */ 656 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 657 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0); 658 } 659 660 static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel) 661 { 662 /* Enable internal VCO needed for interruptions */ 663 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 664 nau8825_xtalk_clean_dac(nau8825); 665 nau8825_xtalk_clean_adc(nau8825); 666 /* Clear cross talk parameters and disable */ 667 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0); 668 /* RMS intrruption disable */ 669 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK, 670 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN); 671 /* Recover default value for IIS */ 672 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 673 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 674 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE); 675 /* Restore value of specific register for cross talk */ 676 nau8825_xtalk_restore(nau8825, cause_cancel); 677 } 678 679 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol) 680 { 681 /* Apply ADC volume for better cross talk performance */ 682 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL, 683 NAU8825_ADC_DIG_VOL_MASK, vol); 684 /* Disables JKTIP(HPL) DAC channel for right to left measurement. 685 * Do it before sending signal in order to erase pop noise. 686 */ 687 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 688 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN, 689 NAU8825_BIAS_TESTDACL_EN); 690 switch (nau8825->xtalk_state) { 691 case NAU8825_XTALK_HPR_R2L: 692 /* Enable right headphone impedance */ 693 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 694 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 695 NAU8825_BIAS_HPR_IMP); 696 break; 697 case NAU8825_XTALK_HPL_R2L: 698 /* Enable left headphone impedance */ 699 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 700 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 701 NAU8825_BIAS_HPL_IMP); 702 break; 703 default: 704 break; 705 } 706 msleep(100); 707 /* Impedance measurement mode enable */ 708 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 709 NAU8825_IMM_EN, NAU8825_IMM_EN); 710 } 711 712 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825) 713 { 714 /* Impedance measurement mode disable */ 715 regmap_update_bits(nau8825->regmap, 716 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0); 717 } 718 719 /* The cross talk measurement function can reduce cross talk across the 720 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal 721 * level to determine what cross talk reduction gain is. This system works by 722 * sending a 23Hz -24dBV sine wave into the headset output DAC and through 723 * the PGA. The output of the PGA is then connected to an internal current 724 * sense which measures the attenuated 23Hz signal and passing the output to 725 * an ADC which converts the measurement to a binary code. With two separated 726 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data 727 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement. 728 * Thus, the measurement function has four states to complete whole sequence. 729 * 1. Prepare state : Prepare the resource for detection and transfer to HPR 730 * IMM stat to make JKR1(HPR) impedance measure. 731 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer 732 * to HPL IMM state to make JKTIP(HPL) impedance measure. 733 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and 734 * transfer to IMM state to determine suppression sidetone gain. 735 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal 736 * and cross talk signal level. Apply this gain and then restore codec 737 * configuration. Then transfer to Done state for ending. 738 */ 739 static void nau8825_xtalk_measure(struct nau8825 *nau8825) 740 { 741 u32 sidetone; 742 743 switch (nau8825->xtalk_state) { 744 case NAU8825_XTALK_PREPARE: 745 /* In prepare state, set up clock, intrruption, DAC path, ADC 746 * path and cross talk detection parameters for preparation. 747 */ 748 nau8825_xtalk_prepare(nau8825); 749 msleep(280); 750 /* Trigger right headphone impedance detection */ 751 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L; 752 nau8825_xtalk_imm_start(nau8825, 0x00d2); 753 break; 754 case NAU8825_XTALK_HPR_R2L: 755 /* In right headphone IMM state, read out right headphone 756 * impedance measure result, and then start up left side. 757 */ 758 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 759 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 760 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n", 761 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 762 /* Disable then re-enable IMM mode to update */ 763 nau8825_xtalk_imm_stop(nau8825); 764 /* Trigger left headphone impedance detection */ 765 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L; 766 nau8825_xtalk_imm_start(nau8825, 0x00ff); 767 break; 768 case NAU8825_XTALK_HPL_R2L: 769 /* In left headphone IMM state, read out left headphone 770 * impedance measure result, and delay some time to wait 771 * detection sine wave output finish. Then, we can calculate 772 * the cross talk suppresstion side tone according to the L/R 773 * headphone imedance. 774 */ 775 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 776 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 777 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n", 778 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 779 nau8825_xtalk_imm_stop(nau8825); 780 msleep(150); 781 nau8825->xtalk_state = NAU8825_XTALK_IMM; 782 break; 783 case NAU8825_XTALK_IMM: 784 /* In impedance measure state, the orignal and cross talk 785 * signal level vlues are ready. The side tone gain is deter- 786 * mined with these signal level. After all, restore codec 787 * configuration. 788 */ 789 sidetone = nau8825_xtalk_sidetone( 790 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L], 791 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 792 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone); 793 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL, 794 (sidetone << 8) | sidetone); 795 nau8825_xtalk_clean(nau8825, false); 796 nau8825->xtalk_state = NAU8825_XTALK_DONE; 797 break; 798 default: 799 break; 800 } 801 } 802 803 static void nau8825_xtalk_work(struct work_struct *work) 804 { 805 struct nau8825 *nau8825 = container_of( 806 work, struct nau8825, xtalk_work); 807 808 nau8825_xtalk_measure(nau8825); 809 /* To determine the cross talk side tone gain when reach 810 * the impedance measure state. 811 */ 812 if (nau8825->xtalk_state == NAU8825_XTALK_IMM) 813 nau8825_xtalk_measure(nau8825); 814 815 /* Delay jack report until cross talk detection process 816 * completed. It can avoid application to do playback 817 * preparation before cross talk detection is still working. 818 * Meanwhile, the protection of the cross talk detection 819 * is released. 820 */ 821 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) { 822 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event, 823 nau8825->xtalk_event_mask); 824 nau8825_sema_release(nau8825); 825 nau8825->xtalk_protect = false; 826 } 827 } 828 829 static void nau8825_xtalk_cancel(struct nau8825 *nau8825) 830 { 831 /* If the crosstalk is eanbled and the process is on going, 832 * the driver forces to cancel the crosstalk task and 833 * restores the configuration to original status. 834 */ 835 if (nau8825->xtalk_enable && nau8825->xtalk_state != 836 NAU8825_XTALK_DONE) { 837 cancel_work_sync(&nau8825->xtalk_work); 838 nau8825_xtalk_clean(nau8825, true); 839 } 840 /* Reset parameters for cross talk suppression function */ 841 nau8825_sema_reset(nau8825); 842 nau8825->xtalk_state = NAU8825_XTALK_DONE; 843 nau8825->xtalk_protect = false; 844 } 845 846 static bool nau8825_readable_reg(struct device *dev, unsigned int reg) 847 { 848 switch (reg) { 849 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV: 850 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 851 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL: 852 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 853 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 854 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 855 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R: 856 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 857 case NAU8825_REG_MISC_CTRL: 858 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS: 859 case NAU8825_REG_BIAS_ADJ: 860 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 861 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 862 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 863 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS: 864 return true; 865 default: 866 return false; 867 } 868 869 } 870 871 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg) 872 { 873 switch (reg) { 874 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV: 875 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 876 case NAU8825_REG_INTERRUPT_MASK: 877 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL: 878 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 879 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 880 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 881 case NAU8825_REG_IMM_MODE_CTRL: 882 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 883 case NAU8825_REG_MISC_CTRL: 884 case NAU8825_REG_BIAS_ADJ: 885 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 886 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 887 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 888 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP: 889 return true; 890 default: 891 return false; 892 } 893 } 894 895 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg) 896 { 897 switch (reg) { 898 case NAU8825_REG_RESET: 899 case NAU8825_REG_IRQ_STATUS: 900 case NAU8825_REG_INT_CLR_KEY_STATUS: 901 case NAU8825_REG_IMM_RMS_L: 902 case NAU8825_REG_IMM_RMS_R: 903 case NAU8825_REG_I2C_DEVICE_ID: 904 case NAU8825_REG_SARDOUT_RAM_STATUS: 905 case NAU8825_REG_CHARGE_PUMP_INPUT_READ: 906 case NAU8825_REG_GENERAL_STATUS: 907 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10: 908 return true; 909 default: 910 return false; 911 } 912 } 913 914 static int nau8825_adc_event(struct snd_soc_dapm_widget *w, 915 struct snd_kcontrol *kcontrol, int event) 916 { 917 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 918 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 919 920 switch (event) { 921 case SND_SOC_DAPM_POST_PMU: 922 msleep(125); 923 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 924 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 925 break; 926 case SND_SOC_DAPM_POST_PMD: 927 if (!nau8825->irq) 928 regmap_update_bits(nau8825->regmap, 929 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 930 break; 931 default: 932 return -EINVAL; 933 } 934 935 return 0; 936 } 937 938 static int nau8825_pump_event(struct snd_soc_dapm_widget *w, 939 struct snd_kcontrol *kcontrol, int event) 940 { 941 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 942 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 943 944 switch (event) { 945 case SND_SOC_DAPM_POST_PMU: 946 /* Prevent startup click by letting charge pump to ramp up */ 947 msleep(10); 948 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 949 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW); 950 break; 951 case SND_SOC_DAPM_PRE_PMD: 952 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 953 NAU8825_JAMNODCLOW, 0); 954 break; 955 default: 956 return -EINVAL; 957 } 958 959 return 0; 960 } 961 962 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w, 963 struct snd_kcontrol *kcontrol, int event) 964 { 965 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 966 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 967 968 switch (event) { 969 case SND_SOC_DAPM_PRE_PMU: 970 /* Disables the TESTDAC to let DAC signal pass through. */ 971 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 972 NAU8825_BIAS_TESTDAC_EN, 0); 973 break; 974 case SND_SOC_DAPM_POST_PMD: 975 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 976 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 977 break; 978 default: 979 return -EINVAL; 980 } 981 982 return 0; 983 } 984 985 static int system_clock_control(struct snd_soc_dapm_widget *w, 986 struct snd_kcontrol *k, int event) 987 { 988 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 989 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 990 struct regmap *regmap = nau8825->regmap; 991 992 if (SND_SOC_DAPM_EVENT_OFF(event)) { 993 dev_dbg(nau8825->dev, "system clock control : POWER OFF\n"); 994 /* Set clock source to disable or internal clock before the 995 * playback or capture end. Codec needs clock for Jack 996 * detection and button press if jack inserted; otherwise, 997 * the clock should be closed. 998 */ 999 if (nau8825_is_jack_inserted(regmap)) { 1000 nau8825_configure_sysclk(nau8825, 1001 NAU8825_CLK_INTERNAL, 0); 1002 } else { 1003 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 1004 } 1005 } 1006 1007 return 0; 1008 } 1009 1010 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol, 1011 struct snd_ctl_elem_value *ucontrol) 1012 { 1013 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1014 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 1015 1016 if (!component->regmap) 1017 return -EINVAL; 1018 1019 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1, 1020 ucontrol->value.bytes.data, params->max); 1021 return 0; 1022 } 1023 1024 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol, 1025 struct snd_ctl_elem_value *ucontrol) 1026 { 1027 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1028 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 1029 void *data; 1030 1031 if (!component->regmap) 1032 return -EINVAL; 1033 1034 data = kmemdup(ucontrol->value.bytes.data, 1035 params->max, GFP_KERNEL | GFP_DMA); 1036 if (!data) 1037 return -ENOMEM; 1038 1039 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1040 NAU8825_BIQ_WRT_EN, 0); 1041 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1, 1042 data, params->max); 1043 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1044 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN); 1045 1046 kfree(data); 1047 return 0; 1048 } 1049 1050 static const char * const nau8825_biq_path[] = { 1051 "ADC", "DAC" 1052 }; 1053 1054 static const struct soc_enum nau8825_biq_path_enum = 1055 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT, 1056 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path); 1057 1058 static const char * const nau8825_adc_decimation[] = { 1059 "32", "64", "128", "256" 1060 }; 1061 1062 static const struct soc_enum nau8825_adc_decimation_enum = 1063 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT, 1064 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation); 1065 1066 static const char * const nau8825_dac_oversampl[] = { 1067 "64", "256", "128", "", "32" 1068 }; 1069 1070 static const struct soc_enum nau8825_dac_oversampl_enum = 1071 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT, 1072 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl); 1073 1074 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400); 1075 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 1076 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0); 1077 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 1078 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400); 1079 1080 static const struct snd_kcontrol_new nau8825_controls[] = { 1081 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1082 0, 0xff, 0, adc_vol_tlv), 1083 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1084 12, 8, 0x0f, 0, sidetone_vol_tlv), 1085 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL, 1086 6, 0, 0x3f, 1, dac_vol_tlv), 1087 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL, 1088 8, 37, 0, fepga_gain_tlv), 1089 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL, 1090 0, 8, 0xff, 0, crosstalk_vol_tlv), 1091 1092 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum), 1093 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum), 1094 /* programmable biquad filter */ 1095 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum), 1096 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 1097 nau8825_biq_coeff_get, nau8825_biq_coeff_put), 1098 }; 1099 1100 /* DAC Mux 0x33[9] and 0x34[9] */ 1101 static const char * const nau8825_dac_src[] = { 1102 "DACL", "DACR", 1103 }; 1104 1105 static SOC_ENUM_SINGLE_DECL( 1106 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL, 1107 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src); 1108 1109 static SOC_ENUM_SINGLE_DECL( 1110 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL, 1111 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src); 1112 1113 static const struct snd_kcontrol_new nau8825_dacl_mux = 1114 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum); 1115 1116 static const struct snd_kcontrol_new nau8825_dacr_mux = 1117 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum); 1118 1119 1120 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = { 1121 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2, 1122 15, 1), 1123 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 1124 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 1125 system_clock_control, SND_SOC_DAPM_POST_PMD), 1126 1127 SND_SOC_DAPM_INPUT("MIC"), 1128 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0), 1129 1130 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0, 1131 NULL, 0), 1132 1133 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0, 1134 nau8825_adc_event, SND_SOC_DAPM_POST_PMU | 1135 SND_SOC_DAPM_POST_PMD), 1136 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0), 1137 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL, 1138 0), 1139 1140 /* ADC for button press detection. A dapm supply widget is used to 1141 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON 1142 * during suspend. 1143 */ 1144 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL, 1145 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0), 1146 1147 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0), 1148 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0), 1149 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0), 1150 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0), 1151 1152 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL, 1153 NAU8825_ENABLE_DACR_SFT, 0), 1154 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL, 1155 NAU8825_ENABLE_DACL_SFT, 0), 1156 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0), 1157 1158 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux), 1159 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux), 1160 1161 SND_SOC_DAPM_PGA_S("HP amp L", 0, 1162 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0), 1163 SND_SOC_DAPM_PGA_S("HP amp R", 0, 1164 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0), 1165 1166 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0, 1167 nau8825_pump_event, SND_SOC_DAPM_POST_PMU | 1168 SND_SOC_DAPM_PRE_PMD), 1169 1170 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 1171 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0), 1172 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 1173 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0), 1174 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 1175 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 1176 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 1177 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 1178 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 1179 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 1180 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 1181 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 1182 1183 SND_SOC_DAPM_PGA_S("Output DACL", 7, 1184 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event, 1185 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1186 SND_SOC_DAPM_PGA_S("Output DACR", 7, 1187 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event, 1188 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1189 1190 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 1191 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 1192 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0), 1193 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 1194 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0), 1195 1196 /* High current HPOL/R boost driver */ 1197 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 1198 NAU8825_REG_BOOST, 9, 1, NULL, 0), 1199 1200 /* Class G operation control*/ 1201 SND_SOC_DAPM_PGA_S("Class G", 10, 1202 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0), 1203 1204 SND_SOC_DAPM_OUTPUT("HPOL"), 1205 SND_SOC_DAPM_OUTPUT("HPOR"), 1206 }; 1207 1208 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { 1209 {"Frontend PGA", NULL, "MIC"}, 1210 {"ADC", NULL, "Frontend PGA"}, 1211 {"ADC", NULL, "ADC Clock"}, 1212 {"ADC", NULL, "ADC Power"}, 1213 {"AIFTX", NULL, "ADC"}, 1214 {"AIFTX", NULL, "System Clock"}, 1215 1216 {"AIFRX", NULL, "System Clock"}, 1217 {"DDACL", NULL, "AIFRX"}, 1218 {"DDACR", NULL, "AIFRX"}, 1219 {"DDACL", NULL, "DDAC Clock"}, 1220 {"DDACR", NULL, "DDAC Clock"}, 1221 {"DACL Mux", "DACL", "DDACL"}, 1222 {"DACL Mux", "DACR", "DDACR"}, 1223 {"DACR Mux", "DACL", "DDACL"}, 1224 {"DACR Mux", "DACR", "DDACR"}, 1225 {"HP amp L", NULL, "DACL Mux"}, 1226 {"HP amp R", NULL, "DACR Mux"}, 1227 {"Charge Pump", NULL, "HP amp L"}, 1228 {"Charge Pump", NULL, "HP amp R"}, 1229 {"ADACL", NULL, "Charge Pump"}, 1230 {"ADACR", NULL, "Charge Pump"}, 1231 {"ADACL Clock", NULL, "ADACL"}, 1232 {"ADACR Clock", NULL, "ADACR"}, 1233 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 1234 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 1235 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 1236 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 1237 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 1238 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 1239 {"Output DACL", NULL, "Output Driver L Stage 3"}, 1240 {"Output DACR", NULL, "Output Driver R Stage 3"}, 1241 {"HPOL Pulldown", NULL, "Output DACL"}, 1242 {"HPOR Pulldown", NULL, "Output DACR"}, 1243 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 1244 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 1245 {"Class G", NULL, "HP Boost Driver"}, 1246 {"HPOL", NULL, "Class G"}, 1247 {"HPOR", NULL, "Class G"}, 1248 }; 1249 1250 static const struct nau8825_osr_attr * 1251 nau8825_get_osr(struct nau8825 *nau8825, int stream) 1252 { 1253 unsigned int osr; 1254 1255 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1256 regmap_read(nau8825->regmap, 1257 NAU8825_REG_DAC_CTRL1, &osr); 1258 osr &= NAU8825_DAC_OVERSAMPLE_MASK; 1259 if (osr >= ARRAY_SIZE(osr_dac_sel)) 1260 return NULL; 1261 return &osr_dac_sel[osr]; 1262 } else { 1263 regmap_read(nau8825->regmap, 1264 NAU8825_REG_ADC_RATE, &osr); 1265 osr &= NAU8825_ADC_SYNC_DOWN_MASK; 1266 if (osr >= ARRAY_SIZE(osr_adc_sel)) 1267 return NULL; 1268 return &osr_adc_sel[osr]; 1269 } 1270 } 1271 1272 static int nau8825_dai_startup(struct snd_pcm_substream *substream, 1273 struct snd_soc_dai *dai) 1274 { 1275 struct snd_soc_component *component = dai->component; 1276 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1277 const struct nau8825_osr_attr *osr; 1278 1279 osr = nau8825_get_osr(nau8825, substream->stream); 1280 if (!osr || !osr->osr) 1281 return -EINVAL; 1282 1283 return snd_pcm_hw_constraint_minmax(substream->runtime, 1284 SNDRV_PCM_HW_PARAM_RATE, 1285 0, CLK_DA_AD_MAX / osr->osr); 1286 } 1287 1288 static int nau8825_hw_params(struct snd_pcm_substream *substream, 1289 struct snd_pcm_hw_params *params, 1290 struct snd_soc_dai *dai) 1291 { 1292 struct snd_soc_component *component = dai->component; 1293 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1294 unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div; 1295 const struct nau8825_osr_attr *osr; 1296 int err = -EINVAL; 1297 1298 nau8825_sema_acquire(nau8825, 3 * HZ); 1299 1300 /* CLK_DAC or CLK_ADC = OSR * FS 1301 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1302 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1303 * values must be selected such that the maximum frequency is less 1304 * than 6.144 MHz. 1305 */ 1306 osr = nau8825_get_osr(nau8825, substream->stream); 1307 if (!osr || !osr->osr) 1308 goto error; 1309 if (params_rate(params) * osr->osr > CLK_DA_AD_MAX) 1310 goto error; 1311 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1312 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1313 NAU8825_CLK_DAC_SRC_MASK, 1314 osr->clk_src << NAU8825_CLK_DAC_SRC_SFT); 1315 else 1316 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1317 NAU8825_CLK_ADC_SRC_MASK, 1318 osr->clk_src << NAU8825_CLK_ADC_SRC_SFT); 1319 1320 /* make BCLK and LRC divde configuration if the codec as master. */ 1321 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val); 1322 if (ctrl_val & NAU8825_I2S_MS_MASTER) { 1323 /* get the bclk and fs ratio */ 1324 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params); 1325 if (bclk_fs <= 32) 1326 bclk_div = 2; 1327 else if (bclk_fs <= 64) 1328 bclk_div = 1; 1329 else if (bclk_fs <= 128) 1330 bclk_div = 0; 1331 else 1332 goto error; 1333 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1334 NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK, 1335 ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div); 1336 } 1337 1338 switch (params_width(params)) { 1339 case 16: 1340 val_len |= NAU8825_I2S_DL_16; 1341 break; 1342 case 20: 1343 val_len |= NAU8825_I2S_DL_20; 1344 break; 1345 case 24: 1346 val_len |= NAU8825_I2S_DL_24; 1347 break; 1348 case 32: 1349 val_len |= NAU8825_I2S_DL_32; 1350 break; 1351 default: 1352 goto error; 1353 } 1354 1355 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1356 NAU8825_I2S_DL_MASK, val_len); 1357 err = 0; 1358 1359 error: 1360 /* Release the semaphore. */ 1361 nau8825_sema_release(nau8825); 1362 1363 return err; 1364 } 1365 1366 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1367 { 1368 struct snd_soc_component *component = codec_dai->component; 1369 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1370 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1371 1372 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1373 case SND_SOC_DAIFMT_CBM_CFM: 1374 ctrl2_val |= NAU8825_I2S_MS_MASTER; 1375 break; 1376 case SND_SOC_DAIFMT_CBS_CFS: 1377 break; 1378 default: 1379 return -EINVAL; 1380 } 1381 1382 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1383 case SND_SOC_DAIFMT_NB_NF: 1384 break; 1385 case SND_SOC_DAIFMT_IB_NF: 1386 ctrl1_val |= NAU8825_I2S_BP_INV; 1387 break; 1388 default: 1389 return -EINVAL; 1390 } 1391 1392 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1393 case SND_SOC_DAIFMT_I2S: 1394 ctrl1_val |= NAU8825_I2S_DF_I2S; 1395 break; 1396 case SND_SOC_DAIFMT_LEFT_J: 1397 ctrl1_val |= NAU8825_I2S_DF_LEFT; 1398 break; 1399 case SND_SOC_DAIFMT_RIGHT_J: 1400 ctrl1_val |= NAU8825_I2S_DF_RIGTH; 1401 break; 1402 case SND_SOC_DAIFMT_DSP_A: 1403 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1404 break; 1405 case SND_SOC_DAIFMT_DSP_B: 1406 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1407 ctrl1_val |= NAU8825_I2S_PCMB_EN; 1408 break; 1409 default: 1410 return -EINVAL; 1411 } 1412 1413 nau8825_sema_acquire(nau8825, 3 * HZ); 1414 1415 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1416 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK | 1417 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK, 1418 ctrl1_val); 1419 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1420 NAU8825_I2S_MS_MASK, ctrl2_val); 1421 1422 /* Release the semaphore. */ 1423 nau8825_sema_release(nau8825); 1424 1425 return 0; 1426 } 1427 1428 /** 1429 * nau8825_set_tdm_slot - configure DAI TDM. 1430 * @dai: DAI 1431 * @tx_mask: bitmask representing active TX slots. 1432 * @rx_mask: bitmask representing active RX slots. 1433 * @slots: Number of slots in use. 1434 * @slot_width: Width in bits for each slot. 1435 * 1436 * Configures a DAI for TDM operation. Support TDM 4/8 slots. 1437 * The limitation is DAC and ADC need shift 4 slots at 8 slots mode. 1438 */ 1439 static int nau8825_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1440 unsigned int rx_mask, int slots, int slot_width) 1441 { 1442 struct snd_soc_component *component = dai->component; 1443 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1444 unsigned int ctrl_val = 0, ctrl_offset = 0, value = 0, dac_s, adc_s; 1445 1446 if (slots != 4 && slots != 8) { 1447 dev_err(nau8825->dev, "Only support 4 or 8 slots!\n"); 1448 return -EINVAL; 1449 } 1450 1451 /* The driver is limited to 1-channel for ADC, and 2-channel for DAC on TDM mode */ 1452 if (hweight_long((unsigned long) tx_mask) != 1 || 1453 hweight_long((unsigned long) rx_mask) != 2) { 1454 dev_err(nau8825->dev, 1455 "The limitation is 1-channel for ADC, and 2-channel for DAC on TDM mode.\n"); 1456 return -EINVAL; 1457 } 1458 1459 if (((tx_mask & 0xf) && (tx_mask & 0xf0)) || 1460 ((rx_mask & 0xf) && (rx_mask & 0xf0)) || 1461 ((tx_mask & 0xf) && (rx_mask & 0xf0)) || 1462 ((rx_mask & 0xf) && (tx_mask & 0xf0))) { 1463 dev_err(nau8825->dev, 1464 "Slot assignment of DAC and ADC need to set same interval.\n"); 1465 return -EINVAL; 1466 } 1467 1468 /* The offset of fixed 4 slots for 8 slots support */ 1469 if (rx_mask & 0xf0) { 1470 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1471 NAU8825_I2S_PCM_TS_EN_MASK, NAU8825_I2S_PCM_TS_EN); 1472 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, &value); 1473 ctrl_val |= NAU8825_TDM_OFFSET_EN; 1474 ctrl_offset = 4 * slot_width; 1475 if (!(value & NAU8825_I2S_PCMB_MASK)) 1476 ctrl_offset += 1; 1477 dac_s = (rx_mask & 0xf0) >> 4; 1478 adc_s = fls((tx_mask & 0xf0) >> 4); 1479 } else { 1480 dac_s = rx_mask & 0xf; 1481 adc_s = fls(tx_mask & 0xf); 1482 } 1483 1484 ctrl_val |= NAU8825_TDM_MODE; 1485 1486 switch (dac_s) { 1487 case 0x3: 1488 ctrl_val |= 1 << NAU8825_TDM_DACR_RX_SFT; 1489 break; 1490 case 0x5: 1491 ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT; 1492 break; 1493 case 0x6: 1494 ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT; 1495 ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT; 1496 break; 1497 case 0x9: 1498 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; 1499 break; 1500 case 0xa: 1501 ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT; 1502 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; 1503 break; 1504 case 0xc: 1505 ctrl_val |= 2 << NAU8825_TDM_DACL_RX_SFT; 1506 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; 1507 break; 1508 default: 1509 return -EINVAL; 1510 } 1511 1512 ctrl_val |= adc_s - 1; 1513 1514 regmap_update_bits(nau8825->regmap, NAU8825_REG_TDM_CTRL, 1515 NAU8825_TDM_MODE | NAU8825_TDM_OFFSET_EN | 1516 NAU8825_TDM_DACL_RX_MASK | NAU8825_TDM_DACR_RX_MASK | 1517 NAU8825_TDM_TX_MASK, ctrl_val); 1518 regmap_update_bits(nau8825->regmap, NAU8825_REG_LEFT_TIME_SLOT, 1519 NAU8825_TSLOT_L0_MASK, ctrl_offset); 1520 1521 return 0; 1522 } 1523 1524 static const struct snd_soc_dai_ops nau8825_dai_ops = { 1525 .startup = nau8825_dai_startup, 1526 .hw_params = nau8825_hw_params, 1527 .set_fmt = nau8825_set_dai_fmt, 1528 .set_tdm_slot = nau8825_set_tdm_slot, 1529 }; 1530 1531 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000 1532 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1533 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1534 1535 static struct snd_soc_dai_driver nau8825_dai = { 1536 .name = "nau8825-hifi", 1537 .playback = { 1538 .stream_name = "Playback", 1539 .channels_min = 1, 1540 .channels_max = 2, 1541 .rates = NAU8825_RATES, 1542 .formats = NAU8825_FORMATS, 1543 }, 1544 .capture = { 1545 .stream_name = "Capture", 1546 .channels_min = 1, 1547 .channels_max = 2, /* Only 1 channel of data */ 1548 .rates = NAU8825_RATES, 1549 .formats = NAU8825_FORMATS, 1550 }, 1551 .ops = &nau8825_dai_ops, 1552 }; 1553 1554 /** 1555 * nau8825_enable_jack_detect - Specify a jack for event reporting 1556 * 1557 * @component: component to register the jack with 1558 * @jack: jack to use to report headset and button events on 1559 * 1560 * After this function has been called the headset insert/remove and button 1561 * events will be routed to the given jack. Jack can be null to stop 1562 * reporting. 1563 */ 1564 int nau8825_enable_jack_detect(struct snd_soc_component *component, 1565 struct snd_soc_jack *jack) 1566 { 1567 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1568 struct regmap *regmap = nau8825->regmap; 1569 1570 nau8825->jack = jack; 1571 1572 if (!nau8825->jack) { 1573 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1574 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | 1575 NAU8825_SPKR_DWN1L, 0); 1576 return 0; 1577 } 1578 /* Ground HP Outputs[1:0], needed for headset auto detection 1579 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6] 1580 */ 1581 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1582 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 1583 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1584 1585 return 0; 1586 } 1587 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect); 1588 1589 1590 static bool nau8825_is_jack_inserted(struct regmap *regmap) 1591 { 1592 bool active_high, is_high; 1593 int status, jkdet; 1594 1595 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet); 1596 active_high = jkdet & NAU8825_JACK_POLARITY; 1597 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status); 1598 is_high = status & NAU8825_GPIO2JD1; 1599 /* return jack connection status according to jack insertion logic 1600 * active high or active low. 1601 */ 1602 return active_high == is_high; 1603 } 1604 1605 static void nau8825_restart_jack_detection(struct regmap *regmap) 1606 { 1607 /* this will restart the entire jack detection process including MIC/GND 1608 * switching and create interrupts. We have to go from 0 to 1 and back 1609 * to 0 to restart. 1610 */ 1611 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1612 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART); 1613 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1614 NAU8825_JACK_DET_RESTART, 0); 1615 } 1616 1617 static void nau8825_int_status_clear_all(struct regmap *regmap) 1618 { 1619 int active_irq, clear_irq, i; 1620 1621 /* Reset the intrruption status from rightmost bit if the corres- 1622 * ponding irq event occurs. 1623 */ 1624 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq); 1625 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) { 1626 clear_irq = (0x1 << i); 1627 if (active_irq & clear_irq) 1628 regmap_write(regmap, 1629 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 1630 } 1631 } 1632 1633 static void nau8825_eject_jack(struct nau8825 *nau8825) 1634 { 1635 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1636 struct regmap *regmap = nau8825->regmap; 1637 1638 /* Force to cancel the cross talk detection process */ 1639 nau8825_xtalk_cancel(nau8825); 1640 1641 snd_soc_dapm_disable_pin(dapm, "SAR"); 1642 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1643 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 1644 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1645 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 1646 /* ground HPL/HPR, MICGRND1/2 */ 1647 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf); 1648 1649 snd_soc_dapm_sync(dapm); 1650 1651 /* Clear all interruption status */ 1652 nau8825_int_status_clear_all(regmap); 1653 1654 /* Enable the insertion interruption, disable the ejection inter- 1655 * ruption, and then bypass de-bounce circuit. 1656 */ 1657 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 1658 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS, 1659 NAU8825_IRQ_EJECT_DIS); 1660 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1661 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1662 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN, 1663 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1664 NAU8825_IRQ_HEADSET_COMPLETE_EN); 1665 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1666 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 1667 1668 /* Disable ADC needed for interruptions at audo mode */ 1669 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1670 NAU8825_ENABLE_ADC, 0); 1671 1672 /* Close clock for jack type detection at manual mode */ 1673 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 1674 } 1675 1676 /* Enable audo mode interruptions with internal clock. */ 1677 static void nau8825_setup_auto_irq(struct nau8825 *nau8825) 1678 { 1679 struct regmap *regmap = nau8825->regmap; 1680 1681 /* Enable headset jack type detection complete interruption and 1682 * jack ejection interruption. 1683 */ 1684 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1685 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0); 1686 1687 /* Enable internal VCO needed for interruptions */ 1688 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 1689 /* Raise up the internal clock for jack detection */ 1690 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 1691 NAU8825_CLK_MCLK_SRC_MASK, 0); 1692 1693 /* Enable ADC needed for interruptions */ 1694 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1695 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 1696 1697 /* Chip needs one FSCLK cycle in order to generate interruptions, 1698 * as we cannot guarantee one will be provided by the system. Turning 1699 * master mode on then off enables us to generate that FSCLK cycle 1700 * with a minimum of contention on the clock bus. 1701 */ 1702 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1703 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER); 1704 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1705 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE); 1706 1707 /* Not bypass de-bounce circuit */ 1708 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1709 NAU8825_JACK_DET_DB_BYPASS, 0); 1710 1711 /* Unmask all interruptions */ 1712 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0); 1713 1714 /* Restart the jack detection process at auto mode */ 1715 nau8825_restart_jack_detection(regmap); 1716 } 1717 1718 static int nau8825_button_decode(int value) 1719 { 1720 int buttons = 0; 1721 1722 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */ 1723 if (value & BIT(0)) 1724 buttons |= SND_JACK_BTN_0; 1725 if (value & BIT(1)) 1726 buttons |= SND_JACK_BTN_1; 1727 if (value & BIT(2)) 1728 buttons |= SND_JACK_BTN_2; 1729 if (value & BIT(3)) 1730 buttons |= SND_JACK_BTN_3; 1731 if (value & BIT(4)) 1732 buttons |= SND_JACK_BTN_4; 1733 if (value & BIT(5)) 1734 buttons |= SND_JACK_BTN_5; 1735 1736 return buttons; 1737 } 1738 1739 static int nau8825_high_imped_detection(struct nau8825 *nau8825) 1740 { 1741 struct regmap *regmap = nau8825->regmap; 1742 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1743 unsigned int adc_mg1, adc_mg2; 1744 1745 /* Initial phase */ 1746 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1747 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1748 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2); 1749 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1, 1750 NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND); 1751 regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0x6); 1752 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1753 NAU8825_MICBIAS_LOWNOISE_MASK | NAU8825_MICBIAS_VOLTAGE_MASK, 1754 NAU8825_MICBIAS_LOWNOISE_EN); 1755 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1756 NAU8825_SAR_INPUT_MASK | NAU8825_SAR_TRACKING_GAIN_MASK | 1757 NAU8825_SAR_HV_SEL_MASK | NAU8825_SAR_RES_SEL_MASK | 1758 NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK, 1759 NAU8825_SAR_HV_SEL_VDDMIC | NAU8825_SAR_RES_SEL_70K); 1760 1761 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1762 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1763 snd_soc_dapm_sync(dapm); 1764 1765 /* Configure settings for first reading of SARADC */ 1766 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1767 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1768 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND2); 1769 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1770 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1771 NAU8825_MICBIAS_JKR2); 1772 regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg1); 1773 1774 /* Configure settings for second reading of SARADC */ 1775 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1776 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 1777 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1778 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1779 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | 1780 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1781 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1782 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1783 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1); 1784 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1785 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1786 NAU8825_MICBIAS_JKSLV); 1787 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1788 NAU8825_SAR_INPUT_MASK, NAU8825_SAR_INPUT_JKSLV); 1789 regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg2); 1790 1791 /* Disable phase */ 1792 snd_soc_dapm_disable_pin(dapm, "SAR"); 1793 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1794 snd_soc_dapm_sync(dapm); 1795 1796 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1797 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_LOWNOISE_MASK | 1798 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); 1799 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1800 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1801 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | 1802 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1803 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1, 1804 NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND); 1805 regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0); 1806 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1807 NAU8825_SAR_TRACKING_GAIN_MASK | NAU8825_SAR_HV_SEL_MASK, 1808 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); 1809 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1810 NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK, 1811 (nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT) | 1812 (nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT)); 1813 dev_dbg(nau8825->dev, "adc_mg1:%x, adc_mg2:%x\n", adc_mg1, adc_mg2); 1814 1815 /* Confirmation phase */ 1816 if (adc_mg1 > adc_mg2) { 1817 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); 1818 1819 /* Unground MICGND1 */ 1820 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1821 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2, 1822 NAU8825_SPKR_ENGND2); 1823 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ 1824 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1825 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1826 NAU8825_MICBIAS_JKR2); 1827 /* Attach SARADC to MICGND1 */ 1828 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1829 NAU8825_SAR_INPUT_MASK, 1830 NAU8825_SAR_INPUT_JKR2); 1831 } else if (adc_mg1 < adc_mg2) { 1832 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); 1833 1834 /* Unground MICGND2 */ 1835 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1836 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2, 1837 NAU8825_SPKR_ENGND1); 1838 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ 1839 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1840 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1841 NAU8825_MICBIAS_JKSLV); 1842 /* Attach SARADC to MICGND2 */ 1843 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1844 NAU8825_SAR_INPUT_MASK, 1845 NAU8825_SAR_INPUT_JKSLV); 1846 } else { 1847 dev_err(nau8825->dev, "Jack broken.\n"); 1848 return -EINVAL; 1849 } 1850 1851 return 0; 1852 } 1853 1854 static int nau8825_jack_insert(struct nau8825 *nau8825) 1855 { 1856 struct regmap *regmap = nau8825->regmap; 1857 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1858 int jack_status_reg, mic_detected; 1859 int type = 0; 1860 1861 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg); 1862 mic_detected = (jack_status_reg >> 10) & 3; 1863 /* The JKSLV and JKR2 all detected in high impedance headset */ 1864 if (mic_detected == 0x3) 1865 nau8825->high_imped = true; 1866 else 1867 nau8825->high_imped = false; 1868 1869 switch (mic_detected) { 1870 case 0: 1871 /* no mic */ 1872 type = SND_JACK_HEADPHONE; 1873 break; 1874 case 1: 1875 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); 1876 type = SND_JACK_HEADSET; 1877 1878 /* Unground MICGND1 */ 1879 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1880 1 << 2); 1881 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ 1882 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1883 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1884 NAU8825_MICBIAS_JKR2); 1885 /* Attach SARADC to MICGND1 */ 1886 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1887 NAU8825_SAR_INPUT_MASK, 1888 NAU8825_SAR_INPUT_JKR2); 1889 1890 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1891 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1892 snd_soc_dapm_sync(dapm); 1893 break; 1894 case 2: 1895 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); 1896 type = SND_JACK_HEADSET; 1897 1898 /* Unground MICGND2 */ 1899 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1900 2 << 2); 1901 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ 1902 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1903 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1904 NAU8825_MICBIAS_JKSLV); 1905 /* Attach SARADC to MICGND2 */ 1906 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1907 NAU8825_SAR_INPUT_MASK, 1908 NAU8825_SAR_INPUT_JKSLV); 1909 1910 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1911 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1912 snd_soc_dapm_sync(dapm); 1913 break; 1914 case 3: 1915 /* Detection failure case */ 1916 dev_warn(nau8825->dev, 1917 "Detection failure. Try the manually mechanism for jack type checking.\n"); 1918 if (!nau8825_high_imped_detection(nau8825)) { 1919 type = SND_JACK_HEADSET; 1920 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1921 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1922 snd_soc_dapm_sync(dapm); 1923 } else 1924 type = SND_JACK_HEADPHONE; 1925 break; 1926 } 1927 1928 /* Update to the default divider of internal clock for power saving */ 1929 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 1930 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 1931 1932 /* Leaving HPOL/R grounded after jack insert by default. They will be 1933 * ungrounded as part of the widget power up sequence at the beginning 1934 * of playback to reduce pop. 1935 */ 1936 return type; 1937 } 1938 1939 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 1940 SND_JACK_BTN_2 | SND_JACK_BTN_3) 1941 1942 static irqreturn_t nau8825_interrupt(int irq, void *data) 1943 { 1944 struct nau8825 *nau8825 = (struct nau8825 *)data; 1945 struct regmap *regmap = nau8825->regmap; 1946 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 1947 1948 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) { 1949 dev_err(nau8825->dev, "failed to read irq status\n"); 1950 return IRQ_NONE; 1951 } 1952 1953 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) == 1954 NAU8825_JACK_EJECTION_DETECTED) { 1955 1956 nau8825_eject_jack(nau8825); 1957 event_mask |= SND_JACK_HEADSET; 1958 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK; 1959 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) { 1960 int key_status; 1961 1962 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, 1963 &key_status); 1964 1965 /* upper 8 bits of the register are for short pressed keys, 1966 * lower 8 bits - for long pressed buttons 1967 */ 1968 nau8825->button_pressed = nau8825_button_decode( 1969 key_status >> 8); 1970 1971 event |= nau8825->button_pressed; 1972 event_mask |= NAU8825_BUTTONS; 1973 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ; 1974 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) { 1975 event_mask = NAU8825_BUTTONS; 1976 clear_irq = NAU8825_KEY_RELEASE_IRQ; 1977 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) { 1978 if (nau8825_is_jack_inserted(regmap)) { 1979 event |= nau8825_jack_insert(nau8825); 1980 if (nau8825->xtalk_enable && !nau8825->high_imped) { 1981 /* Apply the cross talk suppression in the 1982 * headset without high impedance. 1983 */ 1984 if (!nau8825->xtalk_protect) { 1985 /* Raise protection for cross talk de- 1986 * tection if no protection before. 1987 * The driver has to cancel the pro- 1988 * cess and restore changes if process 1989 * is ongoing when ejection. 1990 */ 1991 int ret; 1992 nau8825->xtalk_protect = true; 1993 ret = nau8825_sema_acquire(nau8825, 0); 1994 if (ret) 1995 nau8825->xtalk_protect = false; 1996 } 1997 /* Startup cross talk detection process */ 1998 if (nau8825->xtalk_protect) { 1999 nau8825->xtalk_state = 2000 NAU8825_XTALK_PREPARE; 2001 schedule_work(&nau8825->xtalk_work); 2002 } 2003 } else { 2004 /* The cross talk suppression shouldn't apply 2005 * in the headset with high impedance. Thus, 2006 * relieve the protection raised before. 2007 */ 2008 if (nau8825->xtalk_protect) { 2009 nau8825_sema_release(nau8825); 2010 nau8825->xtalk_protect = false; 2011 } 2012 } 2013 } else { 2014 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n"); 2015 nau8825_eject_jack(nau8825); 2016 } 2017 2018 event_mask |= SND_JACK_HEADSET; 2019 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ; 2020 /* Record the interruption report event for driver to report 2021 * the event later. The jack report will delay until cross 2022 * talk detection process is done. 2023 */ 2024 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) { 2025 nau8825->xtalk_event = event; 2026 nau8825->xtalk_event_mask = event_mask; 2027 } 2028 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) { 2029 /* crosstalk detection enable and process on going */ 2030 if (nau8825->xtalk_enable && nau8825->xtalk_protect) 2031 schedule_work(&nau8825->xtalk_work); 2032 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ; 2033 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) == 2034 NAU8825_JACK_INSERTION_DETECTED) { 2035 /* One more step to check GPIO status directly. Thus, the 2036 * driver can confirm the real insertion interruption because 2037 * the intrruption at manual mode has bypassed debounce 2038 * circuit which can get rid of unstable status. 2039 */ 2040 if (nau8825_is_jack_inserted(regmap)) { 2041 /* Turn off insertion interruption at manual mode */ 2042 regmap_update_bits(regmap, 2043 NAU8825_REG_INTERRUPT_DIS_CTRL, 2044 NAU8825_IRQ_INSERT_DIS, 2045 NAU8825_IRQ_INSERT_DIS); 2046 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2047 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN); 2048 /* Enable interruption for jack type detection at audo 2049 * mode which can detect microphone and jack type. 2050 */ 2051 nau8825_setup_auto_irq(nau8825); 2052 } 2053 } 2054 2055 if (!clear_irq) 2056 clear_irq = active_irq; 2057 /* clears the rightmost interruption */ 2058 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 2059 2060 /* Delay jack report until cross talk detection is done. It can avoid 2061 * application to do playback preparation when cross talk detection 2062 * process is still working. Otherwise, the resource like clock and 2063 * power will be issued by them at the same time and conflict happens. 2064 */ 2065 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE) 2066 snd_soc_jack_report(nau8825->jack, event, event_mask); 2067 2068 return IRQ_HANDLED; 2069 } 2070 2071 static void nau8825_setup_buttons(struct nau8825 *nau8825) 2072 { 2073 struct regmap *regmap = nau8825->regmap; 2074 2075 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 2076 NAU8825_SAR_TRACKING_GAIN_MASK, 2077 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); 2078 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 2079 NAU8825_SAR_COMPARE_TIME_MASK, 2080 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT); 2081 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 2082 NAU8825_SAR_SAMPLING_TIME_MASK, 2083 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT); 2084 2085 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 2086 NAU8825_KEYDET_LEVELS_NR_MASK, 2087 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT); 2088 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 2089 NAU8825_KEYDET_HYSTERESIS_MASK, 2090 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT); 2091 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 2092 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK, 2093 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT); 2094 2095 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1, 2096 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]); 2097 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2, 2098 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]); 2099 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3, 2100 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]); 2101 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4, 2102 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]); 2103 2104 /* Enable short press and release interruptions */ 2105 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2106 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN, 2107 0); 2108 } 2109 2110 static void nau8825_init_regs(struct nau8825 *nau8825) 2111 { 2112 struct regmap *regmap = nau8825->regmap; 2113 2114 /* Latch IIC LSB value */ 2115 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001); 2116 /* Enable Bias/Vmid */ 2117 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 2118 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID); 2119 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 2120 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN); 2121 2122 /* VMID Tieoff */ 2123 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ, 2124 NAU8825_BIAS_VMID_SEL_MASK, 2125 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT); 2126 /* Disable Boost Driver, Automatic Short circuit protection enable */ 2127 regmap_update_bits(regmap, NAU8825_REG_BOOST, 2128 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 2129 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN, 2130 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 2131 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN); 2132 2133 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 2134 NAU8825_JKDET_OUTPUT_EN, 2135 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN); 2136 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 2137 NAU8825_JKDET_PULL_EN, 2138 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN); 2139 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 2140 NAU8825_JKDET_PULL_UP, 2141 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0); 2142 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2143 NAU8825_JACK_POLARITY, 2144 /* jkdet_polarity - 1 is for active-low */ 2145 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY); 2146 2147 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2148 NAU8825_JACK_INSERT_DEBOUNCE_MASK, 2149 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT); 2150 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2151 NAU8825_JACK_EJECT_DEBOUNCE_MASK, 2152 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT); 2153 2154 /* Pull up IRQ pin */ 2155 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2156 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN, 2157 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN); 2158 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 2159 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff); 2160 2161 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 2162 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); 2163 2164 if (nau8825->sar_threshold_num) 2165 nau8825_setup_buttons(nau8825); 2166 2167 /* Default oversampling/decimations settings are unusable 2168 * (audible hiss). Set it to something better. 2169 */ 2170 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE, 2171 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN, 2172 NAU8825_ADC_SYNC_DOWN_64); 2173 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 2174 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64); 2175 /* Disable DACR/L power */ 2176 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 2177 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 2178 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 2179 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 2180 * signal to avoid any glitches due to power up transients in both 2181 * the analog and digital DAC circuit. 2182 */ 2183 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 2184 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 2185 /* CICCLP off */ 2186 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 2187 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF); 2188 2189 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 2190 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2, 2191 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 2192 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB, 2193 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 2194 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB); 2195 /* Class G timer 64ms */ 2196 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL, 2197 NAU8825_CLASSG_TIMER_MASK, 2198 0x20 << NAU8825_CLASSG_TIMER_SFT); 2199 /* DAC clock delay 2ns, VREF */ 2200 regmap_update_bits(regmap, NAU8825_REG_RDAC, 2201 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK, 2202 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) | 2203 (0x3 << NAU8825_RDAC_VREF_SFT)); 2204 /* Config L/R channel */ 2205 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 2206 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); 2207 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 2208 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); 2209 /* Disable short Frame Sync detection logic */ 2210 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT, 2211 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET); 2212 /* ADCDAT IO drive strength control */ 2213 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 2214 NAU8825_ADCOUT_DS_MASK, 2215 nau8825->adcout_ds << NAU8825_ADCOUT_DS_SFT); 2216 } 2217 2218 static const struct regmap_config nau8825_regmap_config = { 2219 .val_bits = NAU8825_REG_DATA_LEN, 2220 .reg_bits = NAU8825_REG_ADDR_LEN, 2221 2222 .max_register = NAU8825_REG_MAX, 2223 .readable_reg = nau8825_readable_reg, 2224 .writeable_reg = nau8825_writeable_reg, 2225 .volatile_reg = nau8825_volatile_reg, 2226 2227 .cache_type = REGCACHE_RBTREE, 2228 .reg_defaults = nau8825_reg_defaults, 2229 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults), 2230 }; 2231 2232 static int nau8825_component_probe(struct snd_soc_component *component) 2233 { 2234 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2235 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2236 2237 nau8825->dapm = dapm; 2238 2239 return 0; 2240 } 2241 2242 static void nau8825_component_remove(struct snd_soc_component *component) 2243 { 2244 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2245 2246 /* Cancel and reset cross tak suppresstion detection funciton */ 2247 nau8825_xtalk_cancel(nau8825); 2248 } 2249 2250 /** 2251 * nau8825_calc_fll_param - Calculate FLL parameters. 2252 * @fll_in: external clock provided to codec. 2253 * @fs: sampling rate. 2254 * @fll_param: Pointer to structure of FLL parameters. 2255 * 2256 * Calculate FLL parameters to configure codec. 2257 * 2258 * Returns 0 for success or negative error code. 2259 */ 2260 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs, 2261 struct nau8825_fll *fll_param) 2262 { 2263 u64 fvco, fvco_max; 2264 unsigned int fref, i, fvco_sel; 2265 2266 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 2267 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 2268 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK 2269 */ 2270 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 2271 fref = fll_in / fll_pre_scalar[i].param; 2272 if (fref <= NAU_FREF_MAX) 2273 break; 2274 } 2275 if (i == ARRAY_SIZE(fll_pre_scalar)) 2276 return -EINVAL; 2277 fll_param->clk_ref_div = fll_pre_scalar[i].val; 2278 2279 /* Choose the FLL ratio based on FREF */ 2280 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 2281 if (fref >= fll_ratio[i].param) 2282 break; 2283 } 2284 if (i == ARRAY_SIZE(fll_ratio)) 2285 return -EINVAL; 2286 fll_param->ratio = fll_ratio[i].val; 2287 2288 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 2289 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 2290 * guaranteed across the full range of operation. 2291 * FDCO = freq_out * 2 * mclk_src_scaling 2292 */ 2293 fvco_max = 0; 2294 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 2295 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 2296 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 2297 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 2298 fvco_max < fvco) { 2299 fvco_max = fvco; 2300 fvco_sel = i; 2301 } 2302 } 2303 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 2304 return -EINVAL; 2305 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 2306 2307 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 2308 * input based on FDCO, FREF and FLL ratio. 2309 */ 2310 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 2311 fll_param->fll_int = (fvco >> 16) & 0x3FF; 2312 fll_param->fll_frac = fvco & 0xFFFF; 2313 return 0; 2314 } 2315 2316 static void nau8825_fll_apply(struct nau8825 *nau8825, 2317 struct nau8825_fll *fll_param) 2318 { 2319 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2320 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK, 2321 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src); 2322 /* Make DSP operate at high speed for better performance. */ 2323 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 2324 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK, 2325 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT)); 2326 /* FLL 16-bit fractional input */ 2327 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac); 2328 /* FLL 10-bit integer input */ 2329 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3, 2330 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int); 2331 /* FLL pre-scaler */ 2332 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4, 2333 NAU8825_FLL_REF_DIV_MASK, 2334 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT); 2335 /* select divided VCO input */ 2336 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2337 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF); 2338 /* Disable free-running mode */ 2339 regmap_update_bits(nau8825->regmap, 2340 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); 2341 if (fll_param->fll_frac) { 2342 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 2343 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2344 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2345 NAU8825_FLL_FTR_SW_MASK, 2346 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2347 NAU8825_FLL_FTR_SW_FILTER); 2348 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2349 NAU8825_SDM_EN | NAU8825_CUTOFF500, 2350 NAU8825_SDM_EN | NAU8825_CUTOFF500); 2351 } else { 2352 /* disable FLL loop filter and cutoff frequency */ 2353 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2354 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2355 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU); 2356 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2357 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0); 2358 } 2359 } 2360 2361 /* freq_out must be 256*Fs in order to achieve the best performance */ 2362 static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source, 2363 unsigned int freq_in, unsigned int freq_out) 2364 { 2365 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2366 struct nau8825_fll fll_param; 2367 int ret, fs; 2368 2369 fs = freq_out / 256; 2370 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param); 2371 if (ret < 0) { 2372 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2373 return ret; 2374 } 2375 dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 2376 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 2377 fll_param.fll_int, fll_param.clk_ref_div); 2378 2379 nau8825_fll_apply(nau8825, &fll_param); 2380 mdelay(2); 2381 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2382 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2383 return 0; 2384 } 2385 2386 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq) 2387 { 2388 int ret; 2389 2390 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk"); 2391 if (IS_ERR(nau8825->mclk)) { 2392 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2393 return 0; 2394 } 2395 2396 if (!nau8825->mclk_freq) { 2397 ret = clk_prepare_enable(nau8825->mclk); 2398 if (ret) { 2399 dev_err(nau8825->dev, "Unable to prepare codec mclk\n"); 2400 return ret; 2401 } 2402 } 2403 2404 if (nau8825->mclk_freq != freq) { 2405 freq = clk_round_rate(nau8825->mclk, freq); 2406 ret = clk_set_rate(nau8825->mclk, freq); 2407 if (ret) { 2408 dev_err(nau8825->dev, "Unable to set mclk rate\n"); 2409 return ret; 2410 } 2411 nau8825->mclk_freq = freq; 2412 } 2413 2414 return 0; 2415 } 2416 2417 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap) 2418 { 2419 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2420 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); 2421 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2422 NAU8825_DCO_EN, 0); 2423 /* Make DSP operate as default setting for power saving. */ 2424 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2425 NAU8825_ICTRL_LATCH_MASK, 0); 2426 } 2427 2428 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, 2429 unsigned int freq) 2430 { 2431 struct regmap *regmap = nau8825->regmap; 2432 int ret; 2433 2434 switch (clk_id) { 2435 case NAU8825_CLK_DIS: 2436 /* Clock provided externally and disable internal VCO clock */ 2437 nau8825_configure_mclk_as_sysclk(regmap); 2438 if (nau8825->mclk_freq) { 2439 clk_disable_unprepare(nau8825->mclk); 2440 nau8825->mclk_freq = 0; 2441 } 2442 2443 break; 2444 case NAU8825_CLK_MCLK: 2445 /* Acquire the semaphore to synchronize the playback and 2446 * interrupt handler. In order to avoid the playback inter- 2447 * fered by cross talk process, the driver make the playback 2448 * preparation halted until cross talk process finish. 2449 */ 2450 nau8825_sema_acquire(nau8825, 3 * HZ); 2451 nau8825_configure_mclk_as_sysclk(regmap); 2452 /* MCLK not changed by clock tree */ 2453 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2454 NAU8825_CLK_MCLK_SRC_MASK, 0); 2455 /* Release the semaphore. */ 2456 nau8825_sema_release(nau8825); 2457 2458 ret = nau8825_mclk_prepare(nau8825, freq); 2459 if (ret) 2460 return ret; 2461 2462 break; 2463 case NAU8825_CLK_INTERNAL: 2464 if (nau8825_is_jack_inserted(nau8825->regmap)) { 2465 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2466 NAU8825_DCO_EN, NAU8825_DCO_EN); 2467 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2468 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2469 /* Decrease the VCO frequency and make DSP operate 2470 * as default setting for power saving. 2471 */ 2472 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2473 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 2474 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2475 NAU8825_ICTRL_LATCH_MASK | 2476 NAU8825_FLL_RATIO_MASK, 0x10); 2477 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2478 NAU8825_SDM_EN, NAU8825_SDM_EN); 2479 } else { 2480 /* The clock turns off intentionally for power saving 2481 * when no headset connected. 2482 */ 2483 nau8825_configure_mclk_as_sysclk(regmap); 2484 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n"); 2485 } 2486 if (nau8825->mclk_freq) { 2487 clk_disable_unprepare(nau8825->mclk); 2488 nau8825->mclk_freq = 0; 2489 } 2490 2491 break; 2492 case NAU8825_CLK_FLL_MCLK: 2493 /* Acquire the semaphore to synchronize the playback and 2494 * interrupt handler. In order to avoid the playback inter- 2495 * fered by cross talk process, the driver make the playback 2496 * preparation halted until cross talk process finish. 2497 */ 2498 nau8825_sema_acquire(nau8825, 3 * HZ); 2499 /* Higher FLL reference input frequency can only set lower 2500 * gain error, such as 0000 for input reference from MCLK 2501 * 12.288Mhz. 2502 */ 2503 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2504 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2505 NAU8825_FLL_CLK_SRC_MCLK | 0); 2506 /* Release the semaphore. */ 2507 nau8825_sema_release(nau8825); 2508 2509 ret = nau8825_mclk_prepare(nau8825, freq); 2510 if (ret) 2511 return ret; 2512 2513 break; 2514 case NAU8825_CLK_FLL_BLK: 2515 /* Acquire the semaphore to synchronize the playback and 2516 * interrupt handler. In order to avoid the playback inter- 2517 * fered by cross talk process, the driver make the playback 2518 * preparation halted until cross talk process finish. 2519 */ 2520 nau8825_sema_acquire(nau8825, 3 * HZ); 2521 /* If FLL reference input is from low frequency source, 2522 * higher error gain can apply such as 0xf which has 2523 * the most sensitive gain error correction threshold, 2524 * Therefore, FLL has the most accurate DCO to 2525 * target frequency. 2526 */ 2527 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2528 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2529 NAU8825_FLL_CLK_SRC_BLK | 2530 (0xf << NAU8825_GAIN_ERR_SFT)); 2531 /* Release the semaphore. */ 2532 nau8825_sema_release(nau8825); 2533 2534 if (nau8825->mclk_freq) { 2535 clk_disable_unprepare(nau8825->mclk); 2536 nau8825->mclk_freq = 0; 2537 } 2538 2539 break; 2540 case NAU8825_CLK_FLL_FS: 2541 /* Acquire the semaphore to synchronize the playback and 2542 * interrupt handler. In order to avoid the playback inter- 2543 * fered by cross talk process, the driver make the playback 2544 * preparation halted until cross talk process finish. 2545 */ 2546 nau8825_sema_acquire(nau8825, 3 * HZ); 2547 /* If FLL reference input is from low frequency source, 2548 * higher error gain can apply such as 0xf which has 2549 * the most sensitive gain error correction threshold, 2550 * Therefore, FLL has the most accurate DCO to 2551 * target frequency. 2552 */ 2553 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2554 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2555 NAU8825_FLL_CLK_SRC_FS | 2556 (0xf << NAU8825_GAIN_ERR_SFT)); 2557 /* Release the semaphore. */ 2558 nau8825_sema_release(nau8825); 2559 2560 if (nau8825->mclk_freq) { 2561 clk_disable_unprepare(nau8825->mclk); 2562 nau8825->mclk_freq = 0; 2563 } 2564 2565 break; 2566 default: 2567 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id); 2568 return -EINVAL; 2569 } 2570 2571 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq, 2572 clk_id); 2573 return 0; 2574 } 2575 2576 static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id, 2577 int source, unsigned int freq, int dir) 2578 { 2579 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2580 2581 return nau8825_configure_sysclk(nau8825, clk_id, freq); 2582 } 2583 2584 static int nau8825_resume_setup(struct nau8825 *nau8825) 2585 { 2586 struct regmap *regmap = nau8825->regmap; 2587 2588 /* Close clock when jack type detection at manual mode */ 2589 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 2590 2591 /* Clear all interruption status */ 2592 nau8825_int_status_clear_all(regmap); 2593 2594 /* Enable both insertion and ejection interruptions, and then 2595 * bypass de-bounce circuit. 2596 */ 2597 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2598 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN | 2599 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN, 2600 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN); 2601 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2602 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 2603 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 2604 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0); 2605 2606 return 0; 2607 } 2608 2609 static int nau8825_set_bias_level(struct snd_soc_component *component, 2610 enum snd_soc_bias_level level) 2611 { 2612 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2613 int ret; 2614 2615 switch (level) { 2616 case SND_SOC_BIAS_ON: 2617 break; 2618 2619 case SND_SOC_BIAS_PREPARE: 2620 break; 2621 2622 case SND_SOC_BIAS_STANDBY: 2623 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 2624 if (nau8825->mclk_freq) { 2625 ret = clk_prepare_enable(nau8825->mclk); 2626 if (ret) { 2627 dev_err(nau8825->dev, "Unable to prepare component mclk\n"); 2628 return ret; 2629 } 2630 } 2631 /* Setup codec configuration after resume */ 2632 nau8825_resume_setup(nau8825); 2633 } 2634 break; 2635 2636 case SND_SOC_BIAS_OFF: 2637 /* Reset the configuration of jack type for detection */ 2638 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 2639 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS, 2640 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 2641 /* ground HPL/HPR, MICGRND1/2 */ 2642 regmap_update_bits(nau8825->regmap, 2643 NAU8825_REG_HSD_CTRL, 0xf, 0xf); 2644 /* Cancel and reset cross talk detection funciton */ 2645 nau8825_xtalk_cancel(nau8825); 2646 /* Turn off all interruptions before system shutdown. Keep the 2647 * interruption quiet before resume setup completes. 2648 */ 2649 regmap_write(nau8825->regmap, 2650 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff); 2651 /* Disable ADC needed for interruptions at audo mode */ 2652 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 2653 NAU8825_ENABLE_ADC, 0); 2654 if (nau8825->mclk_freq) 2655 clk_disable_unprepare(nau8825->mclk); 2656 break; 2657 } 2658 return 0; 2659 } 2660 2661 static int __maybe_unused nau8825_suspend(struct snd_soc_component *component) 2662 { 2663 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2664 2665 disable_irq(nau8825->irq); 2666 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 2667 /* Power down codec power; don't suppoet button wakeup */ 2668 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR"); 2669 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS"); 2670 snd_soc_dapm_sync(nau8825->dapm); 2671 regcache_cache_only(nau8825->regmap, true); 2672 regcache_mark_dirty(nau8825->regmap); 2673 2674 return 0; 2675 } 2676 2677 static int __maybe_unused nau8825_resume(struct snd_soc_component *component) 2678 { 2679 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2680 int ret; 2681 2682 regcache_cache_only(nau8825->regmap, false); 2683 regcache_sync(nau8825->regmap); 2684 nau8825->xtalk_protect = true; 2685 ret = nau8825_sema_acquire(nau8825, 0); 2686 if (ret) 2687 nau8825->xtalk_protect = false; 2688 enable_irq(nau8825->irq); 2689 2690 return 0; 2691 } 2692 2693 static int nau8825_set_jack(struct snd_soc_component *component, 2694 struct snd_soc_jack *jack, void *data) 2695 { 2696 return nau8825_enable_jack_detect(component, jack); 2697 } 2698 2699 static const struct snd_soc_component_driver nau8825_component_driver = { 2700 .probe = nau8825_component_probe, 2701 .remove = nau8825_component_remove, 2702 .set_sysclk = nau8825_set_sysclk, 2703 .set_pll = nau8825_set_pll, 2704 .set_bias_level = nau8825_set_bias_level, 2705 .suspend = nau8825_suspend, 2706 .resume = nau8825_resume, 2707 .controls = nau8825_controls, 2708 .num_controls = ARRAY_SIZE(nau8825_controls), 2709 .dapm_widgets = nau8825_dapm_widgets, 2710 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets), 2711 .dapm_routes = nau8825_dapm_routes, 2712 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes), 2713 .set_jack = nau8825_set_jack, 2714 .suspend_bias_off = 1, 2715 .idle_bias_on = 1, 2716 .use_pmdown_time = 1, 2717 .endianness = 1, 2718 }; 2719 2720 static void nau8825_reset_chip(struct regmap *regmap) 2721 { 2722 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2723 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2724 } 2725 2726 static void nau8825_print_device_properties(struct nau8825 *nau8825) 2727 { 2728 int i; 2729 struct device *dev = nau8825->dev; 2730 2731 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable); 2732 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable); 2733 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up); 2734 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity); 2735 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage); 2736 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance); 2737 2738 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num); 2739 for (i = 0; i < nau8825->sar_threshold_num; i++) 2740 dev_dbg(dev, "sar-threshold[%d]=%d\n", i, 2741 nau8825->sar_threshold[i]); 2742 2743 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis); 2744 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage); 2745 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time); 2746 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time); 2747 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce); 2748 dev_dbg(dev, "jack-insert-debounce: %d\n", 2749 nau8825->jack_insert_debounce); 2750 dev_dbg(dev, "jack-eject-debounce: %d\n", 2751 nau8825->jack_eject_debounce); 2752 dev_dbg(dev, "crosstalk-enable: %d\n", 2753 nau8825->xtalk_enable); 2754 dev_dbg(dev, "adcout-drive-strong: %d\n", nau8825->adcout_ds); 2755 } 2756 2757 static int nau8825_read_device_properties(struct device *dev, 2758 struct nau8825 *nau8825) { 2759 int ret; 2760 2761 nau8825->jkdet_enable = device_property_read_bool(dev, 2762 "nuvoton,jkdet-enable"); 2763 nau8825->jkdet_pull_enable = device_property_read_bool(dev, 2764 "nuvoton,jkdet-pull-enable"); 2765 nau8825->jkdet_pull_up = device_property_read_bool(dev, 2766 "nuvoton,jkdet-pull-up"); 2767 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 2768 &nau8825->jkdet_polarity); 2769 if (ret) 2770 nau8825->jkdet_polarity = 1; 2771 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 2772 &nau8825->micbias_voltage); 2773 if (ret) 2774 nau8825->micbias_voltage = 6; 2775 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 2776 &nau8825->vref_impedance); 2777 if (ret) 2778 nau8825->vref_impedance = 2; 2779 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 2780 &nau8825->sar_threshold_num); 2781 if (ret) 2782 nau8825->sar_threshold_num = 4; 2783 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 2784 nau8825->sar_threshold, nau8825->sar_threshold_num); 2785 if (ret) { 2786 nau8825->sar_threshold[0] = 0x08; 2787 nau8825->sar_threshold[1] = 0x12; 2788 nau8825->sar_threshold[2] = 0x26; 2789 nau8825->sar_threshold[3] = 0x73; 2790 } 2791 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 2792 &nau8825->sar_hysteresis); 2793 if (ret) 2794 nau8825->sar_hysteresis = 0; 2795 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 2796 &nau8825->sar_voltage); 2797 if (ret) 2798 nau8825->sar_voltage = 6; 2799 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 2800 &nau8825->sar_compare_time); 2801 if (ret) 2802 nau8825->sar_compare_time = 1; 2803 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 2804 &nau8825->sar_sampling_time); 2805 if (ret) 2806 nau8825->sar_sampling_time = 1; 2807 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 2808 &nau8825->key_debounce); 2809 if (ret) 2810 nau8825->key_debounce = 3; 2811 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 2812 &nau8825->jack_insert_debounce); 2813 if (ret) 2814 nau8825->jack_insert_debounce = 7; 2815 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 2816 &nau8825->jack_eject_debounce); 2817 if (ret) 2818 nau8825->jack_eject_debounce = 0; 2819 nau8825->xtalk_enable = device_property_read_bool(dev, 2820 "nuvoton,crosstalk-enable"); 2821 nau8825->adcout_ds = device_property_read_bool(dev, "nuvoton,adcout-drive-strong"); 2822 2823 nau8825->mclk = devm_clk_get(dev, "mclk"); 2824 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) { 2825 return -EPROBE_DEFER; 2826 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) { 2827 /* The MCLK is managed externally or not used at all */ 2828 nau8825->mclk = NULL; 2829 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2830 } else if (IS_ERR(nau8825->mclk)) { 2831 return -EINVAL; 2832 } 2833 2834 return 0; 2835 } 2836 2837 static int nau8825_setup_irq(struct nau8825 *nau8825) 2838 { 2839 int ret; 2840 2841 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL, 2842 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 2843 "nau8825", nau8825); 2844 2845 if (ret) { 2846 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n", 2847 nau8825->irq, ret); 2848 return ret; 2849 } 2850 2851 return 0; 2852 } 2853 2854 static int nau8825_i2c_probe(struct i2c_client *i2c) 2855 { 2856 struct device *dev = &i2c->dev; 2857 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev); 2858 int ret, value; 2859 2860 if (!nau8825) { 2861 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL); 2862 if (!nau8825) 2863 return -ENOMEM; 2864 ret = nau8825_read_device_properties(dev, nau8825); 2865 if (ret) 2866 return ret; 2867 } 2868 2869 i2c_set_clientdata(i2c, nau8825); 2870 2871 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config); 2872 if (IS_ERR(nau8825->regmap)) 2873 return PTR_ERR(nau8825->regmap); 2874 nau8825->dev = dev; 2875 nau8825->irq = i2c->irq; 2876 /* Initiate parameters, semaphore and work queue which are needed in 2877 * cross talk suppression measurment function. 2878 */ 2879 nau8825->xtalk_state = NAU8825_XTALK_DONE; 2880 nau8825->xtalk_protect = false; 2881 nau8825->xtalk_baktab_initialized = false; 2882 sema_init(&nau8825->xtalk_sem, 1); 2883 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work); 2884 2885 nau8825_print_device_properties(nau8825); 2886 2887 nau8825_reset_chip(nau8825->regmap); 2888 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value); 2889 if (ret < 0) { 2890 dev_err(dev, "Failed to read device id from the NAU8825: %d\n", 2891 ret); 2892 return ret; 2893 } 2894 if ((value & NAU8825_SOFTWARE_ID_MASK) != 2895 NAU8825_SOFTWARE_ID_NAU8825) { 2896 dev_err(dev, "Not a NAU8825 chip\n"); 2897 return -ENODEV; 2898 } 2899 2900 nau8825_init_regs(nau8825); 2901 2902 if (i2c->irq) 2903 nau8825_setup_irq(nau8825); 2904 2905 return devm_snd_soc_register_component(&i2c->dev, 2906 &nau8825_component_driver, 2907 &nau8825_dai, 1); 2908 } 2909 2910 static void nau8825_i2c_remove(struct i2c_client *client) 2911 {} 2912 2913 static const struct i2c_device_id nau8825_i2c_ids[] = { 2914 { "nau8825", 0 }, 2915 { } 2916 }; 2917 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids); 2918 2919 #ifdef CONFIG_OF 2920 static const struct of_device_id nau8825_of_ids[] = { 2921 { .compatible = "nuvoton,nau8825", }, 2922 {} 2923 }; 2924 MODULE_DEVICE_TABLE(of, nau8825_of_ids); 2925 #endif 2926 2927 #ifdef CONFIG_ACPI 2928 static const struct acpi_device_id nau8825_acpi_match[] = { 2929 { "10508825", 0 }, 2930 {}, 2931 }; 2932 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match); 2933 #endif 2934 2935 static struct i2c_driver nau8825_driver = { 2936 .driver = { 2937 .name = "nau8825", 2938 .of_match_table = of_match_ptr(nau8825_of_ids), 2939 .acpi_match_table = ACPI_PTR(nau8825_acpi_match), 2940 }, 2941 .probe_new = nau8825_i2c_probe, 2942 .remove = nau8825_i2c_remove, 2943 .id_table = nau8825_i2c_ids, 2944 }; 2945 module_i2c_driver(nau8825_driver); 2946 2947 MODULE_DESCRIPTION("ASoC nau8825 driver"); 2948 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>"); 2949 MODULE_LICENSE("GPL"); 2950