1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Nuvoton NAU8825 audio codec driver 4 * 5 * Copyright 2015 Google Chromium project. 6 * Author: Anatol Pomozov <anatol@chromium.org> 7 * Copyright 2015 Nuvoton Technology Corp. 8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com> 9 */ 10 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/i2c.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/clk.h> 18 #include <linux/acpi.h> 19 #include <linux/math64.h> 20 #include <linux/semaphore.h> 21 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/jack.h> 29 30 31 #include "nau8825.h" 32 33 34 #define NUVOTON_CODEC_DAI "nau8825-hifi" 35 36 #define NAU_FREF_MAX 13500000 37 #define NAU_FVCO_MAX 124000000 38 #define NAU_FVCO_MIN 90000000 39 40 /* cross talk suppression detection */ 41 #define LOG10_MAGIC 646456993 42 #define GAIN_AUGMENT 22500 43 #define SIDETONE_BASE 207000 44 45 /* the maximum frequency of CLK_ADC and CLK_DAC */ 46 #define CLK_DA_AD_MAX 6144000 47 48 static int nau8825_configure_sysclk(struct nau8825 *nau8825, 49 int clk_id, unsigned int freq); 50 static bool nau8825_is_jack_inserted(struct regmap *regmap); 51 52 struct nau8825_fll { 53 int mclk_src; 54 int ratio; 55 int fll_frac; 56 int fll_frac_num; 57 int fll_int; 58 int clk_ref_div; 59 }; 60 61 struct nau8825_fll_attr { 62 unsigned int param; 63 unsigned int val; 64 }; 65 66 /* scaling for mclk from sysclk_src output */ 67 static const struct nau8825_fll_attr mclk_src_scaling[] = { 68 { 1, 0x0 }, 69 { 2, 0x2 }, 70 { 4, 0x3 }, 71 { 8, 0x4 }, 72 { 16, 0x5 }, 73 { 32, 0x6 }, 74 { 3, 0x7 }, 75 { 6, 0xa }, 76 { 12, 0xb }, 77 { 24, 0xc }, 78 { 48, 0xd }, 79 { 96, 0xe }, 80 { 5, 0xf }, 81 }; 82 83 /* ratio for input clk freq */ 84 static const struct nau8825_fll_attr fll_ratio[] = { 85 { 512000, 0x01 }, 86 { 256000, 0x02 }, 87 { 128000, 0x04 }, 88 { 64000, 0x08 }, 89 { 32000, 0x10 }, 90 { 8000, 0x20 }, 91 { 4000, 0x40 }, 92 }; 93 94 static const struct nau8825_fll_attr fll_pre_scalar[] = { 95 { 1, 0x0 }, 96 { 2, 0x1 }, 97 { 4, 0x2 }, 98 { 8, 0x3 }, 99 }; 100 101 /* over sampling rate */ 102 struct nau8825_osr_attr { 103 unsigned int osr; 104 unsigned int clk_src; 105 }; 106 107 static const struct nau8825_osr_attr osr_dac_sel[] = { 108 { 64, 2 }, /* OSR 64, SRC 1/4 */ 109 { 256, 0 }, /* OSR 256, SRC 1 */ 110 { 128, 1 }, /* OSR 128, SRC 1/2 */ 111 { 0, 0 }, 112 { 32, 3 }, /* OSR 32, SRC 1/8 */ 113 }; 114 115 static const struct nau8825_osr_attr osr_adc_sel[] = { 116 { 32, 3 }, /* OSR 32, SRC 1/8 */ 117 { 64, 2 }, /* OSR 64, SRC 1/4 */ 118 { 128, 1 }, /* OSR 128, SRC 1/2 */ 119 { 256, 0 }, /* OSR 256, SRC 1 */ 120 }; 121 122 static const struct reg_default nau8825_reg_defaults[] = { 123 { NAU8825_REG_ENA_CTRL, 0x00ff }, 124 { NAU8825_REG_IIC_ADDR_SET, 0x0 }, 125 { NAU8825_REG_CLK_DIVIDER, 0x0050 }, 126 { NAU8825_REG_FLL1, 0x0 }, 127 { NAU8825_REG_FLL2, 0x3126 }, 128 { NAU8825_REG_FLL3, 0x0008 }, 129 { NAU8825_REG_FLL4, 0x0010 }, 130 { NAU8825_REG_FLL5, 0x0 }, 131 { NAU8825_REG_FLL6, 0x6000 }, 132 { NAU8825_REG_FLL_VCO_RSV, 0xf13c }, 133 { NAU8825_REG_HSD_CTRL, 0x000c }, 134 { NAU8825_REG_JACK_DET_CTRL, 0x0 }, 135 { NAU8825_REG_INTERRUPT_MASK, 0x0 }, 136 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff }, 137 { NAU8825_REG_SAR_CTRL, 0x0015 }, 138 { NAU8825_REG_KEYDET_CTRL, 0x0110 }, 139 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 }, 140 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 }, 141 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 }, 142 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 }, 143 { NAU8825_REG_GPIO34_CTRL, 0x0 }, 144 { NAU8825_REG_GPIO12_CTRL, 0x0 }, 145 { NAU8825_REG_TDM_CTRL, 0x0 }, 146 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b }, 147 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 }, 148 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 }, 149 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 }, 150 { NAU8825_REG_BIQ_CTRL, 0x0 }, 151 { NAU8825_REG_BIQ_COF1, 0x0 }, 152 { NAU8825_REG_BIQ_COF2, 0x0 }, 153 { NAU8825_REG_BIQ_COF3, 0x0 }, 154 { NAU8825_REG_BIQ_COF4, 0x0 }, 155 { NAU8825_REG_BIQ_COF5, 0x0 }, 156 { NAU8825_REG_BIQ_COF6, 0x0 }, 157 { NAU8825_REG_BIQ_COF7, 0x0 }, 158 { NAU8825_REG_BIQ_COF8, 0x0 }, 159 { NAU8825_REG_BIQ_COF9, 0x0 }, 160 { NAU8825_REG_BIQ_COF10, 0x0 }, 161 { NAU8825_REG_ADC_RATE, 0x0010 }, 162 { NAU8825_REG_DAC_CTRL1, 0x0001 }, 163 { NAU8825_REG_DAC_CTRL2, 0x0 }, 164 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 }, 165 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 166 { NAU8825_REG_MUTE_CTRL, 0x0 }, 167 { NAU8825_REG_HSVOL_CTRL, 0x0 }, 168 { NAU8825_REG_DACL_CTRL, 0x02cf }, 169 { NAU8825_REG_DACR_CTRL, 0x00cf }, 170 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 }, 171 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 }, 172 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff }, 173 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 }, 174 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 }, 175 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 }, 176 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 }, 177 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 }, 178 { NAU8825_REG_IMM_MODE_CTRL, 0x0 }, 179 { NAU8825_REG_CLASSG_CTRL, 0x0 }, 180 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 }, 181 { NAU8825_REG_MISC_CTRL, 0x0 }, 182 { NAU8825_REG_FLL2_LOWER, 0x0 }, 183 { NAU8825_REG_FLL2_UPPER, 0x0 }, 184 { NAU8825_REG_BIAS_ADJ, 0x0 }, 185 { NAU8825_REG_TRIM_SETTINGS, 0x0 }, 186 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 }, 187 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 }, 188 { NAU8825_REG_ANALOG_ADC_1, 0x0011 }, 189 { NAU8825_REG_ANALOG_ADC_2, 0x0020 }, 190 { NAU8825_REG_RDAC, 0x0008 }, 191 { NAU8825_REG_MIC_BIAS, 0x0006 }, 192 { NAU8825_REG_BOOST, 0x0 }, 193 { NAU8825_REG_FEPGA, 0x0 }, 194 { NAU8825_REG_POWER_UP_CONTROL, 0x0 }, 195 { NAU8825_REG_CHARGE_PUMP, 0x0 }, 196 }; 197 198 /* register backup table when cross talk detection */ 199 static struct reg_default nau8825_xtalk_baktab[] = { 200 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, 201 { NAU8825_REG_HSVOL_CTRL, 0 }, 202 { NAU8825_REG_DACL_CTRL, 0x00cf }, 203 { NAU8825_REG_DACR_CTRL, 0x02cf }, 204 }; 205 206 /* The regmap patch for Rev C */ 207 static const struct reg_sequence nau8825_regmap_patch[] = { 208 { NAU8825_REG_FLL2, 0x0000 }, 209 { NAU8825_REG_FLL4, 0x8010 }, 210 { NAU8825_REG_FLL_VCO_RSV, 0x0bc0 }, 211 { NAU8825_REG_INTERRUPT_MASK, 0x0800 }, 212 { NAU8825_REG_DACL_CTRL, 0x00cf }, 213 { NAU8825_REG_DACR_CTRL, 0x02cf }, 214 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0400 }, 215 { NAU8825_REG_FLL2_LOWER, 0x26e9 }, 216 { NAU8825_REG_FLL2_UPPER, 0x0031 }, 217 { NAU8825_REG_ANALOG_CONTROL_2, 0x0020 }, 218 { NAU8825_REG_ANALOG_ADC_2, 0x0220 }, 219 { NAU8825_REG_MIC_BIAS, 0x0046 }, 220 }; 221 222 223 static const unsigned short logtable[256] = { 224 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7, 225 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508, 226 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6, 227 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37, 228 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f, 229 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41, 230 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1, 231 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142, 232 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68, 233 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355, 234 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c, 235 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490, 236 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3, 237 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507, 238 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe, 239 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca, 240 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c, 241 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7, 242 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c, 243 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c, 244 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a, 245 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065, 246 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730, 247 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc, 248 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469, 249 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9, 250 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c, 251 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765, 252 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83, 253 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387, 254 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973, 255 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47 256 }; 257 258 /** 259 * nau8825_sema_acquire - acquire the semaphore of nau88l25 260 * @nau8825: component to register the codec private data with 261 * @timeout: how long in jiffies to wait before failure or zero to wait 262 * until release 263 * 264 * Attempts to acquire the semaphore with number of jiffies. If no more 265 * tasks are allowed to acquire the semaphore, calling this function will 266 * put the task to sleep. If the semaphore is not released within the 267 * specified number of jiffies, this function returns. 268 * If the semaphore is not released within the specified number of jiffies, 269 * this function returns -ETIME. If the sleep is interrupted by a signal, 270 * this function will return -EINTR. It returns 0 if the semaphore was 271 * acquired successfully. 272 * 273 * Acquires the semaphore without jiffies. Try to acquire the semaphore 274 * atomically. Returns 0 if the semaphore has been acquired successfully 275 * or 1 if it cannot be acquired. 276 */ 277 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout) 278 { 279 int ret; 280 281 if (timeout) { 282 ret = down_timeout(&nau8825->xtalk_sem, timeout); 283 if (ret < 0) 284 dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); 285 } else { 286 ret = down_trylock(&nau8825->xtalk_sem); 287 if (ret) 288 dev_warn(nau8825->dev, "Acquire semaphore fail\n"); 289 } 290 291 return ret; 292 } 293 294 /** 295 * nau8825_sema_release - release the semaphore of nau88l25 296 * @nau8825: component to register the codec private data with 297 * 298 * Release the semaphore which may be called from any context and 299 * even by tasks which have never called down(). 300 */ 301 static inline void nau8825_sema_release(struct nau8825 *nau8825) 302 { 303 up(&nau8825->xtalk_sem); 304 } 305 306 /** 307 * nau8825_sema_reset - reset the semaphore for nau88l25 308 * @nau8825: component to register the codec private data with 309 * 310 * Reset the counter of the semaphore. Call this function to restart 311 * a new round task management. 312 */ 313 static inline void nau8825_sema_reset(struct nau8825 *nau8825) 314 { 315 nau8825->xtalk_sem.count = 1; 316 } 317 318 /** 319 * nau8825_hpvol_ramp - Ramp up the headphone volume change gradually to target level. 320 * 321 * @nau8825: component to register the codec private data with 322 * @vol_from: the volume to start up 323 * @vol_to: the target volume 324 * @step: the volume span to move on 325 * 326 * The headphone volume is from 0dB to minimum -54dB and -1dB per step. 327 * If the volume changes sharp, there is a pop noise heard in headphone. We 328 * provide the function to ramp up the volume up or down by delaying 10ms 329 * per step. 330 */ 331 static void nau8825_hpvol_ramp(struct nau8825 *nau8825, 332 unsigned int vol_from, unsigned int vol_to, unsigned int step) 333 { 334 unsigned int value, volume, ramp_up, from, to; 335 336 if (vol_from == vol_to || step == 0) { 337 return; 338 } else if (vol_from < vol_to) { 339 ramp_up = true; 340 from = vol_from; 341 to = vol_to; 342 } else { 343 ramp_up = false; 344 from = vol_to; 345 to = vol_from; 346 } 347 /* only handle volume from 0dB to minimum -54dB */ 348 if (to > NAU8825_HP_VOL_MIN) 349 to = NAU8825_HP_VOL_MIN; 350 351 for (volume = from; volume < to; volume += step) { 352 if (ramp_up) 353 value = volume; 354 else 355 value = to - volume + from; 356 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 357 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 358 (value << NAU8825_HPL_VOL_SFT) | value); 359 usleep_range(10000, 10500); 360 } 361 if (ramp_up) 362 value = to; 363 else 364 value = from; 365 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, 366 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, 367 (value << NAU8825_HPL_VOL_SFT) | value); 368 } 369 370 /** 371 * nau8825_intlog10_dec3 - Computes log10 of a value 372 * the result is round off to 3 decimal. This function takes reference to 373 * dvb-math. The source code locates as the following. 374 * Linux/drivers/media/dvb-core/dvb_math.c 375 * @value: input for log10 376 * 377 * return log10(value) * 1000 378 */ 379 static u32 nau8825_intlog10_dec3(u32 value) 380 { 381 u32 msb, logentry, significand, interpolation, log10val; 382 u64 log2val; 383 384 /* first detect the msb (count begins at 0) */ 385 msb = fls(value) - 1; 386 /** 387 * now we use a logtable after the following method: 388 * 389 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24 390 * where x = msb and therefore 1 <= y < 2 391 * first y is determined by shifting the value left 392 * so that msb is bit 31 393 * 0x00231f56 -> 0x8C7D5800 394 * the result is y * 2^31 -> "significand" 395 * then the highest 9 bits are used for a table lookup 396 * the highest bit is discarded because it's always set 397 * the highest nine bits in our example are 100011000 398 * so we would use the entry 0x18 399 */ 400 significand = value << (31 - msb); 401 logentry = (significand >> 23) & 0xff; 402 /** 403 * last step we do is interpolation because of the 404 * limitations of the log table the error is that part of 405 * the significand which isn't used for lookup then we 406 * compute the ratio between the error and the next table entry 407 * and interpolate it between the log table entry used and the 408 * next one the biggest error possible is 0x7fffff 409 * (in our example it's 0x7D5800) 410 * needed value for next table entry is 0x800000 411 * so the interpolation is 412 * (error / 0x800000) * (logtable_next - logtable_current) 413 * in the implementation the division is moved to the end for 414 * better accuracy there is also an overflow correction if 415 * logtable_next is 256 416 */ 417 interpolation = ((significand & 0x7fffff) * 418 ((logtable[(logentry + 1) & 0xff] - 419 logtable[logentry]) & 0xffff)) >> 15; 420 421 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation); 422 /** 423 * log10(x) = log2(x) * log10(2) 424 */ 425 log10val = (log2val * LOG10_MAGIC) >> 31; 426 /** 427 * the result is round off to 3 decimal 428 */ 429 return log10val / ((1 << 24) / 1000); 430 } 431 432 /** 433 * nau8825_xtalk_sidetone - computes cross talk suppression sidetone gain. 434 * 435 * @sig_org: orignal signal level 436 * @sig_cros: cross talk signal level 437 * 438 * The orignal and cross talk signal vlues need to be characterized. 439 * Once these values have been characterized, this sidetone value 440 * can be converted to decibel with the equation below. 441 * sidetone = 20 * log (original signal level / crosstalk signal level) 442 * 443 * return cross talk sidetone gain 444 */ 445 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros) 446 { 447 u32 gain, sidetone; 448 449 if (WARN_ON(sig_org == 0 || sig_cros == 0)) 450 return 0; 451 452 sig_org = nau8825_intlog10_dec3(sig_org); 453 sig_cros = nau8825_intlog10_dec3(sig_cros); 454 if (sig_org >= sig_cros) 455 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT; 456 else 457 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT; 458 sidetone = SIDETONE_BASE - gain * 2; 459 sidetone /= 1000; 460 461 return sidetone; 462 } 463 464 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg) 465 { 466 int index; 467 468 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++) 469 if (nau8825_xtalk_baktab[index].reg == reg) 470 return index; 471 return -EINVAL; 472 } 473 474 static void nau8825_xtalk_backup(struct nau8825 *nau8825) 475 { 476 int i; 477 478 if (nau8825->xtalk_baktab_initialized) 479 return; 480 481 /* Backup some register values to backup table */ 482 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) 483 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 484 &nau8825_xtalk_baktab[i].def); 485 486 nau8825->xtalk_baktab_initialized = true; 487 } 488 489 static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel) 490 { 491 int i, volume; 492 493 if (!nau8825->xtalk_baktab_initialized) 494 return; 495 496 /* Restore register values from backup table; When the driver restores 497 * the headphone volume in XTALK_DONE state, it needs recover to 498 * original level gradually with 3dB per step for less pop noise. 499 * Otherwise, the restore should do ASAP. 500 */ 501 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) { 502 if (!cause_cancel && nau8825_xtalk_baktab[i].reg == 503 NAU8825_REG_HSVOL_CTRL) { 504 /* Ramping up the volume change to reduce pop noise */ 505 volume = nau8825_xtalk_baktab[i].def & 506 NAU8825_HPR_VOL_MASK; 507 nau8825_hpvol_ramp(nau8825, 0, volume, 3); 508 continue; 509 } 510 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg, 511 nau8825_xtalk_baktab[i].def); 512 } 513 514 nau8825->xtalk_baktab_initialized = false; 515 } 516 517 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825) 518 { 519 /* Enable power of DAC path */ 520 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 521 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 522 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK | 523 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR | 524 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC | 525 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK); 526 /* Prevent startup click by letting charge pump to ramp up and 527 * change bump enable 528 */ 529 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 530 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 531 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN); 532 /* Enable clock sync of DAC and DAC clock */ 533 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 534 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN | 535 NAU8825_RDAC_FS_BCLK_ENB, 536 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN); 537 /* Power up output driver with 2 stage */ 538 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 539 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 540 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 541 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 542 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L); 543 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 544 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 545 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L); 546 /* HP outputs not shouted to ground */ 547 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 548 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0); 549 /* Enable HP boost driver */ 550 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 551 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS); 552 /* Enable class G compare path to supply 1.8V or 0.9V. */ 553 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL, 554 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN, 555 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN); 556 } 557 558 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825) 559 { 560 /* Power up left ADC and raise 5dB than Vmid for Vref */ 561 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 562 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 563 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB); 564 } 565 566 static void nau8825_xtalk_clock(struct nau8825 *nau8825) 567 { 568 /* Recover FLL default value */ 569 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0); 570 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126); 571 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008); 572 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010); 573 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0); 574 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000); 575 /* Enable internal VCO clock for detection signal generated */ 576 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 577 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 578 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 579 NAU8825_DCO_EN); 580 /* Given specific clock frequency of internal clock to 581 * generate signal. 582 */ 583 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 584 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 585 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 586 NAU8825_FLL_RATIO_MASK, 0x10); 587 } 588 589 static void nau8825_xtalk_prepare(struct nau8825 *nau8825) 590 { 591 int volume, index; 592 593 /* Backup those registers changed by cross talk detection */ 594 nau8825_xtalk_backup(nau8825); 595 /* Config IIS as master to output signal by codec */ 596 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 597 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 598 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER | 599 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1); 600 /* Ramp up headphone volume to 0dB to get better performance and 601 * avoid pop noise in headphone. 602 */ 603 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL); 604 if (index != -EINVAL) { 605 volume = nau8825_xtalk_baktab[index].def & 606 NAU8825_HPR_VOL_MASK; 607 nau8825_hpvol_ramp(nau8825, volume, 0, 3); 608 } 609 nau8825_xtalk_clock(nau8825); 610 nau8825_xtalk_prepare_dac(nau8825); 611 nau8825_xtalk_prepare_adc(nau8825); 612 /* Config channel path and digital gain */ 613 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 614 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK, 615 NAU8825_DACL_CH_SEL_L | 0xab); 616 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 617 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK, 618 NAU8825_DACR_CH_SEL_R | 0xab); 619 /* Config cross talk parameters and generate the 23Hz sine wave with 620 * 1/16 full scale of signal level for impedance measurement. 621 */ 622 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 623 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK | 624 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK, 625 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th | 626 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN); 627 /* RMS intrruption enable */ 628 regmap_update_bits(nau8825->regmap, 629 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0); 630 /* Power up left and right DAC */ 631 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) 632 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 633 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); 634 else 635 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 636 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 637 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 638 } 639 640 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825) 641 { 642 /* Disable HP boost driver */ 643 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 644 NAU8825_HP_BOOST_DIS, 0); 645 /* HP outputs shouted to ground */ 646 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, 647 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 648 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 649 /* Power down left and right DAC */ 650 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) 651 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 652 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 653 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 654 else 655 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 656 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); 657 658 /* Enable the TESTDAC and disable L/R HP impedance */ 659 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 660 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP | 661 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 662 /* Power down output driver with 2 stage */ 663 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 664 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0); 665 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, 666 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | 667 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0); 668 /* Disable clock sync of DAC and DAC clock */ 669 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, 670 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0); 671 /* Disable charge pump ramp up function and change bump */ 672 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 673 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0); 674 /* Disable power of DAC path */ 675 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 676 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | 677 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0); 678 if (!nau8825->irq) 679 regmap_update_bits(nau8825->regmap, 680 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 681 } 682 683 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825) 684 { 685 /* Power down left ADC and restore voltage to Vmid */ 686 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, 687 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0); 688 } 689 690 static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel) 691 { 692 /* Enable internal VCO needed for interruptions */ 693 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 694 nau8825_xtalk_clean_dac(nau8825); 695 nau8825_xtalk_clean_adc(nau8825); 696 /* Clear cross talk parameters and disable */ 697 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0); 698 /* RMS intrruption disable */ 699 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK, 700 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN); 701 /* Recover default value for IIS */ 702 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 703 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | 704 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE); 705 /* Restore value of specific register for cross talk */ 706 nau8825_xtalk_restore(nau8825, cause_cancel); 707 } 708 709 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol) 710 { 711 /* Apply ADC volume for better cross talk performance */ 712 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL, 713 NAU8825_ADC_DIG_VOL_MASK, vol); 714 /* Disables JKTIP(HPL) DAC channel for right to left measurement. 715 * Do it before sending signal in order to erase pop noise. 716 */ 717 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 718 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN, 719 NAU8825_BIAS_TESTDACL_EN); 720 switch (nau8825->xtalk_state) { 721 case NAU8825_XTALK_HPR_R2L: 722 /* Enable right headphone impedance */ 723 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 724 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 725 NAU8825_BIAS_HPR_IMP); 726 break; 727 case NAU8825_XTALK_HPL_R2L: 728 /* Enable left headphone impedance */ 729 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 730 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, 731 NAU8825_BIAS_HPL_IMP); 732 break; 733 default: 734 break; 735 } 736 msleep(100); 737 /* Impedance measurement mode enable */ 738 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 739 NAU8825_IMM_EN, NAU8825_IMM_EN); 740 } 741 742 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825) 743 { 744 /* Impedance measurement mode disable */ 745 regmap_update_bits(nau8825->regmap, 746 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0); 747 } 748 749 /* The cross talk measurement function can reduce cross talk across the 750 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal 751 * level to determine what cross talk reduction gain is. This system works by 752 * sending a 23Hz -24dBV sine wave into the headset output DAC and through 753 * the PGA. The output of the PGA is then connected to an internal current 754 * sense which measures the attenuated 23Hz signal and passing the output to 755 * an ADC which converts the measurement to a binary code. With two separated 756 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data 757 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement. 758 * Thus, the measurement function has four states to complete whole sequence. 759 * 1. Prepare state : Prepare the resource for detection and transfer to HPR 760 * IMM stat to make JKR1(HPR) impedance measure. 761 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer 762 * to HPL IMM state to make JKTIP(HPL) impedance measure. 763 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and 764 * transfer to IMM state to determine suppression sidetone gain. 765 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal 766 * and cross talk signal level. Apply this gain and then restore codec 767 * configuration. Then transfer to Done state for ending. 768 */ 769 static void nau8825_xtalk_measure(struct nau8825 *nau8825) 770 { 771 u32 sidetone; 772 773 switch (nau8825->xtalk_state) { 774 case NAU8825_XTALK_PREPARE: 775 /* In prepare state, set up clock, intrruption, DAC path, ADC 776 * path and cross talk detection parameters for preparation. 777 */ 778 nau8825_xtalk_prepare(nau8825); 779 msleep(280); 780 /* Trigger right headphone impedance detection */ 781 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L; 782 nau8825_xtalk_imm_start(nau8825, 0x00d2); 783 break; 784 case NAU8825_XTALK_HPR_R2L: 785 /* In right headphone IMM state, read out right headphone 786 * impedance measure result, and then start up left side. 787 */ 788 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 789 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 790 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n", 791 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); 792 /* Disable then re-enable IMM mode to update */ 793 nau8825_xtalk_imm_stop(nau8825); 794 /* Trigger left headphone impedance detection */ 795 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L; 796 nau8825_xtalk_imm_start(nau8825, 0x00ff); 797 break; 798 case NAU8825_XTALK_HPL_R2L: 799 /* In left headphone IMM state, read out left headphone 800 * impedance measure result, and delay some time to wait 801 * detection sine wave output finish. Then, we can calculate 802 * the cross talk suppresstion side tone according to the L/R 803 * headphone imedance. 804 */ 805 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, 806 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 807 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n", 808 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 809 nau8825_xtalk_imm_stop(nau8825); 810 msleep(150); 811 nau8825->xtalk_state = NAU8825_XTALK_IMM; 812 break; 813 case NAU8825_XTALK_IMM: 814 /* In impedance measure state, the orignal and cross talk 815 * signal level vlues are ready. The side tone gain is deter- 816 * mined with these signal level. After all, restore codec 817 * configuration. 818 */ 819 sidetone = nau8825_xtalk_sidetone( 820 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L], 821 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); 822 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone); 823 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL, 824 (sidetone << 8) | sidetone); 825 nau8825_xtalk_clean(nau8825, false); 826 nau8825->xtalk_state = NAU8825_XTALK_DONE; 827 break; 828 default: 829 break; 830 } 831 } 832 833 static void nau8825_xtalk_work(struct work_struct *work) 834 { 835 struct nau8825 *nau8825 = container_of( 836 work, struct nau8825, xtalk_work); 837 838 nau8825_xtalk_measure(nau8825); 839 /* To determine the cross talk side tone gain when reach 840 * the impedance measure state. 841 */ 842 if (nau8825->xtalk_state == NAU8825_XTALK_IMM) 843 nau8825_xtalk_measure(nau8825); 844 845 /* Delay jack report until cross talk detection process 846 * completed. It can avoid application to do playback 847 * preparation before cross talk detection is still working. 848 * Meanwhile, the protection of the cross talk detection 849 * is released. 850 */ 851 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) { 852 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event, 853 nau8825->xtalk_event_mask); 854 nau8825_sema_release(nau8825); 855 nau8825->xtalk_protect = false; 856 } 857 } 858 859 static void nau8825_xtalk_cancel(struct nau8825 *nau8825) 860 { 861 /* If the crosstalk is eanbled and the process is on going, 862 * the driver forces to cancel the crosstalk task and 863 * restores the configuration to original status. 864 */ 865 if (nau8825->xtalk_enable && nau8825->xtalk_state != 866 NAU8825_XTALK_DONE) { 867 cancel_work_sync(&nau8825->xtalk_work); 868 nau8825_xtalk_clean(nau8825, true); 869 } 870 /* Reset parameters for cross talk suppression function */ 871 nau8825_sema_reset(nau8825); 872 nau8825->xtalk_state = NAU8825_XTALK_DONE; 873 nau8825->xtalk_protect = false; 874 } 875 876 static bool nau8825_readable_reg(struct device *dev, unsigned int reg) 877 { 878 switch (reg) { 879 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV: 880 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 881 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL: 882 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 883 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 884 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 885 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R: 886 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 887 case NAU8825_REG_MISC_CTRL: 888 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_FLL2_UPPER: 889 case NAU8825_REG_BIAS_ADJ: 890 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 891 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 892 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 893 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS: 894 return true; 895 default: 896 return false; 897 } 898 899 } 900 901 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg) 902 { 903 switch (reg) { 904 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV: 905 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: 906 case NAU8825_REG_INTERRUPT_MASK: 907 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL: 908 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: 909 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: 910 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: 911 case NAU8825_REG_IMM_MODE_CTRL: 912 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: 913 case NAU8825_REG_MISC_CTRL: 914 case NAU8825_REG_FLL2_LOWER ... NAU8825_REG_FLL2_UPPER: 915 case NAU8825_REG_BIAS_ADJ: 916 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: 917 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: 918 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: 919 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP: 920 return true; 921 default: 922 return false; 923 } 924 } 925 926 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg) 927 { 928 switch (reg) { 929 case NAU8825_REG_RESET: 930 case NAU8825_REG_IRQ_STATUS: 931 case NAU8825_REG_INT_CLR_KEY_STATUS: 932 case NAU8825_REG_IMM_RMS_L: 933 case NAU8825_REG_IMM_RMS_R: 934 case NAU8825_REG_I2C_DEVICE_ID: 935 case NAU8825_REG_SARDOUT_RAM_STATUS: 936 case NAU8825_REG_CHARGE_PUMP_INPUT_READ: 937 case NAU8825_REG_GENERAL_STATUS: 938 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10: 939 return true; 940 default: 941 return false; 942 } 943 } 944 945 static int nau8825_fepga_event(struct snd_soc_dapm_widget *w, 946 struct snd_kcontrol *kcontrol, int event) 947 { 948 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 949 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 950 951 switch (event) { 952 case SND_SOC_DAPM_POST_PMU: 953 regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA, 954 NAU8825_ACDC_CTRL_MASK, 955 NAU8825_ACDC_VREF_MICP | NAU8825_ACDC_VREF_MICN); 956 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 957 NAU8825_DISCHRG_EN, NAU8825_DISCHRG_EN); 958 msleep(40); 959 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 960 NAU8825_DISCHRG_EN, 0); 961 regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA, 962 NAU8825_ACDC_CTRL_MASK, 0); 963 break; 964 default: 965 break; 966 } 967 968 return 0; 969 } 970 971 static int nau8825_adc_event(struct snd_soc_dapm_widget *w, 972 struct snd_kcontrol *kcontrol, int event) 973 { 974 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 975 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 976 977 switch (event) { 978 case SND_SOC_DAPM_POST_PMU: 979 msleep(nau8825->adc_delay); 980 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 981 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 982 break; 983 case SND_SOC_DAPM_POST_PMD: 984 if (!nau8825->irq) 985 regmap_update_bits(nau8825->regmap, 986 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); 987 break; 988 default: 989 return -EINVAL; 990 } 991 992 return 0; 993 } 994 995 static int nau8825_pump_event(struct snd_soc_dapm_widget *w, 996 struct snd_kcontrol *kcontrol, int event) 997 { 998 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 999 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1000 1001 switch (event) { 1002 case SND_SOC_DAPM_POST_PMU: 1003 /* Prevent startup click by letting charge pump to ramp up */ 1004 msleep(10); 1005 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 1006 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW); 1007 break; 1008 case SND_SOC_DAPM_PRE_PMD: 1009 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 1010 NAU8825_JAMNODCLOW, 0); 1011 break; 1012 default: 1013 return -EINVAL; 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w, 1020 struct snd_kcontrol *kcontrol, int event) 1021 { 1022 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1023 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1024 1025 switch (event) { 1026 case SND_SOC_DAPM_PRE_PMU: 1027 /* Disables the TESTDAC to let DAC signal pass through. */ 1028 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 1029 NAU8825_BIAS_TESTDAC_EN, 0); 1030 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) 1031 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 1032 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); 1033 else 1034 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 1035 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 1036 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 1037 break; 1038 case SND_SOC_DAPM_POST_PMD: 1039 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 1040 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 1041 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) 1042 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 1043 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 1044 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 1045 else 1046 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, 1047 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); 1048 1049 break; 1050 default: 1051 return -EINVAL; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int system_clock_control(struct snd_soc_dapm_widget *w, 1058 struct snd_kcontrol *k, int event) 1059 { 1060 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1061 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1062 struct regmap *regmap = nau8825->regmap; 1063 1064 if (SND_SOC_DAPM_EVENT_OFF(event)) { 1065 dev_dbg(nau8825->dev, "system clock control : POWER OFF\n"); 1066 /* Set clock source to disable or internal clock before the 1067 * playback or capture end. Codec needs clock for Jack 1068 * detection and button press if jack inserted; otherwise, 1069 * the clock should be closed. 1070 */ 1071 if (nau8825_is_jack_inserted(regmap)) { 1072 nau8825_configure_sysclk(nau8825, 1073 NAU8825_CLK_INTERNAL, 0); 1074 } else { 1075 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 1076 } 1077 } 1078 1079 return 0; 1080 } 1081 1082 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol, 1083 struct snd_ctl_elem_value *ucontrol) 1084 { 1085 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1086 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 1087 1088 if (!component->regmap) 1089 return -EINVAL; 1090 1091 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1, 1092 ucontrol->value.bytes.data, params->max); 1093 return 0; 1094 } 1095 1096 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol, 1097 struct snd_ctl_elem_value *ucontrol) 1098 { 1099 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1100 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 1101 void *data; 1102 1103 if (!component->regmap) 1104 return -EINVAL; 1105 1106 data = kmemdup(ucontrol->value.bytes.data, 1107 params->max, GFP_KERNEL | GFP_DMA); 1108 if (!data) 1109 return -ENOMEM; 1110 1111 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1112 NAU8825_BIQ_WRT_EN, 0); 1113 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1, 1114 data, params->max); 1115 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, 1116 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN); 1117 1118 kfree(data); 1119 return 0; 1120 } 1121 1122 static const char * const nau8825_biq_path[] = { 1123 "ADC", "DAC" 1124 }; 1125 1126 static const struct soc_enum nau8825_biq_path_enum = 1127 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT, 1128 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path); 1129 1130 static const char * const nau8825_adc_decimation[] = { 1131 "32", "64", "128", "256" 1132 }; 1133 1134 static const struct soc_enum nau8825_adc_decimation_enum = 1135 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT, 1136 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation); 1137 1138 static const char * const nau8825_dac_oversampl[] = { 1139 "64", "256", "128", "", "32" 1140 }; 1141 1142 static const struct soc_enum nau8825_dac_oversampl_enum = 1143 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT, 1144 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl); 1145 1146 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400); 1147 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 1148 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0); 1149 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 1150 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400); 1151 1152 static const struct snd_kcontrol_new nau8825_controls[] = { 1153 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1154 0, 0xff, 0, adc_vol_tlv), 1155 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL, 1156 12, 8, 0x0f, 0, sidetone_vol_tlv), 1157 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL, 1158 6, 0, 0x3f, 1, dac_vol_tlv), 1159 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL, 1160 8, 37, 0, fepga_gain_tlv), 1161 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL, 1162 0, 8, 0xff, 0, crosstalk_vol_tlv), 1163 1164 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum), 1165 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum), 1166 /* programmable biquad filter */ 1167 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum), 1168 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 1169 nau8825_biq_coeff_get, nau8825_biq_coeff_put), 1170 }; 1171 1172 /* DAC Mux 0x33[9] and 0x34[9] */ 1173 static const char * const nau8825_dac_src[] = { 1174 "DACL", "DACR", 1175 }; 1176 1177 static SOC_ENUM_SINGLE_DECL( 1178 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL, 1179 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src); 1180 1181 static SOC_ENUM_SINGLE_DECL( 1182 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL, 1183 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src); 1184 1185 static const struct snd_kcontrol_new nau8825_dacl_mux = 1186 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum); 1187 1188 static const struct snd_kcontrol_new nau8825_dacr_mux = 1189 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum); 1190 1191 1192 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = { 1193 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2, 1194 15, 1), 1195 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 1196 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 1197 system_clock_control, SND_SOC_DAPM_POST_PMD), 1198 1199 SND_SOC_DAPM_INPUT("MIC"), 1200 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0), 1201 1202 SND_SOC_DAPM_PGA_E("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0, 1203 NULL, 0, nau8825_fepga_event, SND_SOC_DAPM_POST_PMU), 1204 1205 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0, 1206 nau8825_adc_event, SND_SOC_DAPM_POST_PMU | 1207 SND_SOC_DAPM_POST_PMD), 1208 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0), 1209 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL, 1210 0), 1211 1212 /* ADC for button press detection. A dapm supply widget is used to 1213 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON 1214 * during suspend. 1215 */ 1216 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL, 1217 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0), 1218 1219 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0), 1220 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0), 1221 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0), 1222 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0), 1223 1224 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL, 1225 NAU8825_ENABLE_DACR_SFT, 0), 1226 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL, 1227 NAU8825_ENABLE_DACL_SFT, 0), 1228 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0), 1229 1230 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux), 1231 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux), 1232 1233 SND_SOC_DAPM_PGA_S("HP amp L", 0, 1234 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0), 1235 SND_SOC_DAPM_PGA_S("HP amp R", 0, 1236 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0), 1237 1238 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0, 1239 nau8825_pump_event, SND_SOC_DAPM_POST_PMU | 1240 SND_SOC_DAPM_PRE_PMD), 1241 1242 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 1243 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0), 1244 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 1245 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0), 1246 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 1247 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 1248 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 1249 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 1250 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 1251 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 1252 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 1253 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 1254 1255 SND_SOC_DAPM_PGA_S("Output DACL", 7, 1256 SND_SOC_NOPM, 0, 0, nau8825_output_dac_event, 1257 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1258 SND_SOC_DAPM_PGA_S("Output DACR", 7, 1259 SND_SOC_NOPM, 0, 0, nau8825_output_dac_event, 1260 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1261 1262 1263 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 1264 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 1265 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0), 1266 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 1267 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0), 1268 1269 /* High current HPOL/R boost driver */ 1270 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 1271 NAU8825_REG_BOOST, 9, 1, NULL, 0), 1272 1273 /* Class G operation control*/ 1274 SND_SOC_DAPM_PGA_S("Class G", 10, 1275 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0), 1276 1277 SND_SOC_DAPM_OUTPUT("HPOL"), 1278 SND_SOC_DAPM_OUTPUT("HPOR"), 1279 }; 1280 1281 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { 1282 {"Frontend PGA", NULL, "MIC"}, 1283 {"ADC", NULL, "Frontend PGA"}, 1284 {"ADC", NULL, "ADC Clock"}, 1285 {"ADC", NULL, "ADC Power"}, 1286 {"AIFTX", NULL, "ADC"}, 1287 {"AIFTX", NULL, "System Clock"}, 1288 1289 {"AIFRX", NULL, "System Clock"}, 1290 {"DDACL", NULL, "AIFRX"}, 1291 {"DDACR", NULL, "AIFRX"}, 1292 {"DDACL", NULL, "DDAC Clock"}, 1293 {"DDACR", NULL, "DDAC Clock"}, 1294 {"DACL Mux", "DACL", "DDACL"}, 1295 {"DACL Mux", "DACR", "DDACR"}, 1296 {"DACR Mux", "DACL", "DDACL"}, 1297 {"DACR Mux", "DACR", "DDACR"}, 1298 {"HP amp L", NULL, "DACL Mux"}, 1299 {"HP amp R", NULL, "DACR Mux"}, 1300 {"Charge Pump", NULL, "HP amp L"}, 1301 {"Charge Pump", NULL, "HP amp R"}, 1302 {"ADACL", NULL, "Charge Pump"}, 1303 {"ADACR", NULL, "Charge Pump"}, 1304 {"ADACL Clock", NULL, "ADACL"}, 1305 {"ADACR Clock", NULL, "ADACR"}, 1306 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 1307 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 1308 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 1309 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 1310 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 1311 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 1312 {"Output DACL", NULL, "Output Driver L Stage 3"}, 1313 {"Output DACR", NULL, "Output Driver R Stage 3"}, 1314 {"HPOL Pulldown", NULL, "Output DACL"}, 1315 {"HPOR Pulldown", NULL, "Output DACR"}, 1316 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 1317 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 1318 {"Class G", NULL, "HP Boost Driver"}, 1319 {"HPOL", NULL, "Class G"}, 1320 {"HPOR", NULL, "Class G"}, 1321 }; 1322 1323 static const struct nau8825_osr_attr * 1324 nau8825_get_osr(struct nau8825 *nau8825, int stream) 1325 { 1326 unsigned int osr; 1327 1328 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1329 regmap_read(nau8825->regmap, 1330 NAU8825_REG_DAC_CTRL1, &osr); 1331 osr &= NAU8825_DAC_OVERSAMPLE_MASK; 1332 if (osr >= ARRAY_SIZE(osr_dac_sel)) 1333 return NULL; 1334 return &osr_dac_sel[osr]; 1335 } else { 1336 regmap_read(nau8825->regmap, 1337 NAU8825_REG_ADC_RATE, &osr); 1338 osr &= NAU8825_ADC_SYNC_DOWN_MASK; 1339 if (osr >= ARRAY_SIZE(osr_adc_sel)) 1340 return NULL; 1341 return &osr_adc_sel[osr]; 1342 } 1343 } 1344 1345 static int nau8825_dai_startup(struct snd_pcm_substream *substream, 1346 struct snd_soc_dai *dai) 1347 { 1348 struct snd_soc_component *component = dai->component; 1349 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1350 const struct nau8825_osr_attr *osr; 1351 1352 osr = nau8825_get_osr(nau8825, substream->stream); 1353 if (!osr || !osr->osr) 1354 return -EINVAL; 1355 1356 return snd_pcm_hw_constraint_minmax(substream->runtime, 1357 SNDRV_PCM_HW_PARAM_RATE, 1358 0, CLK_DA_AD_MAX / osr->osr); 1359 } 1360 1361 static int nau8825_hw_params(struct snd_pcm_substream *substream, 1362 struct snd_pcm_hw_params *params, 1363 struct snd_soc_dai *dai) 1364 { 1365 struct snd_soc_component *component = dai->component; 1366 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1367 unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div; 1368 const struct nau8825_osr_attr *osr; 1369 int err = -EINVAL; 1370 1371 nau8825_sema_acquire(nau8825, 3 * HZ); 1372 1373 /* CLK_DAC or CLK_ADC = OSR * FS 1374 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1375 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1376 * values must be selected such that the maximum frequency is less 1377 * than 6.144 MHz. 1378 */ 1379 osr = nau8825_get_osr(nau8825, substream->stream); 1380 if (!osr || !osr->osr) 1381 goto error; 1382 if (params_rate(params) * osr->osr > CLK_DA_AD_MAX) 1383 goto error; 1384 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1385 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1386 NAU8825_CLK_DAC_SRC_MASK, 1387 osr->clk_src << NAU8825_CLK_DAC_SRC_SFT); 1388 else 1389 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 1390 NAU8825_CLK_ADC_SRC_MASK, 1391 osr->clk_src << NAU8825_CLK_ADC_SRC_SFT); 1392 1393 /* make BCLK and LRC divde configuration if the codec as master. */ 1394 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val); 1395 if (ctrl_val & NAU8825_I2S_MS_MASTER) { 1396 /* get the bclk and fs ratio */ 1397 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params); 1398 if (bclk_fs <= 32) 1399 bclk_div = 2; 1400 else if (bclk_fs <= 64) 1401 bclk_div = 1; 1402 else if (bclk_fs <= 128) 1403 bclk_div = 0; 1404 else 1405 goto error; 1406 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1407 NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK, 1408 ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div); 1409 } 1410 1411 switch (params_width(params)) { 1412 case 16: 1413 val_len |= NAU8825_I2S_DL_16; 1414 break; 1415 case 20: 1416 val_len |= NAU8825_I2S_DL_20; 1417 break; 1418 case 24: 1419 val_len |= NAU8825_I2S_DL_24; 1420 break; 1421 case 32: 1422 val_len |= NAU8825_I2S_DL_32; 1423 break; 1424 default: 1425 goto error; 1426 } 1427 1428 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1429 NAU8825_I2S_DL_MASK, val_len); 1430 err = 0; 1431 1432 error: 1433 /* Release the semaphore. */ 1434 nau8825_sema_release(nau8825); 1435 1436 return err; 1437 } 1438 1439 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1440 { 1441 struct snd_soc_component *component = codec_dai->component; 1442 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1443 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1444 1445 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1446 case SND_SOC_DAIFMT_CBM_CFM: 1447 ctrl2_val |= NAU8825_I2S_MS_MASTER; 1448 break; 1449 case SND_SOC_DAIFMT_CBS_CFS: 1450 break; 1451 default: 1452 return -EINVAL; 1453 } 1454 1455 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1456 case SND_SOC_DAIFMT_NB_NF: 1457 break; 1458 case SND_SOC_DAIFMT_IB_NF: 1459 ctrl1_val |= NAU8825_I2S_BP_INV; 1460 break; 1461 default: 1462 return -EINVAL; 1463 } 1464 1465 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1466 case SND_SOC_DAIFMT_I2S: 1467 ctrl1_val |= NAU8825_I2S_DF_I2S; 1468 break; 1469 case SND_SOC_DAIFMT_LEFT_J: 1470 ctrl1_val |= NAU8825_I2S_DF_LEFT; 1471 break; 1472 case SND_SOC_DAIFMT_RIGHT_J: 1473 ctrl1_val |= NAU8825_I2S_DF_RIGTH; 1474 break; 1475 case SND_SOC_DAIFMT_DSP_A: 1476 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1477 break; 1478 case SND_SOC_DAIFMT_DSP_B: 1479 ctrl1_val |= NAU8825_I2S_DF_PCM_AB; 1480 ctrl1_val |= NAU8825_I2S_PCMB_EN; 1481 break; 1482 default: 1483 return -EINVAL; 1484 } 1485 1486 nau8825_sema_acquire(nau8825, 3 * HZ); 1487 1488 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, 1489 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK | 1490 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK, 1491 ctrl1_val); 1492 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1493 NAU8825_I2S_MS_MASK, ctrl2_val); 1494 1495 /* Release the semaphore. */ 1496 nau8825_sema_release(nau8825); 1497 1498 return 0; 1499 } 1500 1501 /** 1502 * nau8825_set_tdm_slot - configure DAI TDM. 1503 * @dai: DAI 1504 * @tx_mask: bitmask representing active TX slots. 1505 * @rx_mask: bitmask representing active RX slots. 1506 * @slots: Number of slots in use. 1507 * @slot_width: Width in bits for each slot. 1508 * 1509 * Configures a DAI for TDM operation. Support TDM 4/8 slots. 1510 * The limitation is DAC and ADC need shift 4 slots at 8 slots mode. 1511 */ 1512 static int nau8825_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1513 unsigned int rx_mask, int slots, int slot_width) 1514 { 1515 struct snd_soc_component *component = dai->component; 1516 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1517 unsigned int ctrl_val = 0, ctrl_offset = 0, value = 0, dac_s, adc_s; 1518 1519 if (slots != 4 && slots != 8) { 1520 dev_err(nau8825->dev, "Only support 4 or 8 slots!\n"); 1521 return -EINVAL; 1522 } 1523 1524 /* The driver is limited to 1-channel for ADC, and 2-channel for DAC on TDM mode */ 1525 if (hweight_long((unsigned long) tx_mask) != 1 || 1526 hweight_long((unsigned long) rx_mask) != 2) { 1527 dev_err(nau8825->dev, 1528 "The limitation is 1-channel for ADC, and 2-channel for DAC on TDM mode.\n"); 1529 return -EINVAL; 1530 } 1531 1532 if (((tx_mask & 0xf) && (tx_mask & 0xf0)) || 1533 ((rx_mask & 0xf) && (rx_mask & 0xf0)) || 1534 ((tx_mask & 0xf) && (rx_mask & 0xf0)) || 1535 ((rx_mask & 0xf) && (tx_mask & 0xf0))) { 1536 dev_err(nau8825->dev, 1537 "Slot assignment of DAC and ADC need to set same interval.\n"); 1538 return -EINVAL; 1539 } 1540 1541 /* The offset of fixed 4 slots for 8 slots support */ 1542 if (rx_mask & 0xf0) { 1543 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, 1544 NAU8825_I2S_PCM_TS_EN_MASK, NAU8825_I2S_PCM_TS_EN); 1545 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, &value); 1546 ctrl_val |= NAU8825_TDM_OFFSET_EN; 1547 ctrl_offset = 4 * slot_width; 1548 if (!(value & NAU8825_I2S_PCMB_MASK)) 1549 ctrl_offset += 1; 1550 dac_s = (rx_mask & 0xf0) >> 4; 1551 adc_s = fls((tx_mask & 0xf0) >> 4); 1552 } else { 1553 dac_s = rx_mask & 0xf; 1554 adc_s = fls(tx_mask & 0xf); 1555 } 1556 1557 ctrl_val |= NAU8825_TDM_MODE; 1558 1559 switch (dac_s) { 1560 case 0x3: 1561 ctrl_val |= 1 << NAU8825_TDM_DACR_RX_SFT; 1562 break; 1563 case 0x5: 1564 ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT; 1565 break; 1566 case 0x6: 1567 ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT; 1568 ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT; 1569 break; 1570 case 0x9: 1571 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; 1572 break; 1573 case 0xa: 1574 ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT; 1575 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; 1576 break; 1577 case 0xc: 1578 ctrl_val |= 2 << NAU8825_TDM_DACL_RX_SFT; 1579 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; 1580 break; 1581 default: 1582 return -EINVAL; 1583 } 1584 1585 ctrl_val |= adc_s - 1; 1586 1587 regmap_update_bits(nau8825->regmap, NAU8825_REG_TDM_CTRL, 1588 NAU8825_TDM_MODE | NAU8825_TDM_OFFSET_EN | 1589 NAU8825_TDM_DACL_RX_MASK | NAU8825_TDM_DACR_RX_MASK | 1590 NAU8825_TDM_TX_MASK, ctrl_val); 1591 regmap_update_bits(nau8825->regmap, NAU8825_REG_LEFT_TIME_SLOT, 1592 NAU8825_TSLOT_L0_MASK, ctrl_offset); 1593 1594 return 0; 1595 } 1596 1597 static const struct snd_soc_dai_ops nau8825_dai_ops = { 1598 .startup = nau8825_dai_startup, 1599 .hw_params = nau8825_hw_params, 1600 .set_fmt = nau8825_set_dai_fmt, 1601 .set_tdm_slot = nau8825_set_tdm_slot, 1602 }; 1603 1604 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000 1605 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1606 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1607 1608 static struct snd_soc_dai_driver nau8825_dai = { 1609 .name = "nau8825-hifi", 1610 .playback = { 1611 .stream_name = "Playback", 1612 .channels_min = 1, 1613 .channels_max = 2, 1614 .rates = NAU8825_RATES, 1615 .formats = NAU8825_FORMATS, 1616 }, 1617 .capture = { 1618 .stream_name = "Capture", 1619 .channels_min = 1, 1620 .channels_max = 2, /* Only 1 channel of data */ 1621 .rates = NAU8825_RATES, 1622 .formats = NAU8825_FORMATS, 1623 }, 1624 .ops = &nau8825_dai_ops, 1625 }; 1626 1627 /** 1628 * nau8825_enable_jack_detect - Specify a jack for event reporting 1629 * 1630 * @component: component to register the jack with 1631 * @jack: jack to use to report headset and button events on 1632 * 1633 * After this function has been called the headset insert/remove and button 1634 * events will be routed to the given jack. Jack can be null to stop 1635 * reporting. 1636 */ 1637 int nau8825_enable_jack_detect(struct snd_soc_component *component, 1638 struct snd_soc_jack *jack) 1639 { 1640 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 1641 struct regmap *regmap = nau8825->regmap; 1642 1643 nau8825->jack = jack; 1644 1645 if (!nau8825->jack) { 1646 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1647 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | 1648 NAU8825_SPKR_DWN1L, 0); 1649 return 0; 1650 } 1651 /* Ground HP Outputs[1:0], needed for headset auto detection 1652 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6] 1653 */ 1654 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1655 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 1656 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1657 1658 return 0; 1659 } 1660 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect); 1661 1662 1663 static bool nau8825_is_jack_inserted(struct regmap *regmap) 1664 { 1665 bool active_high, is_high; 1666 int status, jkdet; 1667 1668 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet); 1669 active_high = jkdet & NAU8825_JACK_POLARITY; 1670 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status); 1671 is_high = status & NAU8825_GPIO2JD1; 1672 /* return jack connection status according to jack insertion logic 1673 * active high or active low. 1674 */ 1675 return active_high == is_high; 1676 } 1677 1678 static void nau8825_restart_jack_detection(struct regmap *regmap) 1679 { 1680 /* this will restart the entire jack detection process including MIC/GND 1681 * switching and create interrupts. We have to go from 0 to 1 and back 1682 * to 0 to restart. 1683 */ 1684 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1685 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART); 1686 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1687 NAU8825_JACK_DET_RESTART, 0); 1688 } 1689 1690 static void nau8825_int_status_clear_all(struct regmap *regmap) 1691 { 1692 int active_irq, clear_irq, i; 1693 1694 /* Reset the intrruption status from rightmost bit if the corres- 1695 * ponding irq event occurs. 1696 */ 1697 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq); 1698 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) { 1699 clear_irq = (0x1 << i); 1700 if (active_irq & clear_irq) 1701 regmap_write(regmap, 1702 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 1703 } 1704 } 1705 1706 static void nau8825_eject_jack(struct nau8825 *nau8825) 1707 { 1708 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1709 struct regmap *regmap = nau8825->regmap; 1710 1711 /* Force to cancel the cross talk detection process */ 1712 nau8825_xtalk_cancel(nau8825); 1713 1714 snd_soc_dapm_disable_pin(dapm, "SAR"); 1715 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1716 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 1717 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1718 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 1719 /* ground HPL/HPR, MICGRND1/2 */ 1720 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf); 1721 1722 snd_soc_dapm_sync(dapm); 1723 1724 /* Clear all interruption status */ 1725 nau8825_int_status_clear_all(regmap); 1726 1727 /* Enable the insertion interruption, disable the ejection inter- 1728 * ruption, and then bypass de-bounce circuit. 1729 */ 1730 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 1731 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS, 1732 NAU8825_IRQ_EJECT_DIS); 1733 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1734 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1735 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN, 1736 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | 1737 NAU8825_IRQ_HEADSET_COMPLETE_EN); 1738 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1739 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 1740 1741 /* Disable ADC needed for interruptions at audo mode */ 1742 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1743 NAU8825_ENABLE_ADC, 0); 1744 1745 /* Close clock for jack type detection at manual mode */ 1746 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 1747 } 1748 1749 /* Enable audo mode interruptions with internal clock. */ 1750 static void nau8825_setup_auto_irq(struct nau8825 *nau8825) 1751 { 1752 struct regmap *regmap = nau8825->regmap; 1753 1754 /* Enable HSD function */ 1755 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1756 NAU8825_HSD_AUTO_MODE, NAU8825_HSD_AUTO_MODE); 1757 1758 /* Enable headset jack type detection complete interruption and 1759 * jack ejection interruption. 1760 */ 1761 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 1762 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0); 1763 1764 /* Enable internal VCO needed for interruptions */ 1765 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); 1766 /* Raise up the internal clock for jack detection */ 1767 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 1768 NAU8825_CLK_MCLK_SRC_MASK, 0); 1769 1770 /* Enable ADC needed for interruptions */ 1771 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, 1772 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); 1773 1774 /* Chip needs one FSCLK cycle in order to generate interruptions, 1775 * as we cannot guarantee one will be provided by the system. Turning 1776 * master mode on then off enables us to generate that FSCLK cycle 1777 * with a minimum of contention on the clock bus. 1778 */ 1779 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1780 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER); 1781 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, 1782 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE); 1783 1784 /* Not bypass de-bounce circuit */ 1785 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 1786 NAU8825_JACK_DET_DB_BYPASS, 0); 1787 1788 /* Unmask all interruptions */ 1789 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0); 1790 1791 /* Restart the jack detection process at auto mode */ 1792 nau8825_restart_jack_detection(regmap); 1793 } 1794 1795 static int nau8825_button_decode(int value) 1796 { 1797 int buttons = 0; 1798 1799 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */ 1800 if (value & BIT(0)) 1801 buttons |= SND_JACK_BTN_0; 1802 if (value & BIT(1)) 1803 buttons |= SND_JACK_BTN_1; 1804 if (value & BIT(2)) 1805 buttons |= SND_JACK_BTN_2; 1806 if (value & BIT(3)) 1807 buttons |= SND_JACK_BTN_3; 1808 if (value & BIT(4)) 1809 buttons |= SND_JACK_BTN_4; 1810 if (value & BIT(5)) 1811 buttons |= SND_JACK_BTN_5; 1812 1813 return buttons; 1814 } 1815 1816 static int nau8825_high_imped_detection(struct nau8825 *nau8825) 1817 { 1818 struct regmap *regmap = nau8825->regmap; 1819 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1820 unsigned int adc_mg1, adc_mg2; 1821 1822 /* Initial phase */ 1823 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1824 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1825 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2); 1826 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1, 1827 NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND); 1828 regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0x6); 1829 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1830 NAU8825_MICBIAS_LOWNOISE_MASK | NAU8825_MICBIAS_VOLTAGE_MASK, 1831 NAU8825_MICBIAS_LOWNOISE_EN); 1832 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1833 NAU8825_SAR_INPUT_MASK | NAU8825_SAR_TRACKING_GAIN_MASK | 1834 NAU8825_SAR_HV_SEL_MASK | NAU8825_SAR_RES_SEL_MASK | 1835 NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK, 1836 NAU8825_SAR_HV_SEL_VDDMIC | NAU8825_SAR_RES_SEL_70K); 1837 1838 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1839 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1840 snd_soc_dapm_sync(dapm); 1841 1842 /* Configure settings for first reading of SARADC */ 1843 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1844 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1845 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND2); 1846 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1847 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1848 NAU8825_MICBIAS_JKR2); 1849 regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg1); 1850 1851 /* Configure settings for second reading of SARADC */ 1852 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1853 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 1854 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1855 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1856 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | 1857 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1858 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1859 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1860 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1); 1861 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1862 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1863 NAU8825_MICBIAS_JKSLV); 1864 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1865 NAU8825_SAR_INPUT_MASK, NAU8825_SAR_INPUT_JKSLV); 1866 regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg2); 1867 1868 /* Disable phase */ 1869 snd_soc_dapm_disable_pin(dapm, "SAR"); 1870 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1871 snd_soc_dapm_sync(dapm); 1872 1873 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1874 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_LOWNOISE_MASK | 1875 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); 1876 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1877 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | 1878 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | 1879 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); 1880 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1, 1881 NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND); 1882 regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0); 1883 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1884 NAU8825_SAR_TRACKING_GAIN_MASK | NAU8825_SAR_HV_SEL_MASK, 1885 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); 1886 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1887 NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK, 1888 (nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT) | 1889 (nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT)); 1890 dev_dbg(nau8825->dev, "adc_mg1:%x, adc_mg2:%x\n", adc_mg1, adc_mg2); 1891 1892 /* Confirmation phase */ 1893 if (adc_mg1 > adc_mg2) { 1894 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); 1895 1896 /* Unground MICGND1 */ 1897 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1898 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2, 1899 NAU8825_SPKR_ENGND2); 1900 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ 1901 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1902 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1903 NAU8825_MICBIAS_JKR2); 1904 /* Attach SARADC to MICGND1 */ 1905 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1906 NAU8825_SAR_INPUT_MASK, 1907 NAU8825_SAR_INPUT_JKR2); 1908 } else if (adc_mg1 < adc_mg2) { 1909 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); 1910 1911 /* Unground MICGND2 */ 1912 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 1913 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2, 1914 NAU8825_SPKR_ENGND1); 1915 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ 1916 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1917 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1918 NAU8825_MICBIAS_JKSLV); 1919 /* Attach SARADC to MICGND2 */ 1920 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1921 NAU8825_SAR_INPUT_MASK, 1922 NAU8825_SAR_INPUT_JKSLV); 1923 } else { 1924 dev_err(nau8825->dev, "Jack broken.\n"); 1925 return -EINVAL; 1926 } 1927 1928 return 0; 1929 } 1930 1931 static int nau8825_jack_insert(struct nau8825 *nau8825) 1932 { 1933 struct regmap *regmap = nau8825->regmap; 1934 struct snd_soc_dapm_context *dapm = nau8825->dapm; 1935 int jack_status_reg, mic_detected; 1936 int type = 0; 1937 1938 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg); 1939 mic_detected = (jack_status_reg >> 10) & 3; 1940 /* The JKSLV and JKR2 all detected in high impedance headset */ 1941 if (mic_detected == 0x3) 1942 nau8825->high_imped = true; 1943 else 1944 nau8825->high_imped = false; 1945 1946 switch (mic_detected) { 1947 case 0: 1948 /* no mic */ 1949 type = SND_JACK_HEADPHONE; 1950 break; 1951 case 1: 1952 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); 1953 type = SND_JACK_HEADSET; 1954 1955 /* Unground MICGND1 */ 1956 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1957 1 << 2); 1958 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ 1959 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1960 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1961 NAU8825_MICBIAS_JKR2); 1962 /* Attach SARADC to MICGND1 */ 1963 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1964 NAU8825_SAR_INPUT_MASK, 1965 NAU8825_SAR_INPUT_JKR2); 1966 1967 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1968 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1969 snd_soc_dapm_sync(dapm); 1970 break; 1971 case 2: 1972 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); 1973 type = SND_JACK_HEADSET; 1974 1975 /* Unground MICGND2 */ 1976 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, 1977 2 << 2); 1978 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ 1979 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 1980 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 1981 NAU8825_MICBIAS_JKSLV); 1982 /* Attach SARADC to MICGND2 */ 1983 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 1984 NAU8825_SAR_INPUT_MASK, 1985 NAU8825_SAR_INPUT_JKSLV); 1986 1987 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1988 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1989 snd_soc_dapm_sync(dapm); 1990 break; 1991 case 3: 1992 /* Detection failure case */ 1993 dev_warn(nau8825->dev, 1994 "Detection failure. Try the manually mechanism for jack type checking.\n"); 1995 if (!nau8825_high_imped_detection(nau8825)) { 1996 type = SND_JACK_HEADSET; 1997 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); 1998 snd_soc_dapm_force_enable_pin(dapm, "SAR"); 1999 snd_soc_dapm_sync(dapm); 2000 } else 2001 type = SND_JACK_HEADPHONE; 2002 break; 2003 } 2004 2005 /* Update to the default divider of internal clock for power saving */ 2006 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2007 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 2008 2009 /* Disable HSD function */ 2010 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, NAU8825_HSD_AUTO_MODE, 0); 2011 2012 /* Leaving HPOL/R grounded after jack insert by default. They will be 2013 * ungrounded as part of the widget power up sequence at the beginning 2014 * of playback to reduce pop. 2015 */ 2016 return type; 2017 } 2018 2019 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 2020 SND_JACK_BTN_2 | SND_JACK_BTN_3) 2021 2022 static irqreturn_t nau8825_interrupt(int irq, void *data) 2023 { 2024 struct nau8825 *nau8825 = (struct nau8825 *)data; 2025 struct regmap *regmap = nau8825->regmap; 2026 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 2027 2028 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) { 2029 dev_err(nau8825->dev, "failed to read irq status\n"); 2030 return IRQ_NONE; 2031 } 2032 2033 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) == 2034 NAU8825_JACK_EJECTION_DETECTED) { 2035 2036 nau8825_eject_jack(nau8825); 2037 event_mask |= SND_JACK_HEADSET; 2038 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK; 2039 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) { 2040 int key_status; 2041 2042 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, 2043 &key_status); 2044 2045 /* upper 8 bits of the register are for short pressed keys, 2046 * lower 8 bits - for long pressed buttons 2047 */ 2048 nau8825->button_pressed = nau8825_button_decode( 2049 key_status >> 8); 2050 2051 event |= nau8825->button_pressed; 2052 event_mask |= NAU8825_BUTTONS; 2053 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ; 2054 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) { 2055 event_mask = NAU8825_BUTTONS; 2056 clear_irq = NAU8825_KEY_RELEASE_IRQ; 2057 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) { 2058 if (nau8825_is_jack_inserted(regmap)) { 2059 event |= nau8825_jack_insert(nau8825); 2060 if (nau8825->xtalk_enable && !nau8825->high_imped) { 2061 /* Apply the cross talk suppression in the 2062 * headset without high impedance. 2063 */ 2064 if (!nau8825->xtalk_protect) { 2065 /* Raise protection for cross talk de- 2066 * tection if no protection before. 2067 * The driver has to cancel the pro- 2068 * cess and restore changes if process 2069 * is ongoing when ejection. 2070 */ 2071 int ret; 2072 nau8825->xtalk_protect = true; 2073 ret = nau8825_sema_acquire(nau8825, 0); 2074 if (ret) 2075 nau8825->xtalk_protect = false; 2076 } 2077 /* Startup cross talk detection process */ 2078 if (nau8825->xtalk_protect) { 2079 nau8825->xtalk_state = 2080 NAU8825_XTALK_PREPARE; 2081 schedule_work(&nau8825->xtalk_work); 2082 } 2083 } else { 2084 /* The cross talk suppression shouldn't apply 2085 * in the headset with high impedance. Thus, 2086 * relieve the protection raised before. 2087 */ 2088 if (nau8825->xtalk_protect) { 2089 nau8825_sema_release(nau8825); 2090 nau8825->xtalk_protect = false; 2091 } 2092 } 2093 } else { 2094 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n"); 2095 nau8825_eject_jack(nau8825); 2096 } 2097 2098 event_mask |= SND_JACK_HEADSET; 2099 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ; 2100 /* Record the interruption report event for driver to report 2101 * the event later. The jack report will delay until cross 2102 * talk detection process is done. 2103 */ 2104 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) { 2105 nau8825->xtalk_event = event; 2106 nau8825->xtalk_event_mask = event_mask; 2107 } 2108 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) { 2109 /* crosstalk detection enable and process on going */ 2110 if (nau8825->xtalk_enable && nau8825->xtalk_protect) 2111 schedule_work(&nau8825->xtalk_work); 2112 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ; 2113 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) == 2114 NAU8825_JACK_INSERTION_DETECTED) { 2115 /* One more step to check GPIO status directly. Thus, the 2116 * driver can confirm the real insertion interruption because 2117 * the intrruption at manual mode has bypassed debounce 2118 * circuit which can get rid of unstable status. 2119 */ 2120 if (nau8825_is_jack_inserted(regmap)) { 2121 /* Turn off insertion interruption at manual mode */ 2122 regmap_update_bits(regmap, 2123 NAU8825_REG_INTERRUPT_DIS_CTRL, 2124 NAU8825_IRQ_INSERT_DIS, 2125 NAU8825_IRQ_INSERT_DIS); 2126 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2127 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN); 2128 /* Enable interruption for jack type detection at audo 2129 * mode which can detect microphone and jack type. 2130 */ 2131 nau8825_setup_auto_irq(nau8825); 2132 } 2133 } 2134 2135 if (!clear_irq) 2136 clear_irq = active_irq; 2137 /* clears the rightmost interruption */ 2138 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); 2139 2140 /* Delay jack report until cross talk detection is done. It can avoid 2141 * application to do playback preparation when cross talk detection 2142 * process is still working. Otherwise, the resource like clock and 2143 * power will be issued by them at the same time and conflict happens. 2144 */ 2145 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE) 2146 snd_soc_jack_report(nau8825->jack, event, event_mask); 2147 2148 return IRQ_HANDLED; 2149 } 2150 2151 static void nau8825_setup_buttons(struct nau8825 *nau8825) 2152 { 2153 struct regmap *regmap = nau8825->regmap; 2154 2155 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 2156 NAU8825_SAR_TRACKING_GAIN_MASK, 2157 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); 2158 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 2159 NAU8825_SAR_COMPARE_TIME_MASK, 2160 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT); 2161 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, 2162 NAU8825_SAR_SAMPLING_TIME_MASK, 2163 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT); 2164 2165 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 2166 NAU8825_KEYDET_LEVELS_NR_MASK, 2167 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT); 2168 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 2169 NAU8825_KEYDET_HYSTERESIS_MASK, 2170 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT); 2171 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, 2172 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK, 2173 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT); 2174 2175 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1, 2176 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]); 2177 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2, 2178 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]); 2179 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3, 2180 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]); 2181 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4, 2182 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]); 2183 2184 /* Enable short press and release interruptions */ 2185 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2186 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN, 2187 0); 2188 } 2189 2190 static void nau8825_init_regs(struct nau8825 *nau8825) 2191 { 2192 struct regmap *regmap = nau8825->regmap; 2193 2194 /* Latch IIC LSB value */ 2195 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001); 2196 /* Enable Bias/Vmid */ 2197 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 2198 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID); 2199 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, 2200 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN); 2201 2202 /* VMID Tieoff */ 2203 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ, 2204 NAU8825_BIAS_VMID_SEL_MASK, 2205 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT); 2206 /* Disable Boost Driver, Automatic Short circuit protection enable */ 2207 regmap_update_bits(regmap, NAU8825_REG_BOOST, 2208 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 2209 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN, 2210 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | 2211 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN); 2212 2213 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 2214 NAU8825_JKDET_OUTPUT_EN, 2215 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN); 2216 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 2217 NAU8825_JKDET_PULL_EN, 2218 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN); 2219 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, 2220 NAU8825_JKDET_PULL_UP, 2221 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0); 2222 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2223 NAU8825_JACK_POLARITY, 2224 /* jkdet_polarity - 1 is for active-low */ 2225 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY); 2226 2227 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2228 NAU8825_JACK_INSERT_DEBOUNCE_MASK, 2229 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT); 2230 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2231 NAU8825_JACK_EJECT_DEBOUNCE_MASK, 2232 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT); 2233 2234 /* Pull up IRQ pin */ 2235 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2236 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN, 2237 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN); 2238 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 2239 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff); 2240 2241 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, 2242 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); 2243 2244 if (nau8825->sar_threshold_num) 2245 nau8825_setup_buttons(nau8825); 2246 2247 /* Default oversampling/decimations settings are unusable 2248 * (audible hiss). Set it to something better. 2249 */ 2250 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE, 2251 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN, 2252 NAU8825_ADC_SYNC_DOWN_64); 2253 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 2254 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64); 2255 /* Disable DACR/L power */ 2256 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) 2257 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 2258 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 2259 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); 2260 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 2261 * signal to avoid any glitches due to power up transients in both 2262 * the analog and digital DAC circuit. 2263 */ 2264 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, 2265 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); 2266 /* CICCLP off */ 2267 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, 2268 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF); 2269 2270 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 2271 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2, 2272 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 2273 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB, 2274 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | 2275 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB); 2276 /* Class G timer 64ms */ 2277 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL, 2278 NAU8825_CLASSG_TIMER_MASK, 2279 0x20 << NAU8825_CLASSG_TIMER_SFT); 2280 /* DAC clock delay 2ns, VREF */ 2281 regmap_update_bits(regmap, NAU8825_REG_RDAC, 2282 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK, 2283 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) | 2284 (0x3 << NAU8825_RDAC_VREF_SFT)); 2285 /* Config L/R channel */ 2286 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, 2287 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); 2288 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, 2289 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); 2290 /* Disable short Frame Sync detection logic */ 2291 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT, 2292 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET); 2293 /* ADCDAT IO drive strength control */ 2294 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, 2295 NAU8825_ADCOUT_DS_MASK, 2296 nau8825->adcout_ds << NAU8825_ADCOUT_DS_SFT); 2297 } 2298 2299 static const struct regmap_config nau8825_regmap_config = { 2300 .val_bits = NAU8825_REG_DATA_LEN, 2301 .reg_bits = NAU8825_REG_ADDR_LEN, 2302 2303 .max_register = NAU8825_REG_MAX, 2304 .readable_reg = nau8825_readable_reg, 2305 .writeable_reg = nau8825_writeable_reg, 2306 .volatile_reg = nau8825_volatile_reg, 2307 2308 .cache_type = REGCACHE_RBTREE, 2309 .reg_defaults = nau8825_reg_defaults, 2310 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults), 2311 }; 2312 2313 static int nau8825_component_probe(struct snd_soc_component *component) 2314 { 2315 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2316 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2317 2318 nau8825->dapm = dapm; 2319 2320 return 0; 2321 } 2322 2323 static void nau8825_component_remove(struct snd_soc_component *component) 2324 { 2325 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2326 2327 /* Cancel and reset cross tak suppresstion detection funciton */ 2328 nau8825_xtalk_cancel(nau8825); 2329 } 2330 2331 /** 2332 * nau8825_calc_fll_param - Calculate FLL parameters. 2333 * @fll_in: external clock provided to codec. 2334 * @fs: sampling rate. 2335 * @fll_param: Pointer to structure of FLL parameters. 2336 * 2337 * Calculate FLL parameters to configure codec. 2338 * 2339 * Returns 0 for success or negative error code. 2340 */ 2341 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs, 2342 struct nau8825_fll *fll_param) 2343 { 2344 u64 fvco, fvco_max; 2345 unsigned int fref, i, fvco_sel; 2346 2347 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 2348 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 2349 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK 2350 */ 2351 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 2352 fref = fll_in / fll_pre_scalar[i].param; 2353 if (fref <= NAU_FREF_MAX) 2354 break; 2355 } 2356 if (i == ARRAY_SIZE(fll_pre_scalar)) 2357 return -EINVAL; 2358 fll_param->clk_ref_div = fll_pre_scalar[i].val; 2359 2360 /* Choose the FLL ratio based on FREF */ 2361 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 2362 if (fref >= fll_ratio[i].param) 2363 break; 2364 } 2365 if (i == ARRAY_SIZE(fll_ratio)) 2366 return -EINVAL; 2367 fll_param->ratio = fll_ratio[i].val; 2368 2369 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 2370 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 2371 * guaranteed across the full range of operation. 2372 * FDCO = freq_out * 2 * mclk_src_scaling 2373 */ 2374 fvco_max = 0; 2375 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 2376 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 2377 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 2378 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 2379 fvco_max < fvco) { 2380 fvco_max = fvco; 2381 fvco_sel = i; 2382 } 2383 } 2384 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 2385 return -EINVAL; 2386 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 2387 2388 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 2389 * input based on FDCO, FREF and FLL ratio. 2390 */ 2391 fvco = div_u64(fvco_max << fll_param->fll_frac_num, fref * fll_param->ratio); 2392 fll_param->fll_int = (fvco >> fll_param->fll_frac_num) & 0x3FF; 2393 if (fll_param->fll_frac_num == 16) 2394 fll_param->fll_frac = fvco & 0xFFFF; 2395 else 2396 fll_param->fll_frac = fvco & 0xFFFFFF; 2397 return 0; 2398 } 2399 2400 static void nau8825_fll_apply(struct nau8825 *nau8825, 2401 struct nau8825_fll *fll_param) 2402 { 2403 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2404 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK, 2405 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src); 2406 /* Make DSP operate at high speed for better performance. */ 2407 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, 2408 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK, 2409 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT)); 2410 /* FLL 16/24 bit fractional input */ 2411 if (fll_param->fll_frac_num == 16) 2412 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 2413 fll_param->fll_frac); 2414 else { 2415 regmap_write(nau8825->regmap, NAU8825_REG_FLL2_LOWER, 2416 fll_param->fll_frac & 0xffff); 2417 regmap_write(nau8825->regmap, NAU8825_REG_FLL2_UPPER, 2418 (fll_param->fll_frac >> 16) & 0xff); 2419 } 2420 /* FLL 10-bit integer input */ 2421 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3, 2422 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int); 2423 /* FLL pre-scaler */ 2424 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4, 2425 NAU8825_FLL_REF_DIV_MASK, 2426 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT); 2427 /* select divided VCO input */ 2428 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2429 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF); 2430 /* Disable free-running mode */ 2431 regmap_update_bits(nau8825->regmap, 2432 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); 2433 if (fll_param->fll_frac) { 2434 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 2435 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2436 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2437 NAU8825_FLL_FTR_SW_MASK, 2438 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2439 NAU8825_FLL_FTR_SW_FILTER); 2440 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2441 NAU8825_SDM_EN | NAU8825_CUTOFF500, 2442 NAU8825_SDM_EN | NAU8825_CUTOFF500); 2443 } else { 2444 /* disable FLL loop filter and cutoff frequency */ 2445 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, 2446 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | 2447 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU); 2448 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, 2449 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0); 2450 } 2451 } 2452 2453 /* freq_out must be 256*Fs in order to achieve the best performance */ 2454 static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source, 2455 unsigned int freq_in, unsigned int freq_out) 2456 { 2457 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2458 struct nau8825_fll fll_param; 2459 int ret, fs; 2460 2461 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) 2462 fll_param.fll_frac_num = 16; 2463 else 2464 fll_param.fll_frac_num = 24; 2465 2466 fs = freq_out / 256; 2467 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param); 2468 if (ret < 0) { 2469 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2470 return ret; 2471 } 2472 dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 2473 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 2474 fll_param.fll_int, fll_param.clk_ref_div); 2475 2476 nau8825_fll_apply(nau8825, &fll_param); 2477 mdelay(2); 2478 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, 2479 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2480 return 0; 2481 } 2482 2483 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq) 2484 { 2485 int ret; 2486 2487 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk"); 2488 if (IS_ERR(nau8825->mclk)) { 2489 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2490 return 0; 2491 } 2492 2493 if (!nau8825->mclk_freq) { 2494 ret = clk_prepare_enable(nau8825->mclk); 2495 if (ret) { 2496 dev_err(nau8825->dev, "Unable to prepare codec mclk\n"); 2497 return ret; 2498 } 2499 } 2500 2501 if (nau8825->mclk_freq != freq) { 2502 freq = clk_round_rate(nau8825->mclk, freq); 2503 ret = clk_set_rate(nau8825->mclk, freq); 2504 if (ret) { 2505 dev_err(nau8825->dev, "Unable to set mclk rate\n"); 2506 return ret; 2507 } 2508 nau8825->mclk_freq = freq; 2509 } 2510 2511 return 0; 2512 } 2513 2514 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap) 2515 { 2516 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2517 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); 2518 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2519 NAU8825_DCO_EN, 0); 2520 /* Make DSP operate as default setting for power saving. */ 2521 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2522 NAU8825_ICTRL_LATCH_MASK, 0); 2523 } 2524 2525 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, 2526 unsigned int freq) 2527 { 2528 struct regmap *regmap = nau8825->regmap; 2529 int ret; 2530 2531 switch (clk_id) { 2532 case NAU8825_CLK_DIS: 2533 /* Clock provided externally and disable internal VCO clock */ 2534 nau8825_configure_mclk_as_sysclk(regmap); 2535 if (nau8825->mclk_freq) { 2536 clk_disable_unprepare(nau8825->mclk); 2537 nau8825->mclk_freq = 0; 2538 } 2539 2540 break; 2541 case NAU8825_CLK_MCLK: 2542 /* Acquire the semaphore to synchronize the playback and 2543 * interrupt handler. In order to avoid the playback inter- 2544 * fered by cross talk process, the driver make the playback 2545 * preparation halted until cross talk process finish. 2546 */ 2547 nau8825_sema_acquire(nau8825, 3 * HZ); 2548 nau8825_configure_mclk_as_sysclk(regmap); 2549 /* MCLK not changed by clock tree */ 2550 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2551 NAU8825_CLK_MCLK_SRC_MASK, 0); 2552 /* Release the semaphore. */ 2553 nau8825_sema_release(nau8825); 2554 2555 ret = nau8825_mclk_prepare(nau8825, freq); 2556 if (ret) 2557 return ret; 2558 2559 break; 2560 case NAU8825_CLK_INTERNAL: 2561 if (nau8825_is_jack_inserted(nau8825->regmap)) { 2562 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2563 NAU8825_DCO_EN, NAU8825_DCO_EN); 2564 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2565 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); 2566 /* Decrease the VCO frequency and make DSP operate 2567 * as default setting for power saving. 2568 */ 2569 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, 2570 NAU8825_CLK_MCLK_SRC_MASK, 0xf); 2571 regmap_update_bits(regmap, NAU8825_REG_FLL1, 2572 NAU8825_ICTRL_LATCH_MASK | 2573 NAU8825_FLL_RATIO_MASK, 0x10); 2574 regmap_update_bits(regmap, NAU8825_REG_FLL6, 2575 NAU8825_SDM_EN, NAU8825_SDM_EN); 2576 } else { 2577 /* The clock turns off intentionally for power saving 2578 * when no headset connected. 2579 */ 2580 nau8825_configure_mclk_as_sysclk(regmap); 2581 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n"); 2582 } 2583 if (nau8825->mclk_freq) { 2584 clk_disable_unprepare(nau8825->mclk); 2585 nau8825->mclk_freq = 0; 2586 } 2587 2588 break; 2589 case NAU8825_CLK_FLL_MCLK: 2590 /* Acquire the semaphore to synchronize the playback and 2591 * interrupt handler. In order to avoid the playback inter- 2592 * fered by cross talk process, the driver make the playback 2593 * preparation halted until cross talk process finish. 2594 */ 2595 nau8825_sema_acquire(nau8825, 3 * HZ); 2596 /* Higher FLL reference input frequency can only set lower 2597 * gain error, such as 0000 for input reference from MCLK 2598 * 12.288Mhz. 2599 */ 2600 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2601 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2602 NAU8825_FLL_CLK_SRC_MCLK | 0); 2603 /* Release the semaphore. */ 2604 nau8825_sema_release(nau8825); 2605 2606 ret = nau8825_mclk_prepare(nau8825, freq); 2607 if (ret) 2608 return ret; 2609 2610 break; 2611 case NAU8825_CLK_FLL_BLK: 2612 /* Acquire the semaphore to synchronize the playback and 2613 * interrupt handler. In order to avoid the playback inter- 2614 * fered by cross talk process, the driver make the playback 2615 * preparation halted until cross talk process finish. 2616 */ 2617 nau8825_sema_acquire(nau8825, 3 * HZ); 2618 /* If FLL reference input is from low frequency source, 2619 * higher error gain can apply such as 0xf which has 2620 * the most sensitive gain error correction threshold, 2621 * Therefore, FLL has the most accurate DCO to 2622 * target frequency. 2623 */ 2624 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2625 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2626 NAU8825_FLL_CLK_SRC_BLK | 2627 (0xf << NAU8825_GAIN_ERR_SFT)); 2628 /* Release the semaphore. */ 2629 nau8825_sema_release(nau8825); 2630 2631 if (nau8825->mclk_freq) { 2632 clk_disable_unprepare(nau8825->mclk); 2633 nau8825->mclk_freq = 0; 2634 } 2635 2636 break; 2637 case NAU8825_CLK_FLL_FS: 2638 /* Acquire the semaphore to synchronize the playback and 2639 * interrupt handler. In order to avoid the playback inter- 2640 * fered by cross talk process, the driver make the playback 2641 * preparation halted until cross talk process finish. 2642 */ 2643 nau8825_sema_acquire(nau8825, 3 * HZ); 2644 /* If FLL reference input is from low frequency source, 2645 * higher error gain can apply such as 0xf which has 2646 * the most sensitive gain error correction threshold, 2647 * Therefore, FLL has the most accurate DCO to 2648 * target frequency. 2649 */ 2650 regmap_update_bits(regmap, NAU8825_REG_FLL3, 2651 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, 2652 NAU8825_FLL_CLK_SRC_FS | 2653 (0xf << NAU8825_GAIN_ERR_SFT)); 2654 /* Release the semaphore. */ 2655 nau8825_sema_release(nau8825); 2656 2657 if (nau8825->mclk_freq) { 2658 clk_disable_unprepare(nau8825->mclk); 2659 nau8825->mclk_freq = 0; 2660 } 2661 2662 break; 2663 default: 2664 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id); 2665 return -EINVAL; 2666 } 2667 2668 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq, 2669 clk_id); 2670 return 0; 2671 } 2672 2673 static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id, 2674 int source, unsigned int freq, int dir) 2675 { 2676 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2677 2678 return nau8825_configure_sysclk(nau8825, clk_id, freq); 2679 } 2680 2681 static int nau8825_resume_setup(struct nau8825 *nau8825) 2682 { 2683 struct regmap *regmap = nau8825->regmap; 2684 2685 /* Close clock when jack type detection at manual mode */ 2686 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); 2687 2688 /* Clear all interruption status */ 2689 nau8825_int_status_clear_all(regmap); 2690 2691 /* Enable both insertion and ejection interruptions, and then 2692 * bypass de-bounce circuit. 2693 */ 2694 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 2695 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN | 2696 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN, 2697 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN); 2698 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, 2699 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); 2700 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 2701 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0); 2702 2703 return 0; 2704 } 2705 2706 static int nau8825_set_bias_level(struct snd_soc_component *component, 2707 enum snd_soc_bias_level level) 2708 { 2709 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2710 int ret; 2711 2712 switch (level) { 2713 case SND_SOC_BIAS_ON: 2714 break; 2715 2716 case SND_SOC_BIAS_PREPARE: 2717 break; 2718 2719 case SND_SOC_BIAS_STANDBY: 2720 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 2721 if (nau8825->mclk_freq) { 2722 ret = clk_prepare_enable(nau8825->mclk); 2723 if (ret) { 2724 dev_err(nau8825->dev, "Unable to prepare component mclk\n"); 2725 return ret; 2726 } 2727 } 2728 /* Setup codec configuration after resume */ 2729 nau8825_resume_setup(nau8825); 2730 } 2731 break; 2732 2733 case SND_SOC_BIAS_OFF: 2734 /* Reset the configuration of jack type for detection */ 2735 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ 2736 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS, 2737 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); 2738 /* ground HPL/HPR, MICGRND1/2 */ 2739 regmap_update_bits(nau8825->regmap, 2740 NAU8825_REG_HSD_CTRL, 0xf, 0xf); 2741 /* Cancel and reset cross talk detection funciton */ 2742 nau8825_xtalk_cancel(nau8825); 2743 /* Turn off all interruptions before system shutdown. Keep the 2744 * interruption quiet before resume setup completes. 2745 */ 2746 regmap_write(nau8825->regmap, 2747 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff); 2748 /* Disable ADC needed for interruptions at audo mode */ 2749 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, 2750 NAU8825_ENABLE_ADC, 0); 2751 if (nau8825->mclk_freq) 2752 clk_disable_unprepare(nau8825->mclk); 2753 break; 2754 } 2755 return 0; 2756 } 2757 2758 static int __maybe_unused nau8825_suspend(struct snd_soc_component *component) 2759 { 2760 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2761 2762 disable_irq(nau8825->irq); 2763 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 2764 /* Power down codec power; don't suppoet button wakeup */ 2765 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR"); 2766 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS"); 2767 snd_soc_dapm_sync(nau8825->dapm); 2768 regcache_cache_only(nau8825->regmap, true); 2769 regcache_mark_dirty(nau8825->regmap); 2770 2771 return 0; 2772 } 2773 2774 static int __maybe_unused nau8825_resume(struct snd_soc_component *component) 2775 { 2776 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); 2777 int ret; 2778 2779 regcache_cache_only(nau8825->regmap, false); 2780 regcache_sync(nau8825->regmap); 2781 nau8825->xtalk_protect = true; 2782 ret = nau8825_sema_acquire(nau8825, 0); 2783 if (ret) 2784 nau8825->xtalk_protect = false; 2785 enable_irq(nau8825->irq); 2786 2787 return 0; 2788 } 2789 2790 static int nau8825_set_jack(struct snd_soc_component *component, 2791 struct snd_soc_jack *jack, void *data) 2792 { 2793 return nau8825_enable_jack_detect(component, jack); 2794 } 2795 2796 static const struct snd_soc_component_driver nau8825_component_driver = { 2797 .probe = nau8825_component_probe, 2798 .remove = nau8825_component_remove, 2799 .set_sysclk = nau8825_set_sysclk, 2800 .set_pll = nau8825_set_pll, 2801 .set_bias_level = nau8825_set_bias_level, 2802 .suspend = nau8825_suspend, 2803 .resume = nau8825_resume, 2804 .controls = nau8825_controls, 2805 .num_controls = ARRAY_SIZE(nau8825_controls), 2806 .dapm_widgets = nau8825_dapm_widgets, 2807 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets), 2808 .dapm_routes = nau8825_dapm_routes, 2809 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes), 2810 .set_jack = nau8825_set_jack, 2811 .suspend_bias_off = 1, 2812 .idle_bias_on = 1, 2813 .use_pmdown_time = 1, 2814 .endianness = 1, 2815 }; 2816 2817 static void nau8825_reset_chip(struct regmap *regmap) 2818 { 2819 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2820 regmap_write(regmap, NAU8825_REG_RESET, 0x00); 2821 } 2822 2823 static void nau8825_print_device_properties(struct nau8825 *nau8825) 2824 { 2825 int i; 2826 struct device *dev = nau8825->dev; 2827 2828 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable); 2829 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable); 2830 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up); 2831 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity); 2832 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage); 2833 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance); 2834 2835 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num); 2836 for (i = 0; i < nau8825->sar_threshold_num; i++) 2837 dev_dbg(dev, "sar-threshold[%d]=%d\n", i, 2838 nau8825->sar_threshold[i]); 2839 2840 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis); 2841 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage); 2842 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time); 2843 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time); 2844 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce); 2845 dev_dbg(dev, "jack-insert-debounce: %d\n", 2846 nau8825->jack_insert_debounce); 2847 dev_dbg(dev, "jack-eject-debounce: %d\n", 2848 nau8825->jack_eject_debounce); 2849 dev_dbg(dev, "crosstalk-enable: %d\n", 2850 nau8825->xtalk_enable); 2851 dev_dbg(dev, "adcout-drive-strong: %d\n", nau8825->adcout_ds); 2852 dev_dbg(dev, "adc-delay-ms: %d\n", nau8825->adc_delay); 2853 } 2854 2855 static int nau8825_read_device_properties(struct device *dev, 2856 struct nau8825 *nau8825) { 2857 int ret; 2858 2859 nau8825->jkdet_enable = device_property_read_bool(dev, 2860 "nuvoton,jkdet-enable"); 2861 nau8825->jkdet_pull_enable = device_property_read_bool(dev, 2862 "nuvoton,jkdet-pull-enable"); 2863 nau8825->jkdet_pull_up = device_property_read_bool(dev, 2864 "nuvoton,jkdet-pull-up"); 2865 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 2866 &nau8825->jkdet_polarity); 2867 if (ret) 2868 nau8825->jkdet_polarity = 1; 2869 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 2870 &nau8825->micbias_voltage); 2871 if (ret) 2872 nau8825->micbias_voltage = 6; 2873 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 2874 &nau8825->vref_impedance); 2875 if (ret) 2876 nau8825->vref_impedance = 2; 2877 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 2878 &nau8825->sar_threshold_num); 2879 if (ret) 2880 nau8825->sar_threshold_num = 4; 2881 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 2882 nau8825->sar_threshold, nau8825->sar_threshold_num); 2883 if (ret) { 2884 nau8825->sar_threshold[0] = 0x08; 2885 nau8825->sar_threshold[1] = 0x12; 2886 nau8825->sar_threshold[2] = 0x26; 2887 nau8825->sar_threshold[3] = 0x73; 2888 } 2889 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 2890 &nau8825->sar_hysteresis); 2891 if (ret) 2892 nau8825->sar_hysteresis = 0; 2893 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 2894 &nau8825->sar_voltage); 2895 if (ret) 2896 nau8825->sar_voltage = 6; 2897 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 2898 &nau8825->sar_compare_time); 2899 if (ret) 2900 nau8825->sar_compare_time = 1; 2901 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 2902 &nau8825->sar_sampling_time); 2903 if (ret) 2904 nau8825->sar_sampling_time = 1; 2905 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 2906 &nau8825->key_debounce); 2907 if (ret) 2908 nau8825->key_debounce = 3; 2909 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 2910 &nau8825->jack_insert_debounce); 2911 if (ret) 2912 nau8825->jack_insert_debounce = 7; 2913 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 2914 &nau8825->jack_eject_debounce); 2915 if (ret) 2916 nau8825->jack_eject_debounce = 0; 2917 nau8825->xtalk_enable = device_property_read_bool(dev, 2918 "nuvoton,crosstalk-enable"); 2919 nau8825->adcout_ds = device_property_read_bool(dev, "nuvoton,adcout-drive-strong"); 2920 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", &nau8825->adc_delay); 2921 if (ret) 2922 nau8825->adc_delay = 125; 2923 if (nau8825->adc_delay < 125 || nau8825->adc_delay > 500) 2924 dev_warn(dev, "Please set the suitable delay time!\n"); 2925 2926 nau8825->mclk = devm_clk_get(dev, "mclk"); 2927 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) { 2928 return -EPROBE_DEFER; 2929 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) { 2930 /* The MCLK is managed externally or not used at all */ 2931 nau8825->mclk = NULL; 2932 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally"); 2933 } else if (IS_ERR(nau8825->mclk)) { 2934 return -EINVAL; 2935 } 2936 2937 return 0; 2938 } 2939 2940 static int nau8825_setup_irq(struct nau8825 *nau8825) 2941 { 2942 int ret; 2943 2944 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL, 2945 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 2946 "nau8825", nau8825); 2947 2948 if (ret) { 2949 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n", 2950 nau8825->irq, ret); 2951 return ret; 2952 } 2953 2954 return 0; 2955 } 2956 2957 static int nau8825_i2c_probe(struct i2c_client *i2c) 2958 { 2959 struct device *dev = &i2c->dev; 2960 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev); 2961 int ret, value; 2962 2963 if (!nau8825) { 2964 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL); 2965 if (!nau8825) 2966 return -ENOMEM; 2967 ret = nau8825_read_device_properties(dev, nau8825); 2968 if (ret) 2969 return ret; 2970 } 2971 2972 i2c_set_clientdata(i2c, nau8825); 2973 2974 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config); 2975 if (IS_ERR(nau8825->regmap)) 2976 return PTR_ERR(nau8825->regmap); 2977 nau8825->dev = dev; 2978 nau8825->irq = i2c->irq; 2979 /* Initiate parameters, semaphore and work queue which are needed in 2980 * cross talk suppression measurment function. 2981 */ 2982 nau8825->xtalk_state = NAU8825_XTALK_DONE; 2983 nau8825->xtalk_protect = false; 2984 nau8825->xtalk_baktab_initialized = false; 2985 sema_init(&nau8825->xtalk_sem, 1); 2986 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work); 2987 2988 nau8825_print_device_properties(nau8825); 2989 2990 nau8825_reset_chip(nau8825->regmap); 2991 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value); 2992 if (ret < 0) { 2993 dev_err(dev, "Failed to read device id from the NAU8825: %d\n", 2994 ret); 2995 return ret; 2996 } 2997 nau8825->sw_id = value & NAU8825_SOFTWARE_ID_MASK; 2998 switch (nau8825->sw_id) { 2999 case NAU8825_SOFTWARE_ID_NAU8825: 3000 break; 3001 case NAU8825_SOFTWARE_ID_NAU8825C: 3002 ret = regmap_register_patch(nau8825->regmap, nau8825_regmap_patch, 3003 ARRAY_SIZE(nau8825_regmap_patch)); 3004 if (ret) { 3005 dev_err(dev, "Failed to register Rev C patch: %d\n", ret); 3006 return ret; 3007 } 3008 break; 3009 default: 3010 dev_err(dev, "Not a NAU8825 chip\n"); 3011 return -ENODEV; 3012 } 3013 3014 nau8825_init_regs(nau8825); 3015 3016 if (i2c->irq) 3017 nau8825_setup_irq(nau8825); 3018 3019 return devm_snd_soc_register_component(&i2c->dev, 3020 &nau8825_component_driver, 3021 &nau8825_dai, 1); 3022 } 3023 3024 static void nau8825_i2c_remove(struct i2c_client *client) 3025 {} 3026 3027 static const struct i2c_device_id nau8825_i2c_ids[] = { 3028 { "nau8825", 0 }, 3029 { } 3030 }; 3031 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids); 3032 3033 #ifdef CONFIG_OF 3034 static const struct of_device_id nau8825_of_ids[] = { 3035 { .compatible = "nuvoton,nau8825", }, 3036 {} 3037 }; 3038 MODULE_DEVICE_TABLE(of, nau8825_of_ids); 3039 #endif 3040 3041 #ifdef CONFIG_ACPI 3042 static const struct acpi_device_id nau8825_acpi_match[] = { 3043 { "10508825", 0 }, 3044 {}, 3045 }; 3046 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match); 3047 #endif 3048 3049 static struct i2c_driver nau8825_driver = { 3050 .driver = { 3051 .name = "nau8825", 3052 .of_match_table = of_match_ptr(nau8825_of_ids), 3053 .acpi_match_table = ACPI_PTR(nau8825_acpi_match), 3054 }, 3055 .probe = nau8825_i2c_probe, 3056 .remove = nau8825_i2c_remove, 3057 .id_table = nau8825_i2c_ids, 3058 }; 3059 module_i2c_driver(nau8825_driver); 3060 3061 MODULE_DESCRIPTION("ASoC nau8825 driver"); 3062 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>"); 3063 MODULE_LICENSE("GPL"); 3064