1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * NAU88L24 ALSA SoC audio driver 4 * 5 * Copyright 2016 Nuvoton Technology Corp. 6 * Author: John Hsu <KCHSU0@nuvoton.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/delay.h> 11 #include <linux/init.h> 12 #include <linux/i2c.h> 13 #include <linux/regmap.h> 14 #include <linux/slab.h> 15 #include <linux/clk.h> 16 #include <linux/acpi.h> 17 #include <linux/math64.h> 18 #include <linux/semaphore.h> 19 20 #include <sound/initval.h> 21 #include <sound/tlv.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/jack.h> 27 28 #include "nau8824.h" 29 30 31 static int nau8824_config_sysclk(struct nau8824 *nau8824, 32 int clk_id, unsigned int freq); 33 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824); 34 35 /* the ADC threshold of headset */ 36 #define DMIC_CLK 3072000 37 38 /* the ADC threshold of headset */ 39 #define HEADSET_SARADC_THD 0x80 40 41 /* the parameter threshold of FLL */ 42 #define NAU_FREF_MAX 13500000 43 #define NAU_FVCO_MAX 100000000 44 #define NAU_FVCO_MIN 90000000 45 46 /* scaling for mclk from sysclk_src output */ 47 static const struct nau8824_fll_attr mclk_src_scaling[] = { 48 { 1, 0x0 }, 49 { 2, 0x2 }, 50 { 4, 0x3 }, 51 { 8, 0x4 }, 52 { 16, 0x5 }, 53 { 32, 0x6 }, 54 { 3, 0x7 }, 55 { 6, 0xa }, 56 { 12, 0xb }, 57 { 24, 0xc }, 58 }; 59 60 /* ratio for input clk freq */ 61 static const struct nau8824_fll_attr fll_ratio[] = { 62 { 512000, 0x01 }, 63 { 256000, 0x02 }, 64 { 128000, 0x04 }, 65 { 64000, 0x08 }, 66 { 32000, 0x10 }, 67 { 8000, 0x20 }, 68 { 4000, 0x40 }, 69 }; 70 71 static const struct nau8824_fll_attr fll_pre_scalar[] = { 72 { 1, 0x0 }, 73 { 2, 0x1 }, 74 { 4, 0x2 }, 75 { 8, 0x3 }, 76 }; 77 78 /* the maximum frequency of CLK_ADC and CLK_DAC */ 79 #define CLK_DA_AD_MAX 6144000 80 81 /* over sampling rate */ 82 static const struct nau8824_osr_attr osr_dac_sel[] = { 83 { 64, 2 }, /* OSR 64, SRC 1/4 */ 84 { 256, 0 }, /* OSR 256, SRC 1 */ 85 { 128, 1 }, /* OSR 128, SRC 1/2 */ 86 { 0, 0 }, 87 { 32, 3 }, /* OSR 32, SRC 1/8 */ 88 }; 89 90 static const struct nau8824_osr_attr osr_adc_sel[] = { 91 { 32, 3 }, /* OSR 32, SRC 1/8 */ 92 { 64, 2 }, /* OSR 64, SRC 1/4 */ 93 { 128, 1 }, /* OSR 128, SRC 1/2 */ 94 { 256, 0 }, /* OSR 256, SRC 1 */ 95 }; 96 97 static const struct reg_default nau8824_reg_defaults[] = { 98 { NAU8824_REG_ENA_CTRL, 0x0000 }, 99 { NAU8824_REG_CLK_GATING_ENA, 0x0000 }, 100 { NAU8824_REG_CLK_DIVIDER, 0x0000 }, 101 { NAU8824_REG_FLL1, 0x0000 }, 102 { NAU8824_REG_FLL2, 0x3126 }, 103 { NAU8824_REG_FLL3, 0x0008 }, 104 { NAU8824_REG_FLL4, 0x0010 }, 105 { NAU8824_REG_FLL5, 0xC000 }, 106 { NAU8824_REG_FLL6, 0x6000 }, 107 { NAU8824_REG_FLL_VCO_RSV, 0xF13C }, 108 { NAU8824_REG_JACK_DET_CTRL, 0x0000 }, 109 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 }, 110 { NAU8824_REG_IRQ, 0x0000 }, 111 { NAU8824_REG_CLEAR_INT_REG, 0x0000 }, 112 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 }, 113 { NAU8824_REG_SAR_ADC, 0x0015 }, 114 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 }, 115 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 }, 116 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 }, 117 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 }, 118 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 }, 119 { NAU8824_REG_GPIO_SEL, 0x0000 }, 120 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B }, 121 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 }, 122 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 }, 123 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 }, 124 { NAU8824_REG_TDM_CTRL, 0x0000 }, 125 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 }, 126 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 }, 127 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 }, 128 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 }, 129 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 }, 130 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 }, 131 { NAU8824_REG_EQ1_LOW, 0x112C }, 132 { NAU8824_REG_EQ2_EQ3, 0x2C2C }, 133 { NAU8824_REG_EQ4_EQ5, 0x2C2C }, 134 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 }, 135 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 }, 136 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 }, 137 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 }, 138 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 }, 139 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 }, 140 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 }, 141 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 }, 142 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 }, 143 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 }, 144 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF }, 145 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 }, 146 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 }, 147 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 }, 148 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF }, 149 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 }, 150 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 }, 151 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 }, 152 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 }, 153 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 }, 154 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 }, 155 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 }, 156 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 }, 157 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 }, 158 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 }, 159 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 }, 160 { NAU8824_REG_MODE, 0x0000 }, 161 { NAU8824_REG_MODE1, 0x0000 }, 162 { NAU8824_REG_MODE2, 0x0000 }, 163 { NAU8824_REG_CLASSG, 0x0000 }, 164 { NAU8824_REG_OTP_EFUSE, 0x0000 }, 165 { NAU8824_REG_OTPDOUT_1, 0x0000 }, 166 { NAU8824_REG_OTPDOUT_2, 0x0000 }, 167 { NAU8824_REG_MISC_CTRL, 0x0000 }, 168 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF }, 169 { NAU8824_REG_TEST_MODE, 0x0000 }, 170 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 }, 171 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF }, 172 { NAU8824_REG_BIAS_ADJ, 0x0000 }, 173 { NAU8824_REG_PGA_GAIN, 0x0000 }, 174 { NAU8824_REG_TRIM_SETTINGS, 0x0000 }, 175 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 }, 176 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 }, 177 { NAU8824_REG_ENABLE_LO, 0x0000 }, 178 { NAU8824_REG_GAIN_LO, 0x0000 }, 179 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 }, 180 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 }, 181 { NAU8824_REG_ANALOG_ADC_1, 0x0011 }, 182 { NAU8824_REG_ANALOG_ADC_2, 0x0020 }, 183 { NAU8824_REG_RDAC, 0x0008 }, 184 { NAU8824_REG_MIC_BIAS, 0x0006 }, 185 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 }, 186 { NAU8824_REG_BOOST, 0x0000 }, 187 { NAU8824_REG_FEPGA, 0x0000 }, 188 { NAU8824_REG_FEPGA_II, 0x0000 }, 189 { NAU8824_REG_FEPGA_SE, 0x0000 }, 190 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 }, 191 { NAU8824_REG_ATT_PORT0, 0x0000 }, 192 { NAU8824_REG_ATT_PORT1, 0x0000 }, 193 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 }, 194 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 }, 195 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 }, 196 }; 197 198 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout) 199 { 200 int ret; 201 202 if (timeout) { 203 ret = down_timeout(&nau8824->jd_sem, timeout); 204 if (ret < 0) 205 dev_warn(nau8824->dev, "Acquire semaphore timeout\n"); 206 } else { 207 ret = down_interruptible(&nau8824->jd_sem); 208 if (ret < 0) 209 dev_warn(nau8824->dev, "Acquire semaphore fail\n"); 210 } 211 212 return ret; 213 } 214 215 static inline void nau8824_sema_release(struct nau8824 *nau8824) 216 { 217 up(&nau8824->jd_sem); 218 } 219 220 static bool nau8824_readable_reg(struct device *dev, unsigned int reg) 221 { 222 switch (reg) { 223 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV: 224 case NAU8824_REG_JACK_DET_CTRL: 225 case NAU8824_REG_INTERRUPT_SETTING_1: 226 case NAU8824_REG_IRQ: 227 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 228 case NAU8824_REG_GPIO_SEL: 229 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 230 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 231 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 232 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3: 233 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1: 234 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 235 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 236 case NAU8824_REG_I2C_TIMEOUT: 237 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 238 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 239 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 240 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT: 241 return true; 242 default: 243 return false; 244 } 245 246 } 247 248 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg) 249 { 250 switch (reg) { 251 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV: 252 case NAU8824_REG_JACK_DET_CTRL: 253 case NAU8824_REG_INTERRUPT_SETTING_1: 254 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: 255 case NAU8824_REG_GPIO_SEL: 256 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: 257 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: 258 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: 259 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01: 260 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01: 261 case NAU8824_REG_DRC_SLOPE_ADC_CH01: 262 case NAU8824_REG_DRC_ATKDCY_ADC_CH01: 263 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23: 264 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23: 265 case NAU8824_REG_DRC_SLOPE_ADC_CH23: 266 case NAU8824_REG_DRC_ATKDCY_ADC_CH23: 267 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC: 268 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: 269 case NAU8824_REG_I2C_TIMEOUT: 270 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: 271 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: 272 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL: 273 return true; 274 default: 275 return false; 276 } 277 } 278 279 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg) 280 { 281 switch (reg) { 282 case NAU8824_REG_RESET: 283 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG: 284 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3: 285 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1: 286 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: 287 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: 288 case NAU8824_REG_CHARGE_PUMP_INPUT: 289 return true; 290 default: 291 return false; 292 } 293 } 294 295 static const char * const nau8824_companding[] = { 296 "Off", "NC", "u-law", "A-law" }; 297 298 static const struct soc_enum nau8824_companding_adc_enum = 299 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12, 300 ARRAY_SIZE(nau8824_companding), nau8824_companding); 301 302 static const struct soc_enum nau8824_companding_dac_enum = 303 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14, 304 ARRAY_SIZE(nau8824_companding), nau8824_companding); 305 306 static const char * const nau8824_adc_decimation[] = { 307 "32", "64", "128", "256" }; 308 309 static const struct soc_enum nau8824_adc_decimation_enum = 310 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0, 311 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation); 312 313 static const char * const nau8824_dac_oversampl[] = { 314 "64", "256", "128", "", "32" }; 315 316 static const struct soc_enum nau8824_dac_oversampl_enum = 317 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0, 318 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl); 319 320 static const char * const nau8824_input_channel[] = { 321 "Input CH0", "Input CH1", "Input CH2", "Input CH3" }; 322 323 static const struct soc_enum nau8824_adc_ch0_enum = 324 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9, 325 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 326 327 static const struct soc_enum nau8824_adc_ch1_enum = 328 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9, 329 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 330 331 static const struct soc_enum nau8824_adc_ch2_enum = 332 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9, 333 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 334 335 static const struct soc_enum nau8824_adc_ch3_enum = 336 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9, 337 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); 338 339 static const char * const nau8824_tdm_slot[] = { 340 "Slot 0", "Slot 1", "Slot 2", "Slot 3" }; 341 342 static const struct soc_enum nau8824_dac_left_sel_enum = 343 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6, 344 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 345 346 static const struct soc_enum nau8824_dac_right_sel_enum = 347 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4, 348 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); 349 350 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400); 351 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0); 352 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0); 353 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0); 354 355 static const struct snd_kcontrol_new nau8824_snd_controls[] = { 356 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum), 357 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum), 358 359 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum), 360 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum), 361 362 SOC_SINGLE_TLV("Speaker Right DACR Volume", 363 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv), 364 SOC_SINGLE_TLV("Speaker Left DACL Volume", 365 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv), 366 SOC_SINGLE_TLV("Speaker Left DACR Volume", 367 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv), 368 SOC_SINGLE_TLV("Speaker Right DACL Volume", 369 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv), 370 371 SOC_SINGLE_TLV("Headphone Right DACR Volume", 372 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv), 373 SOC_SINGLE_TLV("Headphone Left DACL Volume", 374 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv), 375 SOC_SINGLE_TLV("Headphone Right DACL Volume", 376 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv), 377 SOC_SINGLE_TLV("Headphone Left DACR Volume", 378 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv), 379 380 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II, 381 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv), 382 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II, 383 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv), 384 385 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL, 386 0, 0x164, 0, dmic_vol_tlv), 387 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL, 388 0, 0x164, 0, dmic_vol_tlv), 389 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL, 390 0, 0x164, 0, dmic_vol_tlv), 391 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL, 392 0, 0x164, 0, dmic_vol_tlv), 393 394 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum), 395 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum), 396 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum), 397 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum), 398 399 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0), 400 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0), 401 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0), 402 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0), 403 404 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum), 405 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum), 406 407 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0), 408 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0), 409 410 SOC_SINGLE("THD for key media", 411 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0), 412 SOC_SINGLE("THD for key voice command", 413 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0), 414 SOC_SINGLE("THD for key volume up", 415 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0), 416 SOC_SINGLE("THD for key volume down", 417 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0), 418 }; 419 420 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w, 421 struct snd_kcontrol *kcontrol, int event) 422 { 423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 424 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 425 426 switch (event) { 427 case SND_SOC_DAPM_PRE_PMU: 428 /* Disables the TESTDAC to let DAC signal pass through. */ 429 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 430 NAU8824_TEST_DAC_EN, 0); 431 break; 432 case SND_SOC_DAPM_POST_PMD: 433 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, 434 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 435 break; 436 default: 437 return -EINVAL; 438 } 439 440 return 0; 441 } 442 443 static int nau8824_spk_event(struct snd_soc_dapm_widget *w, 444 struct snd_kcontrol *kcontrol, int event) 445 { 446 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 447 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 448 449 switch (event) { 450 case SND_SOC_DAPM_PRE_PMU: 451 regmap_update_bits(nau8824->regmap, 452 NAU8824_REG_ANALOG_CONTROL_2, 453 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS); 454 break; 455 case SND_SOC_DAPM_POST_PMD: 456 regmap_update_bits(nau8824->regmap, 457 NAU8824_REG_ANALOG_CONTROL_2, 458 NAU8824_CLASSD_CLAMP_DIS, 0); 459 break; 460 default: 461 return -EINVAL; 462 } 463 464 return 0; 465 } 466 467 static int nau8824_pump_event(struct snd_soc_dapm_widget *w, 468 struct snd_kcontrol *kcontrol, int event) 469 { 470 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 471 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 472 473 switch (event) { 474 case SND_SOC_DAPM_POST_PMU: 475 /* Prevent startup click by letting charge pump to ramp up */ 476 msleep(10); 477 regmap_update_bits(nau8824->regmap, 478 NAU8824_REG_CHARGE_PUMP_CONTROL, 479 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW); 480 break; 481 case SND_SOC_DAPM_PRE_PMD: 482 regmap_update_bits(nau8824->regmap, 483 NAU8824_REG_CHARGE_PUMP_CONTROL, 484 NAU8824_JAMNODCLOW, 0); 485 break; 486 default: 487 return -EINVAL; 488 } 489 490 return 0; 491 } 492 493 static int system_clock_control(struct snd_soc_dapm_widget *w, 494 struct snd_kcontrol *k, int event) 495 { 496 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 497 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 498 struct regmap *regmap = nau8824->regmap; 499 unsigned int value; 500 bool clk_fll, error; 501 502 if (SND_SOC_DAPM_EVENT_OFF(event)) { 503 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n"); 504 /* Set clock source to disable or internal clock before the 505 * playback or capture end. Codec needs clock for Jack 506 * detection and button press if jack inserted; otherwise, 507 * the clock should be closed. 508 */ 509 if (nau8824_is_jack_inserted(nau8824)) { 510 nau8824_config_sysclk(nau8824, 511 NAU8824_CLK_INTERNAL, 0); 512 } else { 513 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 514 } 515 } else { 516 dev_dbg(nau8824->dev, "system clock control : POWER ON\n"); 517 /* Check the clock source setting is proper or not 518 * no matter the source is from FLL or MCLK. 519 */ 520 regmap_read(regmap, NAU8824_REG_FLL1, &value); 521 clk_fll = value & NAU8824_FLL_RATIO_MASK; 522 /* It's error to use internal clock when playback */ 523 regmap_read(regmap, NAU8824_REG_FLL6, &value); 524 error = value & NAU8824_DCO_EN; 525 if (!error) { 526 /* Check error depending on source is FLL or MCLK. */ 527 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value); 528 if (clk_fll) 529 error = !(value & NAU8824_CLK_SRC_VCO); 530 else 531 error = value & NAU8824_CLK_SRC_VCO; 532 } 533 /* Recover the clock source setting if error. */ 534 if (error) { 535 if (clk_fll) { 536 regmap_update_bits(regmap, 537 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 538 regmap_update_bits(regmap, 539 NAU8824_REG_CLK_DIVIDER, 540 NAU8824_CLK_SRC_MASK, 541 NAU8824_CLK_SRC_VCO); 542 } else { 543 nau8824_config_sysclk(nau8824, 544 NAU8824_CLK_MCLK, 0); 545 } 546 } 547 } 548 549 return 0; 550 } 551 552 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 553 struct snd_kcontrol *k, int event) 554 { 555 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 556 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 557 int src; 558 559 /* The DMIC clock is gotten from system clock (256fs) divided by 560 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or 561 * less than 3.072 MHz. 562 */ 563 for (src = 0; src < 5; src++) { 564 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK) 565 break; 566 } 567 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256); 568 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 569 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT)); 570 571 return 0; 572 } 573 574 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic = 575 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 576 NAU8824_ADC_CH0_DMIC_SFT, 1, 0); 577 578 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic = 579 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 580 NAU8824_ADC_CH1_DMIC_SFT, 1, 0); 581 582 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic = 583 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 584 NAU8824_ADC_CH2_DMIC_SFT, 1, 0); 585 586 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic = 587 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, 588 NAU8824_ADC_CH3_DMIC_SFT, 1, 0); 589 590 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = { 591 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 592 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0), 593 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 594 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0), 595 }; 596 597 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = { 598 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, 599 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0), 600 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, 601 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0), 602 }; 603 604 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = { 605 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 606 NAU8824_DACR_HPL_EN_SFT, 1, 0), 607 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 608 NAU8824_DACL_HPL_EN_SFT, 1, 0), 609 }; 610 611 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = { 612 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, 613 NAU8824_DACL_HPR_EN_SFT, 1, 0), 614 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, 615 NAU8824_DACR_HPR_EN_SFT, 1, 0), 616 }; 617 618 static const char * const nau8824_dac_src[] = { "DACL", "DACR" }; 619 620 static SOC_ENUM_SINGLE_DECL( 621 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 622 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src); 623 624 static SOC_ENUM_SINGLE_DECL( 625 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 626 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src); 627 628 static const struct snd_kcontrol_new nau8824_dacl_mux = 629 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum); 630 631 static const struct snd_kcontrol_new nau8824_dacr_mux = 632 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum); 633 634 635 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = { 636 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 637 system_clock_control, SND_SOC_DAPM_POST_PMD | 638 SND_SOC_DAPM_POST_PMU), 639 640 SND_SOC_DAPM_INPUT("HSMIC1"), 641 SND_SOC_DAPM_INPUT("HSMIC2"), 642 SND_SOC_DAPM_INPUT("MIC1"), 643 SND_SOC_DAPM_INPUT("MIC2"), 644 SND_SOC_DAPM_INPUT("DMIC1"), 645 SND_SOC_DAPM_INPUT("DMIC2"), 646 SND_SOC_DAPM_INPUT("DMIC3"), 647 SND_SOC_DAPM_INPUT("DMIC4"), 648 649 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC, 650 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0), 651 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS, 652 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0), 653 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ, 654 NAU8824_DMIC1_EN_SFT, 0, NULL, 0), 655 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ, 656 NAU8824_DMIC2_EN_SFT, 0, NULL, 0), 657 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 658 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 659 660 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM, 661 0, 0, &nau8824_adc_ch0_dmic), 662 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM, 663 0, 0, &nau8824_adc_ch1_dmic), 664 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM, 665 0, 0, &nau8824_adc_ch2_dmic), 666 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM, 667 0, 0, &nau8824_adc_ch3_dmic), 668 669 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL, 670 12, 0, nau8824_adc_left_mixer, 671 ARRAY_SIZE(nau8824_adc_left_mixer)), 672 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL, 673 13, 0, nau8824_adc_right_mixer, 674 ARRAY_SIZE(nau8824_adc_right_mixer)), 675 676 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2, 677 NAU8824_ADCL_EN_SFT, 0), 678 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2, 679 NAU8824_ADCR_EN_SFT, 0), 680 681 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0), 682 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 683 684 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC, 685 NAU8824_DACL_EN_SFT, 0), 686 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC, 687 NAU8824_DACL_CLK_SFT, 0, NULL, 0), 688 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC, 689 NAU8824_DACR_EN_SFT, 0), 690 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC, 691 NAU8824_DACR_CLK_SFT, 0, NULL, 0), 692 693 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux), 694 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux), 695 696 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 697 8, 1, nau8824_output_dac_event, 698 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 699 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, 700 9, 1, nau8824_output_dac_event, 701 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 702 703 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1, 704 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event, 705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 706 707 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG, 708 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer, 709 ARRAY_SIZE(nau8824_hp_left_mixer)), 710 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG, 711 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer, 712 ARRAY_SIZE(nau8824_hp_right_mixer)), 713 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL, 714 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event, 715 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 716 SND_SOC_DAPM_PGA("Output Driver L", 717 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), 718 SND_SOC_DAPM_PGA("Output Driver R", 719 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), 720 SND_SOC_DAPM_PGA("Main Driver L", 721 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), 722 SND_SOC_DAPM_PGA("Main Driver R", 723 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), 724 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST, 725 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0), 726 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG, 727 NAU8824_CLASSG_EN_SFT, 0, NULL, 0), 728 729 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 730 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 731 SND_SOC_DAPM_OUTPUT("HPOL"), 732 SND_SOC_DAPM_OUTPUT("HPOR"), 733 }; 734 735 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = { 736 {"DMIC1 Enable", "Switch", "DMIC1"}, 737 {"DMIC2 Enable", "Switch", "DMIC2"}, 738 {"DMIC3 Enable", "Switch", "DMIC3"}, 739 {"DMIC4 Enable", "Switch", "DMIC4"}, 740 741 {"DMIC1", NULL, "DMIC12 Power"}, 742 {"DMIC2", NULL, "DMIC12 Power"}, 743 {"DMIC3", NULL, "DMIC34 Power"}, 744 {"DMIC4", NULL, "DMIC34 Power"}, 745 {"DMIC12 Power", NULL, "DMIC Clock"}, 746 {"DMIC34 Power", NULL, "DMIC Clock"}, 747 748 {"Left ADC", "MIC Switch", "MIC1"}, 749 {"Left ADC", "HSMIC Switch", "HSMIC1"}, 750 {"Right ADC", "MIC Switch", "MIC2"}, 751 {"Right ADC", "HSMIC Switch", "HSMIC2"}, 752 753 {"ADCL", NULL, "Left ADC"}, 754 {"ADCR", NULL, "Right ADC"}, 755 756 {"AIFTX", NULL, "MICBIAS"}, 757 {"AIFTX", NULL, "ADCL"}, 758 {"AIFTX", NULL, "ADCR"}, 759 {"AIFTX", NULL, "DMIC1 Enable"}, 760 {"AIFTX", NULL, "DMIC2 Enable"}, 761 {"AIFTX", NULL, "DMIC3 Enable"}, 762 {"AIFTX", NULL, "DMIC4 Enable"}, 763 764 {"AIFTX", NULL, "System Clock"}, 765 {"AIFRX", NULL, "System Clock"}, 766 767 {"DACL", NULL, "AIFRX"}, 768 {"DACL", NULL, "DACL Clock"}, 769 {"DACR", NULL, "AIFRX"}, 770 {"DACR", NULL, "DACR Clock"}, 771 772 {"DACL Mux", "DACL", "DACL"}, 773 {"DACL Mux", "DACR", "DACR"}, 774 {"DACR Mux", "DACL", "DACL"}, 775 {"DACR Mux", "DACR", "DACR"}, 776 777 {"Output DACL", NULL, "DACL Mux"}, 778 {"Output DACR", NULL, "DACR Mux"}, 779 780 {"ClassD", NULL, "Output DACL"}, 781 {"ClassD", NULL, "Output DACR"}, 782 783 {"Left Headphone", "DAC Left Switch", "Output DACL"}, 784 {"Left Headphone", "DAC Right Switch", "Output DACR"}, 785 {"Right Headphone", "DAC Left Switch", "Output DACL"}, 786 {"Right Headphone", "DAC Right Switch", "Output DACR"}, 787 788 {"Charge Pump", NULL, "Left Headphone"}, 789 {"Charge Pump", NULL, "Right Headphone"}, 790 {"Output Driver L", NULL, "Charge Pump"}, 791 {"Output Driver R", NULL, "Charge Pump"}, 792 {"Main Driver L", NULL, "Output Driver L"}, 793 {"Main Driver R", NULL, "Output Driver R"}, 794 {"Class G", NULL, "Main Driver L"}, 795 {"Class G", NULL, "Main Driver R"}, 796 {"HP Boost Driver", NULL, "Class G"}, 797 798 {"SPKOUTL", NULL, "ClassD"}, 799 {"SPKOUTR", NULL, "ClassD"}, 800 {"HPOL", NULL, "HP Boost Driver"}, 801 {"HPOR", NULL, "HP Boost Driver"}, 802 }; 803 804 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824) 805 { 806 struct snd_soc_jack *jack = nau8824->jack; 807 bool insert = false; 808 809 if (nau8824->irq && jack) 810 insert = jack->status & SND_JACK_HEADPHONE; 811 812 return insert; 813 } 814 815 static void nau8824_int_status_clear_all(struct regmap *regmap) 816 { 817 int active_irq, clear_irq, i; 818 819 /* Reset the intrruption status from rightmost bit if the corres- 820 * ponding irq event occurs. 821 */ 822 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq); 823 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) { 824 clear_irq = (0x1 << i); 825 if (active_irq & clear_irq) 826 regmap_write(regmap, 827 NAU8824_REG_CLEAR_INT_REG, clear_irq); 828 } 829 } 830 831 static void nau8824_eject_jack(struct nau8824 *nau8824) 832 { 833 struct snd_soc_dapm_context *dapm = nau8824->dapm; 834 struct regmap *regmap = nau8824->regmap; 835 836 /* Clear all interruption status */ 837 nau8824_int_status_clear_all(regmap); 838 839 snd_soc_dapm_disable_pin(dapm, "SAR"); 840 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 841 snd_soc_dapm_sync(dapm); 842 843 /* Enable the insertion interruption, disable the ejection 844 * interruption, and then bypass de-bounce circuit. 845 */ 846 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 847 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 848 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 849 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | 850 NAU8824_IRQ_EJECT_DIS); 851 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 852 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 853 NAU8824_IRQ_INSERT_EN); 854 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 855 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 856 857 /* Close clock for jack type detection at manual mode */ 858 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 859 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 860 } 861 862 static void nau8824_jdet_work(struct work_struct *work) 863 { 864 struct nau8824 *nau8824 = container_of( 865 work, struct nau8824, jdet_work); 866 struct snd_soc_dapm_context *dapm = nau8824->dapm; 867 struct regmap *regmap = nau8824->regmap; 868 int adc_value, event = 0, event_mask = 0; 869 870 snd_soc_dapm_enable_pin(dapm, "MICBIAS"); 871 snd_soc_dapm_enable_pin(dapm, "SAR"); 872 snd_soc_dapm_sync(dapm); 873 874 msleep(100); 875 876 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value); 877 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK; 878 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value); 879 if (adc_value < HEADSET_SARADC_THD) { 880 event |= SND_JACK_HEADPHONE; 881 882 snd_soc_dapm_disable_pin(dapm, "SAR"); 883 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 884 snd_soc_dapm_sync(dapm); 885 } else { 886 event |= SND_JACK_HEADSET; 887 } 888 event_mask |= SND_JACK_HEADSET; 889 snd_soc_jack_report(nau8824->jack, event, event_mask); 890 891 /* Enable short key press and release interruption. */ 892 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 893 NAU8824_IRQ_KEY_RELEASE_DIS | 894 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0); 895 896 nau8824_sema_release(nau8824); 897 } 898 899 static void nau8824_setup_auto_irq(struct nau8824 *nau8824) 900 { 901 struct regmap *regmap = nau8824->regmap; 902 903 /* Enable jack ejection interruption. */ 904 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, 905 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, 906 NAU8824_IRQ_EJECT_EN); 907 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, 908 NAU8824_IRQ_EJECT_DIS, 0); 909 /* Enable internal VCO needed for interruptions */ 910 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE) 911 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0); 912 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 913 NAU8824_JD_SLEEP_MODE, 0); 914 } 915 916 static int nau8824_button_decode(int value) 917 { 918 int buttons = 0; 919 920 /* The chip supports up to 8 buttons, but ALSA defines 921 * only 6 buttons. 922 */ 923 if (value & BIT(0)) 924 buttons |= SND_JACK_BTN_0; 925 if (value & BIT(1)) 926 buttons |= SND_JACK_BTN_1; 927 if (value & BIT(2)) 928 buttons |= SND_JACK_BTN_2; 929 if (value & BIT(3)) 930 buttons |= SND_JACK_BTN_3; 931 if (value & BIT(4)) 932 buttons |= SND_JACK_BTN_4; 933 if (value & BIT(5)) 934 buttons |= SND_JACK_BTN_5; 935 936 return buttons; 937 } 938 939 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ 940 SND_JACK_BTN_2 | SND_JACK_BTN_3) 941 942 static irqreturn_t nau8824_interrupt(int irq, void *data) 943 { 944 struct nau8824 *nau8824 = (struct nau8824 *)data; 945 struct regmap *regmap = nau8824->regmap; 946 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 947 948 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) { 949 dev_err(nau8824->dev, "failed to read irq status\n"); 950 return IRQ_NONE; 951 } 952 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq); 953 954 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) { 955 nau8824_eject_jack(nau8824); 956 event_mask |= SND_JACK_HEADSET; 957 clear_irq = NAU8824_JACK_EJECTION_DETECTED; 958 /* release semaphore held after resume, 959 * and cancel jack detection 960 */ 961 nau8824_sema_release(nau8824); 962 cancel_work_sync(&nau8824->jdet_work); 963 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) { 964 int key_status, button_pressed; 965 966 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG, 967 &key_status); 968 969 /* lower 8 bits of the register are for pressed keys */ 970 button_pressed = nau8824_button_decode(key_status); 971 972 event |= button_pressed; 973 dev_dbg(nau8824->dev, "button %x pressed\n", event); 974 event_mask |= NAU8824_BUTTONS; 975 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ; 976 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) { 977 event_mask = NAU8824_BUTTONS; 978 clear_irq = NAU8824_KEY_RELEASE_IRQ; 979 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) { 980 /* Turn off insertion interruption at manual mode */ 981 regmap_update_bits(regmap, 982 NAU8824_REG_INTERRUPT_SETTING, 983 NAU8824_IRQ_INSERT_DIS, 984 NAU8824_IRQ_INSERT_DIS); 985 regmap_update_bits(regmap, 986 NAU8824_REG_INTERRUPT_SETTING_1, 987 NAU8824_IRQ_INSERT_EN, 0); 988 /* detect microphone and jack type */ 989 cancel_work_sync(&nau8824->jdet_work); 990 schedule_work(&nau8824->jdet_work); 991 992 /* Enable interruption for jack type detection at audo 993 * mode which can detect microphone and jack type. 994 */ 995 nau8824_setup_auto_irq(nau8824); 996 } 997 998 if (!clear_irq) 999 clear_irq = active_irq; 1000 /* clears the rightmost interruption */ 1001 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq); 1002 1003 if (event_mask) 1004 snd_soc_jack_report(nau8824->jack, event, event_mask); 1005 1006 return IRQ_HANDLED; 1007 } 1008 1009 static int nau8824_clock_check(struct nau8824 *nau8824, 1010 int stream, int rate, int osr) 1011 { 1012 int osrate; 1013 1014 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1015 if (osr >= ARRAY_SIZE(osr_dac_sel)) 1016 return -EINVAL; 1017 osrate = osr_dac_sel[osr].osr; 1018 } else { 1019 if (osr >= ARRAY_SIZE(osr_adc_sel)) 1020 return -EINVAL; 1021 osrate = osr_adc_sel[osr].osr; 1022 } 1023 1024 if (!osrate || rate * osr > CLK_DA_AD_MAX) { 1025 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); 1026 return -EINVAL; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int nau8824_hw_params(struct snd_pcm_substream *substream, 1033 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1034 { 1035 struct snd_soc_component *component = dai->component; 1036 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1037 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div; 1038 1039 nau8824_sema_acquire(nau8824, HZ); 1040 1041 /* CLK_DAC or CLK_ADC = OSR * FS 1042 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 1043 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 1044 * values must be selected such that the maximum frequency is less 1045 * than 6.144 MHz. 1046 */ 1047 nau8824->fs = params_rate(params); 1048 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1049 regmap_read(nau8824->regmap, 1050 NAU8824_REG_DAC_FILTER_CTRL_1, &osr); 1051 osr &= NAU8824_DAC_OVERSAMPLE_MASK; 1052 if (nau8824_clock_check(nau8824, substream->stream, 1053 nau8824->fs, osr)) 1054 return -EINVAL; 1055 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1056 NAU8824_CLK_DAC_SRC_MASK, 1057 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT); 1058 } else { 1059 regmap_read(nau8824->regmap, 1060 NAU8824_REG_ADC_FILTER_CTRL, &osr); 1061 osr &= NAU8824_ADC_SYNC_DOWN_MASK; 1062 if (nau8824_clock_check(nau8824, substream->stream, 1063 nau8824->fs, osr)) 1064 return -EINVAL; 1065 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1066 NAU8824_CLK_ADC_SRC_MASK, 1067 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT); 1068 } 1069 1070 /* make BCLK and LRC divde configuration if the codec as master. */ 1071 regmap_read(nau8824->regmap, 1072 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val); 1073 if (ctrl_val & NAU8824_I2S_MS_MASTER) { 1074 /* get the bclk and fs ratio */ 1075 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs; 1076 if (bclk_fs <= 32) 1077 bclk_div = 0x3; 1078 else if (bclk_fs <= 64) 1079 bclk_div = 0x2; 1080 else if (bclk_fs <= 128) 1081 bclk_div = 0x1; 1082 else if (bclk_fs <= 256) 1083 bclk_div = 0; 1084 else 1085 return -EINVAL; 1086 regmap_update_bits(nau8824->regmap, 1087 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1088 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK, 1089 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div); 1090 } 1091 1092 switch (params_width(params)) { 1093 case 16: 1094 val_len |= NAU8824_I2S_DL_16; 1095 break; 1096 case 20: 1097 val_len |= NAU8824_I2S_DL_20; 1098 break; 1099 case 24: 1100 val_len |= NAU8824_I2S_DL_24; 1101 break; 1102 case 32: 1103 val_len |= NAU8824_I2S_DL_32; 1104 break; 1105 default: 1106 return -EINVAL; 1107 } 1108 1109 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1110 NAU8824_I2S_DL_MASK, val_len); 1111 1112 nau8824_sema_release(nau8824); 1113 1114 return 0; 1115 } 1116 1117 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1118 { 1119 struct snd_soc_component *component = dai->component; 1120 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1121 unsigned int ctrl1_val = 0, ctrl2_val = 0; 1122 1123 nau8824_sema_acquire(nau8824, HZ); 1124 1125 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1126 case SND_SOC_DAIFMT_CBM_CFM: 1127 ctrl2_val |= NAU8824_I2S_MS_MASTER; 1128 break; 1129 case SND_SOC_DAIFMT_CBS_CFS: 1130 break; 1131 default: 1132 return -EINVAL; 1133 } 1134 1135 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1136 case SND_SOC_DAIFMT_NB_NF: 1137 break; 1138 case SND_SOC_DAIFMT_IB_NF: 1139 ctrl1_val |= NAU8824_I2S_BP_INV; 1140 break; 1141 default: 1142 return -EINVAL; 1143 } 1144 1145 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1146 case SND_SOC_DAIFMT_I2S: 1147 ctrl1_val |= NAU8824_I2S_DF_I2S; 1148 break; 1149 case SND_SOC_DAIFMT_LEFT_J: 1150 ctrl1_val |= NAU8824_I2S_DF_LEFT; 1151 break; 1152 case SND_SOC_DAIFMT_RIGHT_J: 1153 ctrl1_val |= NAU8824_I2S_DF_RIGTH; 1154 break; 1155 case SND_SOC_DAIFMT_DSP_A: 1156 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1157 break; 1158 case SND_SOC_DAIFMT_DSP_B: 1159 ctrl1_val |= NAU8824_I2S_DF_PCM_AB; 1160 ctrl1_val |= NAU8824_I2S_PCMB_EN; 1161 break; 1162 default: 1163 return -EINVAL; 1164 } 1165 1166 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 1167 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK | 1168 NAU8824_I2S_PCMB_EN, ctrl1_val); 1169 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 1170 NAU8824_I2S_MS_MASK, ctrl2_val); 1171 1172 nau8824_sema_release(nau8824); 1173 1174 return 0; 1175 } 1176 1177 /** 1178 * nau8824_set_tdm_slot - configure DAI TDM. 1179 * @dai: DAI 1180 * @tx_mask: Bitmask representing active TX slots. Ex. 1181 * 0xf for normal 4 channel TDM. 1182 * 0xf0 for shifted 4 channel TDM 1183 * @rx_mask: Bitmask [0:1] representing active DACR RX slots. 1184 * Bitmask [2:3] representing active DACL RX slots. 1185 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex. 1186 * 0xf for DACL/R selecting TDM CH3. 1187 * 0xf0 for DACL/R selecting shifted TDM CH3. 1188 * @slots: Number of slots in use. 1189 * @slot_width: Width in bits for each slot. 1190 * 1191 * Configures a DAI for TDM operation. Only support 4 slots TDM. 1192 */ 1193 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai, 1194 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1195 { 1196 struct snd_soc_component *component = dai->component; 1197 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1198 unsigned int tslot_l = 0, ctrl_val = 0; 1199 1200 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) || 1201 ((rx_mask & 0xf0) && (rx_mask & 0xf)) || 1202 ((rx_mask & 0xf0) && (tx_mask & 0xf)) || 1203 ((rx_mask & 0xf) && (tx_mask & 0xf0))) 1204 return -EINVAL; 1205 1206 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN); 1207 if (tx_mask & 0xf0) { 1208 tslot_l = 4 * slot_width; 1209 ctrl_val |= (tx_mask >> 4); 1210 } else { 1211 ctrl_val |= tx_mask; 1212 } 1213 if (rx_mask & 0xf0) 1214 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT); 1215 else 1216 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT); 1217 1218 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL, 1219 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN | 1220 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK | 1221 NAU8824_TDM_TX_MASK, ctrl_val); 1222 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT, 1223 NAU8824_TSLOT_L_MASK, tslot_l); 1224 1225 return 0; 1226 } 1227 1228 /** 1229 * nau8824_calc_fll_param - Calculate FLL parameters. 1230 * @fll_in: external clock provided to codec. 1231 * @fs: sampling rate. 1232 * @fll_param: Pointer to structure of FLL parameters. 1233 * 1234 * Calculate FLL parameters to configure codec. 1235 * 1236 * Returns 0 for success or negative error code. 1237 */ 1238 static int nau8824_calc_fll_param(unsigned int fll_in, 1239 unsigned int fs, struct nau8824_fll *fll_param) 1240 { 1241 u64 fvco, fvco_max; 1242 unsigned int fref, i, fvco_sel; 1243 1244 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 1245 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1246 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK 1247 */ 1248 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1249 fref = fll_in / fll_pre_scalar[i].param; 1250 if (fref <= NAU_FREF_MAX) 1251 break; 1252 } 1253 if (i == ARRAY_SIZE(fll_pre_scalar)) 1254 return -EINVAL; 1255 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1256 1257 /* Choose the FLL ratio based on FREF */ 1258 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1259 if (fref >= fll_ratio[i].param) 1260 break; 1261 } 1262 if (i == ARRAY_SIZE(fll_ratio)) 1263 return -EINVAL; 1264 fll_param->ratio = fll_ratio[i].val; 1265 1266 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1267 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 1268 * guaranteed across the full range of operation. 1269 * FDCO = freq_out * 2 * mclk_src_scaling 1270 */ 1271 fvco_max = 0; 1272 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1273 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1274 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1275 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1276 fvco_max < fvco) { 1277 fvco_max = fvco; 1278 fvco_sel = i; 1279 } 1280 } 1281 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1282 return -EINVAL; 1283 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1284 1285 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 1286 * input based on FDCO, FREF and FLL ratio. 1287 */ 1288 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 1289 fll_param->fll_int = (fvco >> 16) & 0x3FF; 1290 fll_param->fll_frac = fvco & 0xFFFF; 1291 return 0; 1292 } 1293 1294 static void nau8824_fll_apply(struct regmap *regmap, 1295 struct nau8824_fll *fll_param) 1296 { 1297 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1298 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK, 1299 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src); 1300 regmap_update_bits(regmap, NAU8824_REG_FLL1, 1301 NAU8824_FLL_RATIO_MASK, fll_param->ratio); 1302 /* FLL 16-bit fractional input */ 1303 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac); 1304 /* FLL 10-bit integer input */ 1305 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1306 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int); 1307 /* FLL pre-scaler */ 1308 regmap_update_bits(regmap, NAU8824_REG_FLL4, 1309 NAU8824_FLL_REF_DIV_MASK, 1310 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT); 1311 /* select divided VCO input */ 1312 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1313 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF); 1314 /* Disable free-running mode */ 1315 regmap_update_bits(regmap, 1316 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); 1317 if (fll_param->fll_frac) { 1318 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1319 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1320 NAU8824_FLL_FTR_SW_MASK, 1321 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1322 NAU8824_FLL_FTR_SW_FILTER); 1323 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1324 NAU8824_SDM_EN, NAU8824_SDM_EN); 1325 } else { 1326 regmap_update_bits(regmap, NAU8824_REG_FLL5, 1327 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | 1328 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU); 1329 regmap_update_bits(regmap, 1330 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0); 1331 } 1332 } 1333 1334 /* freq_out must be 256*Fs in order to achieve the best performance */ 1335 static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source, 1336 unsigned int freq_in, unsigned int freq_out) 1337 { 1338 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1339 struct nau8824_fll fll_param; 1340 int ret, fs; 1341 1342 fs = freq_out / 256; 1343 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param); 1344 if (ret < 0) { 1345 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in); 1346 return ret; 1347 } 1348 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1349 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 1350 fll_param.fll_int, fll_param.clk_ref_div); 1351 1352 nau8824_fll_apply(nau8824->regmap, &fll_param); 1353 mdelay(2); 1354 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, 1355 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1356 1357 return 0; 1358 } 1359 1360 static int nau8824_config_sysclk(struct nau8824 *nau8824, 1361 int clk_id, unsigned int freq) 1362 { 1363 struct regmap *regmap = nau8824->regmap; 1364 1365 switch (clk_id) { 1366 case NAU8824_CLK_DIS: 1367 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1368 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1369 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1370 NAU8824_DCO_EN, 0); 1371 break; 1372 1373 case NAU8824_CLK_MCLK: 1374 nau8824_sema_acquire(nau8824, HZ); 1375 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1376 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); 1377 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1378 NAU8824_DCO_EN, 0); 1379 nau8824_sema_release(nau8824); 1380 break; 1381 1382 case NAU8824_CLK_INTERNAL: 1383 regmap_update_bits(regmap, NAU8824_REG_FLL6, 1384 NAU8824_DCO_EN, NAU8824_DCO_EN); 1385 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1386 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); 1387 break; 1388 1389 case NAU8824_CLK_FLL_MCLK: 1390 nau8824_sema_acquire(nau8824, HZ); 1391 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1392 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK); 1393 nau8824_sema_release(nau8824); 1394 break; 1395 1396 case NAU8824_CLK_FLL_BLK: 1397 nau8824_sema_acquire(nau8824, HZ); 1398 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1399 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK); 1400 nau8824_sema_release(nau8824); 1401 break; 1402 1403 case NAU8824_CLK_FLL_FS: 1404 nau8824_sema_acquire(nau8824, HZ); 1405 regmap_update_bits(regmap, NAU8824_REG_FLL3, 1406 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS); 1407 nau8824_sema_release(nau8824); 1408 break; 1409 1410 default: 1411 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id); 1412 return -EINVAL; 1413 } 1414 1415 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1416 clk_id); 1417 1418 return 0; 1419 } 1420 1421 static int nau8824_set_sysclk(struct snd_soc_component *component, 1422 int clk_id, int source, unsigned int freq, int dir) 1423 { 1424 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1425 1426 return nau8824_config_sysclk(nau8824, clk_id, freq); 1427 } 1428 1429 static void nau8824_resume_setup(struct nau8824 *nau8824) 1430 { 1431 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); 1432 if (nau8824->irq) { 1433 /* Clear all interruption status */ 1434 nau8824_int_status_clear_all(nau8824->regmap); 1435 /* Enable jack detection at sleep mode, insertion detection, 1436 * and ejection detection. 1437 */ 1438 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1439 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1440 regmap_update_bits(nau8824->regmap, 1441 NAU8824_REG_INTERRUPT_SETTING_1, 1442 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 1443 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN); 1444 regmap_update_bits(nau8824->regmap, 1445 NAU8824_REG_INTERRUPT_SETTING, 1446 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0); 1447 } 1448 } 1449 1450 static int nau8824_set_bias_level(struct snd_soc_component *component, 1451 enum snd_soc_bias_level level) 1452 { 1453 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1454 1455 switch (level) { 1456 case SND_SOC_BIAS_ON: 1457 break; 1458 1459 case SND_SOC_BIAS_PREPARE: 1460 break; 1461 1462 case SND_SOC_BIAS_STANDBY: 1463 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1464 /* Setup codec configuration after resume */ 1465 nau8824_resume_setup(nau8824); 1466 } 1467 break; 1468 1469 case SND_SOC_BIAS_OFF: 1470 regmap_update_bits(nau8824->regmap, 1471 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1472 regmap_update_bits(nau8824->regmap, 1473 NAU8824_REG_INTERRUPT_SETTING_1, 1474 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1475 break; 1476 } 1477 1478 return 0; 1479 } 1480 1481 static int nau8824_component_probe(struct snd_soc_component *component) 1482 { 1483 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1484 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1485 1486 nau8824->dapm = dapm; 1487 1488 return 0; 1489 } 1490 1491 static int __maybe_unused nau8824_suspend(struct snd_soc_component *component) 1492 { 1493 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1494 1495 if (nau8824->irq) { 1496 disable_irq(nau8824->irq); 1497 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 1498 } 1499 regcache_cache_only(nau8824->regmap, true); 1500 regcache_mark_dirty(nau8824->regmap); 1501 1502 return 0; 1503 } 1504 1505 static int __maybe_unused nau8824_resume(struct snd_soc_component *component) 1506 { 1507 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1508 1509 regcache_cache_only(nau8824->regmap, false); 1510 regcache_sync(nau8824->regmap); 1511 if (nau8824->irq) { 1512 /* Hold semaphore to postpone playback happening 1513 * until jack detection done. 1514 */ 1515 nau8824_sema_acquire(nau8824, 0); 1516 enable_irq(nau8824->irq); 1517 } 1518 1519 return 0; 1520 } 1521 1522 static const struct snd_soc_component_driver nau8824_component_driver = { 1523 .probe = nau8824_component_probe, 1524 .set_sysclk = nau8824_set_sysclk, 1525 .set_pll = nau8824_set_pll, 1526 .set_bias_level = nau8824_set_bias_level, 1527 .suspend = nau8824_suspend, 1528 .resume = nau8824_resume, 1529 .controls = nau8824_snd_controls, 1530 .num_controls = ARRAY_SIZE(nau8824_snd_controls), 1531 .dapm_widgets = nau8824_dapm_widgets, 1532 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets), 1533 .dapm_routes = nau8824_dapm_routes, 1534 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes), 1535 .suspend_bias_off = 1, 1536 .idle_bias_on = 1, 1537 .use_pmdown_time = 1, 1538 .endianness = 1, 1539 .non_legacy_dai_naming = 1, 1540 }; 1541 1542 static const struct snd_soc_dai_ops nau8824_dai_ops = { 1543 .hw_params = nau8824_hw_params, 1544 .set_fmt = nau8824_set_fmt, 1545 .set_tdm_slot = nau8824_set_tdm_slot, 1546 }; 1547 1548 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000 1549 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1550 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1551 1552 static struct snd_soc_dai_driver nau8824_dai = { 1553 .name = NAU8824_CODEC_DAI, 1554 .playback = { 1555 .stream_name = "Playback", 1556 .channels_min = 1, 1557 .channels_max = 2, 1558 .rates = NAU8824_RATES, 1559 .formats = NAU8824_FORMATS, 1560 }, 1561 .capture = { 1562 .stream_name = "Capture", 1563 .channels_min = 1, 1564 .channels_max = 2, 1565 .rates = NAU8824_RATES, 1566 .formats = NAU8824_FORMATS, 1567 }, 1568 .ops = &nau8824_dai_ops, 1569 }; 1570 1571 static const struct regmap_config nau8824_regmap_config = { 1572 .val_bits = NAU8824_REG_ADDR_LEN, 1573 .reg_bits = NAU8824_REG_DATA_LEN, 1574 1575 .max_register = NAU8824_REG_MAX, 1576 .readable_reg = nau8824_readable_reg, 1577 .writeable_reg = nau8824_writeable_reg, 1578 .volatile_reg = nau8824_volatile_reg, 1579 1580 .cache_type = REGCACHE_RBTREE, 1581 .reg_defaults = nau8824_reg_defaults, 1582 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults), 1583 }; 1584 1585 /** 1586 * nau8824_enable_jack_detect - Specify a jack for event reporting 1587 * 1588 * @component: component to register the jack with 1589 * @jack: jack to use to report headset and button events on 1590 * 1591 * After this function has been called the headset insert/remove and button 1592 * events will be routed to the given jack. Jack can be null to stop 1593 * reporting. 1594 */ 1595 int nau8824_enable_jack_detect(struct snd_soc_component *component, 1596 struct snd_soc_jack *jack) 1597 { 1598 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); 1599 int ret; 1600 1601 nau8824->jack = jack; 1602 /* Initiate jack detection work queue */ 1603 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work); 1604 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL, 1605 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1606 "nau8824", nau8824); 1607 if (ret) { 1608 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n", 1609 nau8824->irq, ret); 1610 } 1611 1612 return ret; 1613 } 1614 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect); 1615 1616 static void nau8824_reset_chip(struct regmap *regmap) 1617 { 1618 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1619 regmap_write(regmap, NAU8824_REG_RESET, 0x00); 1620 } 1621 1622 static void nau8824_setup_buttons(struct nau8824 *nau8824) 1623 { 1624 struct regmap *regmap = nau8824->regmap; 1625 1626 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1627 NAU8824_SAR_TRACKING_GAIN_MASK, 1628 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT); 1629 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1630 NAU8824_SAR_COMPARE_TIME_MASK, 1631 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT); 1632 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, 1633 NAU8824_SAR_SAMPLING_TIME_MASK, 1634 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT); 1635 1636 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1637 NAU8824_LEVELS_NR_MASK, 1638 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT); 1639 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1640 NAU8824_HYSTERESIS_MASK, 1641 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT); 1642 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, 1643 NAU8824_SHORTKEY_DEBOUNCE_MASK, 1644 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT); 1645 1646 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1, 1647 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]); 1648 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2, 1649 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]); 1650 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3, 1651 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]); 1652 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4, 1653 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]); 1654 } 1655 1656 static void nau8824_init_regs(struct nau8824 *nau8824) 1657 { 1658 struct regmap *regmap = nau8824->regmap; 1659 1660 /* Enable Bias/VMID/VMID Tieoff */ 1661 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ, 1662 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID | 1663 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT)); 1664 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1665 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN); 1666 mdelay(2); 1667 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS, 1668 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage); 1669 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1670 regmap_update_bits(regmap, NAU8824_REG_BOOST, 1671 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1672 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN, 1673 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | 1674 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN); 1675 /* Scaling for ADC and DAC clock */ 1676 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, 1677 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK, 1678 (0x1 << NAU8824_CLK_ADC_SRC_SFT) | 1679 (0x1 << NAU8824_CLK_DAC_SRC_SFT)); 1680 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL, 1681 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN); 1682 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, 1683 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1684 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1685 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN, 1686 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | 1687 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | 1688 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN); 1689 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA, 1690 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1691 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1692 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1693 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN, 1694 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | 1695 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | 1696 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | 1697 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN); 1698 /* Class G timer 64ms */ 1699 regmap_update_bits(regmap, NAU8824_REG_CLASSG, 1700 NAU8824_CLASSG_TIMER_MASK, 1701 0x20 << NAU8824_CLASSG_TIMER_SFT); 1702 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS, 1703 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC); 1704 /* Disable DACR/L power */ 1705 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL, 1706 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1707 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL, 1708 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | 1709 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL); 1710 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input 1711 * signal to avoid any glitches due to power up transients in both 1712 * the analog and digital DAC circuit. 1713 */ 1714 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1715 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); 1716 /* Config L/R channel */ 1717 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL, 1718 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0); 1719 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL, 1720 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1); 1721 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, 1722 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN, 1723 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN); 1724 /* Default oversampling/decimations settings are unusable 1725 * (audible hiss). Set it to something better. 1726 */ 1727 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL, 1728 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64); 1729 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1, 1730 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK, 1731 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64); 1732 /* DAC clock delay 2ns, VREF */ 1733 regmap_update_bits(regmap, NAU8824_REG_RDAC, 1734 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK, 1735 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) | 1736 (0x3 << NAU8824_RDAC_VREF_SFT)); 1737 /* PGA input mode selection */ 1738 regmap_update_bits(regmap, NAU8824_REG_FEPGA, 1739 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN, 1740 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN); 1741 /* Digital microphone control */ 1742 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1, 1743 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST, 1744 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST); 1745 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL, 1746 NAU8824_JACK_LOGIC, 1747 /* jkdet_polarity - 1 is for active-low */ 1748 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC); 1749 regmap_update_bits(regmap, 1750 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK, 1751 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT)); 1752 if (nau8824->sar_threshold_num) 1753 nau8824_setup_buttons(nau8824); 1754 } 1755 1756 static int nau8824_setup_irq(struct nau8824 *nau8824) 1757 { 1758 /* Disable interruption before codec initiation done */ 1759 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, 1760 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); 1761 regmap_update_bits(nau8824->regmap, 1762 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); 1763 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1, 1764 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); 1765 1766 return 0; 1767 } 1768 1769 static void nau8824_print_device_properties(struct nau8824 *nau8824) 1770 { 1771 struct device *dev = nau8824->dev; 1772 int i; 1773 1774 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity); 1775 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage); 1776 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance); 1777 1778 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num); 1779 for (i = 0; i < nau8824->sar_threshold_num; i++) 1780 dev_dbg(dev, "sar-threshold[%d]=%x\n", i, 1781 nau8824->sar_threshold[i]); 1782 1783 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis); 1784 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage); 1785 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time); 1786 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time); 1787 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce); 1788 dev_dbg(dev, "jack-eject-debounce: %d\n", 1789 nau8824->jack_eject_debounce); 1790 } 1791 1792 static int nau8824_read_device_properties(struct device *dev, 1793 struct nau8824 *nau8824) { 1794 int ret; 1795 1796 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1797 &nau8824->jkdet_polarity); 1798 if (ret) 1799 nau8824->jkdet_polarity = 1; 1800 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1801 &nau8824->micbias_voltage); 1802 if (ret) 1803 nau8824->micbias_voltage = 6; 1804 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1805 &nau8824->vref_impedance); 1806 if (ret) 1807 nau8824->vref_impedance = 2; 1808 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", 1809 &nau8824->sar_threshold_num); 1810 if (ret) 1811 nau8824->sar_threshold_num = 4; 1812 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", 1813 nau8824->sar_threshold, nau8824->sar_threshold_num); 1814 if (ret) { 1815 nau8824->sar_threshold[0] = 0x0a; 1816 nau8824->sar_threshold[1] = 0x14; 1817 nau8824->sar_threshold[2] = 0x26; 1818 nau8824->sar_threshold[3] = 0x73; 1819 } 1820 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", 1821 &nau8824->sar_hysteresis); 1822 if (ret) 1823 nau8824->sar_hysteresis = 0; 1824 ret = device_property_read_u32(dev, "nuvoton,sar-voltage", 1825 &nau8824->sar_voltage); 1826 if (ret) 1827 nau8824->sar_voltage = 6; 1828 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", 1829 &nau8824->sar_compare_time); 1830 if (ret) 1831 nau8824->sar_compare_time = 1; 1832 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", 1833 &nau8824->sar_sampling_time); 1834 if (ret) 1835 nau8824->sar_sampling_time = 1; 1836 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", 1837 &nau8824->key_debounce); 1838 if (ret) 1839 nau8824->key_debounce = 0; 1840 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1841 &nau8824->jack_eject_debounce); 1842 if (ret) 1843 nau8824->jack_eject_debounce = 1; 1844 1845 return 0; 1846 } 1847 1848 static int nau8824_i2c_probe(struct i2c_client *i2c, 1849 const struct i2c_device_id *id) 1850 { 1851 struct device *dev = &i2c->dev; 1852 struct nau8824 *nau8824 = dev_get_platdata(dev); 1853 int ret, value; 1854 1855 if (!nau8824) { 1856 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL); 1857 if (!nau8824) 1858 return -ENOMEM; 1859 ret = nau8824_read_device_properties(dev, nau8824); 1860 if (ret) 1861 return ret; 1862 } 1863 i2c_set_clientdata(i2c, nau8824); 1864 1865 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config); 1866 if (IS_ERR(nau8824->regmap)) 1867 return PTR_ERR(nau8824->regmap); 1868 nau8824->dev = dev; 1869 nau8824->irq = i2c->irq; 1870 sema_init(&nau8824->jd_sem, 1); 1871 1872 nau8824_print_device_properties(nau8824); 1873 1874 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value); 1875 if (ret < 0) { 1876 dev_err(dev, "Failed to read device id from the NAU8824: %d\n", 1877 ret); 1878 return ret; 1879 } 1880 nau8824_reset_chip(nau8824->regmap); 1881 nau8824_init_regs(nau8824); 1882 1883 if (i2c->irq) 1884 nau8824_setup_irq(nau8824); 1885 1886 return devm_snd_soc_register_component(dev, 1887 &nau8824_component_driver, &nau8824_dai, 1); 1888 } 1889 1890 static const struct i2c_device_id nau8824_i2c_ids[] = { 1891 { "nau8824", 0 }, 1892 { } 1893 }; 1894 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids); 1895 1896 #ifdef CONFIG_OF 1897 static const struct of_device_id nau8824_of_ids[] = { 1898 { .compatible = "nuvoton,nau8824", }, 1899 {} 1900 }; 1901 MODULE_DEVICE_TABLE(of, nau8824_of_ids); 1902 #endif 1903 1904 #ifdef CONFIG_ACPI 1905 static const struct acpi_device_id nau8824_acpi_match[] = { 1906 { "10508824", 0 }, 1907 {}, 1908 }; 1909 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match); 1910 #endif 1911 1912 static struct i2c_driver nau8824_i2c_driver = { 1913 .driver = { 1914 .name = "nau8824", 1915 .of_match_table = of_match_ptr(nau8824_of_ids), 1916 .acpi_match_table = ACPI_PTR(nau8824_acpi_match), 1917 }, 1918 .probe = nau8824_i2c_probe, 1919 .id_table = nau8824_i2c_ids, 1920 }; 1921 module_i2c_driver(nau8824_i2c_driver); 1922 1923 1924 MODULE_DESCRIPTION("ASoC NAU88L24 driver"); 1925 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); 1926 MODULE_LICENSE("GPL v2"); 1927