1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver 4 // 5 // Copyright 2021 Nuvoton Technology Corp. 6 // Author: John Hsu <kchsu0@nuvoton.com> 7 // Co-author: Seven Lee <wtli@nuvoton.com> 8 // 9 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmi.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/module.h> 17 #include <linux/math64.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <sound/core.h> 21 #include <sound/initval.h> 22 #include <sound/jack.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/tlv.h> 27 #include "nau8821.h" 28 29 #define NAU8821_JD_ACTIVE_HIGH BIT(0) 30 31 static int nau8821_quirk; 32 static int quirk_override = -1; 33 module_param_named(quirk, quirk_override, uint, 0444); 34 MODULE_PARM_DESC(quirk, "Board-specific quirk override"); 35 36 #define NAU_FREF_MAX 13500000 37 #define NAU_FVCO_MAX 100000000 38 #define NAU_FVCO_MIN 90000000 39 40 #define NAU8821_BUTTON SND_JACK_BTN_0 41 42 /* the maximum frequency of CLK_ADC and CLK_DAC */ 43 #define CLK_DA_AD_MAX 6144000 44 45 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 46 int clk_id, unsigned int freq); 47 static bool nau8821_is_jack_inserted(struct regmap *regmap); 48 49 struct nau8821_fll { 50 int mclk_src; 51 int ratio; 52 int fll_frac; 53 int fll_int; 54 int clk_ref_div; 55 }; 56 57 struct nau8821_fll_attr { 58 unsigned int param; 59 unsigned int val; 60 }; 61 62 /* scaling for mclk from sysclk_src output */ 63 static const struct nau8821_fll_attr mclk_src_scaling[] = { 64 { 1, 0x0 }, 65 { 2, 0x2 }, 66 { 4, 0x3 }, 67 { 8, 0x4 }, 68 { 16, 0x5 }, 69 { 32, 0x6 }, 70 { 3, 0x7 }, 71 { 6, 0xa }, 72 { 12, 0xb }, 73 { 24, 0xc }, 74 { 48, 0xd }, 75 { 96, 0xe }, 76 { 5, 0xf }, 77 }; 78 79 /* ratio for input clk freq */ 80 static const struct nau8821_fll_attr fll_ratio[] = { 81 { 512000, 0x01 }, 82 { 256000, 0x02 }, 83 { 128000, 0x04 }, 84 { 64000, 0x08 }, 85 { 32000, 0x10 }, 86 { 8000, 0x20 }, 87 { 4000, 0x40 }, 88 }; 89 90 static const struct nau8821_fll_attr fll_pre_scalar[] = { 91 { 0, 0x0 }, 92 { 1, 0x1 }, 93 { 2, 0x2 }, 94 { 3, 0x3 }, 95 }; 96 97 /* over sampling rate */ 98 struct nau8821_osr_attr { 99 unsigned int osr; 100 unsigned int clk_src; 101 }; 102 103 static const struct nau8821_osr_attr osr_dac_sel[] = { 104 { 64, 2 }, /* OSR 64, SRC 1/4 */ 105 { 256, 0 }, /* OSR 256, SRC 1 */ 106 { 128, 1 }, /* OSR 128, SRC 1/2 */ 107 { 0, 0 }, 108 { 32, 3 }, /* OSR 32, SRC 1/8 */ 109 }; 110 111 static const struct nau8821_osr_attr osr_adc_sel[] = { 112 { 32, 3 }, /* OSR 32, SRC 1/8 */ 113 { 64, 2 }, /* OSR 64, SRC 1/4 */ 114 { 128, 1 }, /* OSR 128, SRC 1/2 */ 115 { 256, 0 }, /* OSR 256, SRC 1 */ 116 }; 117 118 struct nau8821_dmic_speed { 119 unsigned int param; 120 unsigned int val; 121 }; 122 123 static const struct nau8821_dmic_speed dmic_speed_sel[] = { 124 { 0, 0x0 }, /*SPEED 1, SRC 1 */ 125 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */ 126 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */ 127 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */ 128 }; 129 130 static const struct reg_default nau8821_reg_defaults[] = { 131 { NAU8821_R01_ENA_CTRL, 0x00ff }, 132 { NAU8821_R03_CLK_DIVIDER, 0x0050 }, 133 { NAU8821_R04_FLL1, 0x0 }, 134 { NAU8821_R05_FLL2, 0x00bc }, 135 { NAU8821_R06_FLL3, 0x0008 }, 136 { NAU8821_R07_FLL4, 0x0010 }, 137 { NAU8821_R08_FLL5, 0x4000 }, 138 { NAU8821_R09_FLL6, 0x6900 }, 139 { NAU8821_R0A_FLL7, 0x0031 }, 140 { NAU8821_R0B_FLL8, 0x26e9 }, 141 { NAU8821_R0D_JACK_DET_CTRL, 0x0 }, 142 { NAU8821_R0F_INTERRUPT_MASK, 0x0 }, 143 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff }, 144 { NAU8821_R13_DMIC_CTRL, 0x0 }, 145 { NAU8821_R1A_GPIO12_CTRL, 0x0 }, 146 { NAU8821_R1B_TDM_CTRL, 0x0 }, 147 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a }, 148 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 }, 149 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 }, 150 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 }, 151 { NAU8821_R21_BIQ0_COF1, 0x0 }, 152 { NAU8821_R22_BIQ0_COF2, 0x0 }, 153 { NAU8821_R23_BIQ0_COF3, 0x0 }, 154 { NAU8821_R24_BIQ0_COF4, 0x0 }, 155 { NAU8821_R25_BIQ0_COF5, 0x0 }, 156 { NAU8821_R26_BIQ0_COF6, 0x0 }, 157 { NAU8821_R27_BIQ0_COF7, 0x0 }, 158 { NAU8821_R28_BIQ0_COF8, 0x0 }, 159 { NAU8821_R29_BIQ0_COF9, 0x0 }, 160 { NAU8821_R2A_BIQ0_COF10, 0x0 }, 161 { NAU8821_R2B_ADC_RATE, 0x0002 }, 162 { NAU8821_R2C_DAC_CTRL1, 0x0082 }, 163 { NAU8821_R2D_DAC_CTRL2, 0x0 }, 164 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 }, 165 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 }, 166 { NAU8821_R31_MUTE_CTRL, 0x0 }, 167 { NAU8821_R32_HSVOL_CTRL, 0x0 }, 168 { NAU8821_R34_DACR_CTRL, 0xcfcf }, 169 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf }, 170 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 }, 171 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 }, 172 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff }, 173 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 }, 174 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 }, 175 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 }, 176 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 }, 177 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 }, 178 { NAU8821_R41_BIQ1_COF1, 0x0 }, 179 { NAU8821_R42_BIQ1_COF2, 0x0 }, 180 { NAU8821_R43_BIQ1_COF3, 0x0 }, 181 { NAU8821_R44_BIQ1_COF4, 0x0 }, 182 { NAU8821_R45_BIQ1_COF5, 0x0 }, 183 { NAU8821_R46_BIQ1_COF6, 0x0 }, 184 { NAU8821_R47_BIQ1_COF7, 0x0 }, 185 { NAU8821_R48_BIQ1_COF8, 0x0 }, 186 { NAU8821_R49_BIQ1_COF9, 0x0 }, 187 { NAU8821_R4A_BIQ1_COF10, 0x0 }, 188 { NAU8821_R4B_CLASSG_CTRL, 0x0 }, 189 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 }, 190 { NAU8821_R4D_IMM_RMS_L, 0x0 }, 191 { NAU8821_R53_OTPDOUT_1, 0xaad8 }, 192 { NAU8821_R54_OTPDOUT_2, 0x0002 }, 193 { NAU8821_R55_MISC_CTRL, 0x0 }, 194 { NAU8821_R66_BIAS_ADJ, 0x0 }, 195 { NAU8821_R68_TRIM_SETTINGS, 0x0 }, 196 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 }, 197 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 }, 198 { NAU8821_R6B_PGA_MUTE, 0x0 }, 199 { NAU8821_R71_ANALOG_ADC_1, 0x0011 }, 200 { NAU8821_R72_ANALOG_ADC_2, 0x0020 }, 201 { NAU8821_R73_RDAC, 0x0008 }, 202 { NAU8821_R74_MIC_BIAS, 0x0006 }, 203 { NAU8821_R76_BOOST, 0x0 }, 204 { NAU8821_R77_FEPGA, 0x0 }, 205 { NAU8821_R7E_PGA_GAIN, 0x0 }, 206 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 }, 207 { NAU8821_R80_CHARGE_PUMP, 0x0 }, 208 }; 209 210 static bool nau8821_readable_reg(struct device *dev, unsigned int reg) 211 { 212 switch (reg) { 213 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 214 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 215 case NAU8821_R0D_JACK_DET_CTRL: 216 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL: 217 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 218 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 219 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 220 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 221 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3: 222 case NAU8821_R51_FUSE_CTRL1: 223 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL: 224 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 225 case NAU8821_R66_BIAS_ADJ: 226 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 227 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 228 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 229 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS: 230 return true; 231 default: 232 return false; 233 } 234 } 235 236 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg) 237 { 238 switch (reg) { 239 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 240 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 241 case NAU8821_R0D_JACK_DET_CTRL: 242 case NAU8821_R0F_INTERRUPT_MASK: 243 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL: 244 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 245 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 246 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 247 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 248 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL: 249 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3: 250 case NAU8821_R51_FUSE_CTRL1: 251 case NAU8821_R55_MISC_CTRL: 252 case NAU8821_R5A_SOFTWARE_RST: 253 case NAU8821_R66_BIAS_ADJ: 254 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 255 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 256 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 257 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg) 265 { 266 switch (reg) { 267 case NAU8821_R00_RESET: 268 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS: 269 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10: 270 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10: 271 case NAU8821_R4D_IMM_RMS_L: 272 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2: 273 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 274 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS: 275 return true; 276 default: 277 return false; 278 } 279 } 280 281 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol, 282 struct snd_ctl_elem_value *ucontrol) 283 { 284 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 285 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 286 287 if (!component->regmap) 288 return -EINVAL; 289 290 return regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1, 291 ucontrol->value.bytes.data, params->max); 292 } 293 294 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol, 295 struct snd_ctl_elem_value *ucontrol) 296 { 297 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 298 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 299 void *data; 300 int ret; 301 302 if (!component->regmap) 303 return -EINVAL; 304 305 data = kmemdup(ucontrol->value.bytes.data, 306 params->max, GFP_KERNEL | GFP_DMA); 307 if (!data) 308 return -ENOMEM; 309 310 ret = regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1, 311 data, params->max); 312 313 kfree(data); 314 315 return ret; 316 } 317 318 static const char * const nau8821_adc_decimation[] = { 319 "32", "64", "128", "256" }; 320 321 static const struct soc_enum nau8821_adc_decimation_enum = 322 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT, 323 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation); 324 325 static const char * const nau8821_dac_oversampl[] = { 326 "64", "256", "128", "", "32" }; 327 328 static const struct soc_enum nau8821_dac_oversampl_enum = 329 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT, 330 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl); 331 332 static const char * const nau8821_adc_drc_noise_gate[] = { 333 "1:1", "2:1", "4:1", "8:1" }; 334 335 static const struct soc_enum nau8821_adc_drc_noise_gate_enum = 336 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT, 337 ARRAY_SIZE(nau8821_adc_drc_noise_gate), 338 nau8821_adc_drc_noise_gate); 339 340 static const char * const nau8821_adc_drc_expansion_slope[] = { 341 "1:1", "2:1", "4:1" }; 342 343 static const struct soc_enum nau8821_adc_drc_expansion_slope_enum = 344 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT, 345 ARRAY_SIZE(nau8821_adc_drc_expansion_slope), 346 nau8821_adc_drc_expansion_slope); 347 348 static const char * const nau8821_adc_drc_lower_region[] = { 349 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 350 351 static const struct soc_enum nau8821_adc_drc_lower_region_enum = 352 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 353 NAU8821_DRC_CMP2_SLP_ADC_SFT, 354 ARRAY_SIZE(nau8821_adc_drc_lower_region), 355 nau8821_adc_drc_lower_region); 356 357 static const char * const nau8821_higher_region[] = { 358 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 359 360 static const struct soc_enum nau8821_higher_region_enum = 361 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 362 NAU8821_DRC_CMP1_SLP_ADC_SFT, 363 ARRAY_SIZE(nau8821_higher_region), 364 nau8821_higher_region); 365 366 static const char * const nau8821_limiter_slope[] = { 367 "0", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" }; 368 369 static const struct soc_enum nau8821_limiter_slope_enum = 370 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 371 NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope), 372 nau8821_limiter_slope); 373 374 static const char * const nau8821_detection_attack_time[] = { 375 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 376 "", "511Ts" }; 377 378 static const struct soc_enum nau8821_detection_attack_time_enum = 379 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 380 NAU8821_DRC_PK_COEF1_ADC_SFT, 381 ARRAY_SIZE(nau8821_detection_attack_time), 382 nau8821_detection_attack_time); 383 384 static const char * const nau8821_detection_release_time[] = { 385 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 386 "8191Ts", "", "16383Ts" }; 387 388 static const struct soc_enum nau8821_detection_release_time_enum = 389 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 390 NAU8821_DRC_PK_COEF2_ADC_SFT, 391 ARRAY_SIZE(nau8821_detection_release_time), 392 nau8821_detection_release_time); 393 394 static const char * const nau8821_attack_time[] = { 395 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 396 "511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" }; 397 398 static const struct soc_enum nau8821_attack_time_enum = 399 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT, 400 ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time); 401 402 static const char * const nau8821_decay_time[] = { 403 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 404 "8191Ts", "16383Ts", "32757Ts", "65535Ts" }; 405 406 static const struct soc_enum nau8821_decay_time_enum = 407 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT, 408 ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time); 409 410 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400); 411 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 412 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0); 413 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1); 414 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 415 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400); 416 static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500); 417 static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800); 418 419 static const struct snd_kcontrol_new nau8821_controls[] = { 420 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1, 421 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT, 422 0xff, 0, adc_vol_tlv), 423 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL, 424 12, 8, 0x0f, 0, sidetone_vol_tlv), 425 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL, 426 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv), 427 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL, 428 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT, 429 0xcf, 0, playback_vol_tlv), 430 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN, 431 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT, 432 37, 0, fepga_gain_tlv), 433 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", 434 NAU8821_R2F_DAC_DGAIN_CTRL, 435 0, 8, 0xff, 0, crosstalk_vol_tlv), 436 SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34, 437 NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv), 438 SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34, 439 NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv), 440 441 SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum), 442 SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum), 443 SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum), 444 SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum), 445 SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum), 446 SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum), 447 SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum), 448 SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum), 449 SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum), 450 SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12, 451 NAU8821_DRC_ENA_ADC_SFT, 1, 0), 452 453 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum), 454 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum), 455 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 456 nau8821_biq_coeff_get, nau8821_biq_coeff_put), 457 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL, 458 NAU8821_ADCPHS_SFT, 1, 0), 459 }; 460 461 static const struct snd_kcontrol_new nau8821_dmic_mode_switch = 462 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL, 463 NAU8821_DMIC_EN_SFT, 1, 0); 464 465 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 466 struct snd_kcontrol *k, int event) 467 { 468 struct snd_soc_component *component = 469 snd_soc_dapm_to_component(w->dapm); 470 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 471 int i, speed_selection = -1, clk_adc_src, clk_adc; 472 unsigned int clk_divider_r03; 473 474 /* The DMIC clock is gotten from adc clock divided by 475 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or 476 * less than nau8821->dmic_clk_threshold. 477 */ 478 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 479 &clk_divider_r03); 480 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK) 481 >> NAU8821_CLK_ADC_SRC_SFT; 482 clk_adc = (nau8821->fs * 256) >> clk_adc_src; 483 484 for (i = 0 ; i < 4 ; i++) 485 if ((clk_adc >> dmic_speed_sel[i].param) <= 486 nau8821->dmic_clk_threshold) { 487 speed_selection = dmic_speed_sel[i].val; 488 break; 489 } 490 if (i == 4) 491 return -EINVAL; 492 493 dev_dbg(nau8821->dev, 494 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n", 495 clk_adc, nau8821->dmic_clk_threshold, 496 dmic_speed_sel[i].param, dmic_speed_sel[i].val); 497 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL, 498 NAU8821_DMIC_SRC_MASK, 499 (speed_selection << NAU8821_DMIC_SRC_SFT)); 500 501 return 0; 502 } 503 504 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w, 505 struct snd_kcontrol *kcontrol, int event) 506 { 507 struct snd_soc_component *component = 508 snd_soc_dapm_to_component(w->dapm); 509 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 510 511 switch (event) { 512 case SND_SOC_DAPM_POST_PMU: 513 msleep(nau8821->adc_delay); 514 break; 515 case SND_SOC_DAPM_POST_PMD: 516 break; 517 default: 518 return -EINVAL; 519 } 520 521 return 0; 522 } 523 524 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w, 525 struct snd_kcontrol *kcontrol, int event) 526 { 527 struct snd_soc_component *component = 528 snd_soc_dapm_to_component(w->dapm); 529 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 530 531 switch (event) { 532 case SND_SOC_DAPM_POST_PMU: 533 msleep(nau8821->adc_delay); 534 break; 535 case SND_SOC_DAPM_POST_PMD: 536 break; 537 default: 538 return -EINVAL; 539 } 540 541 return 0; 542 } 543 544 static int nau8821_pump_event(struct snd_soc_dapm_widget *w, 545 struct snd_kcontrol *kcontrol, int event) 546 { 547 struct snd_soc_component *component = 548 snd_soc_dapm_to_component(w->dapm); 549 struct nau8821 *nau8821 = 550 snd_soc_component_get_drvdata(component); 551 552 switch (event) { 553 case SND_SOC_DAPM_POST_PMU: 554 /* Prevent startup click by letting charge pump to ramp up */ 555 msleep(20); 556 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 557 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW); 558 break; 559 case SND_SOC_DAPM_PRE_PMD: 560 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 561 NAU8821_JAMNODCLOW, 0); 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 return 0; 568 } 569 570 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w, 571 struct snd_kcontrol *kcontrol, int event) 572 { 573 struct snd_soc_component *component = 574 snd_soc_dapm_to_component(w->dapm); 575 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 576 577 switch (event) { 578 case SND_SOC_DAPM_PRE_PMU: 579 /* Disables the TESTDAC to let DAC signal pass through. */ 580 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 581 NAU8821_BIAS_TESTDAC_EN, 0); 582 break; 583 case SND_SOC_DAPM_POST_PMD: 584 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 585 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN); 586 break; 587 default: 588 return -EINVAL; 589 } 590 591 return 0; 592 } 593 594 static int system_clock_control(struct snd_soc_dapm_widget *w, 595 struct snd_kcontrol *k, int event) 596 { 597 struct snd_soc_component *component = 598 snd_soc_dapm_to_component(w->dapm); 599 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 600 601 if (SND_SOC_DAPM_EVENT_OFF(event)) { 602 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n"); 603 /* Set clock source to disable or internal clock before the 604 * playback or capture end. Codec needs clock for Jack 605 * detection and button press if jack inserted; otherwise, 606 * the clock should be closed. 607 */ 608 if (nau8821_is_jack_inserted(nau8821->regmap)) { 609 nau8821_configure_sysclk(nau8821, 610 NAU8821_CLK_INTERNAL, 0); 611 } else { 612 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 613 } 614 } 615 return 0; 616 } 617 618 static int nau8821_left_fepga_event(struct snd_soc_dapm_widget *w, 619 struct snd_kcontrol *kcontrol, int event) 620 { 621 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 622 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 623 624 if (!nau8821->left_input_single_end) 625 return 0; 626 627 switch (event) { 628 case SND_SOC_DAPM_POST_PMU: 629 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 630 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 631 NAU8821_ACDC_VREF_MICN | NAU8821_FEPGA_MODEL_AAF); 632 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 633 NAU8821_HP_BOOST_DISCHRG_EN, NAU8821_HP_BOOST_DISCHRG_EN); 634 break; 635 case SND_SOC_DAPM_POST_PMD: 636 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 637 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 0); 638 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 639 NAU8821_HP_BOOST_DISCHRG_EN, 0); 640 break; 641 default: 642 break; 643 } 644 645 return 0; 646 } 647 648 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = { 649 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 650 system_clock_control, SND_SOC_DAPM_POST_PMD), 651 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS, 652 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0), 653 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 654 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 655 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2, 656 NAU8821_POWERUP_ADCL_SFT, 0), 657 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2, 658 NAU8821_POWERUP_ADCR_SFT, 0), 659 /* single-ended design only on the left */ 660 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL, 661 NAU8821_PUP_PGA_L_SFT, 0, nau8821_left_fepga_event, 662 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 663 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL, 664 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0), 665 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL, 666 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event, 667 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 668 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL, 669 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event, 670 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 671 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM, 672 0, 0, &nau8821_dmic_mode_switch), 673 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2, 674 NAU8821_I2S_TRISTATE_SFT, 1), 675 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 676 677 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC, 678 NAU8821_DACL_EN_SFT, 0, NULL, 0), 679 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC, 680 NAU8821_DACR_EN_SFT, 0, NULL, 0), 681 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC, 682 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0), 683 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC, 684 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0), 685 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL, 686 NAU8821_EN_DACR_SFT, 0), 687 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL, 688 NAU8821_EN_DACL_SFT, 0), 689 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL, 690 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0), 691 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL, 692 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0), 693 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP, 694 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event, 695 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 696 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 697 NAU8821_R7F_POWER_UP_CONTROL, 698 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0), 699 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 700 NAU8821_R7F_POWER_UP_CONTROL, 701 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0), 702 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 703 NAU8821_R7F_POWER_UP_CONTROL, 704 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0), 705 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 706 NAU8821_R7F_POWER_UP_CONTROL, 707 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0), 708 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 709 NAU8821_R7F_POWER_UP_CONTROL, 710 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0), 711 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 712 NAU8821_R7F_POWER_UP_CONTROL, 713 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0), 714 SND_SOC_DAPM_PGA_S("Output DACL", 7, 715 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT, 716 0, nau8821_output_dac_event, 717 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 718 SND_SOC_DAPM_PGA_S("Output DACR", 7, 719 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT, 720 0, nau8821_output_dac_event, 721 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 722 723 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 724 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 725 NAU8821_R0D_JACK_DET_CTRL, 726 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0), 727 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 728 NAU8821_R0D_JACK_DET_CTRL, 729 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0), 730 731 /* High current HPOL/R boost driver */ 732 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 733 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0), 734 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL, 735 NAU8821_CLASSG_EN_SFT, 0, NULL, 0), 736 737 SND_SOC_DAPM_INPUT("MICL"), 738 SND_SOC_DAPM_INPUT("MICR"), 739 SND_SOC_DAPM_INPUT("DMIC"), 740 SND_SOC_DAPM_OUTPUT("HPOL"), 741 SND_SOC_DAPM_OUTPUT("HPOR"), 742 }; 743 744 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = { 745 {"DMIC Enable", "Switch", "DMIC"}, 746 {"DMIC Enable", NULL, "DMIC Clock"}, 747 748 {"Frontend PGA L", NULL, "MICL"}, 749 {"Frontend PGA R", NULL, "MICR"}, 750 {"Frontend PGA L", NULL, "MICBIAS"}, 751 {"Frontend PGA R", NULL, "MICBIAS"}, 752 753 {"ADCL Power", NULL, "Frontend PGA L"}, 754 {"ADCR Power", NULL, "Frontend PGA R"}, 755 756 {"ADCL Digital path", NULL, "ADCL Power"}, 757 {"ADCR Digital path", NULL, "ADCR Power"}, 758 {"ADCL Digital path", NULL, "DMIC Enable"}, 759 {"ADCR Digital path", NULL, "DMIC Enable"}, 760 761 {"AIFTX", NULL, "ADCL Digital path"}, 762 {"AIFTX", NULL, "ADCR Digital path"}, 763 764 {"AIFTX", NULL, "System Clock"}, 765 {"AIFRX", NULL, "System Clock"}, 766 767 {"DDACL", NULL, "AIFRX"}, 768 {"DDACR", NULL, "AIFRX"}, 769 770 {"HP amp L", NULL, "DDACL"}, 771 {"HP amp R", NULL, "DDACR"}, 772 773 {"Charge Pump", NULL, "HP amp L"}, 774 {"Charge Pump", NULL, "HP amp R"}, 775 776 {"ADACL", NULL, "Charge Pump"}, 777 {"ADACR", NULL, "Charge Pump"}, 778 {"ADACL Clock", NULL, "ADACL"}, 779 {"ADACR Clock", NULL, "ADACR"}, 780 781 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 782 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 783 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 784 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 785 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 786 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 787 {"Output DACL", NULL, "Output Driver L Stage 3"}, 788 {"Output DACR", NULL, "Output Driver R Stage 3"}, 789 790 {"HPOL Pulldown", NULL, "Output DACL"}, 791 {"HPOR Pulldown", NULL, "Output DACR"}, 792 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 793 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 794 795 {"Class G", NULL, "HP Boost Driver"}, 796 {"HPOL", NULL, "Class G"}, 797 {"HPOR", NULL, "Class G"}, 798 }; 799 800 static const struct nau8821_osr_attr * 801 nau8821_get_osr(struct nau8821 *nau8821, int stream) 802 { 803 unsigned int osr; 804 805 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 806 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr); 807 osr &= NAU8821_DAC_OVERSAMPLE_MASK; 808 if (osr >= ARRAY_SIZE(osr_dac_sel)) 809 return NULL; 810 return &osr_dac_sel[osr]; 811 } else { 812 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr); 813 osr &= NAU8821_ADC_SYNC_DOWN_MASK; 814 if (osr >= ARRAY_SIZE(osr_adc_sel)) 815 return NULL; 816 return &osr_adc_sel[osr]; 817 } 818 } 819 820 static int nau8821_dai_startup(struct snd_pcm_substream *substream, 821 struct snd_soc_dai *dai) 822 { 823 struct snd_soc_component *component = dai->component; 824 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 825 const struct nau8821_osr_attr *osr; 826 827 osr = nau8821_get_osr(nau8821, substream->stream); 828 if (!osr || !osr->osr) 829 return -EINVAL; 830 831 return snd_pcm_hw_constraint_minmax(substream->runtime, 832 SNDRV_PCM_HW_PARAM_RATE, 833 0, CLK_DA_AD_MAX / osr->osr); 834 } 835 836 static int nau8821_hw_params(struct snd_pcm_substream *substream, 837 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 838 { 839 struct snd_soc_component *component = dai->component; 840 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 841 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div; 842 const struct nau8821_osr_attr *osr; 843 844 nau8821->fs = params_rate(params); 845 /* CLK_DAC or CLK_ADC = OSR * FS 846 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 847 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 848 * values must be selected such that the maximum frequency is less 849 * than 6.144 MHz. 850 */ 851 osr = nau8821_get_osr(nau8821, substream->stream); 852 if (!osr || !osr->osr) 853 return -EINVAL; 854 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX) 855 return -EINVAL; 856 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 857 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 858 NAU8821_CLK_DAC_SRC_MASK, 859 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT); 860 else 861 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 862 NAU8821_CLK_ADC_SRC_MASK, 863 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT); 864 865 /* make BCLK and LRC divde configuration if the codec as master. */ 866 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val); 867 if (ctrl_val & NAU8821_I2S_MS_MASTER) { 868 /* get the bclk and fs ratio */ 869 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs; 870 if (bclk_fs <= 32) 871 clk_div = 3; 872 else if (bclk_fs <= 64) 873 clk_div = 2; 874 else if (bclk_fs <= 128) 875 clk_div = 1; 876 else { 877 return -EINVAL; 878 } 879 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 880 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK, 881 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div); 882 } 883 884 switch (params_width(params)) { 885 case 16: 886 val_len |= NAU8821_I2S_DL_16; 887 break; 888 case 20: 889 val_len |= NAU8821_I2S_DL_20; 890 break; 891 case 24: 892 val_len |= NAU8821_I2S_DL_24; 893 break; 894 case 32: 895 val_len |= NAU8821_I2S_DL_32; 896 break; 897 default: 898 return -EINVAL; 899 } 900 901 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 902 NAU8821_I2S_DL_MASK, val_len); 903 904 return 0; 905 } 906 907 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 908 { 909 struct snd_soc_component *component = codec_dai->component; 910 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 911 unsigned int ctrl1_val = 0, ctrl2_val = 0; 912 913 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 914 case SND_SOC_DAIFMT_CBP_CFP: 915 ctrl2_val |= NAU8821_I2S_MS_MASTER; 916 break; 917 case SND_SOC_DAIFMT_CBC_CFC: 918 break; 919 default: 920 return -EINVAL; 921 } 922 923 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 924 case SND_SOC_DAIFMT_NB_NF: 925 break; 926 case SND_SOC_DAIFMT_IB_NF: 927 ctrl1_val |= NAU8821_I2S_BP_INV; 928 break; 929 default: 930 return -EINVAL; 931 } 932 933 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 934 case SND_SOC_DAIFMT_I2S: 935 ctrl1_val |= NAU8821_I2S_DF_I2S; 936 break; 937 case SND_SOC_DAIFMT_LEFT_J: 938 ctrl1_val |= NAU8821_I2S_DF_LEFT; 939 break; 940 case SND_SOC_DAIFMT_RIGHT_J: 941 ctrl1_val |= NAU8821_I2S_DF_RIGTH; 942 break; 943 case SND_SOC_DAIFMT_DSP_A: 944 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 945 break; 946 case SND_SOC_DAIFMT_DSP_B: 947 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 948 ctrl1_val |= NAU8821_I2S_PCMB_EN; 949 break; 950 default: 951 return -EINVAL; 952 } 953 954 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 955 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK | 956 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val); 957 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 958 NAU8821_I2S_MS_MASK, ctrl2_val); 959 960 return 0; 961 } 962 963 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute, 964 int direction) 965 { 966 struct snd_soc_component *component = dai->component; 967 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 968 unsigned int val = 0; 969 970 if (mute) 971 val = NAU8821_DAC_SOFT_MUTE; 972 973 return regmap_update_bits(nau8821->regmap, 974 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val); 975 } 976 977 static const struct snd_soc_dai_ops nau8821_dai_ops = { 978 .startup = nau8821_dai_startup, 979 .hw_params = nau8821_hw_params, 980 .set_fmt = nau8821_set_dai_fmt, 981 .mute_stream = nau8821_digital_mute, 982 .no_capture_mute = 1, 983 }; 984 985 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000 986 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 987 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 988 989 static struct snd_soc_dai_driver nau8821_dai = { 990 .name = NUVOTON_CODEC_DAI, 991 .playback = { 992 .stream_name = "Playback", 993 .channels_min = 1, 994 .channels_max = 2, 995 .rates = NAU8821_RATES, 996 .formats = NAU8821_FORMATS, 997 }, 998 .capture = { 999 .stream_name = "Capture", 1000 .channels_min = 1, 1001 .channels_max = 2, 1002 .rates = NAU8821_RATES, 1003 .formats = NAU8821_FORMATS, 1004 }, 1005 .ops = &nau8821_dai_ops, 1006 }; 1007 1008 1009 static bool nau8821_is_jack_inserted(struct regmap *regmap) 1010 { 1011 bool active_high, is_high; 1012 int status, jkdet; 1013 1014 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet); 1015 active_high = jkdet & NAU8821_JACK_POLARITY; 1016 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status); 1017 is_high = status & NAU8821_GPIO2_IN; 1018 /* return jack connection status according to jack insertion logic 1019 * active high or active low. 1020 */ 1021 return active_high == is_high; 1022 } 1023 1024 static void nau8821_int_status_clear_all(struct regmap *regmap) 1025 { 1026 int active_irq, clear_irq, i; 1027 1028 /* Reset the intrruption status from rightmost bit if the corres- 1029 * ponding irq event occurs. 1030 */ 1031 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq); 1032 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) { 1033 clear_irq = (0x1 << i); 1034 if (active_irq & clear_irq) 1035 regmap_write(regmap, 1036 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1037 } 1038 } 1039 1040 static void nau8821_eject_jack(struct nau8821 *nau8821) 1041 { 1042 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1043 struct regmap *regmap = nau8821->regmap; 1044 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1045 1046 /* Detach 2kOhm Resistors from MICBIAS to MICGND */ 1047 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1048 NAU8821_MICBIAS_JKR2, 0); 1049 /* HPL/HPR short to ground */ 1050 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1051 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1052 snd_soc_component_disable_pin(component, "MICBIAS"); 1053 snd_soc_dapm_sync(dapm); 1054 1055 /* Clear all interruption status */ 1056 nau8821_int_status_clear_all(regmap); 1057 1058 /* Enable the insertion interruption, disable the ejection inter- 1059 * ruption, and then bypass de-bounce circuit. 1060 */ 1061 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1062 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS, 1063 NAU8821_IRQ_EJECT_DIS); 1064 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1065 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1066 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1067 NAU8821_IRQ_EJECT_EN); 1068 1069 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1070 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS); 1071 1072 /* Close clock for jack type detection at manual mode */ 1073 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 1074 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1075 1076 /* Recover to normal channel input */ 1077 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1078 NAU8821_ADC_R_SRC_EN, 0); 1079 if (nau8821->key_enable) { 1080 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1081 NAU8821_IRQ_KEY_RELEASE_EN | 1082 NAU8821_IRQ_KEY_PRESS_EN, 1083 NAU8821_IRQ_KEY_RELEASE_EN | 1084 NAU8821_IRQ_KEY_PRESS_EN); 1085 regmap_update_bits(regmap, 1086 NAU8821_R12_INTERRUPT_DIS_CTRL, 1087 NAU8821_IRQ_KEY_RELEASE_DIS | 1088 NAU8821_IRQ_KEY_PRESS_DIS, 1089 NAU8821_IRQ_KEY_RELEASE_DIS | 1090 NAU8821_IRQ_KEY_PRESS_DIS); 1091 } 1092 1093 } 1094 1095 static void nau8821_jdet_work(struct work_struct *work) 1096 { 1097 struct nau8821 *nau8821 = 1098 container_of(work, struct nau8821, jdet_work); 1099 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1100 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1101 struct regmap *regmap = nau8821->regmap; 1102 int jack_status_reg, mic_detected, event = 0, event_mask = 0; 1103 1104 snd_soc_component_force_enable_pin(component, "MICBIAS"); 1105 snd_soc_dapm_sync(dapm); 1106 msleep(20); 1107 1108 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg); 1109 mic_detected = !(jack_status_reg & NAU8821_KEYDET); 1110 if (mic_detected) { 1111 dev_dbg(nau8821->dev, "Headset connected\n"); 1112 event |= SND_JACK_HEADSET; 1113 1114 /* 2kOhm Resistor from MICBIAS to MICGND1 */ 1115 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1116 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2); 1117 /* Latch Right Channel Analog data 1118 * input into the Right Channel Filter 1119 */ 1120 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1121 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN); 1122 if (nau8821->key_enable) { 1123 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1124 NAU8821_IRQ_KEY_RELEASE_EN | 1125 NAU8821_IRQ_KEY_PRESS_EN, 0); 1126 regmap_update_bits(regmap, 1127 NAU8821_R12_INTERRUPT_DIS_CTRL, 1128 NAU8821_IRQ_KEY_RELEASE_DIS | 1129 NAU8821_IRQ_KEY_PRESS_DIS, 0); 1130 } else { 1131 snd_soc_component_disable_pin(component, "MICBIAS"); 1132 snd_soc_dapm_sync(nau8821->dapm); 1133 } 1134 } else { 1135 dev_dbg(nau8821->dev, "Headphone connected\n"); 1136 event |= SND_JACK_HEADPHONE; 1137 snd_soc_component_disable_pin(component, "MICBIAS"); 1138 snd_soc_dapm_sync(dapm); 1139 } 1140 event_mask |= SND_JACK_HEADSET; 1141 snd_soc_jack_report(nau8821->jack, event, event_mask); 1142 } 1143 1144 /* Enable interruptions with internal clock. */ 1145 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821) 1146 { 1147 struct regmap *regmap = nau8821->regmap; 1148 1149 /* Enable internal VCO needed for interruptions */ 1150 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE) 1151 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0); 1152 1153 /* Chip needs one FSCLK cycle in order to generate interruptions, 1154 * as we cannot guarantee one will be provided by the system. Turning 1155 * master mode on then off enables us to generate that FSCLK cycle 1156 * with a minimum of contention on the clock bus. 1157 */ 1158 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1159 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER); 1160 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1161 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE); 1162 1163 /* Not bypass de-bounce circuit */ 1164 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1165 NAU8821_JACK_DET_DB_BYPASS, 0); 1166 1167 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1168 NAU8821_IRQ_EJECT_EN, 0); 1169 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1170 NAU8821_IRQ_EJECT_DIS, 0); 1171 } 1172 1173 static irqreturn_t nau8821_interrupt(int irq, void *data) 1174 { 1175 struct nau8821 *nau8821 = (struct nau8821 *)data; 1176 struct regmap *regmap = nau8821->regmap; 1177 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 1178 1179 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) { 1180 dev_err(nau8821->dev, "failed to read irq status\n"); 1181 return IRQ_NONE; 1182 } 1183 1184 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq); 1185 1186 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) == 1187 NAU8821_JACK_EJECT_DETECTED) { 1188 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1189 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS); 1190 nau8821_eject_jack(nau8821); 1191 event_mask |= SND_JACK_HEADSET; 1192 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK; 1193 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) { 1194 event |= NAU8821_BUTTON; 1195 event_mask |= NAU8821_BUTTON; 1196 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ; 1197 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) { 1198 event_mask = NAU8821_BUTTON; 1199 clear_irq = NAU8821_KEY_RELEASE_IRQ; 1200 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) == 1201 NAU8821_JACK_INSERT_DETECTED) { 1202 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1203 NAU8821_MICDET_MASK, NAU8821_MICDET_EN); 1204 if (nau8821_is_jack_inserted(regmap)) { 1205 /* detect microphone and jack type */ 1206 cancel_work_sync(&nau8821->jdet_work); 1207 schedule_work(&nau8821->jdet_work); 1208 /* Turn off insertion interruption at manual mode */ 1209 regmap_update_bits(regmap, 1210 NAU8821_R12_INTERRUPT_DIS_CTRL, 1211 NAU8821_IRQ_INSERT_DIS, 1212 NAU8821_IRQ_INSERT_DIS); 1213 regmap_update_bits(regmap, 1214 NAU8821_R0F_INTERRUPT_MASK, 1215 NAU8821_IRQ_INSERT_EN, 1216 NAU8821_IRQ_INSERT_EN); 1217 nau8821_setup_inserted_irq(nau8821); 1218 } else { 1219 dev_warn(nau8821->dev, 1220 "Inserted IRQ fired but not connected\n"); 1221 nau8821_eject_jack(nau8821); 1222 } 1223 } 1224 1225 if (!clear_irq) 1226 clear_irq = active_irq; 1227 /* clears the rightmost interruption */ 1228 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1229 1230 if (event_mask) 1231 snd_soc_jack_report(nau8821->jack, event, event_mask); 1232 1233 return IRQ_HANDLED; 1234 } 1235 1236 static const struct regmap_config nau8821_regmap_config = { 1237 .val_bits = NAU8821_REG_DATA_LEN, 1238 .reg_bits = NAU8821_REG_ADDR_LEN, 1239 1240 .max_register = NAU8821_REG_MAX, 1241 .readable_reg = nau8821_readable_reg, 1242 .writeable_reg = nau8821_writeable_reg, 1243 .volatile_reg = nau8821_volatile_reg, 1244 1245 .cache_type = REGCACHE_RBTREE, 1246 .reg_defaults = nau8821_reg_defaults, 1247 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults), 1248 }; 1249 1250 static int nau8821_component_probe(struct snd_soc_component *component) 1251 { 1252 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1253 struct snd_soc_dapm_context *dapm = 1254 snd_soc_component_get_dapm(component); 1255 1256 nau8821->dapm = dapm; 1257 1258 return 0; 1259 } 1260 1261 /** 1262 * nau8821_calc_fll_param - Calculate FLL parameters. 1263 * @fll_in: external clock provided to codec. 1264 * @fs: sampling rate. 1265 * @fll_param: Pointer to structure of FLL parameters. 1266 * 1267 * Calculate FLL parameters to configure codec. 1268 * 1269 * Returns 0 for success or negative error code. 1270 */ 1271 static int nau8821_calc_fll_param(unsigned int fll_in, 1272 unsigned int fs, struct nau8821_fll *fll_param) 1273 { 1274 u64 fvco, fvco_max; 1275 unsigned int fref, i, fvco_sel; 1276 1277 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by 1278 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1279 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK 1280 */ 1281 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1282 fref = fll_in >> fll_pre_scalar[i].param; 1283 if (fref <= NAU_FREF_MAX) 1284 break; 1285 } 1286 if (i == ARRAY_SIZE(fll_pre_scalar)) 1287 return -EINVAL; 1288 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1289 1290 /* Choose the FLL ratio based on FREF */ 1291 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1292 if (fref >= fll_ratio[i].param) 1293 break; 1294 } 1295 if (i == ARRAY_SIZE(fll_ratio)) 1296 return -EINVAL; 1297 fll_param->ratio = fll_ratio[i].val; 1298 1299 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1300 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be 1301 * guaranteed across the full range of operation. 1302 * FDCO = freq_out * 2 * mclk_src_scaling 1303 */ 1304 fvco_max = 0; 1305 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1306 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1307 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1308 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1309 fvco_max < fvco) { 1310 fvco_max = fvco; 1311 fvco_sel = i; 1312 } 1313 } 1314 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1315 return -EINVAL; 1316 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1317 1318 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional 1319 * input based on FDCO, FREF and FLL ratio. 1320 */ 1321 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio); 1322 fll_param->fll_int = (fvco >> 24) & 0x3ff; 1323 fll_param->fll_frac = fvco & 0xffffff; 1324 1325 return 0; 1326 } 1327 1328 static void nau8821_fll_apply(struct nau8821 *nau8821, 1329 struct nau8821_fll *fll_param) 1330 { 1331 struct regmap *regmap = nau8821->regmap; 1332 1333 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1334 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK, 1335 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src); 1336 /* Make DSP operate at high speed for better performance. */ 1337 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1338 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK, 1339 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT)); 1340 /* FLL 24-bit fractional input */ 1341 regmap_write(regmap, NAU8821_R0A_FLL7, 1342 (fll_param->fll_frac >> 16) & 0xff); 1343 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff); 1344 /* FLL 10-bit integer input */ 1345 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1346 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int); 1347 /* FLL pre-scaler */ 1348 regmap_update_bits(regmap, NAU8821_R07_FLL4, 1349 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK, 1350 NAU8821_HIGHBW_EN | 1351 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT)); 1352 /* select divided VCO input */ 1353 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1354 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF); 1355 /* Disable free-running mode */ 1356 regmap_update_bits(regmap, 1357 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0); 1358 if (fll_param->fll_frac) { 1359 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 1360 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1361 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1362 NAU8821_FLL_FTR_SW_MASK, 1363 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1364 NAU8821_FLL_FTR_SW_FILTER); 1365 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1366 NAU8821_SDM_EN | NAU8821_CUTOFF500, 1367 NAU8821_SDM_EN | NAU8821_CUTOFF500); 1368 } else { 1369 /* disable FLL loop filter and cutoff frequency */ 1370 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1371 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1372 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU); 1373 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1374 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0); 1375 } 1376 } 1377 1378 /** 1379 * nau8821_set_fll - FLL configuration of nau8821 1380 * @component: codec component 1381 * @pll_id: PLL requested 1382 * @source: clock source 1383 * @freq_in: frequency of input clock source 1384 * @freq_out: must be 256*Fs in order to achieve the best performance 1385 * 1386 * The FLL function can select BCLK or MCLK as the input clock source. 1387 * 1388 * Returns 0 if the parameters have been applied successfully 1389 * or negative error code. 1390 */ 1391 static int nau8821_set_fll(struct snd_soc_component *component, 1392 int pll_id, int source, unsigned int freq_in, unsigned int freq_out) 1393 { 1394 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1395 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param; 1396 int ret, fs; 1397 1398 fs = freq_out >> 8; 1399 ret = nau8821_calc_fll_param(freq_in, fs, fll_param); 1400 if (ret) { 1401 dev_err(nau8821->dev, 1402 "Unsupported input clock %d to output clock %d\n", 1403 freq_in, freq_out); 1404 return ret; 1405 } 1406 dev_dbg(nau8821->dev, 1407 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1408 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac, 1409 fll_param->fll_int, fll_param->clk_ref_div); 1410 1411 nau8821_fll_apply(nau8821, fll_param); 1412 mdelay(2); 1413 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 1414 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1415 1416 return 0; 1417 } 1418 1419 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap) 1420 { 1421 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1422 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK); 1423 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1424 NAU8821_DCO_EN, 0); 1425 /* Make DSP operate as default setting for power saving. */ 1426 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1427 NAU8821_ICTRL_LATCH_MASK, 0); 1428 } 1429 1430 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 1431 int clk_id, unsigned int freq) 1432 { 1433 struct regmap *regmap = nau8821->regmap; 1434 1435 switch (clk_id) { 1436 case NAU8821_CLK_DIS: 1437 /* Clock provided externally and disable internal VCO clock */ 1438 nau8821_configure_mclk_as_sysclk(regmap); 1439 break; 1440 case NAU8821_CLK_MCLK: 1441 nau8821_configure_mclk_as_sysclk(regmap); 1442 /* MCLK not changed by clock tree */ 1443 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1444 NAU8821_CLK_MCLK_SRC_MASK, 0); 1445 break; 1446 case NAU8821_CLK_INTERNAL: 1447 if (nau8821_is_jack_inserted(regmap)) { 1448 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1449 NAU8821_DCO_EN, NAU8821_DCO_EN); 1450 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1451 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1452 /* Decrease the VCO frequency and make DSP operate 1453 * as default setting for power saving. 1454 */ 1455 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1456 NAU8821_CLK_MCLK_SRC_MASK, 0xf); 1457 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1458 NAU8821_ICTRL_LATCH_MASK | 1459 NAU8821_FLL_RATIO_MASK, 0x10); 1460 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1461 NAU8821_SDM_EN, NAU8821_SDM_EN); 1462 } 1463 break; 1464 case NAU8821_CLK_FLL_MCLK: 1465 /* Higher FLL reference input frequency can only set lower 1466 * gain error, such as 0000 for input reference from MCLK 1467 * 12.288Mhz. 1468 */ 1469 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1470 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1471 NAU8821_FLL_CLK_SRC_MCLK | 0); 1472 break; 1473 case NAU8821_CLK_FLL_BLK: 1474 /* If FLL reference input is from low frequency source, 1475 * higher error gain can apply such as 0xf which has 1476 * the most sensitive gain error correction threshold, 1477 * Therefore, FLL has the most accurate DCO to 1478 * target frequency. 1479 */ 1480 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1481 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1482 NAU8821_FLL_CLK_SRC_BLK | 1483 (0xf << NAU8821_GAIN_ERR_SFT)); 1484 break; 1485 case NAU8821_CLK_FLL_FS: 1486 /* If FLL reference input is from low frequency source, 1487 * higher error gain can apply such as 0xf which has 1488 * the most sensitive gain error correction threshold, 1489 * Therefore, FLL has the most accurate DCO to 1490 * target frequency. 1491 */ 1492 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1493 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1494 NAU8821_FLL_CLK_SRC_FS | 1495 (0xf << NAU8821_GAIN_ERR_SFT)); 1496 break; 1497 default: 1498 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id); 1499 return -EINVAL; 1500 } 1501 nau8821->clk_id = clk_id; 1502 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1503 nau8821->clk_id); 1504 1505 return 0; 1506 } 1507 1508 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id, 1509 int source, unsigned int freq, int dir) 1510 { 1511 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1512 1513 return nau8821_configure_sysclk(nau8821, clk_id, freq); 1514 } 1515 1516 static int nau8821_resume_setup(struct nau8821 *nau8821) 1517 { 1518 struct regmap *regmap = nau8821->regmap; 1519 1520 /* Close clock when jack type detection at manual mode */ 1521 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1522 if (nau8821->irq) { 1523 /* Clear all interruption status */ 1524 nau8821_int_status_clear_all(regmap); 1525 1526 /* Enable both insertion and ejection interruptions, and then 1527 * bypass de-bounce circuit. 1528 */ 1529 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1530 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0); 1531 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1532 NAU8821_JACK_DET_DB_BYPASS, 1533 NAU8821_JACK_DET_DB_BYPASS); 1534 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1535 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0); 1536 } 1537 1538 return 0; 1539 } 1540 1541 static int nau8821_set_bias_level(struct snd_soc_component *component, 1542 enum snd_soc_bias_level level) 1543 { 1544 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1545 struct regmap *regmap = nau8821->regmap; 1546 1547 switch (level) { 1548 case SND_SOC_BIAS_ON: 1549 break; 1550 1551 case SND_SOC_BIAS_PREPARE: 1552 break; 1553 1554 case SND_SOC_BIAS_STANDBY: 1555 /* Setup codec configuration after resume */ 1556 if (snd_soc_component_get_bias_level(component) == 1557 SND_SOC_BIAS_OFF) 1558 nau8821_resume_setup(nau8821); 1559 break; 1560 1561 case SND_SOC_BIAS_OFF: 1562 /* HPL/HPR short to ground */ 1563 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1564 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1565 if (nau8821->irq) { 1566 /* Reset the configuration of jack type for detection. 1567 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2. 1568 */ 1569 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1570 NAU8821_MICBIAS_JKR2, 0); 1571 /* Turn off all interruptions before system shutdown. 1572 * Keep theinterruption quiet before resume 1573 * setup completes. 1574 */ 1575 regmap_write(regmap, 1576 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff); 1577 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1578 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1579 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN); 1580 } 1581 break; 1582 default: 1583 break; 1584 } 1585 1586 return 0; 1587 } 1588 1589 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component) 1590 { 1591 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1592 1593 if (nau8821->irq) 1594 disable_irq(nau8821->irq); 1595 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 1596 /* Power down codec power; don't support button wakeup */ 1597 snd_soc_component_disable_pin(component, "MICBIAS"); 1598 snd_soc_dapm_sync(nau8821->dapm); 1599 regcache_cache_only(nau8821->regmap, true); 1600 regcache_mark_dirty(nau8821->regmap); 1601 1602 return 0; 1603 } 1604 1605 static int __maybe_unused nau8821_resume(struct snd_soc_component *component) 1606 { 1607 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1608 1609 regcache_cache_only(nau8821->regmap, false); 1610 regcache_sync(nau8821->regmap); 1611 if (nau8821->irq) 1612 enable_irq(nau8821->irq); 1613 1614 return 0; 1615 } 1616 1617 static const struct snd_soc_component_driver nau8821_component_driver = { 1618 .probe = nau8821_component_probe, 1619 .set_sysclk = nau8821_set_sysclk, 1620 .set_pll = nau8821_set_fll, 1621 .set_bias_level = nau8821_set_bias_level, 1622 .suspend = nau8821_suspend, 1623 .resume = nau8821_resume, 1624 .controls = nau8821_controls, 1625 .num_controls = ARRAY_SIZE(nau8821_controls), 1626 .dapm_widgets = nau8821_dapm_widgets, 1627 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets), 1628 .dapm_routes = nau8821_dapm_routes, 1629 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes), 1630 .suspend_bias_off = 1, 1631 .idle_bias_on = 1, 1632 .use_pmdown_time = 1, 1633 .endianness = 1, 1634 }; 1635 1636 /** 1637 * nau8821_enable_jack_detect - Specify a jack for event reporting 1638 * 1639 * @component: component to register the jack with 1640 * @jack: jack to use to report headset and button events on 1641 * 1642 * After this function has been called the headset insert/remove and button 1643 * events will be routed to the given jack. Jack can be null to stop 1644 * reporting. 1645 */ 1646 int nau8821_enable_jack_detect(struct snd_soc_component *component, 1647 struct snd_soc_jack *jack) 1648 { 1649 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1650 int ret; 1651 1652 nau8821->jack = jack; 1653 /* Initiate jack detection work queue */ 1654 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work); 1655 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL, 1656 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1657 "nau8821", nau8821); 1658 if (ret) { 1659 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n", 1660 nau8821->irq, ret); 1661 return ret; 1662 } 1663 1664 return ret; 1665 } 1666 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect); 1667 1668 static void nau8821_reset_chip(struct regmap *regmap) 1669 { 1670 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1671 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1672 } 1673 1674 static void nau8821_print_device_properties(struct nau8821 *nau8821) 1675 { 1676 struct device *dev = nau8821->dev; 1677 1678 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable); 1679 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable); 1680 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up); 1681 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity); 1682 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage); 1683 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance); 1684 dev_dbg(dev, "jack-insert-debounce: %d\n", 1685 nau8821->jack_insert_debounce); 1686 dev_dbg(dev, "jack-eject-debounce: %d\n", 1687 nau8821->jack_eject_debounce); 1688 dev_dbg(dev, "dmic-clk-threshold: %d\n", 1689 nau8821->dmic_clk_threshold); 1690 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable); 1691 dev_dbg(dev, "adc-delay-ms: %d\n", nau8821->adc_delay); 1692 } 1693 1694 static int nau8821_read_device_properties(struct device *dev, 1695 struct nau8821 *nau8821) 1696 { 1697 int ret; 1698 1699 nau8821->jkdet_enable = device_property_read_bool(dev, 1700 "nuvoton,jkdet-enable"); 1701 nau8821->jkdet_pull_enable = device_property_read_bool(dev, 1702 "nuvoton,jkdet-pull-enable"); 1703 nau8821->jkdet_pull_up = device_property_read_bool(dev, 1704 "nuvoton,jkdet-pull-up"); 1705 nau8821->key_enable = device_property_read_bool(dev, 1706 "nuvoton,key-enable"); 1707 nau8821->left_input_single_end = device_property_read_bool(dev, 1708 "nuvoton,left-input-single-end"); 1709 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1710 &nau8821->jkdet_polarity); 1711 if (ret) 1712 nau8821->jkdet_polarity = 1; 1713 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1714 &nau8821->micbias_voltage); 1715 if (ret) 1716 nau8821->micbias_voltage = 6; 1717 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1718 &nau8821->vref_impedance); 1719 if (ret) 1720 nau8821->vref_impedance = 2; 1721 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 1722 &nau8821->jack_insert_debounce); 1723 if (ret) 1724 nau8821->jack_insert_debounce = 7; 1725 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1726 &nau8821->jack_eject_debounce); 1727 if (ret) 1728 nau8821->jack_eject_debounce = 0; 1729 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold", 1730 &nau8821->dmic_clk_threshold); 1731 if (ret) 1732 nau8821->dmic_clk_threshold = 3072000; 1733 ret = device_property_read_u32(dev, "nuvoton,dmic-slew-rate", 1734 &nau8821->dmic_slew_rate); 1735 if (ret) 1736 nau8821->dmic_slew_rate = 0; 1737 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", 1738 &nau8821->adc_delay); 1739 if (ret) 1740 nau8821->adc_delay = 125; 1741 if (nau8821->adc_delay < 125 || nau8821->adc_delay > 500) 1742 dev_warn(dev, "Please set the suitable delay time!\n"); 1743 1744 return 0; 1745 } 1746 1747 static void nau8821_init_regs(struct nau8821 *nau8821) 1748 { 1749 struct regmap *regmap = nau8821->regmap; 1750 1751 /* Enable Bias/Vmid */ 1752 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1753 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID); 1754 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1755 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN); 1756 /* VMID Tieoff setting and enable TESTDAC. 1757 * This sets the analog DAC inputs to a '0' input signal to avoid 1758 * any glitches due to power up transients in both the analog and 1759 * digital DAC circuit. 1760 */ 1761 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1762 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN, 1763 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) | 1764 NAU8821_BIAS_TESTDAC_EN); 1765 /* Disable short Frame Sync detection logic */ 1766 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT, 1767 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET); 1768 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1769 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1770 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1771 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN, 1772 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1773 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN); 1774 /* Class G timer 64ms */ 1775 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL, 1776 NAU8821_CLASSG_TIMER_MASK, 1777 0x20 << NAU8821_CLASSG_TIMER_SFT); 1778 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1779 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2, 1780 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1781 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB, 1782 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1783 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB); 1784 /* Disable DACR/L power */ 1785 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP, 1786 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0); 1787 /* DAC clock delay 2ns, VREF */ 1788 regmap_update_bits(regmap, NAU8821_R73_RDAC, 1789 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK, 1790 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) | 1791 (0x3 << NAU8821_DAC_VREF_SFT)); 1792 1793 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1794 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage); 1795 /* Default oversampling/decimations settings are unusable 1796 * (audible hiss). Set it to something better. 1797 */ 1798 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1799 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64); 1800 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1, 1801 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64); 1802 regmap_update_bits(regmap, NAU8821_R13_DMIC_CTRL, 1803 NAU8821_DMIC_SLEW_MASK, nau8821->dmic_slew_rate << 1804 NAU8821_DMIC_SLEW_SFT); 1805 if (nau8821->left_input_single_end) { 1806 regmap_update_bits(regmap, NAU8821_R6B_PGA_MUTE, 1807 NAU8821_MUTE_MICNL_EN, NAU8821_MUTE_MICNL_EN); 1808 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1809 NAU8821_MICBIAS_LOWNOISE_EN, NAU8821_MICBIAS_LOWNOISE_EN); 1810 } 1811 } 1812 1813 static int nau8821_setup_irq(struct nau8821 *nau8821) 1814 { 1815 struct regmap *regmap = nau8821->regmap; 1816 1817 /* Jack detection */ 1818 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1819 NAU8821_JKDET_OUTPUT_EN, 1820 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN); 1821 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1822 NAU8821_JKDET_PULL_EN, 1823 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN); 1824 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1825 NAU8821_JKDET_PULL_UP, 1826 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0); 1827 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1828 NAU8821_JACK_POLARITY, 1829 /* jkdet_polarity - 1 is for active-low */ 1830 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY); 1831 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1832 NAU8821_JACK_INSERT_DEBOUNCE_MASK, 1833 nau8821->jack_insert_debounce << 1834 NAU8821_JACK_INSERT_DEBOUNCE_SFT); 1835 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1836 NAU8821_JACK_EJECT_DEBOUNCE_MASK, 1837 nau8821->jack_eject_debounce << 1838 NAU8821_JACK_EJECT_DEBOUNCE_SFT); 1839 /* Pull up IRQ pin */ 1840 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1841 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN | 1842 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP | 1843 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN); 1844 /* Disable interruption before codec initiation done */ 1845 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1846 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5); 1847 1848 return 0; 1849 } 1850 1851 /* Please keep this list alphabetically sorted */ 1852 static const struct dmi_system_id nau8821_quirk_table[] = { 1853 { 1854 /* Positivo CW14Q01P-V2 */ 1855 .matches = { 1856 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), 1857 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"), 1858 }, 1859 .driver_data = (void *)(NAU8821_JD_ACTIVE_HIGH), 1860 }, 1861 {} 1862 }; 1863 1864 static void nau8821_check_quirks(void) 1865 { 1866 const struct dmi_system_id *dmi_id; 1867 1868 if (quirk_override != -1) { 1869 nau8821_quirk = quirk_override; 1870 return; 1871 } 1872 1873 dmi_id = dmi_first_match(nau8821_quirk_table); 1874 if (dmi_id) 1875 nau8821_quirk = (unsigned long)dmi_id->driver_data; 1876 } 1877 1878 static int nau8821_i2c_probe(struct i2c_client *i2c) 1879 { 1880 struct device *dev = &i2c->dev; 1881 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev); 1882 int ret, value; 1883 1884 if (!nau8821) { 1885 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL); 1886 if (!nau8821) 1887 return -ENOMEM; 1888 nau8821_read_device_properties(dev, nau8821); 1889 } 1890 i2c_set_clientdata(i2c, nau8821); 1891 1892 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config); 1893 if (IS_ERR(nau8821->regmap)) 1894 return PTR_ERR(nau8821->regmap); 1895 1896 nau8821->dev = dev; 1897 nau8821->irq = i2c->irq; 1898 1899 nau8821_check_quirks(); 1900 1901 if (nau8821_quirk & NAU8821_JD_ACTIVE_HIGH) 1902 nau8821->jkdet_polarity = 0; 1903 1904 nau8821_print_device_properties(nau8821); 1905 1906 nau8821_reset_chip(nau8821->regmap); 1907 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value); 1908 if (ret) { 1909 dev_err(dev, "Failed to read device id (%d)\n", ret); 1910 return ret; 1911 } 1912 nau8821_init_regs(nau8821); 1913 1914 if (i2c->irq) 1915 nau8821_setup_irq(nau8821); 1916 1917 ret = devm_snd_soc_register_component(&i2c->dev, 1918 &nau8821_component_driver, &nau8821_dai, 1); 1919 1920 return ret; 1921 } 1922 1923 static const struct i2c_device_id nau8821_i2c_ids[] = { 1924 { "nau8821" }, 1925 { } 1926 }; 1927 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids); 1928 1929 #ifdef CONFIG_OF 1930 static const struct of_device_id nau8821_of_ids[] = { 1931 { .compatible = "nuvoton,nau8821", }, 1932 {} 1933 }; 1934 MODULE_DEVICE_TABLE(of, nau8821_of_ids); 1935 #endif 1936 1937 #ifdef CONFIG_ACPI 1938 static const struct acpi_device_id nau8821_acpi_match[] = { 1939 { "NVTN2020", 0 }, 1940 {}, 1941 }; 1942 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match); 1943 #endif 1944 1945 static struct i2c_driver nau8821_driver = { 1946 .driver = { 1947 .name = "nau8821", 1948 .of_match_table = of_match_ptr(nau8821_of_ids), 1949 .acpi_match_table = ACPI_PTR(nau8821_acpi_match), 1950 }, 1951 .probe = nau8821_i2c_probe, 1952 .id_table = nau8821_i2c_ids, 1953 }; 1954 module_i2c_driver(nau8821_driver); 1955 1956 MODULE_DESCRIPTION("ASoC nau8821 driver"); 1957 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>"); 1958 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>"); 1959 MODULE_LICENSE("GPL"); 1960