1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver 4 // 5 // Copyright 2021 Nuvoton Technology Corp. 6 // Author: John Hsu <kchsu0@nuvoton.com> 7 // Co-author: Seven Lee <wtli@nuvoton.com> 8 // 9 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmi.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/module.h> 17 #include <linux/math64.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <sound/core.h> 21 #include <sound/initval.h> 22 #include <sound/jack.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/tlv.h> 27 #include "nau8821.h" 28 29 #define NAU8821_JD_ACTIVE_HIGH BIT(0) 30 31 static int nau8821_quirk; 32 static int quirk_override = -1; 33 module_param_named(quirk, quirk_override, uint, 0444); 34 MODULE_PARM_DESC(quirk, "Board-specific quirk override"); 35 36 #define NAU_FREF_MAX 13500000 37 #define NAU_FVCO_MAX 100000000 38 #define NAU_FVCO_MIN 90000000 39 40 #define NAU8821_BUTTON SND_JACK_BTN_0 41 42 /* the maximum frequency of CLK_ADC and CLK_DAC */ 43 #define CLK_DA_AD_MAX 6144000 44 45 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 46 int clk_id, unsigned int freq); 47 static bool nau8821_is_jack_inserted(struct regmap *regmap); 48 49 struct nau8821_fll { 50 int mclk_src; 51 int ratio; 52 int fll_frac; 53 int fll_int; 54 int clk_ref_div; 55 }; 56 57 struct nau8821_fll_attr { 58 unsigned int param; 59 unsigned int val; 60 }; 61 62 /* scaling for mclk from sysclk_src output */ 63 static const struct nau8821_fll_attr mclk_src_scaling[] = { 64 { 1, 0x0 }, 65 { 2, 0x2 }, 66 { 4, 0x3 }, 67 { 8, 0x4 }, 68 { 16, 0x5 }, 69 { 32, 0x6 }, 70 { 3, 0x7 }, 71 { 6, 0xa }, 72 { 12, 0xb }, 73 { 24, 0xc }, 74 { 48, 0xd }, 75 { 96, 0xe }, 76 { 5, 0xf }, 77 }; 78 79 /* ratio for input clk freq */ 80 static const struct nau8821_fll_attr fll_ratio[] = { 81 { 512000, 0x01 }, 82 { 256000, 0x02 }, 83 { 128000, 0x04 }, 84 { 64000, 0x08 }, 85 { 32000, 0x10 }, 86 { 8000, 0x20 }, 87 { 4000, 0x40 }, 88 }; 89 90 static const struct nau8821_fll_attr fll_pre_scalar[] = { 91 { 0, 0x0 }, 92 { 1, 0x1 }, 93 { 2, 0x2 }, 94 { 3, 0x3 }, 95 }; 96 97 /* over sampling rate */ 98 struct nau8821_osr_attr { 99 unsigned int osr; 100 unsigned int clk_src; 101 }; 102 103 static const struct nau8821_osr_attr osr_dac_sel[] = { 104 { 64, 2 }, /* OSR 64, SRC 1/4 */ 105 { 256, 0 }, /* OSR 256, SRC 1 */ 106 { 128, 1 }, /* OSR 128, SRC 1/2 */ 107 { 0, 0 }, 108 { 32, 3 }, /* OSR 32, SRC 1/8 */ 109 }; 110 111 static const struct nau8821_osr_attr osr_adc_sel[] = { 112 { 32, 3 }, /* OSR 32, SRC 1/8 */ 113 { 64, 2 }, /* OSR 64, SRC 1/4 */ 114 { 128, 1 }, /* OSR 128, SRC 1/2 */ 115 { 256, 0 }, /* OSR 256, SRC 1 */ 116 }; 117 118 struct nau8821_dmic_speed { 119 unsigned int param; 120 unsigned int val; 121 }; 122 123 static const struct nau8821_dmic_speed dmic_speed_sel[] = { 124 { 0, 0x0 }, /*SPEED 1, SRC 1 */ 125 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */ 126 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */ 127 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */ 128 }; 129 130 static const struct reg_default nau8821_reg_defaults[] = { 131 { NAU8821_R01_ENA_CTRL, 0x00ff }, 132 { NAU8821_R03_CLK_DIVIDER, 0x0050 }, 133 { NAU8821_R04_FLL1, 0x0 }, 134 { NAU8821_R05_FLL2, 0x00bc }, 135 { NAU8821_R06_FLL3, 0x0008 }, 136 { NAU8821_R07_FLL4, 0x0010 }, 137 { NAU8821_R08_FLL5, 0x4000 }, 138 { NAU8821_R09_FLL6, 0x6900 }, 139 { NAU8821_R0A_FLL7, 0x0031 }, 140 { NAU8821_R0B_FLL8, 0x26e9 }, 141 { NAU8821_R0D_JACK_DET_CTRL, 0x0 }, 142 { NAU8821_R0F_INTERRUPT_MASK, 0x0 }, 143 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff }, 144 { NAU8821_R13_DMIC_CTRL, 0x0 }, 145 { NAU8821_R1A_GPIO12_CTRL, 0x0 }, 146 { NAU8821_R1B_TDM_CTRL, 0x0 }, 147 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a }, 148 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 }, 149 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 }, 150 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 }, 151 { NAU8821_R21_BIQ0_COF1, 0x0 }, 152 { NAU8821_R22_BIQ0_COF2, 0x0 }, 153 { NAU8821_R23_BIQ0_COF3, 0x0 }, 154 { NAU8821_R24_BIQ0_COF4, 0x0 }, 155 { NAU8821_R25_BIQ0_COF5, 0x0 }, 156 { NAU8821_R26_BIQ0_COF6, 0x0 }, 157 { NAU8821_R27_BIQ0_COF7, 0x0 }, 158 { NAU8821_R28_BIQ0_COF8, 0x0 }, 159 { NAU8821_R29_BIQ0_COF9, 0x0 }, 160 { NAU8821_R2A_BIQ0_COF10, 0x0 }, 161 { NAU8821_R2B_ADC_RATE, 0x0002 }, 162 { NAU8821_R2C_DAC_CTRL1, 0x0082 }, 163 { NAU8821_R2D_DAC_CTRL2, 0x0 }, 164 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 }, 165 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 }, 166 { NAU8821_R31_MUTE_CTRL, 0x0 }, 167 { NAU8821_R32_HSVOL_CTRL, 0x0 }, 168 { NAU8821_R34_DACR_CTRL, 0xcfcf }, 169 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf }, 170 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 }, 171 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 }, 172 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff }, 173 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 }, 174 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 }, 175 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 }, 176 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 }, 177 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 }, 178 { NAU8821_R41_BIQ1_COF1, 0x0 }, 179 { NAU8821_R42_BIQ1_COF2, 0x0 }, 180 { NAU8821_R43_BIQ1_COF3, 0x0 }, 181 { NAU8821_R44_BIQ1_COF4, 0x0 }, 182 { NAU8821_R45_BIQ1_COF5, 0x0 }, 183 { NAU8821_R46_BIQ1_COF6, 0x0 }, 184 { NAU8821_R47_BIQ1_COF7, 0x0 }, 185 { NAU8821_R48_BIQ1_COF8, 0x0 }, 186 { NAU8821_R49_BIQ1_COF9, 0x0 }, 187 { NAU8821_R4A_BIQ1_COF10, 0x0 }, 188 { NAU8821_R4B_CLASSG_CTRL, 0x0 }, 189 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 }, 190 { NAU8821_R4D_IMM_RMS_L, 0x0 }, 191 { NAU8821_R53_OTPDOUT_1, 0xaad8 }, 192 { NAU8821_R54_OTPDOUT_2, 0x0002 }, 193 { NAU8821_R55_MISC_CTRL, 0x0 }, 194 { NAU8821_R66_BIAS_ADJ, 0x0 }, 195 { NAU8821_R68_TRIM_SETTINGS, 0x0 }, 196 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 }, 197 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 }, 198 { NAU8821_R6B_PGA_MUTE, 0x0 }, 199 { NAU8821_R71_ANALOG_ADC_1, 0x0011 }, 200 { NAU8821_R72_ANALOG_ADC_2, 0x0020 }, 201 { NAU8821_R73_RDAC, 0x0008 }, 202 { NAU8821_R74_MIC_BIAS, 0x0006 }, 203 { NAU8821_R76_BOOST, 0x0 }, 204 { NAU8821_R77_FEPGA, 0x0 }, 205 { NAU8821_R7E_PGA_GAIN, 0x0 }, 206 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 }, 207 { NAU8821_R80_CHARGE_PUMP, 0x0 }, 208 }; 209 210 static bool nau8821_readable_reg(struct device *dev, unsigned int reg) 211 { 212 switch (reg) { 213 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 214 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 215 case NAU8821_R0D_JACK_DET_CTRL: 216 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL: 217 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 218 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 219 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 220 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 221 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3: 222 case NAU8821_R51_FUSE_CTRL1: 223 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL: 224 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 225 case NAU8821_R66_BIAS_ADJ: 226 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 227 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 228 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 229 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS: 230 return true; 231 default: 232 return false; 233 } 234 } 235 236 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg) 237 { 238 switch (reg) { 239 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 240 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 241 case NAU8821_R0D_JACK_DET_CTRL: 242 case NAU8821_R0F_INTERRUPT_MASK: 243 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL: 244 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 245 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 246 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 247 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 248 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL: 249 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3: 250 case NAU8821_R51_FUSE_CTRL1: 251 case NAU8821_R55_MISC_CTRL: 252 case NAU8821_R5A_SOFTWARE_RST: 253 case NAU8821_R66_BIAS_ADJ: 254 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 255 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 256 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 257 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg) 265 { 266 switch (reg) { 267 case NAU8821_R00_RESET: 268 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS: 269 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10: 270 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10: 271 case NAU8821_R4D_IMM_RMS_L: 272 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2: 273 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 274 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS: 275 return true; 276 default: 277 return false; 278 } 279 } 280 281 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol, 282 struct snd_ctl_elem_value *ucontrol) 283 { 284 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 285 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 286 287 if (!component->regmap) 288 return -EINVAL; 289 290 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1, 291 ucontrol->value.bytes.data, params->max); 292 293 return 0; 294 } 295 296 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol, 297 struct snd_ctl_elem_value *ucontrol) 298 { 299 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 300 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 301 void *data; 302 303 if (!component->regmap) 304 return -EINVAL; 305 306 data = kmemdup(ucontrol->value.bytes.data, 307 params->max, GFP_KERNEL | GFP_DMA); 308 if (!data) 309 return -ENOMEM; 310 311 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1, 312 data, params->max); 313 314 kfree(data); 315 316 return 0; 317 } 318 319 static const char * const nau8821_adc_decimation[] = { 320 "32", "64", "128", "256" }; 321 322 static const struct soc_enum nau8821_adc_decimation_enum = 323 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT, 324 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation); 325 326 static const char * const nau8821_dac_oversampl[] = { 327 "64", "256", "128", "", "32" }; 328 329 static const struct soc_enum nau8821_dac_oversampl_enum = 330 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT, 331 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl); 332 333 static const char * const nau8821_adc_drc_noise_gate[] = { 334 "1:1", "2:1", "4:1", "8:1" }; 335 336 static const struct soc_enum nau8821_adc_drc_noise_gate_enum = 337 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT, 338 ARRAY_SIZE(nau8821_adc_drc_noise_gate), 339 nau8821_adc_drc_noise_gate); 340 341 static const char * const nau8821_adc_drc_expansion_slope[] = { 342 "1:1", "2:1", "4:1" }; 343 344 static const struct soc_enum nau8821_adc_drc_expansion_slope_enum = 345 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT, 346 ARRAY_SIZE(nau8821_adc_drc_expansion_slope), 347 nau8821_adc_drc_expansion_slope); 348 349 static const char * const nau8821_adc_drc_lower_region[] = { 350 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 351 352 static const struct soc_enum nau8821_adc_drc_lower_region_enum = 353 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 354 NAU8821_DRC_CMP2_SLP_ADC_SFT, 355 ARRAY_SIZE(nau8821_adc_drc_lower_region), 356 nau8821_adc_drc_lower_region); 357 358 static const char * const nau8821_higher_region[] = { 359 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 360 361 static const struct soc_enum nau8821_higher_region_enum = 362 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 363 NAU8821_DRC_CMP1_SLP_ADC_SFT, 364 ARRAY_SIZE(nau8821_higher_region), 365 nau8821_higher_region); 366 367 static const char * const nau8821_limiter_slope[] = { 368 "0", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" }; 369 370 static const struct soc_enum nau8821_limiter_slope_enum = 371 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 372 NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope), 373 nau8821_limiter_slope); 374 375 static const char * const nau8821_detection_attack_time[] = { 376 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 377 "", "511Ts" }; 378 379 static const struct soc_enum nau8821_detection_attack_time_enum = 380 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 381 NAU8821_DRC_PK_COEF1_ADC_SFT, 382 ARRAY_SIZE(nau8821_detection_attack_time), 383 nau8821_detection_attack_time); 384 385 static const char * const nau8821_detection_release_time[] = { 386 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 387 "8191Ts", "", "16383Ts" }; 388 389 static const struct soc_enum nau8821_detection_release_time_enum = 390 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 391 NAU8821_DRC_PK_COEF2_ADC_SFT, 392 ARRAY_SIZE(nau8821_detection_release_time), 393 nau8821_detection_release_time); 394 395 static const char * const nau8821_attack_time[] = { 396 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 397 "511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" }; 398 399 static const struct soc_enum nau8821_attack_time_enum = 400 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT, 401 ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time); 402 403 static const char * const nau8821_decay_time[] = { 404 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 405 "8191Ts", "16383Ts", "32757Ts", "65535Ts" }; 406 407 static const struct soc_enum nau8821_decay_time_enum = 408 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT, 409 ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time); 410 411 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400); 412 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 413 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0); 414 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1); 415 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 416 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400); 417 static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500); 418 static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800); 419 420 static const struct snd_kcontrol_new nau8821_controls[] = { 421 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1, 422 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT, 423 0xff, 0, adc_vol_tlv), 424 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL, 425 12, 8, 0x0f, 0, sidetone_vol_tlv), 426 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL, 427 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv), 428 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL, 429 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT, 430 0xcf, 0, playback_vol_tlv), 431 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN, 432 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT, 433 37, 0, fepga_gain_tlv), 434 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", 435 NAU8821_R2F_DAC_DGAIN_CTRL, 436 0, 8, 0xff, 0, crosstalk_vol_tlv), 437 SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34, 438 NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv), 439 SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34, 440 NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv), 441 442 SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum), 443 SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum), 444 SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum), 445 SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum), 446 SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum), 447 SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum), 448 SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum), 449 SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum), 450 SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum), 451 SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12, 452 NAU8821_DRC_ENA_ADC_SFT, 1, 0), 453 454 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum), 455 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum), 456 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 457 nau8821_biq_coeff_get, nau8821_biq_coeff_put), 458 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL, 459 NAU8821_ADCPHS_SFT, 1, 0), 460 }; 461 462 static const struct snd_kcontrol_new nau8821_dmic_mode_switch = 463 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL, 464 NAU8821_DMIC_EN_SFT, 1, 0); 465 466 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 467 struct snd_kcontrol *k, int event) 468 { 469 struct snd_soc_component *component = 470 snd_soc_dapm_to_component(w->dapm); 471 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 472 int i, speed_selection = -1, clk_adc_src, clk_adc; 473 unsigned int clk_divider_r03; 474 475 /* The DMIC clock is gotten from adc clock divided by 476 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or 477 * less than nau8821->dmic_clk_threshold. 478 */ 479 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 480 &clk_divider_r03); 481 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK) 482 >> NAU8821_CLK_ADC_SRC_SFT; 483 clk_adc = (nau8821->fs * 256) >> clk_adc_src; 484 485 for (i = 0 ; i < 4 ; i++) 486 if ((clk_adc >> dmic_speed_sel[i].param) <= 487 nau8821->dmic_clk_threshold) { 488 speed_selection = dmic_speed_sel[i].val; 489 break; 490 } 491 if (i == 4) 492 return -EINVAL; 493 494 dev_dbg(nau8821->dev, 495 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n", 496 clk_adc, nau8821->dmic_clk_threshold, 497 dmic_speed_sel[i].param, dmic_speed_sel[i].val); 498 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL, 499 NAU8821_DMIC_SRC_MASK, 500 (speed_selection << NAU8821_DMIC_SRC_SFT)); 501 502 return 0; 503 } 504 505 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w, 506 struct snd_kcontrol *kcontrol, int event) 507 { 508 struct snd_soc_component *component = 509 snd_soc_dapm_to_component(w->dapm); 510 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 511 512 switch (event) { 513 case SND_SOC_DAPM_POST_PMU: 514 msleep(125); 515 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL, 516 NAU8821_EN_ADCL, NAU8821_EN_ADCL); 517 break; 518 case SND_SOC_DAPM_POST_PMD: 519 regmap_update_bits(nau8821->regmap, 520 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0); 521 break; 522 default: 523 return -EINVAL; 524 } 525 526 return 0; 527 } 528 529 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w, 530 struct snd_kcontrol *kcontrol, int event) 531 { 532 struct snd_soc_component *component = 533 snd_soc_dapm_to_component(w->dapm); 534 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 535 536 switch (event) { 537 case SND_SOC_DAPM_POST_PMU: 538 msleep(125); 539 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL, 540 NAU8821_EN_ADCR, NAU8821_EN_ADCR); 541 break; 542 case SND_SOC_DAPM_POST_PMD: 543 regmap_update_bits(nau8821->regmap, 544 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0); 545 break; 546 default: 547 return -EINVAL; 548 } 549 550 return 0; 551 } 552 553 static int nau8821_pump_event(struct snd_soc_dapm_widget *w, 554 struct snd_kcontrol *kcontrol, int event) 555 { 556 struct snd_soc_component *component = 557 snd_soc_dapm_to_component(w->dapm); 558 struct nau8821 *nau8821 = 559 snd_soc_component_get_drvdata(component); 560 561 switch (event) { 562 case SND_SOC_DAPM_POST_PMU: 563 /* Prevent startup click by letting charge pump to ramp up */ 564 msleep(20); 565 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 566 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW); 567 break; 568 case SND_SOC_DAPM_PRE_PMD: 569 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 570 NAU8821_JAMNODCLOW, 0); 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 return 0; 577 } 578 579 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w, 580 struct snd_kcontrol *kcontrol, int event) 581 { 582 struct snd_soc_component *component = 583 snd_soc_dapm_to_component(w->dapm); 584 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 585 586 switch (event) { 587 case SND_SOC_DAPM_PRE_PMU: 588 /* Disables the TESTDAC to let DAC signal pass through. */ 589 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 590 NAU8821_BIAS_TESTDAC_EN, 0); 591 break; 592 case SND_SOC_DAPM_POST_PMD: 593 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 594 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN); 595 break; 596 default: 597 return -EINVAL; 598 } 599 600 return 0; 601 } 602 603 static int system_clock_control(struct snd_soc_dapm_widget *w, 604 struct snd_kcontrol *k, int event) 605 { 606 struct snd_soc_component *component = 607 snd_soc_dapm_to_component(w->dapm); 608 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 609 610 if (SND_SOC_DAPM_EVENT_OFF(event)) { 611 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n"); 612 /* Set clock source to disable or internal clock before the 613 * playback or capture end. Codec needs clock for Jack 614 * detection and button press if jack inserted; otherwise, 615 * the clock should be closed. 616 */ 617 if (nau8821_is_jack_inserted(nau8821->regmap)) { 618 nau8821_configure_sysclk(nau8821, 619 NAU8821_CLK_INTERNAL, 0); 620 } else { 621 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 622 } 623 } 624 return 0; 625 } 626 627 static int nau8821_left_fepga_event(struct snd_soc_dapm_widget *w, 628 struct snd_kcontrol *kcontrol, int event) 629 { 630 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 631 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 632 633 if (!nau8821->left_input_single_end) 634 return 0; 635 636 switch (event) { 637 case SND_SOC_DAPM_POST_PMU: 638 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 639 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 640 NAU8821_ACDC_VREF_MICN | NAU8821_FEPGA_MODEL_AAF); 641 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 642 NAU8821_HP_BOOST_DISCHRG_EN, NAU8821_HP_BOOST_DISCHRG_EN); 643 break; 644 case SND_SOC_DAPM_POST_PMD: 645 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 646 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 0); 647 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 648 NAU8821_HP_BOOST_DISCHRG_EN, 0); 649 break; 650 default: 651 break; 652 } 653 654 return 0; 655 } 656 657 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = { 658 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 659 system_clock_control, SND_SOC_DAPM_POST_PMD), 660 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS, 661 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0), 662 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 663 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 664 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2, 665 NAU8821_POWERUP_ADCL_SFT, 0), 666 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2, 667 NAU8821_POWERUP_ADCR_SFT, 0), 668 /* single-ended design only on the left */ 669 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL, 670 NAU8821_PUP_PGA_L_SFT, 0, nau8821_left_fepga_event, 671 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 672 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL, 673 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0), 674 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL, 675 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event, 676 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 677 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL, 678 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event, 679 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 680 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM, 681 0, 0, &nau8821_dmic_mode_switch), 682 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2, 683 NAU8821_I2S_TRISTATE_SFT, 1), 684 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 685 686 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC, 687 NAU8821_DACL_EN_SFT, 0, NULL, 0), 688 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC, 689 NAU8821_DACR_EN_SFT, 0, NULL, 0), 690 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC, 691 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0), 692 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC, 693 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0), 694 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL, 695 NAU8821_EN_DACR_SFT, 0), 696 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL, 697 NAU8821_EN_DACL_SFT, 0), 698 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL, 699 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0), 700 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL, 701 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0), 702 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP, 703 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event, 704 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 705 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 706 NAU8821_R7F_POWER_UP_CONTROL, 707 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0), 708 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 709 NAU8821_R7F_POWER_UP_CONTROL, 710 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0), 711 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 712 NAU8821_R7F_POWER_UP_CONTROL, 713 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0), 714 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 715 NAU8821_R7F_POWER_UP_CONTROL, 716 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0), 717 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 718 NAU8821_R7F_POWER_UP_CONTROL, 719 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0), 720 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 721 NAU8821_R7F_POWER_UP_CONTROL, 722 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0), 723 SND_SOC_DAPM_PGA_S("Output DACL", 7, 724 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT, 725 0, nau8821_output_dac_event, 726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 727 SND_SOC_DAPM_PGA_S("Output DACR", 7, 728 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT, 729 0, nau8821_output_dac_event, 730 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 731 732 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 733 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 734 NAU8821_R0D_JACK_DET_CTRL, 735 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0), 736 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 737 NAU8821_R0D_JACK_DET_CTRL, 738 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0), 739 740 /* High current HPOL/R boost driver */ 741 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 742 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0), 743 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL, 744 NAU8821_CLASSG_EN_SFT, 0, NULL, 0), 745 746 SND_SOC_DAPM_INPUT("MICL"), 747 SND_SOC_DAPM_INPUT("MICR"), 748 SND_SOC_DAPM_INPUT("DMIC"), 749 SND_SOC_DAPM_OUTPUT("HPOL"), 750 SND_SOC_DAPM_OUTPUT("HPOR"), 751 }; 752 753 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = { 754 {"DMIC Enable", "Switch", "DMIC"}, 755 {"DMIC Enable", NULL, "DMIC Clock"}, 756 757 {"Frontend PGA L", NULL, "MICL"}, 758 {"Frontend PGA R", NULL, "MICR"}, 759 {"Frontend PGA L", NULL, "MICBIAS"}, 760 {"Frontend PGA R", NULL, "MICBIAS"}, 761 762 {"ADCL Power", NULL, "Frontend PGA L"}, 763 {"ADCR Power", NULL, "Frontend PGA R"}, 764 765 {"ADCL Digital path", NULL, "ADCL Power"}, 766 {"ADCR Digital path", NULL, "ADCR Power"}, 767 {"ADCL Digital path", NULL, "DMIC Enable"}, 768 {"ADCR Digital path", NULL, "DMIC Enable"}, 769 770 {"AIFTX", NULL, "ADCL Digital path"}, 771 {"AIFTX", NULL, "ADCR Digital path"}, 772 773 {"AIFTX", NULL, "System Clock"}, 774 {"AIFRX", NULL, "System Clock"}, 775 776 {"DDACL", NULL, "AIFRX"}, 777 {"DDACR", NULL, "AIFRX"}, 778 779 {"HP amp L", NULL, "DDACL"}, 780 {"HP amp R", NULL, "DDACR"}, 781 782 {"Charge Pump", NULL, "HP amp L"}, 783 {"Charge Pump", NULL, "HP amp R"}, 784 785 {"ADACL", NULL, "Charge Pump"}, 786 {"ADACR", NULL, "Charge Pump"}, 787 {"ADACL Clock", NULL, "ADACL"}, 788 {"ADACR Clock", NULL, "ADACR"}, 789 790 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 791 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 792 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 793 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 794 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 795 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 796 {"Output DACL", NULL, "Output Driver L Stage 3"}, 797 {"Output DACR", NULL, "Output Driver R Stage 3"}, 798 799 {"HPOL Pulldown", NULL, "Output DACL"}, 800 {"HPOR Pulldown", NULL, "Output DACR"}, 801 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 802 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 803 804 {"Class G", NULL, "HP Boost Driver"}, 805 {"HPOL", NULL, "Class G"}, 806 {"HPOR", NULL, "Class G"}, 807 }; 808 809 static const struct nau8821_osr_attr * 810 nau8821_get_osr(struct nau8821 *nau8821, int stream) 811 { 812 unsigned int osr; 813 814 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 815 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr); 816 osr &= NAU8821_DAC_OVERSAMPLE_MASK; 817 if (osr >= ARRAY_SIZE(osr_dac_sel)) 818 return NULL; 819 return &osr_dac_sel[osr]; 820 } else { 821 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr); 822 osr &= NAU8821_ADC_SYNC_DOWN_MASK; 823 if (osr >= ARRAY_SIZE(osr_adc_sel)) 824 return NULL; 825 return &osr_adc_sel[osr]; 826 } 827 } 828 829 static int nau8821_dai_startup(struct snd_pcm_substream *substream, 830 struct snd_soc_dai *dai) 831 { 832 struct snd_soc_component *component = dai->component; 833 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 834 const struct nau8821_osr_attr *osr; 835 836 osr = nau8821_get_osr(nau8821, substream->stream); 837 if (!osr || !osr->osr) 838 return -EINVAL; 839 840 return snd_pcm_hw_constraint_minmax(substream->runtime, 841 SNDRV_PCM_HW_PARAM_RATE, 842 0, CLK_DA_AD_MAX / osr->osr); 843 } 844 845 static int nau8821_hw_params(struct snd_pcm_substream *substream, 846 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 847 { 848 struct snd_soc_component *component = dai->component; 849 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 850 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div; 851 const struct nau8821_osr_attr *osr; 852 853 nau8821->fs = params_rate(params); 854 /* CLK_DAC or CLK_ADC = OSR * FS 855 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 856 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 857 * values must be selected such that the maximum frequency is less 858 * than 6.144 MHz. 859 */ 860 osr = nau8821_get_osr(nau8821, substream->stream); 861 if (!osr || !osr->osr) 862 return -EINVAL; 863 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX) 864 return -EINVAL; 865 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 866 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 867 NAU8821_CLK_DAC_SRC_MASK, 868 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT); 869 else 870 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 871 NAU8821_CLK_ADC_SRC_MASK, 872 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT); 873 874 /* make BCLK and LRC divde configuration if the codec as master. */ 875 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val); 876 if (ctrl_val & NAU8821_I2S_MS_MASTER) { 877 /* get the bclk and fs ratio */ 878 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs; 879 if (bclk_fs <= 32) 880 clk_div = 3; 881 else if (bclk_fs <= 64) 882 clk_div = 2; 883 else if (bclk_fs <= 128) 884 clk_div = 1; 885 else { 886 return -EINVAL; 887 } 888 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 889 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK, 890 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div); 891 } 892 893 switch (params_width(params)) { 894 case 16: 895 val_len |= NAU8821_I2S_DL_16; 896 break; 897 case 20: 898 val_len |= NAU8821_I2S_DL_20; 899 break; 900 case 24: 901 val_len |= NAU8821_I2S_DL_24; 902 break; 903 case 32: 904 val_len |= NAU8821_I2S_DL_32; 905 break; 906 default: 907 return -EINVAL; 908 } 909 910 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 911 NAU8821_I2S_DL_MASK, val_len); 912 913 return 0; 914 } 915 916 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 917 { 918 struct snd_soc_component *component = codec_dai->component; 919 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 920 unsigned int ctrl1_val = 0, ctrl2_val = 0; 921 922 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 923 case SND_SOC_DAIFMT_CBP_CFP: 924 ctrl2_val |= NAU8821_I2S_MS_MASTER; 925 break; 926 case SND_SOC_DAIFMT_CBC_CFC: 927 break; 928 default: 929 return -EINVAL; 930 } 931 932 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 933 case SND_SOC_DAIFMT_NB_NF: 934 break; 935 case SND_SOC_DAIFMT_IB_NF: 936 ctrl1_val |= NAU8821_I2S_BP_INV; 937 break; 938 default: 939 return -EINVAL; 940 } 941 942 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 943 case SND_SOC_DAIFMT_I2S: 944 ctrl1_val |= NAU8821_I2S_DF_I2S; 945 break; 946 case SND_SOC_DAIFMT_LEFT_J: 947 ctrl1_val |= NAU8821_I2S_DF_LEFT; 948 break; 949 case SND_SOC_DAIFMT_RIGHT_J: 950 ctrl1_val |= NAU8821_I2S_DF_RIGTH; 951 break; 952 case SND_SOC_DAIFMT_DSP_A: 953 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 954 break; 955 case SND_SOC_DAIFMT_DSP_B: 956 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 957 ctrl1_val |= NAU8821_I2S_PCMB_EN; 958 break; 959 default: 960 return -EINVAL; 961 } 962 963 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 964 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK | 965 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val); 966 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 967 NAU8821_I2S_MS_MASK, ctrl2_val); 968 969 return 0; 970 } 971 972 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute, 973 int direction) 974 { 975 struct snd_soc_component *component = dai->component; 976 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 977 unsigned int val = 0; 978 979 if (mute) 980 val = NAU8821_DAC_SOFT_MUTE; 981 982 return regmap_update_bits(nau8821->regmap, 983 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val); 984 } 985 986 static const struct snd_soc_dai_ops nau8821_dai_ops = { 987 .startup = nau8821_dai_startup, 988 .hw_params = nau8821_hw_params, 989 .set_fmt = nau8821_set_dai_fmt, 990 .mute_stream = nau8821_digital_mute, 991 .no_capture_mute = 1, 992 }; 993 994 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000 995 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 996 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 997 998 static struct snd_soc_dai_driver nau8821_dai = { 999 .name = NUVOTON_CODEC_DAI, 1000 .playback = { 1001 .stream_name = "Playback", 1002 .channels_min = 1, 1003 .channels_max = 2, 1004 .rates = NAU8821_RATES, 1005 .formats = NAU8821_FORMATS, 1006 }, 1007 .capture = { 1008 .stream_name = "Capture", 1009 .channels_min = 1, 1010 .channels_max = 2, 1011 .rates = NAU8821_RATES, 1012 .formats = NAU8821_FORMATS, 1013 }, 1014 .ops = &nau8821_dai_ops, 1015 }; 1016 1017 1018 static bool nau8821_is_jack_inserted(struct regmap *regmap) 1019 { 1020 bool active_high, is_high; 1021 int status, jkdet; 1022 1023 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet); 1024 active_high = jkdet & NAU8821_JACK_POLARITY; 1025 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status); 1026 is_high = status & NAU8821_GPIO2_IN; 1027 /* return jack connection status according to jack insertion logic 1028 * active high or active low. 1029 */ 1030 return active_high == is_high; 1031 } 1032 1033 static void nau8821_int_status_clear_all(struct regmap *regmap) 1034 { 1035 int active_irq, clear_irq, i; 1036 1037 /* Reset the intrruption status from rightmost bit if the corres- 1038 * ponding irq event occurs. 1039 */ 1040 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq); 1041 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) { 1042 clear_irq = (0x1 << i); 1043 if (active_irq & clear_irq) 1044 regmap_write(regmap, 1045 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1046 } 1047 } 1048 1049 static void nau8821_eject_jack(struct nau8821 *nau8821) 1050 { 1051 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1052 struct regmap *regmap = nau8821->regmap; 1053 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1054 1055 /* Detach 2kOhm Resistors from MICBIAS to MICGND */ 1056 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1057 NAU8821_MICBIAS_JKR2, 0); 1058 /* HPL/HPR short to ground */ 1059 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1060 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1061 snd_soc_component_disable_pin(component, "MICBIAS"); 1062 snd_soc_dapm_sync(dapm); 1063 1064 /* Clear all interruption status */ 1065 nau8821_int_status_clear_all(regmap); 1066 1067 /* Enable the insertion interruption, disable the ejection inter- 1068 * ruption, and then bypass de-bounce circuit. 1069 */ 1070 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1071 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS, 1072 NAU8821_IRQ_EJECT_DIS); 1073 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1074 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1075 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1076 NAU8821_IRQ_EJECT_EN); 1077 1078 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1079 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS); 1080 1081 /* Close clock for jack type detection at manual mode */ 1082 if (dapm->bias_level < SND_SOC_BIAS_PREPARE) 1083 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1084 1085 /* Recover to normal channel input */ 1086 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1087 NAU8821_ADC_R_SRC_EN, 0); 1088 if (nau8821->key_enable) { 1089 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1090 NAU8821_IRQ_KEY_RELEASE_EN | 1091 NAU8821_IRQ_KEY_PRESS_EN, 1092 NAU8821_IRQ_KEY_RELEASE_EN | 1093 NAU8821_IRQ_KEY_PRESS_EN); 1094 regmap_update_bits(regmap, 1095 NAU8821_R12_INTERRUPT_DIS_CTRL, 1096 NAU8821_IRQ_KEY_RELEASE_DIS | 1097 NAU8821_IRQ_KEY_PRESS_DIS, 1098 NAU8821_IRQ_KEY_RELEASE_DIS | 1099 NAU8821_IRQ_KEY_PRESS_DIS); 1100 } 1101 1102 } 1103 1104 static void nau8821_jdet_work(struct work_struct *work) 1105 { 1106 struct nau8821 *nau8821 = 1107 container_of(work, struct nau8821, jdet_work); 1108 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1109 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1110 struct regmap *regmap = nau8821->regmap; 1111 int jack_status_reg, mic_detected, event = 0, event_mask = 0; 1112 1113 snd_soc_component_force_enable_pin(component, "MICBIAS"); 1114 snd_soc_dapm_sync(dapm); 1115 msleep(20); 1116 1117 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg); 1118 mic_detected = !(jack_status_reg & NAU8821_KEYDET); 1119 if (mic_detected) { 1120 dev_dbg(nau8821->dev, "Headset connected\n"); 1121 event |= SND_JACK_HEADSET; 1122 1123 /* 2kOhm Resistor from MICBIAS to MICGND1 */ 1124 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1125 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2); 1126 /* Latch Right Channel Analog data 1127 * input into the Right Channel Filter 1128 */ 1129 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1130 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN); 1131 if (nau8821->key_enable) { 1132 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1133 NAU8821_IRQ_KEY_RELEASE_EN | 1134 NAU8821_IRQ_KEY_PRESS_EN, 0); 1135 regmap_update_bits(regmap, 1136 NAU8821_R12_INTERRUPT_DIS_CTRL, 1137 NAU8821_IRQ_KEY_RELEASE_DIS | 1138 NAU8821_IRQ_KEY_PRESS_DIS, 0); 1139 } else { 1140 snd_soc_component_disable_pin(component, "MICBIAS"); 1141 snd_soc_dapm_sync(nau8821->dapm); 1142 } 1143 } else { 1144 dev_dbg(nau8821->dev, "Headphone connected\n"); 1145 event |= SND_JACK_HEADPHONE; 1146 snd_soc_component_disable_pin(component, "MICBIAS"); 1147 snd_soc_dapm_sync(dapm); 1148 } 1149 event_mask |= SND_JACK_HEADSET; 1150 snd_soc_jack_report(nau8821->jack, event, event_mask); 1151 } 1152 1153 /* Enable interruptions with internal clock. */ 1154 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821) 1155 { 1156 struct regmap *regmap = nau8821->regmap; 1157 1158 /* Enable internal VCO needed for interruptions */ 1159 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE) 1160 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0); 1161 1162 /* Chip needs one FSCLK cycle in order to generate interruptions, 1163 * as we cannot guarantee one will be provided by the system. Turning 1164 * master mode on then off enables us to generate that FSCLK cycle 1165 * with a minimum of contention on the clock bus. 1166 */ 1167 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1168 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER); 1169 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1170 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE); 1171 1172 /* Not bypass de-bounce circuit */ 1173 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1174 NAU8821_JACK_DET_DB_BYPASS, 0); 1175 1176 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1177 NAU8821_IRQ_EJECT_EN, 0); 1178 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1179 NAU8821_IRQ_EJECT_DIS, 0); 1180 } 1181 1182 static irqreturn_t nau8821_interrupt(int irq, void *data) 1183 { 1184 struct nau8821 *nau8821 = (struct nau8821 *)data; 1185 struct regmap *regmap = nau8821->regmap; 1186 int active_irq, clear_irq = 0, event = 0, event_mask = 0; 1187 1188 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) { 1189 dev_err(nau8821->dev, "failed to read irq status\n"); 1190 return IRQ_NONE; 1191 } 1192 1193 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq); 1194 1195 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) == 1196 NAU8821_JACK_EJECT_DETECTED) { 1197 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1198 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS); 1199 nau8821_eject_jack(nau8821); 1200 event_mask |= SND_JACK_HEADSET; 1201 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK; 1202 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) { 1203 event |= NAU8821_BUTTON; 1204 event_mask |= NAU8821_BUTTON; 1205 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ; 1206 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) { 1207 event_mask = NAU8821_BUTTON; 1208 clear_irq = NAU8821_KEY_RELEASE_IRQ; 1209 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) == 1210 NAU8821_JACK_INSERT_DETECTED) { 1211 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1212 NAU8821_MICDET_MASK, NAU8821_MICDET_EN); 1213 if (nau8821_is_jack_inserted(regmap)) { 1214 /* detect microphone and jack type */ 1215 cancel_work_sync(&nau8821->jdet_work); 1216 schedule_work(&nau8821->jdet_work); 1217 /* Turn off insertion interruption at manual mode */ 1218 regmap_update_bits(regmap, 1219 NAU8821_R12_INTERRUPT_DIS_CTRL, 1220 NAU8821_IRQ_INSERT_DIS, 1221 NAU8821_IRQ_INSERT_DIS); 1222 regmap_update_bits(regmap, 1223 NAU8821_R0F_INTERRUPT_MASK, 1224 NAU8821_IRQ_INSERT_EN, 1225 NAU8821_IRQ_INSERT_EN); 1226 nau8821_setup_inserted_irq(nau8821); 1227 } else { 1228 dev_warn(nau8821->dev, 1229 "Inserted IRQ fired but not connected\n"); 1230 nau8821_eject_jack(nau8821); 1231 } 1232 } 1233 1234 if (!clear_irq) 1235 clear_irq = active_irq; 1236 /* clears the rightmost interruption */ 1237 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1238 1239 if (event_mask) 1240 snd_soc_jack_report(nau8821->jack, event, event_mask); 1241 1242 return IRQ_HANDLED; 1243 } 1244 1245 static const struct regmap_config nau8821_regmap_config = { 1246 .val_bits = NAU8821_REG_DATA_LEN, 1247 .reg_bits = NAU8821_REG_ADDR_LEN, 1248 1249 .max_register = NAU8821_REG_MAX, 1250 .readable_reg = nau8821_readable_reg, 1251 .writeable_reg = nau8821_writeable_reg, 1252 .volatile_reg = nau8821_volatile_reg, 1253 1254 .cache_type = REGCACHE_RBTREE, 1255 .reg_defaults = nau8821_reg_defaults, 1256 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults), 1257 }; 1258 1259 static int nau8821_component_probe(struct snd_soc_component *component) 1260 { 1261 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1262 struct snd_soc_dapm_context *dapm = 1263 snd_soc_component_get_dapm(component); 1264 1265 nau8821->dapm = dapm; 1266 1267 return 0; 1268 } 1269 1270 /** 1271 * nau8821_calc_fll_param - Calculate FLL parameters. 1272 * @fll_in: external clock provided to codec. 1273 * @fs: sampling rate. 1274 * @fll_param: Pointer to structure of FLL parameters. 1275 * 1276 * Calculate FLL parameters to configure codec. 1277 * 1278 * Returns 0 for success or negative error code. 1279 */ 1280 static int nau8821_calc_fll_param(unsigned int fll_in, 1281 unsigned int fs, struct nau8821_fll *fll_param) 1282 { 1283 u64 fvco, fvco_max; 1284 unsigned int fref, i, fvco_sel; 1285 1286 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by 1287 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1288 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK 1289 */ 1290 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1291 fref = fll_in >> fll_pre_scalar[i].param; 1292 if (fref <= NAU_FREF_MAX) 1293 break; 1294 } 1295 if (i == ARRAY_SIZE(fll_pre_scalar)) 1296 return -EINVAL; 1297 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1298 1299 /* Choose the FLL ratio based on FREF */ 1300 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1301 if (fref >= fll_ratio[i].param) 1302 break; 1303 } 1304 if (i == ARRAY_SIZE(fll_ratio)) 1305 return -EINVAL; 1306 fll_param->ratio = fll_ratio[i].val; 1307 1308 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1309 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be 1310 * guaranteed across the full range of operation. 1311 * FDCO = freq_out * 2 * mclk_src_scaling 1312 */ 1313 fvco_max = 0; 1314 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1315 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1316 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1317 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1318 fvco_max < fvco) { 1319 fvco_max = fvco; 1320 fvco_sel = i; 1321 } 1322 } 1323 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1324 return -EINVAL; 1325 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1326 1327 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional 1328 * input based on FDCO, FREF and FLL ratio. 1329 */ 1330 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio); 1331 fll_param->fll_int = (fvco >> 24) & 0x3ff; 1332 fll_param->fll_frac = fvco & 0xffffff; 1333 1334 return 0; 1335 } 1336 1337 static void nau8821_fll_apply(struct nau8821 *nau8821, 1338 struct nau8821_fll *fll_param) 1339 { 1340 struct regmap *regmap = nau8821->regmap; 1341 1342 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1343 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK, 1344 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src); 1345 /* Make DSP operate at high speed for better performance. */ 1346 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1347 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK, 1348 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT)); 1349 /* FLL 24-bit fractional input */ 1350 regmap_write(regmap, NAU8821_R0A_FLL7, 1351 (fll_param->fll_frac >> 16) & 0xff); 1352 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff); 1353 /* FLL 10-bit integer input */ 1354 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1355 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int); 1356 /* FLL pre-scaler */ 1357 regmap_update_bits(regmap, NAU8821_R07_FLL4, 1358 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK, 1359 NAU8821_HIGHBW_EN | 1360 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT)); 1361 /* select divided VCO input */ 1362 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1363 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF); 1364 /* Disable free-running mode */ 1365 regmap_update_bits(regmap, 1366 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0); 1367 if (fll_param->fll_frac) { 1368 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 1369 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1370 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1371 NAU8821_FLL_FTR_SW_MASK, 1372 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1373 NAU8821_FLL_FTR_SW_FILTER); 1374 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1375 NAU8821_SDM_EN | NAU8821_CUTOFF500, 1376 NAU8821_SDM_EN | NAU8821_CUTOFF500); 1377 } else { 1378 /* disable FLL loop filter and cutoff frequency */ 1379 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1380 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1381 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU); 1382 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1383 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0); 1384 } 1385 } 1386 1387 /** 1388 * nau8821_set_fll - FLL configuration of nau8821 1389 * @component: codec component 1390 * @pll_id: PLL requested 1391 * @source: clock source 1392 * @freq_in: frequency of input clock source 1393 * @freq_out: must be 256*Fs in order to achieve the best performance 1394 * 1395 * The FLL function can select BCLK or MCLK as the input clock source. 1396 * 1397 * Returns 0 if the parameters have been applied successfully 1398 * or negative error code. 1399 */ 1400 static int nau8821_set_fll(struct snd_soc_component *component, 1401 int pll_id, int source, unsigned int freq_in, unsigned int freq_out) 1402 { 1403 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1404 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param; 1405 int ret, fs; 1406 1407 fs = freq_out >> 8; 1408 ret = nau8821_calc_fll_param(freq_in, fs, fll_param); 1409 if (ret) { 1410 dev_err(nau8821->dev, 1411 "Unsupported input clock %d to output clock %d\n", 1412 freq_in, freq_out); 1413 return ret; 1414 } 1415 dev_dbg(nau8821->dev, 1416 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1417 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac, 1418 fll_param->fll_int, fll_param->clk_ref_div); 1419 1420 nau8821_fll_apply(nau8821, fll_param); 1421 mdelay(2); 1422 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 1423 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1424 1425 return 0; 1426 } 1427 1428 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap) 1429 { 1430 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1431 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK); 1432 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1433 NAU8821_DCO_EN, 0); 1434 /* Make DSP operate as default setting for power saving. */ 1435 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1436 NAU8821_ICTRL_LATCH_MASK, 0); 1437 } 1438 1439 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 1440 int clk_id, unsigned int freq) 1441 { 1442 struct regmap *regmap = nau8821->regmap; 1443 1444 switch (clk_id) { 1445 case NAU8821_CLK_DIS: 1446 /* Clock provided externally and disable internal VCO clock */ 1447 nau8821_configure_mclk_as_sysclk(regmap); 1448 break; 1449 case NAU8821_CLK_MCLK: 1450 nau8821_configure_mclk_as_sysclk(regmap); 1451 /* MCLK not changed by clock tree */ 1452 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1453 NAU8821_CLK_MCLK_SRC_MASK, 0); 1454 break; 1455 case NAU8821_CLK_INTERNAL: 1456 if (nau8821_is_jack_inserted(regmap)) { 1457 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1458 NAU8821_DCO_EN, NAU8821_DCO_EN); 1459 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1460 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1461 /* Decrease the VCO frequency and make DSP operate 1462 * as default setting for power saving. 1463 */ 1464 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1465 NAU8821_CLK_MCLK_SRC_MASK, 0xf); 1466 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1467 NAU8821_ICTRL_LATCH_MASK | 1468 NAU8821_FLL_RATIO_MASK, 0x10); 1469 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1470 NAU8821_SDM_EN, NAU8821_SDM_EN); 1471 } 1472 break; 1473 case NAU8821_CLK_FLL_MCLK: 1474 /* Higher FLL reference input frequency can only set lower 1475 * gain error, such as 0000 for input reference from MCLK 1476 * 12.288Mhz. 1477 */ 1478 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1479 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1480 NAU8821_FLL_CLK_SRC_MCLK | 0); 1481 break; 1482 case NAU8821_CLK_FLL_BLK: 1483 /* If FLL reference input is from low frequency source, 1484 * higher error gain can apply such as 0xf which has 1485 * the most sensitive gain error correction threshold, 1486 * Therefore, FLL has the most accurate DCO to 1487 * target frequency. 1488 */ 1489 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1490 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1491 NAU8821_FLL_CLK_SRC_BLK | 1492 (0xf << NAU8821_GAIN_ERR_SFT)); 1493 break; 1494 case NAU8821_CLK_FLL_FS: 1495 /* If FLL reference input is from low frequency source, 1496 * higher error gain can apply such as 0xf which has 1497 * the most sensitive gain error correction threshold, 1498 * Therefore, FLL has the most accurate DCO to 1499 * target frequency. 1500 */ 1501 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1502 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1503 NAU8821_FLL_CLK_SRC_FS | 1504 (0xf << NAU8821_GAIN_ERR_SFT)); 1505 break; 1506 default: 1507 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id); 1508 return -EINVAL; 1509 } 1510 nau8821->clk_id = clk_id; 1511 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1512 nau8821->clk_id); 1513 1514 return 0; 1515 } 1516 1517 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id, 1518 int source, unsigned int freq, int dir) 1519 { 1520 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1521 1522 return nau8821_configure_sysclk(nau8821, clk_id, freq); 1523 } 1524 1525 static int nau8821_resume_setup(struct nau8821 *nau8821) 1526 { 1527 struct regmap *regmap = nau8821->regmap; 1528 1529 /* Close clock when jack type detection at manual mode */ 1530 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1531 if (nau8821->irq) { 1532 /* Clear all interruption status */ 1533 nau8821_int_status_clear_all(regmap); 1534 1535 /* Enable both insertion and ejection interruptions, and then 1536 * bypass de-bounce circuit. 1537 */ 1538 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1539 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0); 1540 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1541 NAU8821_JACK_DET_DB_BYPASS, 1542 NAU8821_JACK_DET_DB_BYPASS); 1543 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1544 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0); 1545 } 1546 1547 return 0; 1548 } 1549 1550 static int nau8821_set_bias_level(struct snd_soc_component *component, 1551 enum snd_soc_bias_level level) 1552 { 1553 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1554 struct regmap *regmap = nau8821->regmap; 1555 1556 switch (level) { 1557 case SND_SOC_BIAS_ON: 1558 break; 1559 1560 case SND_SOC_BIAS_PREPARE: 1561 break; 1562 1563 case SND_SOC_BIAS_STANDBY: 1564 /* Setup codec configuration after resume */ 1565 if (snd_soc_component_get_bias_level(component) == 1566 SND_SOC_BIAS_OFF) 1567 nau8821_resume_setup(nau8821); 1568 break; 1569 1570 case SND_SOC_BIAS_OFF: 1571 /* HPL/HPR short to ground */ 1572 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1573 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1574 if (nau8821->irq) { 1575 /* Reset the configuration of jack type for detection. 1576 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2. 1577 */ 1578 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1579 NAU8821_MICBIAS_JKR2, 0); 1580 /* Turn off all interruptions before system shutdown. 1581 * Keep theinterruption quiet before resume 1582 * setup completes. 1583 */ 1584 regmap_write(regmap, 1585 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff); 1586 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1587 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1588 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN); 1589 } 1590 break; 1591 default: 1592 break; 1593 } 1594 1595 return 0; 1596 } 1597 1598 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component) 1599 { 1600 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1601 1602 if (nau8821->irq) 1603 disable_irq(nau8821->irq); 1604 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 1605 /* Power down codec power; don't support button wakeup */ 1606 snd_soc_component_disable_pin(component, "MICBIAS"); 1607 snd_soc_dapm_sync(nau8821->dapm); 1608 regcache_cache_only(nau8821->regmap, true); 1609 regcache_mark_dirty(nau8821->regmap); 1610 1611 return 0; 1612 } 1613 1614 static int __maybe_unused nau8821_resume(struct snd_soc_component *component) 1615 { 1616 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1617 1618 regcache_cache_only(nau8821->regmap, false); 1619 regcache_sync(nau8821->regmap); 1620 if (nau8821->irq) 1621 enable_irq(nau8821->irq); 1622 1623 return 0; 1624 } 1625 1626 static const struct snd_soc_component_driver nau8821_component_driver = { 1627 .probe = nau8821_component_probe, 1628 .set_sysclk = nau8821_set_sysclk, 1629 .set_pll = nau8821_set_fll, 1630 .set_bias_level = nau8821_set_bias_level, 1631 .suspend = nau8821_suspend, 1632 .resume = nau8821_resume, 1633 .controls = nau8821_controls, 1634 .num_controls = ARRAY_SIZE(nau8821_controls), 1635 .dapm_widgets = nau8821_dapm_widgets, 1636 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets), 1637 .dapm_routes = nau8821_dapm_routes, 1638 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes), 1639 .suspend_bias_off = 1, 1640 .idle_bias_on = 1, 1641 .use_pmdown_time = 1, 1642 .endianness = 1, 1643 }; 1644 1645 /** 1646 * nau8821_enable_jack_detect - Specify a jack for event reporting 1647 * 1648 * @component: component to register the jack with 1649 * @jack: jack to use to report headset and button events on 1650 * 1651 * After this function has been called the headset insert/remove and button 1652 * events will be routed to the given jack. Jack can be null to stop 1653 * reporting. 1654 */ 1655 int nau8821_enable_jack_detect(struct snd_soc_component *component, 1656 struct snd_soc_jack *jack) 1657 { 1658 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1659 int ret; 1660 1661 nau8821->jack = jack; 1662 /* Initiate jack detection work queue */ 1663 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work); 1664 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL, 1665 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1666 "nau8821", nau8821); 1667 if (ret) { 1668 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n", 1669 nau8821->irq, ret); 1670 return ret; 1671 } 1672 1673 return ret; 1674 } 1675 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect); 1676 1677 static void nau8821_reset_chip(struct regmap *regmap) 1678 { 1679 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1680 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1681 } 1682 1683 static void nau8821_print_device_properties(struct nau8821 *nau8821) 1684 { 1685 struct device *dev = nau8821->dev; 1686 1687 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable); 1688 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable); 1689 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up); 1690 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity); 1691 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage); 1692 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance); 1693 dev_dbg(dev, "jack-insert-debounce: %d\n", 1694 nau8821->jack_insert_debounce); 1695 dev_dbg(dev, "jack-eject-debounce: %d\n", 1696 nau8821->jack_eject_debounce); 1697 dev_dbg(dev, "dmic-clk-threshold: %d\n", 1698 nau8821->dmic_clk_threshold); 1699 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable); 1700 } 1701 1702 static int nau8821_read_device_properties(struct device *dev, 1703 struct nau8821 *nau8821) 1704 { 1705 int ret; 1706 1707 nau8821->jkdet_enable = device_property_read_bool(dev, 1708 "nuvoton,jkdet-enable"); 1709 nau8821->jkdet_pull_enable = device_property_read_bool(dev, 1710 "nuvoton,jkdet-pull-enable"); 1711 nau8821->jkdet_pull_up = device_property_read_bool(dev, 1712 "nuvoton,jkdet-pull-up"); 1713 nau8821->key_enable = device_property_read_bool(dev, 1714 "nuvoton,key-enable"); 1715 nau8821->left_input_single_end = device_property_read_bool(dev, 1716 "nuvoton,left-input-single-end"); 1717 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1718 &nau8821->jkdet_polarity); 1719 if (ret) 1720 nau8821->jkdet_polarity = 1; 1721 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1722 &nau8821->micbias_voltage); 1723 if (ret) 1724 nau8821->micbias_voltage = 6; 1725 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1726 &nau8821->vref_impedance); 1727 if (ret) 1728 nau8821->vref_impedance = 2; 1729 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 1730 &nau8821->jack_insert_debounce); 1731 if (ret) 1732 nau8821->jack_insert_debounce = 7; 1733 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1734 &nau8821->jack_eject_debounce); 1735 if (ret) 1736 nau8821->jack_eject_debounce = 0; 1737 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold", 1738 &nau8821->dmic_clk_threshold); 1739 if (ret) 1740 nau8821->dmic_clk_threshold = 3072000; 1741 1742 return 0; 1743 } 1744 1745 static void nau8821_init_regs(struct nau8821 *nau8821) 1746 { 1747 struct regmap *regmap = nau8821->regmap; 1748 1749 /* Enable Bias/Vmid */ 1750 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1751 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID); 1752 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1753 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN); 1754 /* VMID Tieoff setting and enable TESTDAC. 1755 * This sets the analog DAC inputs to a '0' input signal to avoid 1756 * any glitches due to power up transients in both the analog and 1757 * digital DAC circuit. 1758 */ 1759 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1760 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN, 1761 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) | 1762 NAU8821_BIAS_TESTDAC_EN); 1763 /* Disable short Frame Sync detection logic */ 1764 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT, 1765 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET); 1766 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1767 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1768 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1769 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN, 1770 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1771 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN); 1772 /* Class G timer 64ms */ 1773 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL, 1774 NAU8821_CLASSG_TIMER_MASK, 1775 0x20 << NAU8821_CLASSG_TIMER_SFT); 1776 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1777 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2, 1778 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1779 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB, 1780 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1781 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB); 1782 /* Disable DACR/L power */ 1783 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP, 1784 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0); 1785 /* DAC clock delay 2ns, VREF */ 1786 regmap_update_bits(regmap, NAU8821_R73_RDAC, 1787 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK, 1788 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) | 1789 (0x3 << NAU8821_DAC_VREF_SFT)); 1790 1791 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1792 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage); 1793 /* Default oversampling/decimations settings are unusable 1794 * (audible hiss). Set it to something better. 1795 */ 1796 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1797 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64); 1798 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1, 1799 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64); 1800 if (nau8821->left_input_single_end) { 1801 regmap_update_bits(regmap, NAU8821_R6B_PGA_MUTE, 1802 NAU8821_MUTE_MICNL_EN, NAU8821_MUTE_MICNL_EN); 1803 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1804 NAU8821_MICBIAS_LOWNOISE_EN, NAU8821_MICBIAS_LOWNOISE_EN); 1805 } 1806 } 1807 1808 static int nau8821_setup_irq(struct nau8821 *nau8821) 1809 { 1810 struct regmap *regmap = nau8821->regmap; 1811 1812 /* Jack detection */ 1813 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1814 NAU8821_JKDET_OUTPUT_EN, 1815 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN); 1816 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1817 NAU8821_JKDET_PULL_EN, 1818 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN); 1819 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1820 NAU8821_JKDET_PULL_UP, 1821 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0); 1822 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1823 NAU8821_JACK_POLARITY, 1824 /* jkdet_polarity - 1 is for active-low */ 1825 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY); 1826 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1827 NAU8821_JACK_INSERT_DEBOUNCE_MASK, 1828 nau8821->jack_insert_debounce << 1829 NAU8821_JACK_INSERT_DEBOUNCE_SFT); 1830 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1831 NAU8821_JACK_EJECT_DEBOUNCE_MASK, 1832 nau8821->jack_eject_debounce << 1833 NAU8821_JACK_EJECT_DEBOUNCE_SFT); 1834 /* Pull up IRQ pin */ 1835 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1836 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN | 1837 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP | 1838 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN); 1839 /* Disable interruption before codec initiation done */ 1840 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1841 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5); 1842 1843 return 0; 1844 } 1845 1846 /* Please keep this list alphabetically sorted */ 1847 static const struct dmi_system_id nau8821_quirk_table[] = { 1848 { 1849 /* Positivo CW14Q01P-V2 */ 1850 .matches = { 1851 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), 1852 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"), 1853 }, 1854 .driver_data = (void *)(NAU8821_JD_ACTIVE_HIGH), 1855 }, 1856 {} 1857 }; 1858 1859 static void nau8821_check_quirks(void) 1860 { 1861 const struct dmi_system_id *dmi_id; 1862 1863 if (quirk_override != -1) { 1864 nau8821_quirk = quirk_override; 1865 return; 1866 } 1867 1868 dmi_id = dmi_first_match(nau8821_quirk_table); 1869 if (dmi_id) 1870 nau8821_quirk = (unsigned long)dmi_id->driver_data; 1871 } 1872 1873 static int nau8821_i2c_probe(struct i2c_client *i2c) 1874 { 1875 struct device *dev = &i2c->dev; 1876 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev); 1877 int ret, value; 1878 1879 if (!nau8821) { 1880 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL); 1881 if (!nau8821) 1882 return -ENOMEM; 1883 nau8821_read_device_properties(dev, nau8821); 1884 } 1885 i2c_set_clientdata(i2c, nau8821); 1886 1887 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config); 1888 if (IS_ERR(nau8821->regmap)) 1889 return PTR_ERR(nau8821->regmap); 1890 1891 nau8821->dev = dev; 1892 nau8821->irq = i2c->irq; 1893 1894 nau8821_check_quirks(); 1895 1896 if (nau8821_quirk & NAU8821_JD_ACTIVE_HIGH) 1897 nau8821->jkdet_polarity = 0; 1898 1899 nau8821_print_device_properties(nau8821); 1900 1901 nau8821_reset_chip(nau8821->regmap); 1902 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value); 1903 if (ret) { 1904 dev_err(dev, "Failed to read device id (%d)\n", ret); 1905 return ret; 1906 } 1907 nau8821_init_regs(nau8821); 1908 1909 if (i2c->irq) 1910 nau8821_setup_irq(nau8821); 1911 1912 ret = devm_snd_soc_register_component(&i2c->dev, 1913 &nau8821_component_driver, &nau8821_dai, 1); 1914 1915 return ret; 1916 } 1917 1918 static const struct i2c_device_id nau8821_i2c_ids[] = { 1919 { "nau8821", 0 }, 1920 { } 1921 }; 1922 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids); 1923 1924 #ifdef CONFIG_OF 1925 static const struct of_device_id nau8821_of_ids[] = { 1926 { .compatible = "nuvoton,nau8821", }, 1927 {} 1928 }; 1929 MODULE_DEVICE_TABLE(of, nau8821_of_ids); 1930 #endif 1931 1932 #ifdef CONFIG_ACPI 1933 static const struct acpi_device_id nau8821_acpi_match[] = { 1934 { "NVTN2020", 0 }, 1935 {}, 1936 }; 1937 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match); 1938 #endif 1939 1940 static struct i2c_driver nau8821_driver = { 1941 .driver = { 1942 .name = "nau8821", 1943 .of_match_table = of_match_ptr(nau8821_of_ids), 1944 .acpi_match_table = ACPI_PTR(nau8821_acpi_match), 1945 }, 1946 .probe = nau8821_i2c_probe, 1947 .id_table = nau8821_i2c_ids, 1948 }; 1949 module_i2c_driver(nau8821_driver); 1950 1951 MODULE_DESCRIPTION("ASoC nau8821 driver"); 1952 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>"); 1953 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>"); 1954 MODULE_LICENSE("GPL"); 1955