1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * NAU85L40 ALSA SoC audio driver 4 * 5 * Copyright 2016 Nuvoton Technology Corp. 6 * Author: John Hsu <KCHSU0@nuvoton.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/spi/spi.h> 18 #include <linux/slab.h> 19 #include <linux/of.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/soc-dapm.h> 25 #include <sound/initval.h> 26 #include <sound/tlv.h> 27 #include "nau8540.h" 28 29 30 #define NAU_FREF_MAX 13500000 31 #define NAU_FVCO_MAX 100000000 32 #define NAU_FVCO_MIN 90000000 33 34 /* the maximum frequency of CLK_ADC */ 35 #define CLK_ADC_MAX 6144000 36 37 /* scaling for mclk from sysclk_src output */ 38 static const struct nau8540_fll_attr mclk_src_scaling[] = { 39 { 1, 0x0 }, 40 { 2, 0x2 }, 41 { 4, 0x3 }, 42 { 8, 0x4 }, 43 { 16, 0x5 }, 44 { 32, 0x6 }, 45 { 3, 0x7 }, 46 { 6, 0xa }, 47 { 12, 0xb }, 48 { 24, 0xc }, 49 }; 50 51 /* ratio for input clk freq */ 52 static const struct nau8540_fll_attr fll_ratio[] = { 53 { 512000, 0x01 }, 54 { 256000, 0x02 }, 55 { 128000, 0x04 }, 56 { 64000, 0x08 }, 57 { 32000, 0x10 }, 58 { 8000, 0x20 }, 59 { 4000, 0x40 }, 60 }; 61 62 static const struct nau8540_fll_attr fll_pre_scalar[] = { 63 { 1, 0x0 }, 64 { 2, 0x1 }, 65 { 4, 0x2 }, 66 { 8, 0x3 }, 67 }; 68 69 /* over sampling rate */ 70 static const struct nau8540_osr_attr osr_adc_sel[] = { 71 { 32, 3 }, /* OSR 32, SRC 1/8 */ 72 { 64, 2 }, /* OSR 64, SRC 1/4 */ 73 { 128, 1 }, /* OSR 128, SRC 1/2 */ 74 { 256, 0 }, /* OSR 256, SRC 1 */ 75 }; 76 77 static const struct reg_default nau8540_reg_defaults[] = { 78 {NAU8540_REG_POWER_MANAGEMENT, 0x0000}, 79 {NAU8540_REG_CLOCK_CTRL, 0x0000}, 80 {NAU8540_REG_CLOCK_SRC, 0x0000}, 81 {NAU8540_REG_FLL1, 0x0001}, 82 {NAU8540_REG_FLL2, 0x3126}, 83 {NAU8540_REG_FLL3, 0x0008}, 84 {NAU8540_REG_FLL4, 0x0010}, 85 {NAU8540_REG_FLL5, 0xC000}, 86 {NAU8540_REG_FLL6, 0x6000}, 87 {NAU8540_REG_FLL_VCO_RSV, 0xF13C}, 88 {NAU8540_REG_PCM_CTRL0, 0x000B}, 89 {NAU8540_REG_PCM_CTRL1, 0x3010}, 90 {NAU8540_REG_PCM_CTRL2, 0x0800}, 91 {NAU8540_REG_PCM_CTRL3, 0x0000}, 92 {NAU8540_REG_PCM_CTRL4, 0x000F}, 93 {NAU8540_REG_ALC_CONTROL_1, 0x0000}, 94 {NAU8540_REG_ALC_CONTROL_2, 0x700B}, 95 {NAU8540_REG_ALC_CONTROL_3, 0x0022}, 96 {NAU8540_REG_ALC_CONTROL_4, 0x1010}, 97 {NAU8540_REG_ALC_CONTROL_5, 0x1010}, 98 {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000}, 99 {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000}, 100 {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000}, 101 {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000}, 102 {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000}, 103 {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000}, 104 {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000}, 105 {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000}, 106 {NAU8540_REG_HPF_FILTER_CH12, 0x0000}, 107 {NAU8540_REG_HPF_FILTER_CH34, 0x0000}, 108 {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002}, 109 {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400}, 110 {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400}, 111 {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400}, 112 {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400}, 113 {NAU8540_REG_DIGITAL_MUX, 0x00E4}, 114 {NAU8540_REG_GPIO_CTRL, 0x0000}, 115 {NAU8540_REG_MISC_CTRL, 0x0000}, 116 {NAU8540_REG_I2C_CTRL, 0xEFFF}, 117 {NAU8540_REG_VMID_CTRL, 0x0000}, 118 {NAU8540_REG_MUTE, 0x0000}, 119 {NAU8540_REG_ANALOG_ADC1, 0x0011}, 120 {NAU8540_REG_ANALOG_ADC2, 0x0020}, 121 {NAU8540_REG_ANALOG_PWR, 0x0000}, 122 {NAU8540_REG_MIC_BIAS, 0x0004}, 123 {NAU8540_REG_REFERENCE, 0x0000}, 124 {NAU8540_REG_FEPGA1, 0x0000}, 125 {NAU8540_REG_FEPGA2, 0x0000}, 126 {NAU8540_REG_FEPGA3, 0x0101}, 127 {NAU8540_REG_FEPGA4, 0x0101}, 128 {NAU8540_REG_PWR, 0x0000}, 129 }; 130 131 static bool nau8540_readable_reg(struct device *dev, unsigned int reg) 132 { 133 switch (reg) { 134 case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV: 135 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4: 136 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5: 137 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE: 138 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX: 139 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL: 140 case NAU8540_REG_I2C_DEVICE_ID: 141 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE: 142 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR: 143 return true; 144 default: 145 return false; 146 } 147 148 } 149 150 static bool nau8540_writeable_reg(struct device *dev, unsigned int reg) 151 { 152 switch (reg) { 153 case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV: 154 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4: 155 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5: 156 case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE: 157 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX: 158 case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL: 159 case NAU8540_REG_RST: 160 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE: 161 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static bool nau8540_volatile_reg(struct device *dev, unsigned int reg) 169 { 170 switch (reg) { 171 case NAU8540_REG_SW_RESET: 172 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS: 173 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4: 174 case NAU8540_REG_I2C_DEVICE_ID: 175 case NAU8540_REG_RST: 176 return true; 177 default: 178 return false; 179 } 180 } 181 182 183 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600); 184 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 185 186 static const struct snd_kcontrol_new nau8540_snd_controls[] = { 187 SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1, 188 0, 0x520, 0, adc_vol_tlv), 189 SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2, 190 0, 0x520, 0, adc_vol_tlv), 191 SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3, 192 0, 0x520, 0, adc_vol_tlv), 193 SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4, 194 0, 0x520, 0, adc_vol_tlv), 195 196 SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3, 197 0, 0x25, 0, fepga_gain_tlv), 198 SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3, 199 8, 0x25, 0, fepga_gain_tlv), 200 SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4, 201 0, 0x25, 0, fepga_gain_tlv), 202 SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4, 203 8, 0x25, 0, fepga_gain_tlv), 204 }; 205 206 static const char * const adc_channel[] = { 207 "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4" 208 }; 209 static SOC_ENUM_SINGLE_DECL( 210 digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel); 211 212 static const struct snd_kcontrol_new digital_ch4_mux = 213 SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum); 214 215 static SOC_ENUM_SINGLE_DECL( 216 digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel); 217 218 static const struct snd_kcontrol_new digital_ch3_mux = 219 SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum); 220 221 static SOC_ENUM_SINGLE_DECL( 222 digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel); 223 224 static const struct snd_kcontrol_new digital_ch2_mux = 225 SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum); 226 227 static SOC_ENUM_SINGLE_DECL( 228 digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel); 229 230 static const struct snd_kcontrol_new digital_ch1_mux = 231 SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum); 232 233 static int adc_power_control(struct snd_soc_dapm_widget *w, 234 struct snd_kcontrol *k, int event) 235 { 236 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 237 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 238 239 if (SND_SOC_DAPM_EVENT_ON(event)) { 240 msleep(300); 241 /* DO12 and DO34 pad output enable */ 242 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 243 NAU8540_I2S_DO12_TRI, 0); 244 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 245 NAU8540_I2S_DO34_TRI, 0); 246 } else if (SND_SOC_DAPM_EVENT_OFF(event)) { 247 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 248 NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI); 249 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 250 NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI); 251 } 252 return 0; 253 } 254 255 static int aiftx_power_control(struct snd_soc_dapm_widget *w, 256 struct snd_kcontrol *k, int event) 257 { 258 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 259 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 260 261 if (SND_SOC_DAPM_EVENT_OFF(event)) { 262 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001); 263 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000); 264 } 265 return 0; 266 } 267 268 static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { 269 SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0), 270 SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0), 271 272 SND_SOC_DAPM_INPUT("MIC1"), 273 SND_SOC_DAPM_INPUT("MIC2"), 274 SND_SOC_DAPM_INPUT("MIC3"), 275 SND_SOC_DAPM_INPUT("MIC4"), 276 277 SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0), 278 SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0), 279 SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0), 280 SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0), 281 282 SND_SOC_DAPM_ADC_E("ADC1", NULL, 283 NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control, 284 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 285 SND_SOC_DAPM_ADC_E("ADC2", NULL, 286 NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control, 287 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 288 SND_SOC_DAPM_ADC_E("ADC3", NULL, 289 NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control, 290 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 291 SND_SOC_DAPM_ADC_E("ADC4", NULL, 292 NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control, 293 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 294 295 SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0), 296 SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0), 297 SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0), 298 SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0), 299 300 SND_SOC_DAPM_MUX("Digital CH4 Mux", 301 SND_SOC_NOPM, 0, 0, &digital_ch4_mux), 302 SND_SOC_DAPM_MUX("Digital CH3 Mux", 303 SND_SOC_NOPM, 0, 0, &digital_ch3_mux), 304 SND_SOC_DAPM_MUX("Digital CH2 Mux", 305 SND_SOC_NOPM, 0, 0, &digital_ch2_mux), 306 SND_SOC_DAPM_MUX("Digital CH1 Mux", 307 SND_SOC_NOPM, 0, 0, &digital_ch1_mux), 308 309 SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0, 310 aiftx_power_control, SND_SOC_DAPM_POST_PMD), 311 }; 312 313 static const struct snd_soc_dapm_route nau8540_dapm_routes[] = { 314 {"Frontend PGA1", NULL, "MIC1"}, 315 {"Frontend PGA2", NULL, "MIC2"}, 316 {"Frontend PGA3", NULL, "MIC3"}, 317 {"Frontend PGA4", NULL, "MIC4"}, 318 319 {"ADC1", NULL, "Frontend PGA1"}, 320 {"ADC2", NULL, "Frontend PGA2"}, 321 {"ADC3", NULL, "Frontend PGA3"}, 322 {"ADC4", NULL, "Frontend PGA4"}, 323 324 {"ADC CH1", NULL, "ADC1"}, 325 {"ADC CH2", NULL, "ADC2"}, 326 {"ADC CH3", NULL, "ADC3"}, 327 {"ADC CH4", NULL, "ADC4"}, 328 329 {"ADC1", NULL, "MICBIAS1"}, 330 {"ADC2", NULL, "MICBIAS1"}, 331 {"ADC3", NULL, "MICBIAS2"}, 332 {"ADC4", NULL, "MICBIAS2"}, 333 334 {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"}, 335 {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"}, 336 {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"}, 337 {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"}, 338 339 {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"}, 340 {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"}, 341 {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"}, 342 {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"}, 343 344 {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"}, 345 {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"}, 346 {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"}, 347 {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"}, 348 349 {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"}, 350 {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"}, 351 {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"}, 352 {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"}, 353 354 {"AIFTX", NULL, "Digital CH1 Mux"}, 355 {"AIFTX", NULL, "Digital CH2 Mux"}, 356 {"AIFTX", NULL, "Digital CH3 Mux"}, 357 {"AIFTX", NULL, "Digital CH4 Mux"}, 358 }; 359 360 static const struct nau8540_osr_attr * 361 nau8540_get_osr(struct nau8540 *nau8540) 362 { 363 unsigned int osr; 364 365 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr); 366 osr &= NAU8540_ADC_OSR_MASK; 367 if (osr >= ARRAY_SIZE(osr_adc_sel)) 368 return NULL; 369 return &osr_adc_sel[osr]; 370 } 371 372 static int nau8540_dai_startup(struct snd_pcm_substream *substream, 373 struct snd_soc_dai *dai) 374 { 375 struct snd_soc_component *component = dai->component; 376 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 377 const struct nau8540_osr_attr *osr; 378 379 osr = nau8540_get_osr(nau8540); 380 if (!osr || !osr->osr) 381 return -EINVAL; 382 383 return snd_pcm_hw_constraint_minmax(substream->runtime, 384 SNDRV_PCM_HW_PARAM_RATE, 385 0, CLK_ADC_MAX / osr->osr); 386 } 387 388 static int nau8540_hw_params(struct snd_pcm_substream *substream, 389 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 390 { 391 struct snd_soc_component *component = dai->component; 392 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 393 unsigned int val_len = 0; 394 const struct nau8540_osr_attr *osr; 395 396 /* CLK_ADC = OSR * FS 397 * ADC clock frequency is defined as Over Sampling Rate (OSR) 398 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 399 * values must be selected such that the maximum frequency is less 400 * than 6.144 MHz. 401 */ 402 osr = nau8540_get_osr(nau8540); 403 if (!osr || !osr->osr) 404 return -EINVAL; 405 if (params_rate(params) * osr->osr > CLK_ADC_MAX) 406 return -EINVAL; 407 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 408 NAU8540_CLK_ADC_SRC_MASK, 409 osr->clk_src << NAU8540_CLK_ADC_SRC_SFT); 410 411 switch (params_width(params)) { 412 case 16: 413 val_len |= NAU8540_I2S_DL_16; 414 break; 415 case 20: 416 val_len |= NAU8540_I2S_DL_20; 417 break; 418 case 24: 419 val_len |= NAU8540_I2S_DL_24; 420 break; 421 case 32: 422 val_len |= NAU8540_I2S_DL_32; 423 break; 424 default: 425 return -EINVAL; 426 } 427 428 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, 429 NAU8540_I2S_DL_MASK, val_len); 430 431 return 0; 432 } 433 434 static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 435 { 436 struct snd_soc_component *component = dai->component; 437 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 438 unsigned int ctrl1_val = 0, ctrl2_val = 0; 439 440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 441 case SND_SOC_DAIFMT_CBM_CFM: 442 ctrl2_val |= NAU8540_I2S_MS_MASTER; 443 break; 444 case SND_SOC_DAIFMT_CBS_CFS: 445 break; 446 default: 447 return -EINVAL; 448 } 449 450 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 451 case SND_SOC_DAIFMT_NB_NF: 452 break; 453 case SND_SOC_DAIFMT_IB_NF: 454 ctrl1_val |= NAU8540_I2S_BP_INV; 455 break; 456 default: 457 return -EINVAL; 458 } 459 460 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 461 case SND_SOC_DAIFMT_I2S: 462 ctrl1_val |= NAU8540_I2S_DF_I2S; 463 break; 464 case SND_SOC_DAIFMT_LEFT_J: 465 ctrl1_val |= NAU8540_I2S_DF_LEFT; 466 break; 467 case SND_SOC_DAIFMT_RIGHT_J: 468 ctrl1_val |= NAU8540_I2S_DF_RIGTH; 469 break; 470 case SND_SOC_DAIFMT_DSP_A: 471 ctrl1_val |= NAU8540_I2S_DF_PCM_AB; 472 break; 473 case SND_SOC_DAIFMT_DSP_B: 474 ctrl1_val |= NAU8540_I2S_DF_PCM_AB; 475 ctrl1_val |= NAU8540_I2S_PCMB_EN; 476 break; 477 default: 478 return -EINVAL; 479 } 480 481 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, 482 NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK | 483 NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val); 484 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 485 NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val); 486 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 487 NAU8540_I2S_DO34_OE, 0); 488 489 return 0; 490 } 491 492 /** 493 * nau8540_set_tdm_slot - configure DAI TX TDM. 494 * @dai: DAI 495 * @tx_mask: bitmask representing active TX slots. Ex. 496 * 0xf for normal 4 channel TDM. 497 * 0xf0 for shifted 4 channel TDM 498 * @rx_mask: no used. 499 * @slots: Number of slots in use. 500 * @slot_width: Width in bits for each slot. 501 * 502 * Configures a DAI for TDM operation. Only support 4 slots TDM. 503 */ 504 static int nau8540_set_tdm_slot(struct snd_soc_dai *dai, 505 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 506 { 507 struct snd_soc_component *component = dai->component; 508 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 509 unsigned int ctrl2_val = 0, ctrl4_val = 0; 510 511 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf))) 512 return -EINVAL; 513 514 ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN); 515 if (tx_mask & 0xf0) { 516 ctrl2_val = 4 * slot_width; 517 ctrl4_val |= (tx_mask >> 4); 518 } else { 519 ctrl4_val |= tx_mask; 520 } 521 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4, 522 NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN | 523 NAU8540_TDM_TX_MASK, ctrl4_val); 524 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 525 NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE); 526 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 527 NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK, 528 NAU8540_I2S_DO34_OE | ctrl2_val); 529 530 return 0; 531 } 532 533 static int nau8540_dai_trigger(struct snd_pcm_substream *substream, 534 int cmd, struct snd_soc_dai *dai) 535 { 536 struct snd_soc_component *component = dai->component; 537 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 538 struct regmap *regmap = nau8540->regmap; 539 unsigned int val; 540 int ret = 0; 541 542 /* Reading the peak data to detect abnormal data in the ADC channel. 543 * If abnormal data happens, the driver takes recovery actions to 544 * refresh the ADC channel. 545 */ 546 switch (cmd) { 547 case SNDRV_PCM_TRIGGER_START: 548 regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, 549 NAU8540_CLK_AGC_EN, NAU8540_CLK_AGC_EN); 550 regmap_update_bits(regmap, NAU8540_REG_ALC_CONTROL_3, 551 NAU8540_ALC_CH_ALL_EN, NAU8540_ALC_CH_ALL_EN); 552 553 regmap_read(regmap, NAU8540_REG_PEAK_CH1, &val); 554 dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val); 555 if (!val) { 556 regmap_update_bits(regmap, NAU8540_REG_MUTE, 557 NAU8540_PGA_CH_ALL_MUTE, NAU8540_PGA_CH_ALL_MUTE); 558 regmap_update_bits(regmap, NAU8540_REG_MUTE, 559 NAU8540_PGA_CH_ALL_MUTE, 0); 560 regmap_write(regmap, NAU8540_REG_RST, 0x1); 561 regmap_write(regmap, NAU8540_REG_RST, 0); 562 regmap_read(regmap, NAU8540_REG_PEAK_CH1, &val); 563 dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val); 564 if (!val) { 565 dev_err(nau8540->dev, "Channel recovery failed!!"); 566 ret = -EIO; 567 } 568 } 569 regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, 570 NAU8540_CLK_AGC_EN, 0); 571 regmap_update_bits(regmap, NAU8540_REG_ALC_CONTROL_3, 572 NAU8540_ALC_CH_ALL_EN, 0); 573 break; 574 575 default: 576 break; 577 } 578 579 return ret; 580 } 581 582 static const struct snd_soc_dai_ops nau8540_dai_ops = { 583 .startup = nau8540_dai_startup, 584 .hw_params = nau8540_hw_params, 585 .set_fmt = nau8540_set_fmt, 586 .set_tdm_slot = nau8540_set_tdm_slot, 587 .trigger = nau8540_dai_trigger, 588 }; 589 590 #define NAU8540_RATES SNDRV_PCM_RATE_8000_48000 591 #define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 592 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 593 594 static struct snd_soc_dai_driver nau8540_dai = { 595 .name = "nau8540-hifi", 596 .capture = { 597 .stream_name = "Capture", 598 .channels_min = 1, 599 .channels_max = 4, 600 .rates = NAU8540_RATES, 601 .formats = NAU8540_FORMATS, 602 }, 603 .ops = &nau8540_dai_ops, 604 }; 605 606 /** 607 * nau8540_calc_fll_param - Calculate FLL parameters. 608 * @fll_in: external clock provided to codec. 609 * @fs: sampling rate. 610 * @fll_param: Pointer to structure of FLL parameters. 611 * 612 * Calculate FLL parameters to configure codec. 613 * 614 * Returns 0 for success or negative error code. 615 */ 616 static int nau8540_calc_fll_param(unsigned int fll_in, 617 unsigned int fs, struct nau8540_fll *fll_param) 618 { 619 u64 fvco, fvco_max; 620 unsigned int fref, i, fvco_sel; 621 622 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 623 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 624 * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK 625 */ 626 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 627 fref = fll_in / fll_pre_scalar[i].param; 628 if (fref <= NAU_FREF_MAX) 629 break; 630 } 631 if (i == ARRAY_SIZE(fll_pre_scalar)) 632 return -EINVAL; 633 fll_param->clk_ref_div = fll_pre_scalar[i].val; 634 635 /* Choose the FLL ratio based on FREF */ 636 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 637 if (fref >= fll_ratio[i].param) 638 break; 639 } 640 if (i == ARRAY_SIZE(fll_ratio)) 641 return -EINVAL; 642 fll_param->ratio = fll_ratio[i].val; 643 644 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 645 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 646 * guaranteed across the full range of operation. 647 * FDCO = freq_out * 2 * mclk_src_scaling 648 */ 649 fvco_max = 0; 650 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 651 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 652 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 653 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 654 fvco_max < fvco) { 655 fvco_max = fvco; 656 fvco_sel = i; 657 } 658 } 659 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 660 return -EINVAL; 661 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 662 663 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 664 * input based on FDCO, FREF and FLL ratio. 665 */ 666 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 667 fll_param->fll_int = (fvco >> 16) & 0x3FF; 668 fll_param->fll_frac = fvco & 0xFFFF; 669 return 0; 670 } 671 672 static void nau8540_fll_apply(struct regmap *regmap, 673 struct nau8540_fll *fll_param) 674 { 675 regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC, 676 NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK, 677 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); 678 regmap_update_bits(regmap, NAU8540_REG_FLL1, 679 NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK, 680 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT)); 681 /* FLL 16-bit fractional input */ 682 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); 683 /* FLL 10-bit integer input */ 684 regmap_update_bits(regmap, NAU8540_REG_FLL3, 685 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int); 686 /* FLL pre-scaler */ 687 regmap_update_bits(regmap, NAU8540_REG_FLL4, 688 NAU8540_FLL_REF_DIV_MASK, 689 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT); 690 regmap_update_bits(regmap, NAU8540_REG_FLL5, 691 NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF); 692 regmap_update_bits(regmap, 693 NAU8540_REG_FLL6, NAU8540_DCO_EN, 0); 694 if (fll_param->fll_frac) { 695 regmap_update_bits(regmap, NAU8540_REG_FLL5, 696 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | 697 NAU8540_FLL_FTR_SW_MASK, 698 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | 699 NAU8540_FLL_FTR_SW_FILTER); 700 regmap_update_bits(regmap, NAU8540_REG_FLL6, 701 NAU8540_SDM_EN | NAU8540_CUTOFF500, 702 NAU8540_SDM_EN | NAU8540_CUTOFF500); 703 } else { 704 regmap_update_bits(regmap, NAU8540_REG_FLL5, 705 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | 706 NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU); 707 regmap_update_bits(regmap, NAU8540_REG_FLL6, 708 NAU8540_SDM_EN | NAU8540_CUTOFF500, 0); 709 } 710 } 711 712 /* freq_out must be 256*Fs in order to achieve the best performance */ 713 static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source, 714 unsigned int freq_in, unsigned int freq_out) 715 { 716 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 717 struct nau8540_fll fll_param; 718 int ret, fs; 719 720 switch (pll_id) { 721 case NAU8540_CLK_FLL_MCLK: 722 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, 723 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, 724 NAU8540_FLL_CLK_SRC_MCLK | 0); 725 break; 726 727 case NAU8540_CLK_FLL_BLK: 728 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, 729 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, 730 NAU8540_FLL_CLK_SRC_BLK | 731 (0xf << NAU8540_GAIN_ERR_SFT)); 732 break; 733 734 case NAU8540_CLK_FLL_FS: 735 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, 736 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, 737 NAU8540_FLL_CLK_SRC_FS | 738 (0xf << NAU8540_GAIN_ERR_SFT)); 739 break; 740 741 default: 742 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id); 743 return -EINVAL; 744 } 745 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", 746 freq_out, pll_id); 747 748 fs = freq_out / 256; 749 ret = nau8540_calc_fll_param(freq_in, fs, &fll_param); 750 if (ret < 0) { 751 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in); 752 return ret; 753 } 754 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 755 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 756 fll_param.fll_int, fll_param.clk_ref_div); 757 758 nau8540_fll_apply(nau8540->regmap, &fll_param); 759 mdelay(2); 760 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 761 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO); 762 763 return 0; 764 } 765 766 static int nau8540_set_sysclk(struct snd_soc_component *component, 767 int clk_id, int source, unsigned int freq, int dir) 768 { 769 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 770 771 switch (clk_id) { 772 case NAU8540_CLK_DIS: 773 case NAU8540_CLK_MCLK: 774 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 775 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK); 776 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, 777 NAU8540_DCO_EN, 0); 778 break; 779 780 case NAU8540_CLK_INTERNAL: 781 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, 782 NAU8540_DCO_EN, NAU8540_DCO_EN); 783 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 784 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO); 785 break; 786 787 default: 788 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id); 789 return -EINVAL; 790 } 791 792 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", 793 freq, clk_id); 794 795 return 0; 796 } 797 798 static void nau8540_reset_chip(struct regmap *regmap) 799 { 800 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); 801 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); 802 } 803 804 static void nau8540_init_regs(struct nau8540 *nau8540) 805 { 806 struct regmap *regmap = nau8540->regmap; 807 808 /* Enable Bias/VMID/VMID Tieoff */ 809 regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL, 810 NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK, 811 NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT)); 812 regmap_update_bits(regmap, NAU8540_REG_REFERENCE, 813 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN, 814 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN); 815 mdelay(2); 816 regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS, 817 NAU8540_PU_PRE, NAU8540_PU_PRE); 818 regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, 819 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN, 820 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN); 821 /* ADC OSR selection, CLK_ADC = Fs * OSR; 822 * Channel time alignment enable. 823 */ 824 regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE, 825 NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK, 826 NAU8540_CH_SYNC | NAU8540_ADC_OSR_64); 827 /* PGA input mode selection */ 828 regmap_update_bits(regmap, NAU8540_REG_FEPGA1, 829 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT, 830 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT); 831 regmap_update_bits(regmap, NAU8540_REG_FEPGA2, 832 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT, 833 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT); 834 /* DO12 and DO34 pad output disable */ 835 regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1, 836 NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI); 837 regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2, 838 NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI); 839 } 840 841 static int __maybe_unused nau8540_suspend(struct snd_soc_component *component) 842 { 843 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 844 845 regcache_cache_only(nau8540->regmap, true); 846 regcache_mark_dirty(nau8540->regmap); 847 848 return 0; 849 } 850 851 static int __maybe_unused nau8540_resume(struct snd_soc_component *component) 852 { 853 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 854 855 regcache_cache_only(nau8540->regmap, false); 856 regcache_sync(nau8540->regmap); 857 858 return 0; 859 } 860 861 static const struct snd_soc_component_driver nau8540_component_driver = { 862 .set_sysclk = nau8540_set_sysclk, 863 .set_pll = nau8540_set_pll, 864 .suspend = nau8540_suspend, 865 .resume = nau8540_resume, 866 .controls = nau8540_snd_controls, 867 .num_controls = ARRAY_SIZE(nau8540_snd_controls), 868 .dapm_widgets = nau8540_dapm_widgets, 869 .num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets), 870 .dapm_routes = nau8540_dapm_routes, 871 .num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes), 872 .suspend_bias_off = 1, 873 .idle_bias_on = 1, 874 .use_pmdown_time = 1, 875 .endianness = 1, 876 }; 877 878 static const struct regmap_config nau8540_regmap_config = { 879 .val_bits = 16, 880 .reg_bits = 16, 881 882 .max_register = NAU8540_REG_MAX, 883 .readable_reg = nau8540_readable_reg, 884 .writeable_reg = nau8540_writeable_reg, 885 .volatile_reg = nau8540_volatile_reg, 886 887 .cache_type = REGCACHE_RBTREE, 888 .reg_defaults = nau8540_reg_defaults, 889 .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults), 890 }; 891 892 static int nau8540_i2c_probe(struct i2c_client *i2c) 893 { 894 struct device *dev = &i2c->dev; 895 struct nau8540 *nau8540 = dev_get_platdata(dev); 896 int ret, value; 897 898 if (!nau8540) { 899 nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL); 900 if (!nau8540) 901 return -ENOMEM; 902 } 903 i2c_set_clientdata(i2c, nau8540); 904 905 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config); 906 if (IS_ERR(nau8540->regmap)) 907 return PTR_ERR(nau8540->regmap); 908 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value); 909 if (ret < 0) { 910 dev_err(dev, "Failed to read device id from the NAU85L40: %d\n", 911 ret); 912 return ret; 913 } 914 915 nau8540->dev = dev; 916 nau8540_reset_chip(nau8540->regmap); 917 nau8540_init_regs(nau8540); 918 919 return devm_snd_soc_register_component(dev, 920 &nau8540_component_driver, &nau8540_dai, 1); 921 } 922 923 static const struct i2c_device_id nau8540_i2c_ids[] = { 924 { "nau8540", 0 }, 925 { } 926 }; 927 MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids); 928 929 #ifdef CONFIG_OF 930 static const struct of_device_id nau8540_of_ids[] = { 931 { .compatible = "nuvoton,nau8540", }, 932 {} 933 }; 934 MODULE_DEVICE_TABLE(of, nau8540_of_ids); 935 #endif 936 937 static struct i2c_driver nau8540_i2c_driver = { 938 .driver = { 939 .name = "nau8540", 940 .of_match_table = of_match_ptr(nau8540_of_ids), 941 }, 942 .probe = nau8540_i2c_probe, 943 .id_table = nau8540_i2c_ids, 944 }; 945 module_i2c_driver(nau8540_i2c_driver); 946 947 MODULE_DESCRIPTION("ASoC NAU85L40 driver"); 948 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); 949 MODULE_LICENSE("GPL v2"); 950