1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // The NAU83G60 Stereo Class-D Amplifier with DSP and I/V-sense driver. 4 // 5 // Copyright (C) 2026 Nuvoton Technology Corp. 6 // Author: David Lin <ctlin0@nuvoton.com> 7 // Seven Lee <wtli@nuvoton.com> 8 // John Hsu <kchsu0@nuvoton.com> 9 // Neo Chang <ylchang2@nuvoton.com> 10 11 12 #include <linux/unaligned.h> 13 #include <linux/acpi.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 #include <linux/units.h> 22 #include <linux/workqueue.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 26 #include "nau8360-dsp.h" 27 #include "nau8360.h" 28 29 /* range of Master Clock MCLK (Hz) */ 30 #define MASTER_CLK_MIN 11025000 31 #define MASTER_CLK_MAX 24576000 32 /* DSP Optimal Clock Range 120MHz~126M(Hz) */ 33 #define DSP_OP_CLK48 122880000 34 #define DSP_OP_CLK44 112896000 35 /* the maximum frequency of DAC and IV sense clock */ 36 #define CLK_DA_IVSNS_MAX 6144000 37 #define ADSP_SR_48000 48000 38 #define ADSP_SR_44100 44100 39 40 static const int ivsns_clk_div[] = { 1, 2, 4, 5, 8, 10 }; 41 42 static const int dac_clk_div[] = { 1, 2, 4, 8 }; 43 44 static const char * const nau8360_rx_func_names[] = { 45 [NAU8360_TDM_DACL] = "DAC_L", 46 [NAU8360_TDM_DACR] = "DAC_R", 47 [NAU8360_TDM_ANCL] = "ANC_L", 48 [NAU8360_TDM_ANCR] = "ANC_R", 49 }; 50 51 static const char * const nau8360_tx_func_names[] = { 52 [NAU8360_TDM_AECL] = "AEC_L", 53 [NAU8360_TDM_AECR] = "AEC_R", 54 [NAU8360_TDM_ISNSL] = "ISNS_L", 55 [NAU8360_TDM_ISNSR] = "ISNS_R", 56 [NAU8360_TDM_VSNSL] = "VSNS_L", 57 [NAU8360_TDM_VSNSR] = "VSNS_R", 58 [NAU8360_TDM_TJ] = "TJ", 59 [NAU8360_TDM_VBAT] = "VBAT", 60 }; 61 62 /* PLL threshold */ 63 #define PLL_FREQ_MIN 1000000 64 #define PLL_FREQ_MAX 32000000 65 #define PLL_FOUT_MIN 12500000 66 #define PLL_FOUT_MAX 125000000 67 #define PLL_FREF_MAX 8000000 68 #define PLL_FVCO_MIN 50000000 69 #define MSEL_MAX 32 70 #define RSEL_MAX 4 71 72 static const struct reg_default nau8360_reg_defaults[] = { 73 { NAU8360_R02_I2C_ADDR, 0x0000 }, 74 { NAU8360_R03_CLK_CTRL0, 0x0000 }, 75 { NAU8360_R04_CLK_CTRL1, 0x0000 }, 76 { NAU8360_R05_INTERRUPT_CTRL, 0x40ff }, 77 { NAU8360_R07_GP_CTRL, 0xaa30 }, 78 { NAU8360_R08_GP_CTRL0, 0x1e1e }, 79 { NAU8360_R09_GP_CTRL1, 0x1e1e }, 80 { NAU8360_R0A_GP_CTRL2, 0x0000 }, 81 { NAU8360_R0B_I2S_PCM_CTRL1, 0x0702 }, 82 { NAU8360_R0C_I2S_PCM_CTRL2, 0x0a10 }, 83 { NAU8360_R0D_I2S_PCM_CTRL3, 0x1300 }, 84 { NAU8360_R0E_I2S_DATA_CTRL1, 0x0304 }, 85 { NAU8360_R0F_I2S_DATA_CTRL2, 0x080b }, 86 { NAU8360_R10_I2S_DATA_CTRL3, 0x0014 }, 87 { NAU8360_R11_I2S_DATA_CTRL4, 0x0014 }, 88 { NAU8360_R12_PATH_CTRL, 0x0400 }, 89 { NAU8360_R17_I2S0_DATA_CTRL5, 0x0014 }, 90 { NAU8360_R1A_DSP_CORE_CTRL2, 0x0010 }, 91 { NAU8360_R2C_ALC_CTRL1, 0x2000 }, 92 { NAU8360_R2D_ALC_CTRL2, 0x8400 }, 93 { NAU8360_R2E_ALC_CTRL3, 0x2083 }, 94 { NAU8360_R31_UVLOP_CTRL1, 0x0000 }, 95 { NAU8360_R32_UVLOP_CTRL2, 0x8400 }, 96 { NAU8360_R33_UVLOP_CTRL3, 0x0000 }, 97 { NAU8360_R40_CLK_DET_CTRL, 0xca60 }, 98 { NAU8360_R41_CLK_CTL2, 0xc400 }, 99 { NAU8360_R5D_SINC_CFG, 0x0010 }, 100 { NAU8360_R5F_ANA_TRIM_CFG1, 0x8400 }, 101 { NAU8360_R60_RST, 0x0010 }, 102 { NAU8360_R67_ANALOG_CONTROL_0, 0x0160 }, 103 { NAU8360_R68_ANALOG_CONTROL_1, 0x00d4 }, 104 { NAU8360_R6A_SARADC_CFG0, 0x5c09 }, 105 { NAU8360_R6B_SARADC_CFG1, 0x0008 }, 106 { NAU8360_R6C_IVSNS_CFG0, 0xf040 }, 107 { NAU8360_R6D_IVSNS_CFG1, 0x3555 }, 108 { NAU8360_R6E_DAC_CFG0, 0x0ed5 }, 109 { NAU8360_R71_CLK_DIV_CFG, 0x0211 }, 110 { NAU8360_R72_PLL_CFG0, 0xccc4 }, 111 { NAU8360_R73_PLL_CFG1, 0x0101 }, 112 { NAU8360_R74_PLL_CFG2, 0x0000 }, 113 { NAU8360_R7A_DAC_TRIM_CFG2, 0x0000 }, 114 { NAU8360_R7B_IVSNS_TRIM_CFG, 0x0000 }, 115 { NAU8360_R7C_MISC_TRIM_CFG, 0x72d5 }, 116 { NAU8360_R86_HW3_CTL0, 0x2000 }, 117 { NAU8360_R88_ALC_CTRL6, 0x0000 }, 118 { NAU8360_R8A_HW3_VL_CTL7, 0xc000 }, 119 { NAU8360_R8B_HW3_VR_CTL8, 0xc000 }, 120 { NAU8360_R8C_HW3_CTL6, 0x0000 }, 121 { NAU8360_R8D_HW3_IL_CTL7, 0xc000 }, 122 { NAU8360_R8E_HW3_IR_CTL8, 0xc000 }, 123 { NAU8360_R8F_HW3_CTL9, 0x0000 }, 124 { NAU8360_R90_HW2_CTL0, 0x2000 }, 125 { NAU8360_R96_HW2_CTL6, 0x0000 }, 126 { NAU8360_R97_HW2_CTL7, 0xc000 }, 127 { NAU8360_R98_HW2_CTL8, 0xc000 }, 128 { NAU8360_R99_HW2_CTL9, 0x0000 }, 129 { NAU8360_R9A_HW1_CTL0, 0xc000 }, 130 { NAU8360_R9B_HW1_CTL1, 0xc000 }, 131 { NAU8360_R9C_HW1_CTL2, 0x0800 }, 132 { NAU8360_R9D_PEQ_CTL, 0x0001 }, 133 { NAU8360_RA0_LEFT_XODRC_CTRL, 0x0000 }, 134 { NAU8360_RA2_RIGHT_XODRC_CTRL, 0x0000 }, 135 { NAU8360_RA4_ANA_REG_0, 0x7f86 }, 136 { NAU8360_RA5_ANA_REG_1, 0x276e }, 137 }; 138 139 static bool nau8360_readable_reg(struct device *dev, unsigned int reg) 140 { 141 switch (reg) { 142 case NAU8360_R00_SOFTWARE_RST ... NAU8360_R12_PATH_CTRL: 143 case NAU8360_R17_I2S0_DATA_CTRL5: 144 case NAU8360_R1A_DSP_CORE_CTRL2: 145 case NAU8360_R21_VBAT_READOUT ... NAU8360_R22_TEMP_READOUT: 146 case NAU8360_R2C_ALC_CTRL1 ... NAU8360_R2E_ALC_CTRL3: 147 case NAU8360_R31_UVLOP_CTRL1 ... NAU8360_R33_UVLOP_CTRL3: 148 case NAU8360_R40_CLK_DET_CTRL ... NAU8360_R41_CLK_CTL2: 149 case NAU8360_R46_I2C_DEVICE_ID: 150 case NAU8360_R5D_SINC_CFG: 151 case NAU8360_R5F_ANA_TRIM_CFG1 ... NAU8360_R60_RST: 152 case NAU8360_R67_ANALOG_CONTROL_0 ... NAU8360_R6E_DAC_CFG0: 153 case NAU8360_R71_CLK_DIV_CFG ... NAU8360_R74_PLL_CFG2: 154 case NAU8360_R77_SOFT_SD ... NAU8360_R7C_MISC_TRIM_CFG: 155 case NAU8360_R7E_CLK_GATED_EN: 156 case NAU8360_R86_HW3_CTL0: 157 case NAU8360_R88_ALC_CTRL6: 158 case NAU8360_R8A_HW3_VL_CTL7 ... NAU8360_R90_HW2_CTL0: 159 case NAU8360_R96_HW2_CTL6 ... NAU8360_R9D_PEQ_CTL: 160 case NAU8360_RA0_LEFT_XODRC_CTRL: 161 case NAU8360_RA2_RIGHT_XODRC_CTRL: 162 case NAU8360_RA4_ANA_REG_0 ... NAU8360_RA5_ANA_REG_1: 163 case NAU8360_R100_LEFT_BIQ0_COE ... (NAU8360_R100_LEFT_BIQ0_COE + 164 NAU8360_PEQ_REG_WIDTH): 165 case NAU8360_R10C_LEFT_BIQ1_COE ... (NAU8360_R10C_LEFT_BIQ1_COE + 166 NAU8360_PEQ_REG_WIDTH): 167 case NAU8360_R118_LEFT_BIQ2_COE ... (NAU8360_R118_LEFT_BIQ2_COE + 168 NAU8360_PEQ_REG_WIDTH): 169 case NAU8360_R124_LEFT_BIQ3_COE ... (NAU8360_R124_LEFT_BIQ3_COE + 170 NAU8360_PEQ_REG_WIDTH): 171 case NAU8360_R130_LEFT_BIQ4_COE ... (NAU8360_R130_LEFT_BIQ4_COE + 172 NAU8360_PEQ_REG_WIDTH): 173 case NAU8360_R13C_LEFT_BIQ5_COE ... (NAU8360_R13C_LEFT_BIQ5_COE + 174 NAU8360_PEQ_REG_WIDTH): 175 case NAU8360_R148_LEFT_BIQ6_COE ... (NAU8360_R148_LEFT_BIQ6_COE + 176 NAU8360_PEQ_REG_WIDTH): 177 case NAU8360_R154_LEFT_BIQ7_COE ... (NAU8360_R154_LEFT_BIQ7_COE + 178 NAU8360_PEQ_REG_WIDTH): 179 case NAU8360_R160_LEFT_BIQ8_COE ... (NAU8360_R160_LEFT_BIQ8_COE + 180 NAU8360_PEQ_REG_WIDTH): 181 case NAU8360_R16C_LEFT_BIQ9_COE ... (NAU8360_R16C_LEFT_BIQ9_COE + 182 NAU8360_PEQ_REG_WIDTH): 183 case NAU8360_R178_LEFT_BIQ10_COE ... (NAU8360_R178_LEFT_BIQ10_COE + 184 NAU8360_PEQ_REG_WIDTH): 185 case NAU8360_R184_LEFT_BIQ11_COE ... (NAU8360_R184_LEFT_BIQ11_COE + 186 NAU8360_PEQ_REG_WIDTH): 187 case NAU8360_R190_LEFT_BIQ12_COE ... (NAU8360_R190_LEFT_BIQ12_COE + 188 NAU8360_PEQ_REG_WIDTH): 189 case NAU8360_R19C_LEFT_BIQ13_COE ... (NAU8360_R19C_LEFT_BIQ13_COE + 190 NAU8360_PEQ_REG_WIDTH): 191 case NAU8360_R1A8_LEFT_BIQ14_COE ... (NAU8360_R1A8_LEFT_BIQ14_COE + 192 NAU8360_PEQ_REG_WIDTH): 193 case NAU8360_R200_RIGHT_BIQ0_COE ... (NAU8360_R200_RIGHT_BIQ0_COE + 194 NAU8360_PEQ_REG_WIDTH): 195 case NAU8360_R20C_RIGHT_BIQ1_COE ... (NAU8360_R20C_RIGHT_BIQ1_COE + 196 NAU8360_PEQ_REG_WIDTH): 197 case NAU8360_R218_RIGHT_BIQ2_COE ... (NAU8360_R218_RIGHT_BIQ2_COE + 198 NAU8360_PEQ_REG_WIDTH): 199 case NAU8360_R224_RIGHT_BIQ3_COE ... (NAU8360_R224_RIGHT_BIQ3_COE + 200 NAU8360_PEQ_REG_WIDTH): 201 case NAU8360_R230_RIGHT_BIQ4_COE ... (NAU8360_R230_RIGHT_BIQ4_COE + 202 NAU8360_PEQ_REG_WIDTH): 203 case NAU8360_R23C_RIGHT_BIQ5_COE ... (NAU8360_R23C_RIGHT_BIQ5_COE + 204 NAU8360_PEQ_REG_WIDTH): 205 case NAU8360_R248_RIGHT_BIQ6_COE ... (NAU8360_R248_RIGHT_BIQ6_COE + 206 NAU8360_PEQ_REG_WIDTH): 207 case NAU8360_R254_RIGHT_BIQ7_COE ... (NAU8360_R254_RIGHT_BIQ7_COE + 208 NAU8360_PEQ_REG_WIDTH): 209 case NAU8360_R260_RIGHT_BIQ8_COE ... (NAU8360_R260_RIGHT_BIQ8_COE + 210 NAU8360_PEQ_REG_WIDTH): 211 case NAU8360_R26C_RIGHT_BIQ9_COE ... (NAU8360_R26C_RIGHT_BIQ9_COE + 212 NAU8360_PEQ_REG_WIDTH): 213 case NAU8360_R278_RIGHT_BIQ10_COE ... (NAU8360_R278_RIGHT_BIQ10_COE + 214 NAU8360_PEQ_REG_WIDTH): 215 case NAU8360_R284_RIGHT_BIQ11_COE ... (NAU8360_R284_RIGHT_BIQ11_COE + 216 NAU8360_PEQ_REG_WIDTH): 217 case NAU8360_R290_RIGHT_BIQ12_COE ... (NAU8360_R290_RIGHT_BIQ12_COE + 218 NAU8360_PEQ_REG_WIDTH): 219 case NAU8360_R29C_RIGHT_BIQ13_COE ... (NAU8360_R29C_RIGHT_BIQ13_COE + 220 NAU8360_PEQ_REG_WIDTH): 221 case NAU8360_R2A8_RIGHT_BIQ14_COE ... (NAU8360_R2A8_RIGHT_BIQ14_COE + 222 NAU8360_PEQ_REG_WIDTH): 223 case NAU8360_RF000_DSP_COMM: 224 case NAU8360_RF002_DSP_COMM: 225 return true; 226 default: 227 return false; 228 } 229 230 } 231 232 static bool nau8360_writeable_reg(struct device *dev, unsigned int reg) 233 { 234 switch (reg) { 235 case NAU8360_R00_SOFTWARE_RST ... NAU8360_R12_PATH_CTRL: 236 case NAU8360_R17_I2S0_DATA_CTRL5: 237 case NAU8360_R1A_DSP_CORE_CTRL2: 238 case NAU8360_R2C_ALC_CTRL1 ... NAU8360_R2E_ALC_CTRL3: 239 case NAU8360_R31_UVLOP_CTRL1 ... NAU8360_R33_UVLOP_CTRL3: 240 case NAU8360_R40_CLK_DET_CTRL ... NAU8360_R41_CLK_CTL2: 241 case NAU8360_R5D_SINC_CFG: 242 case NAU8360_R5F_ANA_TRIM_CFG1: 243 case NAU8360_R60_RST: 244 case NAU8360_R67_ANALOG_CONTROL_0 ... NAU8360_R68_ANALOG_CONTROL_1: 245 case NAU8360_R6A_SARADC_CFG0 ... NAU8360_R6E_DAC_CFG0: 246 case NAU8360_R71_CLK_DIV_CFG ... NAU8360_R74_PLL_CFG2: 247 case NAU8360_R77_SOFT_SD ... NAU8360_R7C_MISC_TRIM_CFG: 248 case NAU8360_R7E_CLK_GATED_EN: 249 case NAU8360_R86_HW3_CTL0: 250 case NAU8360_R88_ALC_CTRL6: 251 case NAU8360_R8A_HW3_VL_CTL7 ... NAU8360_R90_HW2_CTL0: 252 case NAU8360_R96_HW2_CTL6 ... NAU8360_R9D_PEQ_CTL: 253 case NAU8360_RA4_ANA_REG_0 ... NAU8360_RA5_ANA_REG_1: 254 case NAU8360_R100_LEFT_BIQ0_COE ... (NAU8360_R100_LEFT_BIQ0_COE + 255 NAU8360_PEQ_REG_WIDTH): 256 case NAU8360_R10C_LEFT_BIQ1_COE ... (NAU8360_R10C_LEFT_BIQ1_COE + 257 NAU8360_PEQ_REG_WIDTH): 258 case NAU8360_R118_LEFT_BIQ2_COE ... (NAU8360_R118_LEFT_BIQ2_COE + 259 NAU8360_PEQ_REG_WIDTH): 260 case NAU8360_R124_LEFT_BIQ3_COE ... (NAU8360_R124_LEFT_BIQ3_COE + 261 NAU8360_PEQ_REG_WIDTH): 262 case NAU8360_R130_LEFT_BIQ4_COE ... (NAU8360_R130_LEFT_BIQ4_COE + 263 NAU8360_PEQ_REG_WIDTH): 264 case NAU8360_R13C_LEFT_BIQ5_COE ... (NAU8360_R13C_LEFT_BIQ5_COE + 265 NAU8360_PEQ_REG_WIDTH): 266 case NAU8360_R148_LEFT_BIQ6_COE ... (NAU8360_R148_LEFT_BIQ6_COE + 267 NAU8360_PEQ_REG_WIDTH): 268 case NAU8360_R154_LEFT_BIQ7_COE ... (NAU8360_R154_LEFT_BIQ7_COE + 269 NAU8360_PEQ_REG_WIDTH): 270 case NAU8360_R160_LEFT_BIQ8_COE ... (NAU8360_R160_LEFT_BIQ8_COE + 271 NAU8360_PEQ_REG_WIDTH): 272 case NAU8360_R16C_LEFT_BIQ9_COE ... (NAU8360_R16C_LEFT_BIQ9_COE + 273 NAU8360_PEQ_REG_WIDTH): 274 case NAU8360_R178_LEFT_BIQ10_COE ... (NAU8360_R178_LEFT_BIQ10_COE + 275 NAU8360_PEQ_REG_WIDTH): 276 case NAU8360_R184_LEFT_BIQ11_COE ... (NAU8360_R184_LEFT_BIQ11_COE + 277 NAU8360_PEQ_REG_WIDTH): 278 case NAU8360_R190_LEFT_BIQ12_COE ... (NAU8360_R190_LEFT_BIQ12_COE + 279 NAU8360_PEQ_REG_WIDTH): 280 case NAU8360_R19C_LEFT_BIQ13_COE ... (NAU8360_R19C_LEFT_BIQ13_COE + 281 NAU8360_PEQ_REG_WIDTH): 282 case NAU8360_R1A8_LEFT_BIQ14_COE ... (NAU8360_R1A8_LEFT_BIQ14_COE + 283 NAU8360_PEQ_REG_WIDTH): 284 case NAU8360_R200_RIGHT_BIQ0_COE ... (NAU8360_R200_RIGHT_BIQ0_COE + 285 NAU8360_PEQ_REG_WIDTH): 286 case NAU8360_R20C_RIGHT_BIQ1_COE ... (NAU8360_R20C_RIGHT_BIQ1_COE + 287 NAU8360_PEQ_REG_WIDTH): 288 case NAU8360_R218_RIGHT_BIQ2_COE ... (NAU8360_R218_RIGHT_BIQ2_COE + 289 NAU8360_PEQ_REG_WIDTH): 290 case NAU8360_R224_RIGHT_BIQ3_COE ... (NAU8360_R224_RIGHT_BIQ3_COE + 291 NAU8360_PEQ_REG_WIDTH): 292 case NAU8360_R230_RIGHT_BIQ4_COE ... (NAU8360_R230_RIGHT_BIQ4_COE + 293 NAU8360_PEQ_REG_WIDTH): 294 case NAU8360_R23C_RIGHT_BIQ5_COE ... (NAU8360_R23C_RIGHT_BIQ5_COE + 295 NAU8360_PEQ_REG_WIDTH): 296 case NAU8360_R248_RIGHT_BIQ6_COE ... (NAU8360_R248_RIGHT_BIQ6_COE + 297 NAU8360_PEQ_REG_WIDTH): 298 case NAU8360_R254_RIGHT_BIQ7_COE ... (NAU8360_R254_RIGHT_BIQ7_COE + 299 NAU8360_PEQ_REG_WIDTH): 300 case NAU8360_R260_RIGHT_BIQ8_COE ... (NAU8360_R260_RIGHT_BIQ8_COE + 301 NAU8360_PEQ_REG_WIDTH): 302 case NAU8360_R26C_RIGHT_BIQ9_COE ... (NAU8360_R26C_RIGHT_BIQ9_COE + 303 NAU8360_PEQ_REG_WIDTH): 304 case NAU8360_R278_RIGHT_BIQ10_COE ... (NAU8360_R278_RIGHT_BIQ10_COE + 305 NAU8360_PEQ_REG_WIDTH): 306 case NAU8360_R284_RIGHT_BIQ11_COE ... (NAU8360_R284_RIGHT_BIQ11_COE + 307 NAU8360_PEQ_REG_WIDTH): 308 case NAU8360_R290_RIGHT_BIQ12_COE ... (NAU8360_R290_RIGHT_BIQ12_COE + 309 NAU8360_PEQ_REG_WIDTH): 310 case NAU8360_R29C_RIGHT_BIQ13_COE ... (NAU8360_R29C_RIGHT_BIQ13_COE + 311 NAU8360_PEQ_REG_WIDTH): 312 case NAU8360_R2A8_RIGHT_BIQ14_COE ... (NAU8360_R2A8_RIGHT_BIQ14_COE + 313 NAU8360_PEQ_REG_WIDTH): 314 case NAU8360_RF000_DSP_COMM: 315 case NAU8360_RF002_DSP_COMM: 316 return true; 317 default: 318 return false; 319 } 320 } 321 322 static bool nau8360_volatile_reg(struct device *dev, unsigned int reg) 323 { 324 switch (reg) { 325 case NAU8360_R00_SOFTWARE_RST ... NAU8360_R02_I2C_ADDR: 326 case NAU8360_R06_INT_CLR_STATUS: 327 case NAU8360_R21_VBAT_READOUT ... NAU8360_R22_TEMP_READOUT: 328 case NAU8360_R41_CLK_CTL2: 329 case NAU8360_R46_I2C_DEVICE_ID: 330 case NAU8360_R69_ANALOG_CONTROL_3: 331 case NAU8360_R77_SOFT_SD ... NAU8360_R79_EN_HIRC48M: 332 case NAU8360_R7E_CLK_GATED_EN: 333 case NAU8360_R9D_PEQ_CTL: 334 case NAU8360_RF000_DSP_COMM: 335 case NAU8360_RF002_DSP_COMM: 336 return true; 337 default: 338 return false; 339 } 340 } 341 342 static int nau8360_get_tdm_chan_len(struct nau8360 *nau8360) 343 { 344 int val = 0; 345 346 regmap_read(nau8360->regmap, NAU8360_R0C_I2S_PCM_CTRL2, &val); 347 val = (val & NAU8360_TDM_CLEN_MASK) >> NAU8360_TDM_CLEN_SFT; 348 349 return (val << 3) + 16; 350 } 351 352 static inline bool nau8360_dsp_active(struct snd_soc_component *comp) 353 { 354 return (snd_soc_component_read(comp, NAU8360_R12_PATH_CTRL) & 355 NAU8360_DAC_SEL_DSP); 356 } 357 358 static int nau8360_anc_put(struct snd_kcontrol *kcontrol, 359 struct snd_ctl_elem_value *ucontrol) 360 { 361 struct snd_soc_component *cp = snd_kcontrol_chip(kcontrol); 362 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 363 int ret, value = NAU8360_PEQ_BAND_8; 364 365 mutex_lock(&nau8360->lock); 366 367 ret = snd_soc_put_volsw(kcontrol, ucontrol); 368 /* update anc flag if return value 1 and register value changed */ 369 if (ret != 1) 370 goto unlock; 371 372 nau8360->anc_enable = ucontrol->value.integer.value[0]; 373 if (nau8360_dsp_active(cp)) 374 value = nau8360->anc_enable ? NAU8360_PEQ_BAND_15 : NAU8360_PEQ_BAND_12; 375 regmap_update_bits(nau8360->regmap, NAU8360_R9D_PEQ_CTL, NAU8360_PEQ_BAND_MASK, 376 value << NAU8360_PEQ_BAND_SFT); 377 378 unlock: 379 mutex_unlock(&nau8360->lock); 380 381 return ret; 382 } 383 384 static inline void nau8360_peq_mem_enable(struct regmap *regmap, bool enable) 385 { 386 regmap_update_bits(regmap, NAU8360_R9D_PEQ_CTL, 387 NAU8360_HW1_MEM_TEST, enable ? NAU8360_HW1_MEM_TEST : 0); 388 } 389 390 static inline int nau8360_peq_regaddr(const char *id_name) 391 { 392 int reg, band_num, dsp_addr = NAU8360_DSP_ADDR_BYNAME(id_name); 393 char *band = strstr(id_name, "BIQ"); 394 395 if (!band || kstrtoint((band + 3), 10, &band_num)) 396 return -EINVAL; 397 reg = dsp_addr == NAU8360_RF000_DSP_COMM ? NAU8360_R100_LEFT_BIQ0_COE : 398 NAU8360_R200_RIGHT_BIQ0_COE; 399 reg += band_num * NAU8360_TOT_BAND_COE_RANGE; 400 401 return reg; 402 } 403 404 static int nau8360_peq_coeff_get(struct snd_kcontrol *kcontrol, 405 struct snd_ctl_elem_value *ucontrol) 406 { 407 struct snd_soc_component *cp = snd_kcontrol_chip(kcontrol); 408 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(cp); 409 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 410 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 411 int i, value, reg, ret = 0; 412 __be16 *val = (__be16 *)ucontrol->value.bytes.data; 413 414 /* Use the DAPM lock to prevent race conditions during DAPM power-up 415 * state transitions, and check component active status to prohibit 416 * PEQ access during active audio streams (playback and capture). 417 */ 418 snd_soc_dapm_mutex_lock(dapm); 419 if (snd_soc_component_active(cp)) { 420 dev_dbg(nau8360->dev, 421 "PEQ coefficient access is ignored during audio is active"); 422 ret = -EBUSY; 423 goto unlock_dapm; 424 } 425 426 reg = nau8360_peq_regaddr(kcontrol->id.name); 427 if (reg < 0) { 428 ret = reg; 429 goto unlock_dapm; 430 } 431 432 mutex_lock(&nau8360->lock); 433 nau8360_peq_mem_enable(nau8360->regmap, true); 434 for (i = 0; i < params->max / sizeof(u16); i++) { 435 value = snd_soc_component_read(cp, reg + i); 436 *(val + i) = cpu_to_be16(value); 437 } 438 nau8360_peq_mem_enable(nau8360->regmap, false); 439 mutex_unlock(&nau8360->lock); 440 441 unlock_dapm: 442 snd_soc_dapm_mutex_unlock(dapm); 443 444 return ret; 445 } 446 447 static int nau8360_peq_coeff_put(struct snd_kcontrol *kcontrol, 448 struct snd_ctl_elem_value *ucontrol) 449 { 450 struct snd_soc_component *cp = snd_kcontrol_chip(kcontrol); 451 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(cp); 452 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 453 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 454 int i, reg, ret = 0; 455 __be16 *data = NULL; 456 bool changed = false; 457 458 /* Use the DAPM lock to prevent race conditions during DAPM power-up 459 * state transitions, and check component active status to prohibit 460 * PEQ access during active audio streams (playback and capture). 461 */ 462 snd_soc_dapm_mutex_lock(dapm); 463 if (snd_soc_component_active(cp)) { 464 dev_dbg(nau8360->dev, 465 "PEQ coefficient access is ignored during audio is active"); 466 ret = -EBUSY; 467 goto unlock_dapm; 468 } 469 470 reg = nau8360_peq_regaddr(kcontrol->id.name); 471 if (reg < 0) { 472 ret = reg; 473 goto unlock_dapm; 474 } 475 476 data = kmemdup(ucontrol->value.bytes.data, params->max, GFP_KERNEL); 477 if (!data) { 478 ret = -ENOMEM; 479 goto unlock_dapm; 480 } 481 482 mutex_lock(&nau8360->lock); 483 nau8360_peq_mem_enable(nau8360->regmap, true); 484 for (i = 0; i < params->max / sizeof(u16); i++) { 485 if (snd_soc_component_read(cp, reg + i) != be16_to_cpu(*(data + i))) { 486 snd_soc_component_write(cp, reg + i, be16_to_cpu(*(data + i))); 487 changed = true; 488 } 489 } 490 nau8360_peq_mem_enable(nau8360->regmap, false); 491 mutex_unlock(&nau8360->lock); 492 493 ret = changed ? 1 : 0; 494 495 unlock_dapm: 496 snd_soc_dapm_mutex_unlock(dapm); 497 kfree(data); 498 499 return ret; 500 } 501 502 #define NAU8360_PEQ_COEF_BYTES_EXT(ch, band) \ 503 SND_SOC_BYTES_EXT(ch " PEQ Coefficients " band, 20, nau8360_peq_coeff_get, \ 504 nau8360_peq_coeff_put) 505 506 static const struct snd_kcontrol_new nau8360_snd_controls[] = { 507 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ0"), 508 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ1"), 509 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ2"), 510 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ3"), 511 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ4"), 512 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ5"), 513 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ6"), 514 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ7"), 515 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ8"), 516 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ9"), 517 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ10"), 518 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ11"), 519 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ12"), 520 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ13"), 521 NAU8360_PEQ_COEF_BYTES_EXT("Left", "BIQ14"), 522 523 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ0"), 524 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ1"), 525 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ2"), 526 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ3"), 527 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ4"), 528 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ5"), 529 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ6"), 530 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ7"), 531 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ8"), 532 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ9"), 533 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ10"), 534 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ11"), 535 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ12"), 536 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ13"), 537 NAU8360_PEQ_COEF_BYTES_EXT("Right", "BIQ14"), 538 SOC_SINGLE("Low Latency Switch", NAU8360_R96_HW2_CTL6, 539 NAU8360_HW2_LATENCY_SFT, 1, 0), 540 SOC_SINGLE_EXT("ANC Path Switch", NAU8360_R96_HW2_CTL6, NAU8360_HW1_ANC_EN_SFT, 541 1, 0, snd_soc_get_volsw, nau8360_anc_put), 542 }; 543 544 static int nau8360_adci_event(struct snd_soc_dapm_widget *w, 545 struct snd_kcontrol *kcontrol, int event) 546 { 547 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 548 549 if (SND_SOC_DAPM_EVENT_ON(event)) 550 snd_soc_component_update_bits(component, NAU8360_R6C_IVSNS_CFG0, 551 NAU8360_PD_ISNS_R_PMD | NAU8360_PD_ISNS_L_PMD, 0); 552 else if (SND_SOC_DAPM_EVENT_OFF(event)) 553 snd_soc_component_update_bits(component, NAU8360_R6C_IVSNS_CFG0, 554 NAU8360_PD_ISNS_R_PMD | NAU8360_PD_ISNS_L_PMD, 555 NAU8360_PD_ISNS_R_PMD | NAU8360_PD_ISNS_L_PMD); 556 557 return 0; 558 } 559 560 static int nau8360_adcv_event(struct snd_soc_dapm_widget *w, 561 struct snd_kcontrol *kcontrol, int event) 562 { 563 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 564 565 if (SND_SOC_DAPM_EVENT_ON(event)) 566 snd_soc_component_update_bits(component, NAU8360_R6C_IVSNS_CFG0, 567 NAU8360_PD_VSNS_R_PMD | NAU8360_PD_VSNS_L_PMD, 0); 568 else if (SND_SOC_DAPM_EVENT_OFF(event)) 569 snd_soc_component_update_bits(component, NAU8360_R6C_IVSNS_CFG0, 570 NAU8360_PD_VSNS_R_PMD | NAU8360_PD_VSNS_L_PMD, 571 NAU8360_PD_VSNS_R_PMD | NAU8360_PD_VSNS_L_PMD); 572 573 return 0; 574 } 575 576 static int nau8360_aif_event(struct snd_soc_dapm_widget *w, 577 struct snd_kcontrol *kcontrol, int event) 578 { 579 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 580 581 if (SND_SOC_DAPM_EVENT_OFF(event)) 582 snd_soc_component_update_bits(component, NAU8360_R67_ANALOG_CONTROL_0, 583 NAU8360_HV_EN, 0); 584 585 return 0; 586 } 587 588 static int nau8360_hw1_event(struct snd_soc_dapm_widget *w, 589 struct snd_kcontrol *kcontrol, int event) 590 { 591 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 592 593 if (SND_SOC_DAPM_EVENT_OFF(event)) 594 snd_soc_component_update_bits(component, NAU8360_R67_ANALOG_CONTROL_0, 595 NAU8360_ANA_MUTE, NAU8360_ANA_MUTE); 596 597 return 0; 598 } 599 600 static int nau8360_hw1_mux_event(struct snd_soc_dapm_widget *w, 601 struct snd_kcontrol *kcontrol, int event) 602 { 603 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 604 605 if (SND_SOC_DAPM_EVENT_OFF(event)) { 606 snd_soc_component_update_bits(component, NAU8360_R68_ANALOG_CONTROL_1, 607 NAU8360_DRVCTL_SEGL_FULL | NAU8360_DRVCTL_SEGR_FULL, 0); 608 snd_soc_component_update_bits(component, NAU8360_RA5_ANA_REG_1, 609 NAU8360_CLASSD_SHT_IN | NAU8360_HVEN_SYNC_SAW, 610 NAU8360_CLASSD_SHT_IN | NAU8360_HVEN_SYNC_SAW); 611 msleep(20); 612 } 613 614 return 0; 615 } 616 617 static int nau8360_hw2_event(struct snd_soc_dapm_widget *w, 618 struct snd_kcontrol *kcontrol, int event) 619 { 620 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 621 622 if (SND_SOC_DAPM_EVENT_ON(event)) { 623 snd_soc_component_update_bits(component, NAU8360_R99_HW2_CTL9, 624 NAU8360_HW2_CH_MUTE, 0); 625 snd_soc_component_update_bits(component, NAU8360_R9C_HW1_CTL2, 626 NAU8360_HW1_CH_MUTE, 0); 627 } 628 629 return 0; 630 } 631 632 static int nau8360_dac_power_event(struct snd_soc_dapm_widget *w, 633 struct snd_kcontrol *kcontrol, int event) 634 { 635 struct snd_soc_component *cp = snd_soc_dapm_to_component(w->dapm); 636 unsigned int mask = 1 << w->shift; 637 638 if (SND_SOC_DAPM_EVENT_ON(event)) 639 snd_soc_component_update_bits(cp, NAU8360_R6E_DAC_CFG0, mask, 0); 640 else if (SND_SOC_DAPM_EVENT_OFF(event)) 641 snd_soc_component_update_bits(cp, NAU8360_R6E_DAC_CFG0, mask, mask); 642 643 return 0; 644 } 645 646 static int nau8360_hv_event(struct snd_soc_dapm_widget *w, 647 struct snd_kcontrol *kcontrol, int event) 648 { 649 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 650 651 if (SND_SOC_DAPM_EVENT_ON(event)) { 652 /* enable Class D HV power after DAC power is stable */ 653 snd_soc_component_update_bits(component, NAU8360_R67_ANALOG_CONTROL_0, 654 NAU8360_HV_EN, NAU8360_HV_EN); 655 msleep(50); 656 /* Class D modulator input short setting for mute and de-pop purpose. 657 * Restore normal after initiation. Set segment driver as full driving 658 * strength. 659 */ 660 snd_soc_component_update_bits(component, NAU8360_RA5_ANA_REG_1, 661 NAU8360_CLASSD_SHT_IN | NAU8360_HVEN_SYNC_SAW, 0); 662 snd_soc_component_update_bits(component, NAU8360_R68_ANALOG_CONTROL_1, 663 NAU8360_DRVCTL_SEGL_FULL | NAU8360_DRVCTL_SEGR_FULL, 664 NAU8360_DRVCTL_SEGL_FULL | NAU8360_DRVCTL_SEGR_FULL); 665 666 snd_soc_component_update_bits(component, NAU8360_R67_ANALOG_CONTROL_0, 667 NAU8360_ANA_MUTE, 0); 668 } else if (SND_SOC_DAPM_EVENT_OFF(event)) { 669 snd_soc_component_update_bits(component, NAU8360_R9C_HW1_CTL2, 670 NAU8360_HW1_CH_MUTE, NAU8360_HW1_CH_MUTE); 671 snd_soc_component_update_bits(component, NAU8360_R99_HW2_CTL9, 672 NAU8360_HW2_CH_MUTE, NAU8360_HW2_CH_MUTE); 673 } 674 675 return 0; 676 } 677 678 static inline void nau8360_dsp_enable(struct regmap *regmap, bool enable) 679 { 680 regmap_update_bits(regmap, NAU8360_R86_HW3_CTL0, NAU8360_HW3_STALL, 681 enable ? 0 : NAU8360_HW3_STALL); 682 regmap_update_bits(regmap, NAU8360_R1A_DSP_CORE_CTRL2, NAU8360_DSP_RUNSTALL, 683 enable ? 0 : NAU8360_DSP_RUNSTALL); 684 } 685 686 static void nau8360_dsp_switch(struct snd_soc_component *component, bool enable) 687 { 688 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 689 struct regmap *regmap = nau8360->regmap; 690 int value = NAU8360_PEQ_BAND_8; 691 692 /* If DSP is enabled, unstall HW3 engine and DSP, loading DSP firmware, 693 * and configure PEQ after dsp reset. 694 */ 695 if (enable) { 696 value = nau8360->anc_enable ? NAU8360_PEQ_BAND_15 : NAU8360_PEQ_BAND_12; 697 nau8360_dsp_enable(regmap, true); 698 } else { 699 dev_dbg(nau8360->dev, "Bypass DSP path"); 700 nau8360_dsp_enable(regmap, false); 701 } 702 regmap_update_bits(regmap, NAU8360_R9D_PEQ_CTL, NAU8360_PEQ_BAND_MASK, 703 value << NAU8360_PEQ_BAND_SFT); 704 705 } 706 707 static int nau8360_dac_mux_put_enum(struct snd_kcontrol *kcontrol, 708 struct snd_ctl_elem_value *ucontrol) 709 { 710 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 711 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 712 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 713 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 714 unsigned int *item = ucontrol->value.enumerated.item; 715 int ret = 0; 716 717 if (snd_soc_dapm_get_bias_level(dapm) > SND_SOC_BIAS_STANDBY) { 718 dev_warn(nau8360->dev, "changing path is not allowed during playback"); 719 return ret; 720 } 721 722 mutex_lock(&nau8360->lock); 723 724 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 725 if (ret <= 0) 726 goto unlock; 727 728 nau8360_dsp_switch(component, snd_soc_enum_item_to_val(e, item[0])); 729 730 unlock: 731 mutex_unlock(&nau8360->lock); 732 733 return ret; 734 } 735 736 /* Select HW1 output source (enables PEQ bypass) */ 737 static const char *const nau8360_hw1out_src[] = { "Audio", "PEQ" }; 738 739 static SOC_ENUM_SINGLE_DECL(nau8360_hw1out_enum, NAU8360_R12_PATH_CTRL, 740 NAU8360_SEL_HW1_SFT, nau8360_hw1out_src); 741 742 static const struct snd_kcontrol_new nau8360_hw1out_mux = 743 SOC_DAPM_ENUM("HW1 Output Source", nau8360_hw1out_enum); 744 745 /* Select DAC input source (enables DSP bypass) */ 746 static const char *const nau8360_dac_src[] = { "HW1", "DSP" }; 747 748 static SOC_ENUM_SINGLE_DECL(nau8360_dac_enum, NAU8360_R12_PATH_CTRL, 749 NAU8360_DAC_SEL_SFT, nau8360_dac_src); 750 751 static const struct snd_kcontrol_new nau8360_dac_mux = 752 SOC_DAPM_ENUM_EXT("DAC Source", nau8360_dac_enum, 753 snd_soc_dapm_get_enum_double, nau8360_dac_mux_put_enum); 754 755 static const struct snd_soc_dapm_widget nau8360_dapm_widgets[] = { 756 SND_SOC_DAPM_SIGGEN("Sense"), 757 SND_SOC_DAPM_ADC_E("ADC_I", NULL, SND_SOC_NOPM, 0, 0, nau8360_adci_event, 758 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 759 SND_SOC_DAPM_ADC_E("ADC_V", NULL, SND_SOC_NOPM, 0, 0, nau8360_adcv_event, 760 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 761 762 SND_SOC_DAPM_PGA("DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 763 SND_SOC_DAPM_PGA("HW3 Engine", NAU8360_R8C_HW3_CTL6, 3, 0, NULL, 0), 764 765 SND_SOC_DAPM_AIF_IN_E("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0, 766 nau8360_aif_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 767 768 SND_SOC_DAPM_PGA_S("HW1 Engine", 0, NAU8360_R9D_PEQ_CTL, 0, 1, 769 nau8360_hw1_event, SND_SOC_DAPM_POST_PMD), 770 SND_SOC_DAPM_MUX_E("HW1 Mux", SND_SOC_NOPM, 0, 0, &nau8360_hw1out_mux, 771 nau8360_hw1_mux_event, SND_SOC_DAPM_POST_PMD), 772 773 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0, &nau8360_dac_mux), 774 775 SND_SOC_DAPM_PGA_S("HW2 Engine", 1, NAU8360_R96_HW2_CTL6, 5, 0, 776 nau8360_hw2_event, SND_SOC_DAPM_POST_PMU), 777 778 SND_SOC_DAPM_SUPPLY("DAC Clock", NAU8360_R71_CLK_DIV_CFG, 9, 1, NULL, 0), 779 SND_SOC_DAPM_DAC_E("DACL", NULL, SND_SOC_NOPM, NAU8360_PD_DACL_SFT, 0, 780 nau8360_dac_power_event, SND_SOC_DAPM_POST_PMD), 781 SND_SOC_DAPM_DAC_E("DACR", NULL, SND_SOC_NOPM, NAU8360_PD_DACR_SFT, 0, 782 nau8360_dac_power_event, SND_SOC_DAPM_POST_PMD), 783 SND_SOC_DAPM_PGA_S("ADACL", 2, SND_SOC_NOPM, NAU8360_PD_DACL_SFT, 0, 784 nau8360_dac_power_event, SND_SOC_DAPM_POST_PMU), 785 SND_SOC_DAPM_PGA_S("ADACR", 2, SND_SOC_NOPM, NAU8360_PD_DACR_SFT, 0, 786 nau8360_dac_power_event, SND_SOC_DAPM_POST_PMU), 787 SND_SOC_DAPM_PGA_S("Class D", 3, SND_SOC_NOPM, 0, 0, 788 nau8360_hv_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 789 790 SND_SOC_DAPM_OUTPUT("OUTL"), 791 SND_SOC_DAPM_OUTPUT("OUTR"), 792 }; 793 794 static const struct snd_soc_dapm_route nau8360_dapm_routes[] = { 795 { "ADC_I", NULL, "Sense" }, 796 { "ADC_V", NULL, "Sense" }, 797 { "HW3 Engine", NULL, "ADC_I" }, 798 { "HW3 Engine", NULL, "ADC_V" }, 799 { "Capture", NULL, "HW3 Engine" }, 800 801 { "HW1 Engine", NULL, "AIFRX" }, 802 { "HW1 Mux", "Audio", "AIFRX" }, 803 { "HW1 Mux", "PEQ", "HW1 Engine" }, 804 805 { "DSP", NULL, "HW1 Mux" }, 806 { "DAC Mux", "HW1", "HW1 Mux" }, 807 { "DAC Mux", "DSP", "DSP" }, 808 809 { "HW2 Engine", NULL, "DAC Mux" }, 810 { "DACL", NULL, "HW2 Engine" }, 811 { "DACR", NULL, "HW2 Engine" }, 812 { "DACL", NULL, "DAC Clock" }, 813 { "DACR", NULL, "DAC Clock" }, 814 815 { "ADACL", NULL, "DACL" }, 816 { "ADACR", NULL, "DACR" }, 817 { "Class D", NULL, "ADACL" }, 818 { "Class D", NULL, "ADACR" }, 819 820 { "OUTL", NULL, "Class D" }, 821 { "OUTR", NULL, "Class D" }, 822 }; 823 824 static int nau8360_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 825 { 826 struct snd_soc_component *component = dai->component; 827 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 828 unsigned int i2s_mask = NAU8360_FRAME_START_MASK | NAU8360_RX_OFFSET_MASK; 829 unsigned int i2s_fmt = NAU8360_FRAME_START_H2L | NAU8360_RX_OFFSET_I2S; 830 int val = 0; 831 832 flush_work(&nau8360->load_fw_work); 833 834 if (nau8360_dsp_active(component) && !nau8360->load_fw_done) { 835 dev_warn(nau8360->dev, "DSP firmware is not ready yet!"); 836 return -EBUSY; 837 } 838 839 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 840 regmap_read(nau8360->regmap, NAU8360_R0B_I2S_PCM_CTRL1, &val); 841 if ((val & i2s_mask) == i2s_fmt) 842 regmap_update_bits(nau8360->regmap, NAU8360_R0B_I2S_PCM_CTRL1, 843 NAU8360_EN_TDM_RX, NAU8360_EN_TDM_RX); 844 845 if (nau8360_dsp_active(component)) 846 snd_soc_dapm_enable_pin(nau8360->dapm, "Sense"); 847 } 848 849 return 0; 850 } 851 852 static void nau8360_shutdown(struct snd_pcm_substream *substream, 853 struct snd_soc_dai *dai) 854 { 855 struct snd_soc_component *component = dai->component; 856 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 857 unsigned int tdm_mask; 858 859 tdm_mask = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 860 NAU8360_EN_TDM_RX : NAU8360_EN_TDM_TX; 861 regmap_update_bits(nau8360->regmap, NAU8360_R0B_I2S_PCM_CTRL1, 862 tdm_mask, 0); 863 if (nau8360_dsp_active(component) && 864 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 865 snd_soc_dapm_disable_pin(nau8360->dapm, "Sense"); 866 } 867 868 static int nau8360_hw_params(struct snd_pcm_substream *substream, 869 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 870 { 871 struct snd_soc_component *component = dai->component; 872 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 873 unsigned int val_len, val_srate; 874 int dlen = params_width(params); 875 876 if (dlen > nau8360_get_tdm_chan_len(nau8360)) { 877 dev_err(nau8360->dev, "Invalid data length"); 878 return -EINVAL; 879 } 880 881 switch (dlen) { 882 case 16: 883 val_len = NAU8360_TDM_DLEN_16; 884 break; 885 case 20: 886 val_len = NAU8360_TDM_DLEN_20; 887 break; 888 case 24: 889 val_len = NAU8360_TDM_DLEN_24; 890 break; 891 case 32: 892 val_len = NAU8360_TDM_DLEN_32; 893 break; 894 default: 895 return -EINVAL; 896 } 897 898 switch (params_rate(params)) { 899 case 16000: 900 val_srate = NAU8360_SRATE_16000; 901 break; 902 case 32000: 903 val_srate = NAU8360_SRATE_32000; 904 break; 905 case 44100: 906 case 48000: 907 val_srate = NAU8360_SRATE_48000; 908 break; 909 case 88200: 910 case 96000: 911 val_srate = NAU8360_SRATE_96000; 912 break; 913 case 176400: 914 case 192000: 915 val_srate = NAU8360_SRATE_192000; 916 break; 917 default: 918 return -EINVAL; 919 } 920 921 regmap_update_bits(nau8360->regmap, NAU8360_R0C_I2S_PCM_CTRL2, 922 NAU8360_TDM_DLEN_MASK, val_len); 923 regmap_update_bits(nau8360->regmap, NAU8360_R40_CLK_DET_CTRL, 924 NAU8360_SRATE_MASK, val_srate); 925 926 return 0; 927 } 928 929 static int nau8360_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 930 { 931 struct snd_soc_component *component = dai->component; 932 unsigned int ctrl_val, ctrl1_val; 933 934 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 935 case SND_SOC_DAIFMT_CBC_CFC: 936 break; 937 default: 938 return -EINVAL; 939 } 940 941 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 942 case SND_SOC_DAIFMT_NB_NF: 943 break; 944 default: 945 return -EINVAL; 946 } 947 948 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 949 case SND_SOC_DAIFMT_I2S: 950 ctrl_val = NAU8360_FRAME_START_H2L | NAU8360_RX_OFFSET_I2S; 951 ctrl1_val = NAU8360_TX_OFFSET_I2S; 952 break; 953 case SND_SOC_DAIFMT_LEFT_J: 954 ctrl_val = NAU8360_RX_OFFSET_LEFT | NAU8360_RX_LEFT_JUSTIFY; 955 ctrl1_val = NAU8360_TX_OFFSET_LEFT; 956 break; 957 case SND_SOC_DAIFMT_RIGHT_J: 958 ctrl_val = NAU8360_RX_OFFSET_RIGHT | NAU8360_RX_RIGHT_JUSTIFY; 959 ctrl1_val = NAU8360_TX_OFFSET_RIGHT; 960 break; 961 case SND_SOC_DAIFMT_DSP_A: 962 ctrl_val = NAU8360_RX_OFFSET_PCM_A; 963 ctrl1_val = NAU8360_TX_OFFSET_PCM_A; 964 break; 965 case SND_SOC_DAIFMT_DSP_B: 966 ctrl_val = NAU8360_RX_OFFSET_PCM_B; 967 ctrl1_val = NAU8360_TX_OFFSET_PCM_B; 968 break; 969 default: 970 return -EINVAL; 971 } 972 973 snd_soc_component_update_bits(component, NAU8360_R0B_I2S_PCM_CTRL1, 974 NAU8360_FRAME_START_MASK | NAU8360_RX_OFFSET_MASK | 975 NAU8360_RX_JUSTIFY_MASK, ctrl_val); 976 snd_soc_component_update_bits(component, NAU8360_R0D_I2S_PCM_CTRL3, 977 NAU8360_TX_OFFSET_MASK, ctrl1_val); 978 return 0; 979 } 980 981 static void nau8360_set_tdm_rx_slot(struct snd_soc_component *cp, int type, int slot) 982 { 983 switch (type) { 984 case NAU8360_TDM_DACL: 985 snd_soc_component_update_bits(cp, NAU8360_R0C_I2S_PCM_CTRL2, 986 NAU8360_RX_DACL_MASK, slot); 987 break; 988 989 case NAU8360_TDM_DACR: 990 snd_soc_component_update_bits(cp, NAU8360_R0C_I2S_PCM_CTRL2, 991 NAU8360_RX_DACR_MASK, (slot << NAU8360_RX_DACR_SFT)); 992 break; 993 994 case NAU8360_TDM_ANCL: 995 snd_soc_component_update_bits(cp, NAU8360_R10_I2S_DATA_CTRL3, 996 NAU8360_RX_ANC_L_MASK, (slot << NAU8360_RX_ANC_L_SFT)); 997 break; 998 999 case NAU8360_TDM_ANCR: 1000 snd_soc_component_update_bits(cp, NAU8360_R10_I2S_DATA_CTRL3, 1001 NAU8360_RX_ANC_R_MASK, (slot << NAU8360_RX_ANC_R_SFT)); 1002 break; 1003 } 1004 } 1005 1006 static void nau8360_set_tdm_tx_slot(struct snd_soc_component *cp, int type, int slot) 1007 { 1008 switch (type) { 1009 case NAU8360_TDM_AECL: 1010 snd_soc_component_update_bits(cp, NAU8360_R17_I2S0_DATA_CTRL5, 1011 NAU8360_AEC_L_SLOT_MASK, slot << NAU8360_AEC_L_SLOT_SFT); 1012 break; 1013 1014 case NAU8360_TDM_AECR: 1015 snd_soc_component_update_bits(cp, NAU8360_R17_I2S0_DATA_CTRL5, 1016 NAU8360_AEC_R_SLOT_MASK, slot); 1017 break; 1018 1019 case NAU8360_TDM_ISNSL: 1020 snd_soc_component_update_bits(cp, NAU8360_R0E_I2S_DATA_CTRL1, 1021 NAU8360_ISNS_L_SLOT_MASK, slot << NAU8360_ISNS_L_SLOT_SFT); 1022 break; 1023 1024 case NAU8360_TDM_ISNSR: 1025 snd_soc_component_update_bits(cp, NAU8360_R11_I2S_DATA_CTRL4, 1026 NAU8360_ISNS_R_SLOT_MASK, slot); 1027 break; 1028 1029 case NAU8360_TDM_VSNSL: 1030 snd_soc_component_update_bits(cp, NAU8360_R0D_I2S_PCM_CTRL3, 1031 NAU8360_VSNS_L_SLOT_MASK, slot); 1032 break; 1033 1034 case NAU8360_TDM_VSNSR: 1035 snd_soc_component_update_bits(cp, NAU8360_R11_I2S_DATA_CTRL4, 1036 NAU8360_VSNS_R_SLOT_MASK, slot << NAU8360_VSNS_R_SLOT_SFT); 1037 break; 1038 1039 case NAU8360_TDM_TJ: 1040 snd_soc_component_update_bits(cp, NAU8360_R10_I2S_DATA_CTRL3, 1041 NAU8360_TEMP_SLOT_MASK, slot); 1042 break; 1043 1044 case NAU8360_TDM_VBAT: 1045 snd_soc_component_update_bits(cp, NAU8360_R0F_I2S_DATA_CTRL2, 1046 NAU8360_VBAT_SLOT_MASK, slot << NAU8360_VBAT_SLOT_SFT); 1047 break; 1048 } 1049 } 1050 1051 static void nau8360_set_tdm_tx_func(struct snd_soc_component *cp, int type, bool enable) 1052 { 1053 switch (type) { 1054 case NAU8360_TDM_AECL: 1055 snd_soc_component_update_bits(cp, NAU8360_R17_I2S0_DATA_CTRL5, 1056 NAU8360_AEC_L_EN, enable ? NAU8360_AEC_L_EN : 0); 1057 break; 1058 case NAU8360_TDM_AECR: 1059 snd_soc_component_update_bits(cp, NAU8360_R17_I2S0_DATA_CTRL5, 1060 NAU8360_AEC_R_EN, enable ? NAU8360_AEC_R_EN : 0); 1061 break; 1062 case NAU8360_TDM_ISNSL: 1063 snd_soc_component_update_bits(cp, NAU8360_R0E_I2S_DATA_CTRL1, 1064 NAU8360_ISNS_L_TX_EN, enable ? NAU8360_ISNS_L_TX_EN : 0); 1065 break; 1066 case NAU8360_TDM_ISNSR: 1067 snd_soc_component_update_bits(cp, NAU8360_R11_I2S_DATA_CTRL4, 1068 NAU8360_ISNS_R_TX_EN, enable ? NAU8360_ISNS_R_TX_EN : 0); 1069 break; 1070 case NAU8360_TDM_VSNSL: 1071 snd_soc_component_update_bits(cp, NAU8360_R0D_I2S_PCM_CTRL3, 1072 NAU8360_VSNS_L_TX_EN, enable ? NAU8360_VSNS_L_TX_EN : 0); 1073 break; 1074 case NAU8360_TDM_VSNSR: 1075 snd_soc_component_update_bits(cp, NAU8360_R11_I2S_DATA_CTRL4, 1076 NAU8360_VSNS_R_TX_EN, enable ? NAU8360_VSNS_R_TX_EN : 0); 1077 break; 1078 case NAU8360_TDM_TJ: 1079 snd_soc_component_update_bits(cp, NAU8360_R10_I2S_DATA_CTRL3, 1080 NAU8360_TEMP_TX_EN, enable ? NAU8360_TEMP_TX_EN : 0); 1081 break; 1082 case NAU8360_TDM_VBAT: 1083 snd_soc_component_update_bits(cp, NAU8360_R0F_I2S_DATA_CTRL2, 1084 NAU8360_VBAT_TX_EN, enable ? NAU8360_VBAT_TX_EN : 0); 1085 break; 1086 } 1087 } 1088 1089 static int nau8360_validate_tdm_slots(struct device *dev, unsigned int mask, 1090 const u32 *func_slots, const char * const *func_names, 1091 int num_funcs, const char *dir, 1092 unsigned int *slot_used) 1093 { 1094 int i; 1095 unsigned int func_slot; 1096 *slot_used = 0; 1097 1098 if (!mask) 1099 return 0; 1100 1101 for (i = 0; i < num_funcs; i++) { 1102 func_slot = func_slots[i]; 1103 if (func_slot == TDM_SLOT_NONE) { 1104 dev_warn(dev, "%s %s slot disabled", 1105 dir, func_names[i]); 1106 continue; 1107 } 1108 1109 if (!(mask & BIT(func_slot))) { 1110 dev_warn(dev, "%s %s mapped to slot %d, but disabled by mask!", 1111 dir, func_names[i], func_slot); 1112 continue; 1113 } 1114 1115 if (*slot_used & BIT(func_slot)) { 1116 dev_err(dev, "%s %s slot %d collision!", 1117 dir, func_names[i], func_slot); 1118 return -EINVAL; 1119 } 1120 1121 *slot_used |= BIT(func_slot); 1122 } 1123 1124 return 0; 1125 } 1126 1127 static void nau8360_enable_tdm_channels(struct snd_soc_component *cp, 1128 int rx_slot_used, int tx_slot_used) 1129 { 1130 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 1131 int i, slot; 1132 unsigned int val = 0; 1133 bool enable; 1134 1135 for (i = 0; i < NAU8360_TDM_TXN; i++) { 1136 slot = nau8360->tdm_tx_func_slot[i]; 1137 enable = (slot != TDM_SLOT_NONE) && (tx_slot_used & BIT(slot)); 1138 nau8360_set_tdm_tx_func(cp, i, enable); 1139 } 1140 1141 if (rx_slot_used) 1142 val |= NAU8360_EN_TDM_RX; 1143 if (tx_slot_used) 1144 val |= NAU8360_EN_TDM_TX; 1145 1146 snd_soc_component_update_bits(cp, NAU8360_R0B_I2S_PCM_CTRL1, 1147 NAU8360_EN_TDM_RX | NAU8360_EN_TDM_TX, val); 1148 } 1149 1150 static void nau8360_tdm_apply(struct snd_soc_component *cp, int slot_width) 1151 { 1152 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 1153 int i, chan_tx; 1154 1155 for (i = 0; i < NAU8360_TDM_TXN; i++) { 1156 if (nau8360->tdm_tx_func_slot[i] == TDM_SLOT_NONE) 1157 continue; 1158 1159 /* compute the slot location in bytes according to slot/chan width */ 1160 chan_tx = (slot_width >> 3) * nau8360->tdm_tx_func_slot[i]; 1161 nau8360_set_tdm_tx_slot(cp, i, chan_tx); 1162 } 1163 1164 regmap_update_bits(nau8360->regmap, NAU8360_R0C_I2S_PCM_CTRL2, 1165 NAU8360_TDM_CLEN_MASK, 1166 ((slot_width - 16) >> 3) << NAU8360_TDM_CLEN_SFT); 1167 } 1168 1169 static int nau8360_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1170 unsigned int rx_mask, int slots, int slot_width) 1171 { 1172 struct snd_soc_component *cp = dai->component; 1173 struct device *dev = cp->dev; 1174 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 1175 unsigned int tx_slot_used = 0, rx_slot_used = 0; 1176 int ret = 0; 1177 1178 if (!slots || !slot_width) { 1179 nau8360_enable_tdm_channels(cp, 0, 0); 1180 return ret; 1181 } 1182 1183 if (slots > NAU8360_TDM_MAX_CHAN) { 1184 dev_err(dev, "Invalid TDM slots: %d", slots); 1185 return -EINVAL; 1186 } 1187 1188 if (slot_width != 16 && slot_width != 24 && slot_width != 32) { 1189 dev_err(dev, "Invalid TDM channel length: %d", slot_width); 1190 return -EINVAL; 1191 } 1192 1193 ret = nau8360_validate_tdm_slots(cp->dev, rx_mask, 1194 nau8360->tdm_rx_func_slot, 1195 nau8360_rx_func_names, 1196 NAU8360_TDM_RXN, "RX", 1197 &rx_slot_used); 1198 if (ret < 0) 1199 goto err; 1200 1201 ret = nau8360_validate_tdm_slots(cp->dev, tx_mask, 1202 nau8360->tdm_tx_func_slot, 1203 nau8360_tx_func_names, 1204 NAU8360_TDM_TXN, "TX", 1205 &tx_slot_used); 1206 if (ret < 0) 1207 goto err; 1208 1209 if (nau8360_get_tdm_chan_len(nau8360) != slot_width) 1210 nau8360_tdm_apply(cp, slot_width); 1211 1212 nau8360_enable_tdm_channels(cp, rx_slot_used, tx_slot_used); 1213 1214 dev_dbg(dev, "TDM: tx_mask 0x%x, rx_mask 0x%x", tx_mask, rx_mask); 1215 err: 1216 return ret; 1217 } 1218 1219 static inline int dyn_clk_div(int div_max, int fin, int fout) 1220 { 1221 int clk_div; 1222 1223 if (!fin || !fout) 1224 return -EINVAL; 1225 1226 for (clk_div = 0; clk_div <= div_max; clk_div++) 1227 if (fin / (clk_div + 1) <= fout) 1228 break; 1229 if (clk_div > div_max) 1230 return -EINVAL; 1231 1232 return clk_div; 1233 } 1234 1235 static inline int tab_clk_div(const int clk_div[], int num_div, int fin) 1236 { 1237 int i; 1238 1239 if (!fin) 1240 return -EINVAL; 1241 1242 for (i = 0; i < num_div; i++) 1243 if ((fin / clk_div[i]) <= CLK_DA_IVSNS_MAX) 1244 break; 1245 if (i == num_div) 1246 return -EINVAL; 1247 1248 return i; 1249 } 1250 1251 static int nau8360_set_sysclk_output(struct nau8360 *nau8360, unsigned int freq) 1252 { 1253 struct device *dev = nau8360->dev; 1254 int ratio = 0, mclk_rate; 1255 1256 if (freq < MASTER_CLK_MIN || freq > MASTER_CLK_MAX) { 1257 dev_err(dev, "system clock %d Hz exceed range", freq); 1258 return -EINVAL; 1259 } 1260 1261 if (freq % ADSP_SR_48000 == 0) 1262 ratio = freq / ADSP_SR_48000; 1263 else if (freq % ADSP_SR_44100 == 0) 1264 ratio = freq / ADSP_SR_44100; 1265 1266 switch (ratio) { 1267 case NAU8360_MCLK_FS_RATIO_250: 1268 mclk_rate = NAU8360_MCLK_RATE_12000; 1269 break; 1270 case NAU8360_MCLK_FS_RATIO_256: 1271 mclk_rate = NAU8360_MCLK_RATE_12288; 1272 break; 1273 case NAU8360_MCLK_FS_RATIO_400: 1274 mclk_rate = NAU8360_MCLK_RATE_19200; 1275 break; 1276 case NAU8360_MCLK_FS_RATIO_500: 1277 mclk_rate = NAU8360_MCLK_RATE_24000; 1278 break; 1279 case NAU8360_MCLK_FS_RATIO_512: 1280 mclk_rate = NAU8360_MCLK_RATE_24576; 1281 break; 1282 default: 1283 dev_err(dev, "invalid sysclk %d", freq); 1284 return -EINVAL; 1285 } 1286 1287 dev_dbg(dev, "sysclk %d Hz, ratio %d", freq, ratio); 1288 1289 nau8360->sys_clk = freq; 1290 regmap_update_bits(nau8360->regmap, NAU8360_R40_CLK_DET_CTRL, 1291 NAU8360_MCLK_RATE_MASK, mclk_rate); 1292 1293 return 0; 1294 } 1295 1296 static int nau8360_dig_sys_clk(struct nau8360 *nau8360, int source, unsigned int freq) 1297 { 1298 struct device *dev = nau8360->dev; 1299 struct regmap *regmap = nau8360->regmap; 1300 int value, mclk_div; 1301 1302 switch (source) { 1303 case NAU8360_CLK_SRC_MCLK: 1304 value = NAU8360_MCLK_SEL_MCLK; 1305 break; 1306 1307 case NAU8360_CLK_SRC_PLL: 1308 value = NAU8360_MCLK_SEL_PLL; 1309 break; 1310 1311 default: 1312 return -EINVAL; 1313 } 1314 1315 regmap_update_bits(regmap, NAU8360_R04_CLK_CTRL1, NAU8360_MCLK_SEL_MASK, value); 1316 1317 mclk_div = dyn_clk_div(NAU8360_MCLK_DIV_MAX, freq, nau8360->sys_clk); 1318 if (mclk_div < 0) { 1319 dev_err(dev, "mclk_div (%d -> %d): error", freq, nau8360->sys_clk); 1320 return -EINVAL; 1321 } 1322 regmap_update_bits(regmap, NAU8360_R03_CLK_CTRL0, NAU8360_MCLK_DIV_MASK, 1323 mclk_div << NAU8360_MCLK_DIV_SFT); 1324 1325 dev_dbg(dev, " mclk_div (%d -> %d): %d", freq, nau8360->sys_clk, mclk_div + 1); 1326 1327 return 0; 1328 } 1329 1330 static int nau8360_ana_sys_clk(struct nau8360 *nau8360, int source, unsigned int freq) 1331 { 1332 struct device *dev = nau8360->dev; 1333 struct regmap *regmap = nau8360->regmap; 1334 struct nau8360_pll *pll = &nau8360->pll; 1335 int value, pclk_div, ivdiv_sel, ddiv_sel; 1336 1337 switch (source) { 1338 case NAU8360_CLK_SRC_PLL: 1339 value = NAU8360_CLK_ANA_SEL_PLL; 1340 break; 1341 case NAU8360_CLK_SRC_MCLK: 1342 value = NAU8360_CLK_ANA_SEL_MCLK; 1343 break; 1344 case NAU8360_CLK_SRC_BCLK: 1345 value = NAU8360_CLK_ANA_SEL_BCLK; 1346 break; 1347 default: 1348 return -EINVAL; 1349 } 1350 1351 if (source == NAU8360_CLK_SRC_PLL) { 1352 freq = pll->output; 1353 pclk_div = dyn_clk_div(NAU8360_PLLOUT_DIV_MAX, freq, nau8360->sys_clk); 1354 if (pclk_div < 0) { 1355 dev_err(dev, "pll_div (%d -> %d): error", freq, nau8360->sys_clk); 1356 return -EINVAL; 1357 } 1358 1359 dev_dbg(dev, " pll_div (%d -> %d): %d", freq, nau8360->sys_clk, pclk_div + 1); 1360 1361 regmap_update_bits(regmap, NAU8360_R72_PLL_CFG0, NAU8360_PLLOUT_DIV_MASK, 1362 pclk_div << NAU8360_PLLOUT_DIV_SFT); 1363 freq /= (pclk_div + 1); 1364 } 1365 1366 ivdiv_sel = tab_clk_div(ivsns_clk_div, ARRAY_SIZE(ivsns_clk_div), freq); 1367 if (ivdiv_sel < 0) { 1368 dev_err(dev, "iv_div (%d -> %d): error", freq, CLK_DA_IVSNS_MAX); 1369 return -EINVAL; 1370 } 1371 value |= ivdiv_sel << NAU8360_IVSNS_CLK_DIV_SFT; 1372 1373 ddiv_sel = tab_clk_div(dac_clk_div, ARRAY_SIZE(dac_clk_div), freq); 1374 if (ddiv_sel < 0) { 1375 dev_err(dev, "dac_div (%d -> %d): error", freq, CLK_DA_IVSNS_MAX); 1376 return -EINVAL; 1377 } 1378 value |= ddiv_sel << NAU8360_DAC_CLK_DIV_SFT; 1379 1380 dev_dbg(dev, " clk_div (%d -> %d): ivsns %d, dac %d", freq, CLK_DA_IVSNS_MAX, 1381 ivsns_clk_div[ivdiv_sel], dac_clk_div[ddiv_sel]); 1382 1383 regmap_update_bits(regmap, NAU8360_R71_CLK_DIV_CFG, NAU8360_CLK_ANA_SEL_MASK | 1384 NAU8360_IVSNS_CLK_DIV_MASK | NAU8360_DAC_CLK_DIV_MASK, value); 1385 1386 return 0; 1387 } 1388 1389 static int nau8360_dsp_hw_clk(struct nau8360 *nau8360, int source, unsigned int freq) 1390 { 1391 struct device *dev = nau8360->dev; 1392 struct regmap *regmap = nau8360->regmap; 1393 int val_dsp, val_hw, clk_div, dsp_clk; 1394 1395 if (freq % ADSP_SR_48000 == 0) 1396 dsp_clk = DSP_OP_CLK48; 1397 else if (freq % ADSP_SR_44100 == 0) 1398 dsp_clk = DSP_OP_CLK44; 1399 else 1400 return -EINVAL; 1401 clk_div = dyn_clk_div(NAU8360_DSP_CLK_DIV_MAX, freq, dsp_clk); 1402 if (clk_div < 0) { 1403 dev_err(dev, "dsp/hw clk_div (%d -> %d): error", freq, dsp_clk); 1404 return -EINVAL; 1405 } 1406 val_dsp = clk_div << NAU8360_DSP_CLK_DIV_SFT; 1407 val_hw = clk_div << NAU8360_HW_CLK_DIV_SFT; 1408 if (source == NAU8360_CLK_SRC_MCLK) { 1409 val_dsp |= NAU8360_DSP_CLK_SEL_MCLK; 1410 val_hw |= NAU8360_HW_CLK_SEL_MCLK; 1411 } else if (source == NAU8360_CLK_SRC_PLL) { 1412 val_dsp |= NAU8360_DSP_CLK_SEL_PLL; 1413 val_hw |= NAU8360_HW_CLK_SEL_PLL; 1414 } else 1415 return -EINVAL; 1416 1417 dev_dbg(dev, " dsp/hw clk_div (%d -> %d): %d", freq, dsp_clk, clk_div + 1); 1418 1419 regmap_update_bits(regmap, NAU8360_R03_CLK_CTRL0, NAU8360_DSP_CLK_SEL_MASK | 1420 NAU8360_DSP_CLK_DIV_MASK, val_dsp); 1421 regmap_update_bits(regmap, NAU8360_R04_CLK_CTRL1, NAU8360_HW_CLK_SEL_MASK | 1422 NAU8360_HW_CLK_DIV_MASK, val_hw); 1423 1424 return 0; 1425 } 1426 1427 static int nau8360_set_sysclk(struct snd_soc_component *cp, 1428 int clk_id, int source, unsigned int freq, int dir) 1429 { 1430 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 1431 struct regmap *regmap = nau8360->regmap; 1432 struct device *dev = nau8360->dev; 1433 static const char * const idtab[] = { "DIG", "ANA", "Internal" }; 1434 static const char * const srctab[] = { "MCLK", "PLL", "HIRC48M", "BCLK" }; 1435 int ret; 1436 1437 if (clk_id < 0 || clk_id >= ARRAY_SIZE(idtab)) 1438 return -EINVAL; 1439 1440 if (source < 0 || source >= ARRAY_SIZE(srctab)) 1441 return -EINVAL; 1442 1443 if (dir == SND_SOC_CLOCK_OUT) { 1444 dev_dbg(dev, "sysclk: freq %d (out)", freq); 1445 return nau8360_set_sysclk_output(nau8360, freq); 1446 } 1447 1448 switch (clk_id) { 1449 case NAU8360_CLK_ID_INT: 1450 source = NAU8360_CLK_SRC_ICLK; 1451 dev_dbg(dev, "sysclk: id %d (%s), src %d (%s) (in)", 1452 clk_id, idtab[clk_id], source, srctab[source]); 1453 regmap_update_bits(regmap, NAU8360_R03_CLK_CTRL0, 1454 NAU8360_DSP_CLK_SEL_MASK, NAU8360_DSP_CLK_SEL_HIRC48M); 1455 regmap_update_bits(regmap, NAU8360_R04_CLK_CTRL1, 1456 NAU8360_HW_CLK_SEL_MASK | NAU8360_MCLK_SEL_MASK, 1457 NAU8360_HW_CLK_SEL_HIRC48M | NAU8360_MCLK_SEL_HIRC48M); 1458 regmap_update_bits(regmap, NAU8360_R72_PLL_CFG0, 1459 NAU8360_PD_PLL_MASK, NAU8360_PD_PLL_DIS); 1460 break; 1461 1462 case NAU8360_CLK_ID_DIG: 1463 dev_dbg(dev, "sysclk: id %d (%s), src %d (%s), freq %d (in)", 1464 clk_id, idtab[clk_id], source, srctab[source], freq); 1465 1466 if (source == NAU8360_CLK_SRC_BCLK) 1467 return -EINVAL; 1468 1469 if (source == NAU8360_CLK_SRC_MCLK) 1470 regmap_update_bits(regmap, NAU8360_R72_PLL_CFG0, 1471 NAU8360_PD_PLL_MASK, NAU8360_PD_PLL_DIS); 1472 1473 ret = nau8360_dig_sys_clk(nau8360, source, freq); 1474 if (ret) 1475 return -EINVAL; 1476 ret = nau8360_dsp_hw_clk(nau8360, source, freq); 1477 if (ret) 1478 return -EINVAL; 1479 break; 1480 1481 case NAU8360_CLK_ID_ANA: 1482 dev_dbg(dev, "sysclk: id %d (%s), src %d (%s), freq %d (in)", 1483 clk_id, idtab[clk_id], source, srctab[source], freq); 1484 1485 if (source == NAU8360_CLK_SRC_MCLK || source == NAU8360_CLK_SRC_BCLK) 1486 regmap_update_bits(regmap, NAU8360_R72_PLL_CFG0, 1487 NAU8360_PD_PLL_MASK, NAU8360_PD_PLL_DIS); 1488 1489 ret = nau8360_ana_sys_clk(nau8360, source, freq); 1490 if (ret) 1491 return -EINVAL; 1492 break; 1493 1494 default: 1495 return -EINVAL; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static int nau8360_calc_pll(struct nau8360 *nau8360) 1502 { 1503 struct nau8360_pll *pll = &nau8360->pll; 1504 u64 fref = 0ULL, fvco = 0ULL, ratio; 1505 int fr, fv; 1506 1507 if (pll->src != NAU8360_PLL_INTERNAL && 1508 (pll->input > PLL_FREQ_MAX || pll->input < PLL_FREQ_MIN)) 1509 return -EINVAL; 1510 1511 if (pll->output > PLL_FOUT_MAX || pll->output < PLL_FOUT_MIN) 1512 return -EINVAL; 1513 1514 for (pll->msel = 1; pll->msel <= MSEL_MAX; pll->msel++) { 1515 fr = pll->input / pll->msel; 1516 if (fr <= PLL_FREF_MAX) { 1517 fref = fr; 1518 break; 1519 } 1520 } 1521 if (!fref) 1522 return -ERANGE; 1523 1524 for (pll->rsel = 1; pll->rsel <= RSEL_MAX; pll->rsel++) { 1525 fv = pll->output * pll->rsel; 1526 if (fv >= PLL_FVCO_MIN) { 1527 fvco = fv; 1528 break; 1529 } 1530 } 1531 if (!fvco) 1532 return -ERANGE; 1533 1534 dev_dbg(nau8360->dev, "fref(1-8MHz): %lld, fvco(50-125MHz): %lld", fref, fvco); 1535 1536 /* Calculate the PLL 8-bit integer input and 12-bit fractional */ 1537 ratio = div_u64(fvco << 12, fref); 1538 pll->nsel = (ratio >> 12) & 0xff; 1539 pll->xsel = ratio & 0xfff; 1540 1541 return 0; 1542 } 1543 1544 static int nau8360_set_pll(struct snd_soc_component *cp, int pll_id, int source, 1545 unsigned int freq_in, unsigned int freq_out) 1546 { 1547 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 1548 struct device *dev = nau8360->dev; 1549 struct nau8360_pll *pll = &nau8360->pll; 1550 int ctrl_val, ret; 1551 1552 switch (source) { 1553 case NAU8360_PLL_MCLK: 1554 ctrl_val = NAU8360_PLL_CLK_SEL_MCLK; 1555 break; 1556 case NAU8360_PLL_BCLK: 1557 ctrl_val = NAU8360_PLL_CLK_SEL_BCLK; 1558 break; 1559 case NAU8360_PLL_INTERNAL: 1560 ctrl_val = NAU8360_PLL_CLK_SEL_HIRC; 1561 break; 1562 default: 1563 return -EINVAL; 1564 } 1565 pll->src = source; 1566 pll->input = freq_in; 1567 pll->output = freq_out; 1568 ret = nau8360_calc_pll(nau8360); 1569 if (ret) { 1570 dev_err(dev, "clock error input %d output %d", freq_in, freq_out); 1571 return ret; 1572 } 1573 dev_dbg(dev, "src:%d, input:%d, output:%d, M:%d, R:%d, N:%d, X:%d", pll->src, 1574 pll->input, pll->output, pll->msel, pll->rsel, pll->nsel, pll->xsel); 1575 1576 regmap_update_bits(nau8360->regmap, NAU8360_R72_PLL_CFG0, NAU8360_PD_PLL_MASK | 1577 NAU8360_PLL_CLK_SEL_MASK, NAU8360_PD_PLL_EN | ctrl_val); 1578 regmap_write_bits(nau8360->regmap, NAU8360_R73_PLL_CFG1, 1579 NAU8360_RSEL_MASK | NAU8360_MSEL_MASK | NAU8360_NSEL_MASK, 1580 (pll->rsel - 1) << NAU8360_RSEL_SFT | 1581 (pll->msel - 1) << NAU8360_MSEL_SFT | (pll->nsel - 1)); 1582 regmap_write_bits(nau8360->regmap, NAU8360_R74_PLL_CFG2, NAU8360_XSEL_MASK, 1583 pll->xsel); 1584 1585 return 0; 1586 } 1587 1588 static void nau8360_coeff_set_def(struct nau8360 *nau8360) 1589 { 1590 struct regmap *regmap = nau8360->regmap; 1591 int i; 1592 1593 mutex_lock(&nau8360->lock); 1594 regmap_update_bits(regmap, NAU8360_R9D_PEQ_CTL, NAU8360_HW1_MEM_CLEAR, 1595 NAU8360_HW1_MEM_CLEAR); 1596 regmap_update_bits(regmap, NAU8360_R9D_PEQ_CTL, NAU8360_HW1_MEM_CLEAR, 0); 1597 nau8360_peq_mem_enable(regmap, true); 1598 for (i = 0; i < NAU8360_TOT_BAND_PER_CH; i++) { 1599 regmap_write(regmap, NAU8360_R100_LEFT_BIQ0_COE + 1 + 1600 i * NAU8360_TOT_BAND_COE_RANGE, 0x20); 1601 regmap_write(regmap, NAU8360_R200_RIGHT_BIQ0_COE + 1 + 1602 i * NAU8360_TOT_BAND_COE_RANGE, 0x20); 1603 } 1604 nau8360_peq_mem_enable(regmap, false); 1605 regmap_update_bits(regmap, NAU8360_R9D_PEQ_CTL, NAU8360_PEQ_BAND_MASK, 1606 NAU8360_PEQ_BAND_8 << NAU8360_PEQ_BAND_SFT); 1607 mutex_unlock(&nau8360->lock); 1608 } 1609 1610 static inline int nau8360_vbat_level(struct regmap *regmap, int *vbat) 1611 { 1612 struct device *dev = regmap_get_device(regmap); 1613 int value = 0, ret; 1614 1615 ret = regmap_read(regmap, NAU8360_R21_VBAT_READOUT, &value); 1616 if (ret) 1617 return ret; 1618 1619 /* multiple 100 on value scale */ 1620 *vbat = (value * 100 + NAU8360_VBAT_BASE) / NAU8360_VBAT_STEP; 1621 if (*vbat < NAU8360_VBAT_MIN || *vbat > NAU8360_VBAT_MAX) { 1622 dev_err(dev, "VBAT %dV is out of valid range (%dV-%dV)", 1623 *vbat, NAU8360_VBAT_MIN, NAU8360_VBAT_MAX); 1624 return -ERANGE; 1625 } 1626 1627 return 0; 1628 } 1629 1630 static inline void nau8360_sawtooth_params(int vbat, int *vsaw_level, int *vsaw_slope) 1631 { 1632 if (vbat < NAU8360_VBAT_MID_THRES) { 1633 *vsaw_level = 0x1; 1634 *vsaw_slope = 0x0; 1635 } else if (vbat < NAU8360_VBAT_HIGH_THRES) { 1636 *vsaw_level = 0x2; 1637 *vsaw_slope = 0x1; 1638 } else { 1639 *vsaw_level = 0x3; 1640 *vsaw_slope = 0x2; 1641 } 1642 } 1643 1644 static inline void nau8360_dsp_software_reset(struct snd_soc_component *component) 1645 { 1646 /* Enable PLL for successful DSP reset. After DSP is alive, 1647 * system clock switches to internal clock and disable PLL. 1648 */ 1649 snd_soc_component_update_bits(component, NAU8360_R72_PLL_CFG0, 1650 NAU8360_PD_PLL_MASK, NAU8360_PD_PLL_EN); 1651 msleep(50); 1652 snd_soc_component_write(component, NAU8360_R01_DSP_SOFTWARE_RST, 0x5a5a); 1653 snd_soc_component_write(component, NAU8360_R01_DSP_SOFTWARE_RST, 0xa5a5); 1654 snd_soc_component_set_sysclk(component, NAU8360_CLK_ID_INT, 0, 0, 1655 SND_SOC_CLOCK_IN); 1656 } 1657 1658 static void nau8360_dsp_bootup(struct snd_soc_component *component) 1659 { 1660 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 1661 struct regmap *regmap = nau8360->regmap; 1662 1663 regmap_update_bits(regmap, NAU8360_R90_HW2_CTL0, NAU8360_HW2_STALL, 0); 1664 nau8360_dsp_software_reset(component); 1665 nau8360_dsp_enable(regmap, true); 1666 } 1667 1668 static void nau8360_tdm_function_config(struct snd_soc_component *cp) 1669 { 1670 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(cp); 1671 int i, chan_tx, tdm_chan_len; 1672 1673 for (i = 0; i < NAU8360_TDM_RXN; i++) { 1674 if (nau8360->tdm_rx_func_slot[i] == TDM_SLOT_NONE) 1675 continue; 1676 1677 nau8360_set_tdm_rx_slot(cp, i, nau8360->tdm_rx_func_slot[i]); 1678 } 1679 1680 tdm_chan_len = nau8360_get_tdm_chan_len(nau8360) >> 3; 1681 for (i = 0; i < NAU8360_TDM_TXN; i++) { 1682 if (nau8360->tdm_tx_func_slot[i] == TDM_SLOT_NONE) 1683 continue; 1684 1685 /* compute the slot location in bytes according to slot/chan width */ 1686 chan_tx = (tdm_chan_len * nau8360->tdm_tx_func_slot[i]); 1687 nau8360_set_tdm_tx_slot(cp, i, chan_tx); 1688 } 1689 } 1690 1691 static void nau8360_dsp_fw_load(struct nau8360 *nau8360) 1692 { 1693 nau8360->load_fw_done = false; 1694 schedule_work(&nau8360->load_fw_work); 1695 } 1696 1697 static void nau8360_load_fw_work(struct work_struct *work) 1698 { 1699 struct nau8360 *nau8360 = container_of(work, struct nau8360, load_fw_work); 1700 struct snd_soc_component *cp = snd_soc_dapm_to_component(nau8360->dapm); 1701 int ret; 1702 1703 ret = nau8360_dsp_init(cp); 1704 if (ret) { 1705 dev_err(nau8360->dev, "Failed to initialize DSP: %d\n", ret); 1706 nau8360_dsp_enable(nau8360->regmap, false); 1707 return; 1708 } 1709 nau8360->load_fw_done = true; 1710 } 1711 1712 static int nau8360_codec_probe(struct snd_soc_component *component) 1713 { 1714 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1715 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 1716 struct regmap *regmap = nau8360->regmap; 1717 struct device *dev = nau8360->dev; 1718 int ret, vbat, vsaw_level, vsaw_slope; 1719 1720 nau8360->dapm = dapm; 1721 nau8360_dsp_bootup(component); 1722 nau8360_dsp_fw_load(nau8360); 1723 ret = nau8360_dsp_setup_controls(component); 1724 if (ret) { 1725 nau8360_dsp_enable(regmap, false); 1726 dev_err(dev, "DSP setup controls failed(%d)", ret); 1727 goto err; 1728 } 1729 nau8360_tdm_function_config(component); 1730 1731 /* default disable Sense signal after booting */ 1732 snd_soc_dapm_disable_pin(nau8360->dapm, "Sense"); 1733 snd_soc_dapm_sync(nau8360->dapm); 1734 1735 nau8360_coeff_set_def(nau8360); 1736 /* VBAT is sensed by chip. */ 1737 ret = nau8360_vbat_level(regmap, &vbat); 1738 if (ret) { 1739 dev_err(dev, "Failed to get valid VBAT level: %d", ret); 1740 goto err; 1741 } 1742 dev_dbg(dev, "VBAT %dV for nau8360", vbat); 1743 1744 /* Config sawtooth clock according to VBAT. Class D modulator input short setting 1745 * for mute and de-pop purpose. Restore normal after initiation. 1746 */ 1747 nau8360_sawtooth_params(vbat, &vsaw_level, &vsaw_slope); 1748 1749 regmap_update_bits(regmap, NAU8360_RA5_ANA_REG_1, NAU8360_VSAW_LV_MASK | 1750 NAU8360_KVCO_SAW_MASK, (vsaw_level << NAU8360_VSAW_LV_SFT) | 1751 (vsaw_slope << NAU8360_KVCO_SAW_SFT)); 1752 1753 return 0; 1754 1755 err: 1756 cancel_work_sync(&nau8360->load_fw_work); 1757 return ret; 1758 } 1759 1760 static int __maybe_unused nau8360_suspend(struct snd_soc_component *component) 1761 { 1762 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 1763 1764 cancel_work_sync(&nau8360->load_fw_work); 1765 1766 regmap_update_bits(nau8360->regmap, NAU8360_R90_HW2_CTL0, NAU8360_HW2_STALL, 1767 NAU8360_HW2_STALL); 1768 nau8360_dsp_enable(nau8360->regmap, false); 1769 1770 regcache_cache_only(nau8360->regmap, true); 1771 regcache_mark_dirty(nau8360->regmap); 1772 1773 return 0; 1774 } 1775 1776 static int __maybe_unused nau8360_resume(struct snd_soc_component *component) 1777 { 1778 struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component); 1779 struct regmap *regmap = nau8360->regmap; 1780 1781 regcache_cache_only(regmap, false); 1782 1783 nau8360_dsp_bootup(component); 1784 1785 nau8360_peq_mem_enable(regmap, true); 1786 regcache_sync(regmap); 1787 nau8360_peq_mem_enable(regmap, false); 1788 1789 /* disable Sense at standby */ 1790 snd_soc_dapm_disable_pin(nau8360->dapm, "Sense"); 1791 snd_soc_dapm_sync(nau8360->dapm); 1792 1793 nau8360_dsp_fw_load(nau8360); 1794 1795 return 0; 1796 } 1797 1798 static const struct snd_soc_component_driver soc_comp_dev_nau8360 = { 1799 .probe = nau8360_codec_probe, 1800 .set_sysclk = nau8360_set_sysclk, 1801 .set_pll = nau8360_set_pll, 1802 .suspend = nau8360_suspend, 1803 .resume = nau8360_resume, 1804 .controls = nau8360_snd_controls, 1805 .num_controls = ARRAY_SIZE(nau8360_snd_controls), 1806 .dapm_widgets = nau8360_dapm_widgets, 1807 .num_dapm_widgets = ARRAY_SIZE(nau8360_dapm_widgets), 1808 .dapm_routes = nau8360_dapm_routes, 1809 .num_dapm_routes = ARRAY_SIZE(nau8360_dapm_routes), 1810 .suspend_bias_off = 1, 1811 .idle_bias_on = 1, 1812 .use_pmdown_time = 1, 1813 .endianness = 1, 1814 }; 1815 1816 static const struct snd_soc_dai_ops nau8360_dai_ops = { 1817 .startup = nau8360_startup, 1818 .shutdown = nau8360_shutdown, 1819 .hw_params = nau8360_hw_params, 1820 .set_fmt = nau8360_set_fmt, 1821 .set_tdm_slot = nau8360_set_tdm_slot, 1822 }; 1823 1824 #define NAU8360_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | \ 1825 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ 1826 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000) 1827 1828 #define NAU8360_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1829 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1830 1831 static struct snd_soc_dai_driver nau8360_dai = { 1832 .name = NAU8360_CODEC_DAI, 1833 .playback = { 1834 .stream_name = "Playback", 1835 .channels_min = 1, 1836 .channels_max = 4, 1837 .rates = NAU8360_RATES, 1838 .formats = NAU8360_FORMATS, 1839 }, 1840 .capture = { 1841 .stream_name = "Capture", 1842 .channels_min = 1, 1843 .channels_max = 8, 1844 .rates = NAU8360_RATES, 1845 .formats = NAU8360_FORMATS, 1846 }, 1847 .ops = &nau8360_dai_ops, 1848 .symmetric_rate = 1, 1849 }; 1850 1851 static int nau8360_reg_write(void *context, unsigned int reg, unsigned int value) 1852 { 1853 struct i2c_client *client = context; 1854 struct nau8360 *nau8360 = i2c_get_clientdata(client); 1855 int ret, count = 0; 1856 1857 put_unaligned_be16(reg, &nau8360->i2c_write_buf[count]); 1858 count += 2; 1859 1860 if (NAU8360_IS_DSP_REG(reg)) { 1861 /* format for DSP, 4 bytes value and native */ 1862 put_unaligned_le32(value, &nau8360->i2c_write_buf[count]); 1863 count += 4; 1864 } else { 1865 /* format for Codec, 2 bytes value and endian big */ 1866 put_unaligned_be16(value, &nau8360->i2c_write_buf[count]); 1867 count += 2; 1868 } 1869 1870 ret = i2c_master_send(client, nau8360->i2c_write_buf, count); 1871 1872 if (ret == count) 1873 return 0; 1874 if (ret < 0) 1875 return ret; 1876 1877 return -EIO; 1878 } 1879 1880 static int nau8360_reg_read(void *context, unsigned int reg, unsigned int *value) 1881 { 1882 struct i2c_client *client = context; 1883 struct nau8360 *nau8360 = i2c_get_clientdata(client); 1884 struct i2c_msg xfer[2]; 1885 int ret; 1886 1887 put_unaligned_be16(reg, &nau8360->i2c_read_reg); 1888 xfer[0].addr = client->addr; 1889 xfer[0].len = 2; 1890 xfer[0].buf = nau8360->i2c_read_reg; 1891 xfer[0].flags = 0; 1892 1893 xfer[1].addr = client->addr; 1894 xfer[1].len = (NAU8360_IS_DSP_REG(reg)) ? 4 : 2; 1895 xfer[1].buf = nau8360->i2c_read_buf; 1896 xfer[1].flags = I2C_M_RD; 1897 1898 ret = i2c_transfer(client->adapter, xfer, ARRAY_SIZE(xfer)); 1899 if (ret < 0) 1900 return ret; 1901 if (ret != ARRAY_SIZE(xfer)) 1902 return -EIO; 1903 1904 if (NAU8360_IS_DSP_REG(reg)) 1905 *value = get_unaligned_le32(nau8360->i2c_read_buf); 1906 else 1907 *value = get_unaligned_be16(nau8360->i2c_read_buf); 1908 1909 return 0; 1910 } 1911 1912 static const struct regmap_config nau8360_regmap_config = { 1913 .reg_bits = NAU8360_REG_ADDR_LEN, 1914 .val_bits = NAU8360_REG_DATA_LEN, 1915 1916 .max_register = NAU8360_REG_MAX, 1917 .readable_reg = nau8360_readable_reg, 1918 .writeable_reg = nau8360_writeable_reg, 1919 .volatile_reg = nau8360_volatile_reg, 1920 .reg_read = nau8360_reg_read, 1921 .reg_write = nau8360_reg_write, 1922 1923 .cache_type = REGCACHE_MAPLE, 1924 .reg_defaults = nau8360_reg_defaults, 1925 .num_reg_defaults = ARRAY_SIZE(nau8360_reg_defaults), 1926 }; 1927 1928 static inline void nau8360_reset_chip(struct regmap *regmap) 1929 { 1930 regmap_write(regmap, NAU8360_R00_SOFTWARE_RST, 0x5a5a); 1931 regmap_write(regmap, NAU8360_R00_SOFTWARE_RST, 0xa5a5); 1932 } 1933 1934 static void nau8360_init_regs(struct nau8360 *nau8360) 1935 { 1936 struct regmap *regmap = nau8360->regmap; 1937 1938 /* Enable Digital LDO */ 1939 regmap_write(regmap, NAU8360_R78_PD_SW_DLDO, NAU8360_PD_SW_DLDO_EN); 1940 /* Enable Software Shutdown Mode */ 1941 regmap_write(regmap, NAU8360_R77_SOFT_SD, NAU8360_SOFT_SD_EN); 1942 /* Stall HW1 PEQ Engine and Clear DRAM to Zero */ 1943 regmap_update_bits(regmap, NAU8360_R9D_PEQ_CTL, NAU8360_PEQ_STALL, 1944 NAU8360_PEQ_STALL); 1945 /* Stall HW2 engine */ 1946 regmap_update_bits(regmap, NAU8360_R90_HW2_CTL0, NAU8360_HW2_STALL, 1947 NAU8360_HW2_STALL); 1948 /* Stall HW3 engine and DSP processor */ 1949 nau8360_dsp_enable(regmap, false); 1950 /* Enable Clock Gate */ 1951 regmap_write(regmap, NAU8360_R7E_CLK_GATED_EN, NAU8360_CLK_GATED_EN); 1952 /* Latch I2C LSB Value */ 1953 regmap_write(regmap, NAU8360_R02_I2C_ADDR, 0x0001); 1954 /* ANC Left/Right Channel as Slot 2/3 and switch */ 1955 regmap_update_bits(regmap, NAU8360_R10_I2S_DATA_CTRL3, 1956 NAU8360_RX_ANC_R_MASK | NAU8360_RX_ANC_L_MASK, 1957 0x3 << NAU8360_RX_ANC_R_SFT | 0x2 << NAU8360_RX_ANC_L_SFT); 1958 /* Set DAC Clock Divider as 2 and Chopper Divider as 16 */ 1959 regmap_update_bits(regmap, NAU8360_R71_CLK_DIV_CFG, 1960 NAU8360_DAC_CLK_DIV_MASK | NAU8360_DAC_CHOP_CLK_DIV_MASK, 1961 NAU8360_DAC_CLK_DIV_2 | NAU8360_DAC_CHOP_CLK_DIV_16); 1962 /* Set DAC SINC OSR as 128 and IVSENSE BS OSR as 32 */ 1963 regmap_update_bits(regmap, NAU8360_R5D_SINC_CFG, 1964 NAU8360_DAC_SINC_OSR_MASK | NAU8360_IVSENSE_BS_OSR_MASK, 1965 NAU8360_DAC_SINC_OSR_128 | NAU8360_IVSENSE_BS_OSR_32); 1966 1967 /* Set Trim Bit Control of DLDO and GVDD to The Highest Voltage */ 1968 regmap_write(regmap, NAU8360_R5F_ANA_TRIM_CFG1, 0xf407); 1969 1970 /* Disable Data Det and Clock Detection Settings*/ 1971 regmap_update_bits(regmap, NAU8360_R40_CLK_DET_CTRL, NAU8360_APWRUPEN | 1972 NAU8360_CLKPWRUPEN | NAU8360_FS_MCLK_DET | NAU8360_FS_BCLK_DET, 0); 1973 1974 /* Set HW3 Droop and Filter Sample as 192K */ 1975 regmap_update_bits(regmap, NAU8360_R8C_HW3_CTL6, NAU8360_HW3_DROOP_MASK | 1976 NAU8360_HW3_FS_MASK, NAU8360_HW3_DROOP_192K | NAU8360_HW3_FS_192K); 1977 /* Set HW1 Mute, Mute Interval as 699ms and HW1 Zero THD as 0xff */ 1978 regmap_update_bits(regmap, NAU8360_R9C_HW1_CTL2, NAU8360_MUTE_INTRVL_MASK | 1979 NAU8360_HW1_CH_MUTE | NAU8360_HW1_ZERO_THD_MASK, 1980 NAU8360_MUTE_INTRVL_699MS | NAU8360_HW1_CH_MUTE | 0xff); 1981 /* set HW2 droop with 192K*/ 1982 regmap_update_bits(regmap, NAU8360_R96_HW2_CTL6, NAU8360_HW2_DROOP_SEL_MASK | 1983 NAU8360_HW2_DROOP_EN | NAU8360_HW2_FS_MASK, 1984 NAU8360_HW2_DROOP_SEL_LARGE | NAU8360_HW2_DROOP_EN | NAU8360_HW2_FS_192K); 1985 /* Set HW2 default volume */ 1986 regmap_write(regmap, NAU8360_R97_HW2_CTL7, 0xbf66); 1987 regmap_write(regmap, NAU8360_R98_HW2_CTL8, 0xbf66); 1988 /* Set HW2 Mute and Threshold of Zero Crossing */ 1989 regmap_update_bits(regmap, NAU8360_R99_HW2_CTL9, NAU8360_HW2_CH_MUTE | 1990 NAU8360_HW2_ZERO_THD_MASK, NAU8360_HW2_CH_MUTE | 0xff); 1991 /* According to DSP enabled or not, set stream path as 1992 * HW1->DSP->HW2->SINC->HW3 or HW1->HW2->SINC->HW3 1993 */ 1994 regmap_update_bits(regmap, NAU8360_R12_PATH_CTRL, NAU8360_SEL_HW1_MASK | 1995 NAU8360_AUD_SEL_MASK | NAU8360_SEL_HW2_MASK | NAU8360_SEL_HW3_MASK | 1996 NAU8360_DAC_SEL_MASK, NAU8360_SEL_HW1_OUT | NAU8360_AUD_SEL_SINCOUT | 1997 NAU8360_SEL_HW2_OUT | NAU8360_SEL_HW3_OUT); 1998 /* Set Input Status as Low and Input/Output Mode Disable for All GPIO */ 1999 regmap_write(regmap, NAU8360_R07_GP_CTRL, 0x0000); 2000 /* enable SARADC with extra average filter of VBAT */ 2001 regmap_update_bits(regmap, NAU8360_R6A_SARADC_CFG0, NAU8360_SARADC_EN | 2002 NAU8360_VBAT_AVG_EN, NAU8360_SARADC_EN | NAU8360_VBAT_AVG_EN); 2003 /* Enable Temperature Sensor, VBATDIV and VRF. 2004 * Set Average Filter Data as 512 for VTEMP and VBAT. 2005 */ 2006 regmap_update_bits(regmap, NAU8360_R6B_SARADC_CFG1, NAU8360_VTEMP_EN | 2007 NAU8360_VBATDIV_EN | NAU8360_VREF_EN | NAU8360_PRELOAD_VREF_EN | 2008 NAU8360_VTEMP_AVG_N_MASK | NAU8360_VBAT_AVG_N_MASK, NAU8360_VTEMP_EN | 2009 NAU8360_VBATDIV_EN | NAU8360_VREF_EN | NAU8360_PRELOAD_VREF_EN | 2010 NAU8360_VTEMP_AVG_N_512 | NAU8360_VBAT_AVG_N_512); 2011 /* Enable IV sense internal LDO */ 2012 regmap_update_bits(regmap, NAU8360_R6C_IVSNS_CFG0, 2013 NAU8360_PD_LDO_SDM_IVSNS_PMD, 0); 2014 /* Enable Bias Current and Reference Voltage for IVSENSE. Set VSNS Gain 2015 * as 1/12 and ISNS Gain as x16(24dB). Set PGA Current as 2'b11 and SDN 2016 * Delay as 2'b00. 2017 */ 2018 regmap_write(regmap, NAU8360_R6D_IVSNS_CFG1, 0x0f5c); 2019 /* sawtooth clock from ivsense clock, PWM frequency 432 Khz */ 2020 regmap_update_bits(regmap, NAU8360_RA4_ANA_REG_0, NAU8360_SEL_STCLK_MASK | 2021 NAU8360_NSEL_SAW_MASK, NAU8360_SEL_STCLK_IVCLK | 0x8); 2022 /* sawtooth PLL APR */ 2023 regmap_update_bits(regmap, NAU8360_RA5_ANA_REG_1, NAU8360_SAW_PLL_MASK, 2024 NAU8360_SAW_PLL_NOR); 2025 2026 /* Set DAC gain (0dB/+3.2dB) by current cell adjustment */ 2027 regmap_update_bits(regmap, NAU8360_R6E_DAC_CFG0, NAU8360_DAC_CUR_MASK, 2028 nau8360->dac_cur_enable ? NAU8360_DAC_CUR_3_2DB : NAU8360_DAC_CUR_0DB); 2029 /* Config trim short current reference. Enable Non-overlap longer delay. 2030 * Set segment driver as half driving strength. 2031 */ 2032 regmap_update_bits(regmap, NAU8360_R68_ANALOG_CONTROL_1, NAU8360_DTX_EN | 2033 NAU8360_TRIMSCR_MASK | NAU8360_DRVCTL_SEGL_FULL | 2034 NAU8360_DRVCTL_SEGR_FULL, NAU8360_TRIMSCR_MLOW | NAU8360_DTX_EN); 2035 /* Enable SCP Clear Mode and Class D Modulator to Common Mode */ 2036 regmap_update_bits(regmap, NAU8360_R67_ANALOG_CONTROL_0, 2037 NAU8360_SCP_CLEAR_MODE_MASK | NAU8360_CM_COMP_EN, 2038 NAU8360_SCP_CLEAR_MODE_AUTO | NAU8360_CM_COMP_EN); 2039 /* Set Analog Mute and Class D Modulator Gain as 14dB */ 2040 regmap_update_bits(regmap, NAU8360_R67_ANALOG_CONTROL_0, NAU8360_ANA_MUTE | 2041 NAU8360_MOD_GAIN_MASK, NAU8360_ANA_MUTE | NAU8360_MOD_GAIN_14DB); 2042 /* Set Stereo or PBTL Mode */ 2043 regmap_update_bits(regmap, NAU8360_R67_ANALOG_CONTROL_0, 2044 NAU8360_V_PBTL_EN, nau8360->pbtl_enable ? NAU8360_V_PBTL_EN : 0); 2045 regmap_update_bits(regmap, NAU8360_R6C_IVSNS_CFG0, 2046 NAU8360_PBTL_ISENE_LR_MASK, NAU8360_PBTL_ISENE_LR_ILR); 2047 /* adjust HW3 default volume of voltage/current sense */ 2048 regmap_write(regmap, NAU8360_R8A_HW3_VL_CTL7, 0xbe90); 2049 regmap_write(regmap, NAU8360_R8B_HW3_VR_CTL8, 0xbe90); 2050 regmap_write(regmap, NAU8360_R8D_HW3_IL_CTL7, nau8360->pbtl_enable ? 0xc3aa : 0xc24c); 2051 regmap_write(regmap, NAU8360_R8E_HW3_IR_CTL8, nau8360->pbtl_enable ? 0xc3aa : 0xc24c); 2052 /* Set HW3 Zero THD as 0xff */ 2053 regmap_update_bits(regmap, NAU8360_R8F_HW3_CTL9, 2054 NAU8360_HW3_ZERO_THD_MASK, 0xff); 2055 /* Enable TX SDOUT and Data at BCLK Rising. */ 2056 regmap_update_bits(regmap, NAU8360_R0D_I2S_PCM_CTRL3, NAU8360_TX_FILL_MASK, 2057 NAU8360_TX_FILL_ZERO); 2058 regmap_update_bits(regmap, NAU8360_R0D_I2S_PCM_CTRL3, 2059 NAU8360_VSNS_L_SLEN_MASK, NAU8360_VSNS_L_SLEN_16); 2060 regmap_update_bits(regmap, NAU8360_R0E_I2S_DATA_CTRL1, 2061 NAU8360_ISNS_L_SLEN_MASK, NAU8360_ISNS_L_SLEN_16); 2062 regmap_update_bits(regmap, NAU8360_R11_I2S_DATA_CTRL4, 2063 NAU8360_VSNS_R_SLEN_MASK | NAU8360_ISNS_R_SLEN_MASK, 2064 NAU8360_VSNS_R_SLEN_16 | NAU8360_ISNS_R_SLEN_16); 2065 /* set DAC channel temperature trim code slope as 0x7D */ 2066 regmap_update_bits(regmap, NAU8360_R7A_DAC_TRIM_CFG2, 2067 NAU8360_DAC_TEMP_SLOPE_MASK, 0x7D << NAU8360_DAC_TEMP_SLOPE_SFT); 2068 /* set ISNS temperature trim code slope as 0x1a */ 2069 regmap_update_bits(regmap, NAU8360_R7B_IVSNS_TRIM_CFG, 2070 NAU8360_ISNS_TEMP_SLOPE_MASK, 0x1a << NAU8360_ISNS_TEMP_SLOPE_SFT); 2071 /* set misc trim config as 0x67F0 */ 2072 regmap_update_bits(regmap, NAU8360_R7C_MISC_TRIM_CFG, NAU8360_DAC_GAIN_SB_MASK | 2073 NAU8360_DAC_TEMP_SB_MASK | NAU8360_ISNS_TEMP_SB_MASK | 2074 NAU8360_VSNS_TEMP_SB_MASK | NAU8360_ISNS_GAIN_SB_MASK | 2075 NAU8360_VSNS_GAIN_SB_MASK, (0x3 << NAU8360_DAC_TEMP_SB_SFT) | 2076 (0x7 << NAU8360_ISNS_TEMP_SB_SFT) | (0x3 << NAU8360_VSNS_TEMP_SB_SFT)); 2077 /* Enable Efuse Initianllization */ 2078 regmap_update_bits(regmap, NAU8360_R60_RST, NAU8360_EFUSE_CTRL_EN, 2079 NAU8360_EFUSE_CTRL_EN); 2080 /* Clear HW2 DRAM */ 2081 regmap_update_bits(regmap, NAU8360_R90_HW2_CTL0, 2082 NAU8360_HW2_DRAM_CLR, NAU8360_HW2_DRAM_CLR); 2083 /* Finish HW DRAM Clear */ 2084 regmap_update_bits(regmap, NAU8360_R90_HW2_CTL0, NAU8360_HW2_DRAM_CLR, 0); 2085 /* Clear HW3 DRAM */ 2086 regmap_update_bits(regmap, NAU8360_R86_HW3_CTL0, 2087 NAU8360_HW3_DRAM_CLR, NAU8360_HW3_DRAM_CLR); 2088 /* Finish HW DRAM Clear */ 2089 regmap_update_bits(regmap, NAU8360_R86_HW3_CTL0, NAU8360_HW3_DRAM_CLR, 0); 2090 } 2091 2092 static void nau8360_print_device_properties(struct nau8360 *nau8360) 2093 { 2094 int i; 2095 2096 dev_dbg(nau8360->dev, "pbtl-enable: %d", nau8360->pbtl_enable); 2097 dev_dbg(nau8360->dev, "dac-cur-enable: %d", nau8360->dac_cur_enable); 2098 for (i = 0; i < NAU8360_DSP_FW_NUM; i++) 2099 dev_dbg(nau8360->dev, "firmware-name[%d]: %s", i, 2100 nau8360->dsp_firmware[i]); 2101 2102 for (i = 0; i < NAU8360_TDM_TXN; i++) 2103 dev_dbg(nau8360->dev, "dsp-tx-slot[%d] (%s): %d%s", i, 2104 nau8360_tx_func_names[i], nau8360->tdm_tx_func_slot[i], 2105 nau8360->tdm_tx_func_slot[i] == TDM_SLOT_NONE ? " (none)" : ""); 2106 2107 for (i = 0; i < NAU8360_TDM_RXN; i++) 2108 dev_dbg(nau8360->dev, "dsp-rx-slot[%d] (%s): %d%s", i, 2109 nau8360_rx_func_names[i], nau8360->tdm_rx_func_slot[i], 2110 nau8360->tdm_rx_func_slot[i] == TDM_SLOT_NONE ? " (none)" : ""); 2111 } 2112 2113 static int nau8360_read_device_properties(struct nau8360 *nau8360) 2114 { 2115 const char *def_fws[NAU8360_DSP_FW_NUM] = { 2116 NAU8360_DSP_FIRMWARE".l", NAU8360_DSP_FIRMWARE".r" 2117 }; 2118 struct device *dev = nau8360->dev; 2119 const char *firmware_names[NAU8360_DSP_FW_NUM]; 2120 int i, ret; 2121 2122 ret = device_property_read_u32_array(dev, "nuvoton,dsp-tx-slot-mapping", 2123 nau8360->tdm_tx_func_slot, NAU8360_TDM_TXN); 2124 if (ret) { 2125 for (i = 0; i < NAU8360_TDM_TXN; i++) 2126 nau8360->tdm_tx_func_slot[i] = TDM_SLOT_NONE; 2127 } else { 2128 for (i = 0; i < NAU8360_TDM_TXN; i++) { 2129 if (nau8360->tdm_tx_func_slot[i] == TDM_SLOT_NONE) 2130 continue; 2131 if (nau8360->tdm_tx_func_slot[i] >= NAU8360_TDM_MAX_CHAN) { 2132 dev_warn(dev, "Invalid TX slot %d, set to none\n", 2133 nau8360->tdm_tx_func_slot[i]); 2134 nau8360->tdm_tx_func_slot[i] = TDM_SLOT_NONE; 2135 } 2136 } 2137 } 2138 2139 ret = device_property_read_u32_array(dev, "nuvoton,dsp-rx-slot-mapping", 2140 nau8360->tdm_rx_func_slot, NAU8360_TDM_RXN); 2141 if (ret) { 2142 nau8360->tdm_rx_func_slot[NAU8360_TDM_DACL] = 0; 2143 nau8360->tdm_rx_func_slot[NAU8360_TDM_DACR] = 1; 2144 nau8360->tdm_rx_func_slot[NAU8360_TDM_ANCL] = TDM_SLOT_NONE; 2145 nau8360->tdm_rx_func_slot[NAU8360_TDM_ANCR] = TDM_SLOT_NONE; 2146 } else { 2147 for (i = 0; i < NAU8360_TDM_RXN; i++) { 2148 if (nau8360->tdm_rx_func_slot[i] == TDM_SLOT_NONE) 2149 continue; 2150 if (nau8360->tdm_rx_func_slot[i] >= NAU8360_TDM_MAX_CHAN) { 2151 dev_warn(dev, "Invalid RX slot %d, set to none\n", 2152 nau8360->tdm_rx_func_slot[i]); 2153 nau8360->tdm_rx_func_slot[i] = TDM_SLOT_NONE; 2154 } 2155 } 2156 } 2157 2158 nau8360->pbtl_enable = device_property_read_bool(dev, "nuvoton,pbtl-enable"); 2159 nau8360->dac_cur_enable = device_property_read_bool(dev, "nuvoton,dac-cur-enable"); 2160 2161 ret = device_property_read_string_array(dev, "firmware-name", 2162 firmware_names, NAU8360_DSP_FW_NUM); 2163 if (ret != NAU8360_DSP_FW_NUM) { 2164 dev_warn(dev, "The firmware-name was not found, using default."); 2165 for (i = 0; i < NAU8360_DSP_FW_NUM; i++) { 2166 nau8360->dsp_firmware[i] = devm_kstrdup(dev, def_fws[i], GFP_KERNEL); 2167 2168 if (!nau8360->dsp_firmware[i]) 2169 return -ENOMEM; 2170 } 2171 } else { 2172 for (i = 0; i < NAU8360_DSP_FW_NUM; i++) { 2173 nau8360->dsp_firmware[i] = devm_kasprintf(dev, GFP_KERNEL, 2174 NAU8360_DSP_FIRMDIR "%s", firmware_names[i]); 2175 2176 if (!nau8360->dsp_firmware[i]) 2177 return -ENOMEM; 2178 } 2179 } 2180 2181 return 0; 2182 } 2183 2184 static struct reg_default *nau8360_alloc_defaults(struct device *dev, int *total_regs) 2185 { 2186 struct reg_default *dyn_defaults; 2187 int reg_num = ARRAY_SIZE(nau8360_reg_defaults); 2188 int total = reg_num + (2 * NAU8360_TOT_BAND_PER_CH * NAU8360_TOT_BAND_COE); 2189 int i, j, idx; 2190 2191 dyn_defaults = devm_kzalloc(dev, total * sizeof(*dyn_defaults), GFP_KERNEL); 2192 if (!dyn_defaults) 2193 return NULL; 2194 2195 memcpy(dyn_defaults, nau8360_reg_defaults, sizeof(*dyn_defaults) * reg_num); 2196 idx = reg_num; 2197 2198 for (i = 0; i < NAU8360_TOT_BAND_PER_CH; i++) { 2199 unsigned int range = i * NAU8360_TOT_BAND_COE_RANGE; 2200 unsigned int l_base = NAU8360_R100_LEFT_BIQ0_COE + range; 2201 unsigned int r_base = NAU8360_R200_RIGHT_BIQ0_COE + range; 2202 2203 for (j = 0; j < NAU8360_TOT_BAND_COE; j++) { 2204 dyn_defaults[idx++].reg = l_base + j; 2205 dyn_defaults[idx++].reg = r_base + j; 2206 } 2207 } 2208 2209 *total_regs = total; 2210 2211 return dyn_defaults; 2212 } 2213 2214 static int nau8360_i2c_probe(struct i2c_client *i2c) 2215 { 2216 struct device *dev = &i2c->dev; 2217 struct nau8360 *nau8360; 2218 struct regmap_config regmap_cfg = nau8360_regmap_config; 2219 struct reg_default *dyn_defaults; 2220 int num_total_regs; 2221 int ret, value; 2222 2223 nau8360 = devm_kzalloc(dev, sizeof(*nau8360), GFP_KERNEL); 2224 if (!nau8360) 2225 return -ENOMEM; 2226 2227 i2c_set_clientdata(i2c, nau8360); 2228 mutex_init(&nau8360->lock); 2229 INIT_WORK(&nau8360->load_fw_work, nau8360_load_fw_work); 2230 2231 dyn_defaults = nau8360_alloc_defaults(dev, &num_total_regs); 2232 if (!dyn_defaults) 2233 return -ENOMEM; 2234 2235 regmap_cfg.reg_defaults = dyn_defaults; 2236 regmap_cfg.num_reg_defaults = num_total_regs; 2237 2238 nau8360->regmap = devm_regmap_init(dev, NULL, i2c, ®map_cfg); 2239 if (IS_ERR(nau8360->regmap)) 2240 return PTR_ERR(nau8360->regmap); 2241 nau8360->dev = dev; 2242 2243 nau8360_reset_chip(nau8360->regmap); 2244 ret = regmap_read(nau8360->regmap, NAU8360_R46_I2C_DEVICE_ID, &value); 2245 if (ret) { 2246 dev_err(dev, "Failed to read NAU83G60 device id %d", ret); 2247 return ret; 2248 } 2249 2250 ret = nau8360_read_device_properties(nau8360); 2251 if (ret) 2252 return ret; 2253 2254 nau8360_print_device_properties(nau8360); 2255 nau8360_init_regs(nau8360); 2256 2257 return devm_snd_soc_register_component(dev, &soc_comp_dev_nau8360, &nau8360_dai, 1); 2258 } 2259 2260 static void nau8360_i2c_remove(struct i2c_client *client) 2261 { 2262 struct nau8360 *nau8360 = i2c_get_clientdata(client); 2263 2264 cancel_work_sync(&nau8360->load_fw_work); 2265 } 2266 2267 static const struct i2c_device_id nau8360_i2c_ids[] = { 2268 { .name = "nau8360" }, 2269 {} 2270 }; 2271 MODULE_DEVICE_TABLE(i2c, nau8360_i2c_ids); 2272 2273 static const struct of_device_id nau8360_of_ids[] = { 2274 { .compatible = "nuvoton,nau8360" }, 2275 {} 2276 }; 2277 MODULE_DEVICE_TABLE(of, nau8360_of_ids); 2278 2279 static const struct acpi_device_id nau8360_acpi_match[] = { 2280 { .id = "NVTN2002" }, 2281 {} 2282 }; 2283 MODULE_DEVICE_TABLE(acpi, nau8360_acpi_match); 2284 2285 static struct i2c_driver nau8360_i2c_driver = { 2286 .driver = { 2287 .name = "nau8360", 2288 .of_match_table = of_match_ptr(nau8360_of_ids), 2289 .acpi_match_table = ACPI_PTR(nau8360_acpi_match), 2290 }, 2291 .probe = nau8360_i2c_probe, 2292 .remove = nau8360_i2c_remove, 2293 .id_table = nau8360_i2c_ids, 2294 }; 2295 module_i2c_driver(nau8360_i2c_driver); 2296 2297 MODULE_DESCRIPTION("ASoC NAU83G60 Stereo Class-D Amplifier with DSP and I/V-sense driver"); 2298 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>"); 2299 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>"); 2300 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>"); 2301 MODULE_AUTHOR("Neo Chang <ylchang2@nuvoton.com>"); 2302 MODULE_LICENSE("GPL"); 2303