1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mt6358.c -- mt6358 ALSA SoC audio codec driver 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/sched.h> 13 #include <linux/mfd/mt6397/core.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <sound/soc.h> 17 #include <sound/tlv.h> 18 19 #include "mt6358.h" 20 21 enum { 22 AUDIO_ANALOG_VOLUME_HSOUTL, 23 AUDIO_ANALOG_VOLUME_HSOUTR, 24 AUDIO_ANALOG_VOLUME_HPOUTL, 25 AUDIO_ANALOG_VOLUME_HPOUTR, 26 AUDIO_ANALOG_VOLUME_LINEOUTL, 27 AUDIO_ANALOG_VOLUME_LINEOUTR, 28 AUDIO_ANALOG_VOLUME_MICAMP1, 29 AUDIO_ANALOG_VOLUME_MICAMP2, 30 AUDIO_ANALOG_VOLUME_TYPE_MAX 31 }; 32 33 enum { 34 MUX_ADC_L, 35 MUX_ADC_R, 36 MUX_PGA_L, 37 MUX_PGA_R, 38 MUX_MIC_TYPE, 39 MUX_HP_L, 40 MUX_HP_R, 41 MUX_NUM, 42 }; 43 44 enum { 45 DEVICE_HP, 46 DEVICE_LO, 47 DEVICE_RCV, 48 DEVICE_MIC1, 49 DEVICE_MIC2, 50 DEVICE_NUM 51 }; 52 53 /* Supply widget subseq */ 54 enum { 55 /* common */ 56 SUPPLY_SEQ_CLK_BUF, 57 SUPPLY_SEQ_AUD_GLB, 58 SUPPLY_SEQ_CLKSQ, 59 SUPPLY_SEQ_VOW_AUD_LPW, 60 SUPPLY_SEQ_AUD_VOW, 61 SUPPLY_SEQ_VOW_CLK, 62 SUPPLY_SEQ_VOW_LDO, 63 SUPPLY_SEQ_TOP_CK, 64 SUPPLY_SEQ_TOP_CK_LAST, 65 SUPPLY_SEQ_AUD_TOP, 66 SUPPLY_SEQ_AUD_TOP_LAST, 67 SUPPLY_SEQ_AFE, 68 /* capture */ 69 SUPPLY_SEQ_ADC_SUPPLY, 70 }; 71 72 enum { 73 CH_L = 0, 74 CH_R, 75 NUM_CH, 76 }; 77 78 #define REG_STRIDE 2 79 80 struct mt6358_priv { 81 struct device *dev; 82 struct regmap *regmap; 83 84 unsigned int dl_rate; 85 unsigned int ul_rate; 86 87 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; 88 unsigned int mux_select[MUX_NUM]; 89 90 int dev_counter[DEVICE_NUM]; 91 92 int mtkaif_protocol; 93 94 struct regulator *avdd_reg; 95 96 int wov_enabled; 97 98 int dmic_one_wire_mode; 99 }; 100 101 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt, 102 int mtkaif_protocol) 103 { 104 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 105 106 priv->mtkaif_protocol = mtkaif_protocol; 107 return 0; 108 } 109 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol); 110 111 static void playback_gpio_set(struct mt6358_priv *priv) 112 { 113 /* set gpio mosi mode */ 114 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 115 0x01f8, 0x01f8); 116 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, 117 0xffff, 0x0249); 118 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 119 0xffff, 0x0249); 120 } 121 122 static void playback_gpio_reset(struct mt6358_priv *priv) 123 { 124 /* set pad_aud_*_mosi to GPIO mode and dir input 125 * reason: 126 * pad_aud_dat_mosi*, because the pin is used as boot strap 127 * don't clean clk/sync, for mtkaif protocol 2 128 */ 129 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 130 0x01f8, 0x01f8); 131 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 132 0x01f8, 0x0000); 133 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 134 0xf << 8, 0x0); 135 } 136 137 static void capture_gpio_set(struct mt6358_priv *priv) 138 { 139 /* set gpio miso mode */ 140 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 141 0xffff, 0xffff); 142 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET, 143 0xffff, 0x0249); 144 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 145 0xffff, 0x0249); 146 } 147 148 static void capture_gpio_reset(struct mt6358_priv *priv) 149 { 150 /* set pad_aud_*_miso to GPIO mode and dir input 151 * reason: 152 * pad_aud_clk_miso, because when playback only the miso_clk 153 * will also have 26m, so will have power leak 154 * pad_aud_dat_miso*, because the pin is used as boot strap 155 */ 156 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 157 0xffff, 0xffff); 158 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 159 0xffff, 0x0000); 160 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 161 0xf << 12, 0x0); 162 } 163 164 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv) 165 { 166 switch (priv->mtkaif_protocol) { 167 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2: 168 /* MTKAIF TX format setting */ 169 regmap_update_bits(priv->regmap, 170 MT6358_AFE_ADDA_MTKAIF_CFG0, 171 0xffff, 0x0010); 172 /* enable aud_pad TX fifos */ 173 regmap_update_bits(priv->regmap, 174 MT6358_AFE_AUD_PAD_TOP, 175 0xff00, 0x3800); 176 regmap_update_bits(priv->regmap, 177 MT6358_AFE_AUD_PAD_TOP, 178 0xff00, 0x3900); 179 break; 180 case MT6358_MTKAIF_PROTOCOL_2: 181 /* MTKAIF TX format setting */ 182 regmap_update_bits(priv->regmap, 183 MT6358_AFE_ADDA_MTKAIF_CFG0, 184 0xffff, 0x0010); 185 /* enable aud_pad TX fifos */ 186 regmap_update_bits(priv->regmap, 187 MT6358_AFE_AUD_PAD_TOP, 188 0xff00, 0x3100); 189 break; 190 case MT6358_MTKAIF_PROTOCOL_1: 191 default: 192 /* MTKAIF TX format setting */ 193 regmap_update_bits(priv->regmap, 194 MT6358_AFE_ADDA_MTKAIF_CFG0, 195 0xffff, 0x0000); 196 /* enable aud_pad TX fifos */ 197 regmap_update_bits(priv->regmap, 198 MT6358_AFE_AUD_PAD_TOP, 199 0xff00, 0x3100); 200 break; 201 } 202 return 0; 203 } 204 205 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv) 206 { 207 /* disable aud_pad TX fifos */ 208 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP, 209 0xff00, 0x3000); 210 return 0; 211 } 212 213 /* dl pga gain */ 214 enum { 215 DL_GAIN_8DB = 0, 216 DL_GAIN_0DB = 8, 217 DL_GAIN_N_1DB = 9, 218 DL_GAIN_N_10DB = 18, 219 DL_GAIN_N_40DB = 0x1f, 220 }; 221 222 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB) 223 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB) 224 #define DL_GAIN_REG_MASK 0x0f9f 225 226 static void hp_zcd_disable(struct mt6358_priv *priv) 227 { 228 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); 229 } 230 231 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up) 232 { 233 int i, stage; 234 int target = 7; 235 236 /* Enable/Reduce HPL/R main output stage step by step */ 237 for (i = 0; i <= target; i++) { 238 stage = up ? i : target - i; 239 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 240 0x7 << 8, stage << 8); 241 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 242 0x7 << 11, stage << 11); 243 usleep_range(100, 150); 244 } 245 } 246 247 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up) 248 { 249 int i, stage; 250 251 /* Reduce HP aux feedback loop gain step by step */ 252 for (i = 0; i <= 0xf; i++) { 253 stage = up ? i : 0xf - i; 254 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 255 0xf << 12, stage << 12); 256 usleep_range(100, 150); 257 } 258 } 259 260 static void hp_pull_down(struct mt6358_priv *priv, bool enable) 261 { 262 int i; 263 264 if (enable) { 265 for (i = 0x0; i <= 0x6; i++) { 266 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 267 0x7, i); 268 usleep_range(600, 700); 269 } 270 } else { 271 for (i = 0x6; i >= 0x1; i--) { 272 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 273 0x7, i); 274 usleep_range(600, 700); 275 } 276 } 277 } 278 279 static bool is_valid_hp_pga_idx(int reg_idx) 280 { 281 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) || 282 reg_idx == DL_GAIN_N_40DB; 283 } 284 285 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to) 286 { 287 int offset = 0, count = 0, reg_idx; 288 289 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) 290 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", 291 __func__, from, to); 292 293 dev_info(priv->dev, "%s(), from %d, to %d\n", 294 __func__, from, to); 295 296 if (to > from) 297 offset = to - from; 298 else 299 offset = from - to; 300 301 while (offset >= 0) { 302 if (to > from) 303 reg_idx = from + count; 304 else 305 reg_idx = from - count; 306 307 if (is_valid_hp_pga_idx(reg_idx)) { 308 regmap_update_bits(priv->regmap, 309 MT6358_ZCD_CON2, 310 DL_GAIN_REG_MASK, 311 (reg_idx << 7) | reg_idx); 312 usleep_range(200, 300); 313 } 314 offset--; 315 count++; 316 } 317 } 318 319 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol, 320 struct snd_ctl_elem_value *ucontrol) 321 { 322 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 323 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component); 324 struct soc_mixer_control *mc = 325 (struct soc_mixer_control *)kcontrol->private_value; 326 unsigned int reg = 0; 327 int ret; 328 329 ret = snd_soc_put_volsw(kcontrol, ucontrol); 330 if (ret < 0) 331 return ret; 332 333 switch (mc->reg) { 334 case MT6358_ZCD_CON2: 335 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); 336 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 337 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; 338 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 339 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; 340 break; 341 case MT6358_ZCD_CON1: 342 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); 343 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 344 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; 345 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 346 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; 347 break; 348 case MT6358_ZCD_CON3: 349 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®); 350 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = 351 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 352 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] = 353 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 354 break; 355 case MT6358_AUDENC_ANA_CON0: 356 case MT6358_AUDENC_ANA_CON1: 357 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®); 358 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 359 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK; 360 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®); 361 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 362 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK; 363 break; 364 } 365 366 return ret; 367 } 368 369 static void mt6358_restore_pga(struct mt6358_priv *priv); 370 371 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv) 372 { 373 /* analog */ 374 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 375 0xffff, 0x0000); 376 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 377 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 378 0xffff, 0x0800); 379 mt6358_restore_pga(priv); 380 381 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); 382 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 383 0xffff, 0x0025); 384 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 385 0xffff, 0x0005); 386 387 /* digital */ 388 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 389 0xffff, 0x0000); 390 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); 391 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); 392 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); 393 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); 394 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); 395 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); 396 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); 397 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 398 0xffff, 0x0000); 399 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 400 0xffff, 0x0451); 401 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); 402 403 return 0; 404 } 405 406 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv) 407 { 408 /* digital */ 409 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); 410 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 411 0xffff, 0x0450); 412 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 413 0xffff, 0x0c00); 414 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); 415 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); 416 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); 417 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); 418 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); 419 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); 420 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); 421 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 422 0xffff, 0x0000); 423 424 /* analog */ 425 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 426 0xffff, 0x0004); 427 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 428 0xffff, 0x0000); 429 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); 430 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 431 0xffff, 0x0000); 432 mt6358_restore_pga(priv); 433 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 434 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 435 0xffff, 0x0010); 436 437 return 0; 438 } 439 440 static int mt6358_get_wov(struct snd_kcontrol *kcontrol, 441 struct snd_ctl_elem_value *ucontrol) 442 { 443 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 444 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 445 446 ucontrol->value.integer.value[0] = priv->wov_enabled; 447 return 0; 448 } 449 450 static int mt6358_put_wov(struct snd_kcontrol *kcontrol, 451 struct snd_ctl_elem_value *ucontrol) 452 { 453 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 454 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 455 int enabled = ucontrol->value.integer.value[0]; 456 457 if (enabled < 0 || enabled > 1) 458 return -EINVAL; 459 460 if (priv->wov_enabled != enabled) { 461 if (enabled) 462 mt6358_enable_wov_phase2(priv); 463 else 464 mt6358_disable_wov_phase2(priv); 465 466 priv->wov_enabled = enabled; 467 468 return 1; 469 } 470 471 return 0; 472 } 473 474 static int mt6358_dmic_mode_get(struct snd_kcontrol *kcontrol, 475 struct snd_ctl_elem_value *ucontrol) 476 { 477 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 478 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 479 480 ucontrol->value.integer.value[0] = priv->dmic_one_wire_mode; 481 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); 482 483 return 0; 484 } 485 486 static int mt6358_dmic_mode_set(struct snd_kcontrol *kcontrol, 487 struct snd_ctl_elem_value *ucontrol) 488 { 489 struct snd_soc_component *c = snd_kcontrol_chip(kcontrol); 490 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 491 int enabled = ucontrol->value.integer.value[0]; 492 493 if (enabled < 0 || enabled > 1) 494 return -EINVAL; 495 496 if (priv->dmic_one_wire_mode != enabled) { 497 priv->dmic_one_wire_mode = enabled; 498 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); 499 500 return 1; 501 } 502 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); 503 504 return 0; 505 } 506 507 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 508 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); 509 510 static const struct snd_kcontrol_new mt6358_snd_controls[] = { 511 /* dl pga gain */ 512 SOC_DOUBLE_EXT_TLV("Headphone Volume", 513 MT6358_ZCD_CON2, 0, 7, 0x12, 1, 514 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 515 SOC_DOUBLE_EXT_TLV("Lineout Volume", 516 MT6358_ZCD_CON1, 0, 7, 0x12, 1, 517 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 518 SOC_SINGLE_EXT_TLV("Handset Volume", 519 MT6358_ZCD_CON3, 0, 0x12, 1, 520 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 521 /* ul pga gain */ 522 SOC_DOUBLE_R_EXT_TLV("PGA Volume", 523 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1, 524 8, 4, 0, 525 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv), 526 527 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0, 528 mt6358_get_wov, mt6358_put_wov), 529 530 SOC_SINGLE_BOOL_EXT("Dmic Mode Switch", 0, 531 mt6358_dmic_mode_get, mt6358_dmic_mode_set), 532 }; 533 534 /* MUX */ 535 /* LOL MUX */ 536 static const char * const lo_in_mux_map[] = { 537 "Open", "Mute", "Playback", "Test Mode" 538 }; 539 540 static int lo_in_mux_map_value[] = { 541 0x0, 0x1, 0x2, 0x3, 542 }; 543 544 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, 545 MT6358_AUDDEC_ANA_CON7, 546 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT, 547 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK, 548 lo_in_mux_map, 549 lo_in_mux_map_value); 550 551 static const struct snd_kcontrol_new lo_in_mux_control = 552 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum); 553 554 /*HP MUX */ 555 enum { 556 HP_MUX_OPEN = 0, 557 HP_MUX_HPSPK, 558 HP_MUX_HP, 559 HP_MUX_TEST_MODE, 560 HP_MUX_HP_IMPEDANCE, 561 HP_MUX_MASK = 0x7, 562 }; 563 564 static const char * const hp_in_mux_map[] = { 565 "Open", 566 "LoudSPK Playback", 567 "Audio Playback", 568 "Test Mode", 569 "HP Impedance", 570 }; 571 572 static int hp_in_mux_map_value[] = { 573 HP_MUX_OPEN, 574 HP_MUX_HPSPK, 575 HP_MUX_HP, 576 HP_MUX_TEST_MODE, 577 HP_MUX_HP_IMPEDANCE, 578 }; 579 580 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, 581 SND_SOC_NOPM, 582 0, 583 HP_MUX_MASK, 584 hp_in_mux_map, 585 hp_in_mux_map_value); 586 587 static const struct snd_kcontrol_new hpl_in_mux_control = 588 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum); 589 590 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, 591 SND_SOC_NOPM, 592 0, 593 HP_MUX_MASK, 594 hp_in_mux_map, 595 hp_in_mux_map_value); 596 597 static const struct snd_kcontrol_new hpr_in_mux_control = 598 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum); 599 600 /* RCV MUX */ 601 enum { 602 RCV_MUX_OPEN = 0, 603 RCV_MUX_MUTE, 604 RCV_MUX_VOICE_PLAYBACK, 605 RCV_MUX_TEST_MODE, 606 RCV_MUX_MASK = 0x3, 607 }; 608 609 static const char * const rcv_in_mux_map[] = { 610 "Open", "Mute", "Voice Playback", "Test Mode" 611 }; 612 613 static int rcv_in_mux_map_value[] = { 614 RCV_MUX_OPEN, 615 RCV_MUX_MUTE, 616 RCV_MUX_VOICE_PLAYBACK, 617 RCV_MUX_TEST_MODE, 618 }; 619 620 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 621 SND_SOC_NOPM, 622 0, 623 RCV_MUX_MASK, 624 rcv_in_mux_map, 625 rcv_in_mux_map_value); 626 627 static const struct snd_kcontrol_new rcv_in_mux_control = 628 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 629 630 /* DAC In MUX */ 631 static const char * const dac_in_mux_map[] = { 632 "Normal Path", "Sgen" 633 }; 634 635 static int dac_in_mux_map_value[] = { 636 0x0, 0x1, 637 }; 638 639 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 640 MT6358_AFE_TOP_CON0, 641 DL_SINE_ON_SFT, 642 DL_SINE_ON_MASK, 643 dac_in_mux_map, 644 dac_in_mux_map_value); 645 646 static const struct snd_kcontrol_new dac_in_mux_control = 647 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 648 649 /* AIF Out MUX */ 650 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 651 MT6358_AFE_TOP_CON0, 652 UL_SINE_ON_SFT, 653 UL_SINE_ON_MASK, 654 dac_in_mux_map, 655 dac_in_mux_map_value); 656 657 static const struct snd_kcontrol_new aif_out_mux_control = 658 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 659 660 /* Mic Type MUX */ 661 enum { 662 MIC_TYPE_MUX_IDLE = 0, 663 MIC_TYPE_MUX_ACC, 664 MIC_TYPE_MUX_DMIC, 665 MIC_TYPE_MUX_DCC, 666 MIC_TYPE_MUX_DCC_ECM_DIFF, 667 MIC_TYPE_MUX_DCC_ECM_SINGLE, 668 MIC_TYPE_MUX_MASK = 0x7, 669 }; 670 671 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \ 672 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \ 673 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE) 674 675 static const char * const mic_type_mux_map[] = { 676 "Idle", 677 "ACC", 678 "DMIC", 679 "DCC", 680 "DCC_ECM_DIFF", 681 "DCC_ECM_SINGLE", 682 }; 683 684 static int mic_type_mux_map_value[] = { 685 MIC_TYPE_MUX_IDLE, 686 MIC_TYPE_MUX_ACC, 687 MIC_TYPE_MUX_DMIC, 688 MIC_TYPE_MUX_DCC, 689 MIC_TYPE_MUX_DCC_ECM_DIFF, 690 MIC_TYPE_MUX_DCC_ECM_SINGLE, 691 }; 692 693 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum, 694 SND_SOC_NOPM, 695 0, 696 MIC_TYPE_MUX_MASK, 697 mic_type_mux_map, 698 mic_type_mux_map_value); 699 700 static const struct snd_kcontrol_new mic_type_mux_control = 701 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum); 702 703 /* ADC L MUX */ 704 enum { 705 ADC_MUX_IDLE = 0, 706 ADC_MUX_AIN0, 707 ADC_MUX_PREAMPLIFIER, 708 ADC_MUX_IDLE1, 709 ADC_MUX_MASK = 0x3, 710 }; 711 712 static const char * const adc_left_mux_map[] = { 713 "Idle", "AIN0", "Left Preamplifier", "Idle_1" 714 }; 715 716 static int adc_mux_map_value[] = { 717 ADC_MUX_IDLE, 718 ADC_MUX_AIN0, 719 ADC_MUX_PREAMPLIFIER, 720 ADC_MUX_IDLE1, 721 }; 722 723 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 724 SND_SOC_NOPM, 725 0, 726 ADC_MUX_MASK, 727 adc_left_mux_map, 728 adc_mux_map_value); 729 730 static const struct snd_kcontrol_new adc_left_mux_control = 731 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 732 733 /* ADC R MUX */ 734 static const char * const adc_right_mux_map[] = { 735 "Idle", "AIN0", "Right Preamplifier", "Idle_1" 736 }; 737 738 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 739 SND_SOC_NOPM, 740 0, 741 ADC_MUX_MASK, 742 adc_right_mux_map, 743 adc_mux_map_value); 744 745 static const struct snd_kcontrol_new adc_right_mux_control = 746 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 747 748 /* PGA L MUX */ 749 enum { 750 PGA_MUX_NONE = 0, 751 PGA_MUX_AIN0, 752 PGA_MUX_AIN1, 753 PGA_MUX_AIN2, 754 PGA_MUX_MASK = 0x3, 755 }; 756 757 static const char * const pga_mux_map[] = { 758 "None", "AIN0", "AIN1", "AIN2" 759 }; 760 761 static int pga_mux_map_value[] = { 762 PGA_MUX_NONE, 763 PGA_MUX_AIN0, 764 PGA_MUX_AIN1, 765 PGA_MUX_AIN2, 766 }; 767 768 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 769 SND_SOC_NOPM, 770 0, 771 PGA_MUX_MASK, 772 pga_mux_map, 773 pga_mux_map_value); 774 775 static const struct snd_kcontrol_new pga_left_mux_control = 776 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 777 778 /* PGA R MUX */ 779 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 780 SND_SOC_NOPM, 781 0, 782 PGA_MUX_MASK, 783 pga_mux_map, 784 pga_mux_map_value); 785 786 static const struct snd_kcontrol_new pga_right_mux_control = 787 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 788 789 static int mt_clksq_event(struct snd_soc_dapm_widget *w, 790 struct snd_kcontrol *kcontrol, 791 int event) 792 { 793 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 794 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 795 796 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 797 798 switch (event) { 799 case SND_SOC_DAPM_PRE_PMU: 800 /* audio clk source from internal dcxo */ 801 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 802 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 803 0x0); 804 break; 805 default: 806 break; 807 } 808 809 return 0; 810 } 811 812 static int mt_sgen_event(struct snd_soc_dapm_widget *w, 813 struct snd_kcontrol *kcontrol, 814 int event) 815 { 816 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 817 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 818 819 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 820 821 switch (event) { 822 case SND_SOC_DAPM_PRE_PMU: 823 /* sdm audio fifo clock power on */ 824 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 825 /* scrambler clock on enable */ 826 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 827 /* sdm power on */ 828 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 829 /* sdm fifo enable */ 830 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 831 832 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0, 833 0xff3f, 834 0x0000); 835 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1, 836 0xffff, 837 0x0001); 838 break; 839 case SND_SOC_DAPM_POST_PMD: 840 /* DL scrambler disabling sequence */ 841 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 842 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 843 break; 844 default: 845 break; 846 } 847 848 return 0; 849 } 850 851 static int mt_aif_in_event(struct snd_soc_dapm_widget *w, 852 struct snd_kcontrol *kcontrol, 853 int event) 854 { 855 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 856 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 857 858 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", 859 __func__, event, priv->dl_rate); 860 861 switch (event) { 862 case SND_SOC_DAPM_PRE_PMU: 863 playback_gpio_set(priv); 864 865 /* sdm audio fifo clock power on */ 866 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 867 /* scrambler clock on enable */ 868 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 869 /* sdm power on */ 870 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 871 /* sdm fifo enable */ 872 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 873 break; 874 case SND_SOC_DAPM_POST_PMD: 875 /* DL scrambler disabling sequence */ 876 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 877 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 878 879 playback_gpio_reset(priv); 880 break; 881 default: 882 break; 883 } 884 885 return 0; 886 } 887 888 static int mtk_hp_enable(struct mt6358_priv *priv) 889 { 890 /* Pull-down HPL/R to AVSS28_AUD */ 891 hp_pull_down(priv, true); 892 /* release HP CMFB gate rstb */ 893 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 894 0x1 << 6, 0x1 << 6); 895 896 /* Reduce ESD resistance of AU_REFN */ 897 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 898 899 /* Set HPR/HPL gain as minimum (~ -40dB) */ 900 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG); 901 902 /* Turn on DA_600K_NCP_VA18 */ 903 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 904 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 905 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 906 /* Toggle RG_DIVCKS_CHG */ 907 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 908 /* Set NCP soft start mode as default mode: 100us */ 909 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 910 /* Enable NCP */ 911 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 912 usleep_range(250, 270); 913 914 /* Enable cap-less LDOs (1.5V) */ 915 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 916 0x1055, 0x1055); 917 /* Enable NV regulator (-1.2V) */ 918 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 919 usleep_range(100, 120); 920 921 /* Disable AUD_ZCD */ 922 hp_zcd_disable(priv); 923 924 /* Disable headphone short-circuit protection */ 925 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 926 927 /* Enable IBIST */ 928 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 929 930 /* Set HP DR bias current optimization, 010: 6uA */ 931 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 932 /* Set HP & ZCD bias current optimization */ 933 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 934 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 935 /* Set HPP/N STB enhance circuits */ 936 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 937 938 /* Enable HP aux output stage */ 939 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); 940 /* Enable HP aux feedback loop */ 941 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); 942 /* Enable HP aux CMFB loop */ 943 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 944 /* Enable HP driver bias circuits */ 945 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 946 /* Enable HP driver core circuits */ 947 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 948 /* Short HP main output to HP aux output stage */ 949 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); 950 951 /* Enable HP main CMFB loop */ 952 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 953 /* Disable HP aux CMFB loop */ 954 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 955 956 /* Select CMFB resistor bulk to AC mode */ 957 /* Selec HS/LO cap size (6.5pF default) */ 958 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 959 960 /* Enable HP main output stage */ 961 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); 962 /* Enable HPR/L main output stage step by step */ 963 hp_main_output_ramp(priv, true); 964 965 /* Reduce HP aux feedback loop gain */ 966 hp_aux_feedback_loop_gain_ramp(priv, true); 967 /* Disable HP aux feedback loop */ 968 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 969 970 /* apply volume setting */ 971 headset_volume_ramp(priv, 972 DL_GAIN_N_10DB, 973 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 974 975 /* Disable HP aux output stage */ 976 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 977 /* Unshort HP main output to HP aux output stage */ 978 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); 979 usleep_range(100, 120); 980 981 /* Enable AUD_CLK */ 982 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 983 /* Enable Audio DAC */ 984 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); 985 /* Enable low-noise mode of DAC */ 986 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); 987 usleep_range(100, 120); 988 989 /* Switch HPL MUX to audio DAC */ 990 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); 991 /* Switch HPR MUX to audio DAC */ 992 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); 993 994 /* Disable Pull-down HPL/R to AVSS28_AUD */ 995 hp_pull_down(priv, false); 996 997 return 0; 998 } 999 1000 static int mtk_hp_disable(struct mt6358_priv *priv) 1001 { 1002 /* Pull-down HPL/R to AVSS28_AUD */ 1003 hp_pull_down(priv, true); 1004 1005 /* HPR/HPL mux to open */ 1006 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1007 0x0f00, 0x0000); 1008 1009 /* Disable low-noise mode of DAC */ 1010 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1011 0x0001, 0x0000); 1012 1013 /* Disable Audio DAC */ 1014 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1015 0x000f, 0x0000); 1016 1017 /* Disable AUD_CLK */ 1018 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1019 1020 /* Short HP main output to HP aux output stage */ 1021 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1022 /* Enable HP aux output stage */ 1023 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1024 1025 /* decrease HPL/R gain to normal gain step by step */ 1026 headset_volume_ramp(priv, 1027 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1028 DL_GAIN_N_40DB); 1029 1030 /* Enable HP aux feedback loop */ 1031 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1032 1033 /* Reduce HP aux feedback loop gain */ 1034 hp_aux_feedback_loop_gain_ramp(priv, false); 1035 1036 /* decrease HPR/L main output stage step by step */ 1037 hp_main_output_ramp(priv, false); 1038 1039 /* Disable HP main output stage */ 1040 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1041 1042 /* Enable HP aux CMFB loop */ 1043 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 1044 1045 /* Disable HP main CMFB loop */ 1046 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 1047 1048 /* Unshort HP main output to HP aux output stage */ 1049 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1050 0x3 << 6, 0x0); 1051 1052 /* Disable HP driver core circuits */ 1053 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1054 0x3 << 4, 0x0); 1055 1056 /* Disable HP driver bias circuits */ 1057 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1058 0x3 << 6, 0x0); 1059 1060 /* Disable HP aux CMFB loop */ 1061 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1062 1063 /* Disable HP aux feedback loop */ 1064 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1065 0x3 << 4, 0x0); 1066 1067 /* Disable HP aux output stage */ 1068 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1069 0x3 << 2, 0x0); 1070 1071 /* Disable IBIST */ 1072 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1073 0x1 << 8, 0x1 << 8); 1074 1075 /* Disable NV regulator (-1.2V) */ 1076 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1077 /* Disable cap-less LDOs (1.5V) */ 1078 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1079 0x1055, 0x0); 1080 /* Disable NCP */ 1081 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1082 0x1, 0x1); 1083 1084 /* Increase ESD resistance of AU_REFN */ 1085 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2, 1086 0x1 << 14, 0x0); 1087 1088 /* Set HP CMFB gate rstb */ 1089 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1090 0x1 << 6, 0x0); 1091 /* disable Pull-down HPL/R to AVSS28_AUD */ 1092 hp_pull_down(priv, false); 1093 1094 return 0; 1095 } 1096 1097 static int mtk_hp_spk_enable(struct mt6358_priv *priv) 1098 { 1099 /* Pull-down HPL/R to AVSS28_AUD */ 1100 hp_pull_down(priv, true); 1101 /* release HP CMFB gate rstb */ 1102 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1103 0x1 << 6, 0x1 << 6); 1104 1105 /* Reduce ESD resistance of AU_REFN */ 1106 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1107 1108 /* Set HPR/HPL gain to -10dB */ 1109 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG); 1110 1111 /* Turn on DA_600K_NCP_VA18 */ 1112 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1113 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1114 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1115 /* Toggle RG_DIVCKS_CHG */ 1116 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1117 /* Set NCP soft start mode as default mode: 100us */ 1118 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1119 /* Enable NCP */ 1120 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1121 usleep_range(250, 270); 1122 1123 /* Enable cap-less LDOs (1.5V) */ 1124 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1125 0x1055, 0x1055); 1126 /* Enable NV regulator (-1.2V) */ 1127 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1128 usleep_range(100, 120); 1129 1130 /* Disable AUD_ZCD */ 1131 hp_zcd_disable(priv); 1132 1133 /* Disable headphone short-circuit protection */ 1134 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 1135 1136 /* Enable IBIST */ 1137 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1138 1139 /* Set HP DR bias current optimization, 010: 6uA */ 1140 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1141 /* Set HP & ZCD bias current optimization */ 1142 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1143 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1144 /* Set HPP/N STB enhance circuits */ 1145 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 1146 1147 /* Disable Pull-down HPL/R to AVSS28_AUD */ 1148 hp_pull_down(priv, false); 1149 1150 /* Enable HP driver bias circuits */ 1151 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 1152 /* Enable HP driver core circuits */ 1153 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 1154 /* Enable HP main CMFB loop */ 1155 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 1156 1157 /* Select CMFB resistor bulk to AC mode */ 1158 /* Selec HS/LO cap size (6.5pF default) */ 1159 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1160 1161 /* Enable HP main output stage */ 1162 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); 1163 /* Enable HPR/L main output stage step by step */ 1164 hp_main_output_ramp(priv, true); 1165 1166 /* Set LO gain as minimum (~ -40dB) */ 1167 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG); 1168 /* apply volume setting */ 1169 headset_volume_ramp(priv, 1170 DL_GAIN_N_10DB, 1171 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 1172 1173 /* Set LO STB enhance circuits */ 1174 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); 1175 /* Enable LO driver bias circuits */ 1176 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); 1177 /* Enable LO driver core circuits */ 1178 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); 1179 1180 /* Set LOL gain to normal gain step by step */ 1181 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1182 RG_AUDLOLGAIN_MASK_SFT, 1183 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] << 1184 RG_AUDLOLGAIN_SFT); 1185 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1186 RG_AUDLORGAIN_MASK_SFT, 1187 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] << 1188 RG_AUDLORGAIN_SFT); 1189 1190 /* Enable AUD_CLK */ 1191 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 1192 /* Enable Audio DAC */ 1193 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); 1194 /* Enable low-noise mode of DAC */ 1195 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); 1196 /* Switch LOL MUX to audio DAC */ 1197 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); 1198 /* Switch HPL/R MUX to Line-out */ 1199 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); 1200 1201 return 0; 1202 } 1203 1204 static int mtk_hp_spk_disable(struct mt6358_priv *priv) 1205 { 1206 /* HPR/HPL mux to open */ 1207 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1208 0x0f00, 0x0000); 1209 /* LOL mux to open */ 1210 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1211 0x3 << 2, 0x0000); 1212 1213 /* Disable Audio DAC */ 1214 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1215 0x000f, 0x0000); 1216 1217 /* Disable AUD_CLK */ 1218 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1219 1220 /* decrease HPL/R gain to normal gain step by step */ 1221 headset_volume_ramp(priv, 1222 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1223 DL_GAIN_N_40DB); 1224 1225 /* decrease LOL gain to minimum gain step by step */ 1226 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1227 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG); 1228 1229 /* decrease HPR/L main output stage step by step */ 1230 hp_main_output_ramp(priv, false); 1231 1232 /* Disable HP main output stage */ 1233 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1234 1235 /* Short HP main output to HP aux output stage */ 1236 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1237 /* Enable HP aux output stage */ 1238 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1239 1240 /* Enable HP aux feedback loop */ 1241 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1242 1243 /* Reduce HP aux feedback loop gain */ 1244 hp_aux_feedback_loop_gain_ramp(priv, false); 1245 1246 /* Disable HP driver core circuits */ 1247 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1248 0x3 << 4, 0x0); 1249 /* Disable LO driver core circuits */ 1250 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1251 0x1, 0x0); 1252 1253 /* Disable HP driver bias circuits */ 1254 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1255 0x3 << 6, 0x0); 1256 /* Disable LO driver bias circuits */ 1257 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1258 0x1 << 1, 0x0); 1259 1260 /* Disable HP aux CMFB loop */ 1261 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1262 0xff << 8, 0x0000); 1263 1264 /* Disable IBIST */ 1265 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1266 0x1 << 8, 0x1 << 8); 1267 /* Disable NV regulator (-1.2V) */ 1268 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1269 /* Disable cap-less LDOs (1.5V) */ 1270 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); 1271 /* Disable NCP */ 1272 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); 1273 1274 /* Set HP CMFB gate rstb */ 1275 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1276 0x1 << 6, 0x0); 1277 /* disable Pull-down HPL/R to AVSS28_AUD */ 1278 hp_pull_down(priv, false); 1279 1280 return 0; 1281 } 1282 1283 static int mt_hp_event(struct snd_soc_dapm_widget *w, 1284 struct snd_kcontrol *kcontrol, 1285 int event) 1286 { 1287 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1288 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1289 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1290 int device = DEVICE_HP; 1291 1292 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", 1293 __func__, 1294 event, 1295 priv->dev_counter[device], 1296 mux); 1297 1298 switch (event) { 1299 case SND_SOC_DAPM_PRE_PMU: 1300 priv->dev_counter[device]++; 1301 if (priv->dev_counter[device] > 1) 1302 break; /* already enabled, do nothing */ 1303 else if (priv->dev_counter[device] <= 0) 1304 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", 1305 __func__, 1306 priv->dev_counter[device]); 1307 1308 priv->mux_select[MUX_HP_L] = mux; 1309 1310 if (mux == HP_MUX_HP) 1311 mtk_hp_enable(priv); 1312 else if (mux == HP_MUX_HPSPK) 1313 mtk_hp_spk_enable(priv); 1314 break; 1315 case SND_SOC_DAPM_PRE_PMD: 1316 priv->dev_counter[device]--; 1317 if (priv->dev_counter[device] > 0) { 1318 break; /* still being used, don't close */ 1319 } else if (priv->dev_counter[device] < 0) { 1320 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", 1321 __func__, 1322 priv->dev_counter[device]); 1323 priv->dev_counter[device] = 0; 1324 break; 1325 } 1326 1327 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP) 1328 mtk_hp_disable(priv); 1329 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK) 1330 mtk_hp_spk_disable(priv); 1331 1332 priv->mux_select[MUX_HP_L] = mux; 1333 break; 1334 default: 1335 break; 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int mt_rcv_event(struct snd_soc_dapm_widget *w, 1342 struct snd_kcontrol *kcontrol, 1343 int event) 1344 { 1345 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1346 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1347 1348 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", 1349 __func__, 1350 event, 1351 snd_soc_dapm_kcontrol_get_value(w->kcontrols[0])); 1352 1353 switch (event) { 1354 case SND_SOC_DAPM_PRE_PMU: 1355 /* Reduce ESD resistance of AU_REFN */ 1356 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1357 1358 /* Turn on DA_600K_NCP_VA18 */ 1359 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1360 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1361 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1362 /* Toggle RG_DIVCKS_CHG */ 1363 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1364 /* Set NCP soft start mode as default mode: 100us */ 1365 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1366 /* Enable NCP */ 1367 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1368 usleep_range(250, 270); 1369 1370 /* Enable cap-less LDOs (1.5V) */ 1371 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1372 0x1055, 0x1055); 1373 /* Enable NV regulator (-1.2V) */ 1374 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1375 usleep_range(100, 120); 1376 1377 /* Disable AUD_ZCD */ 1378 hp_zcd_disable(priv); 1379 1380 /* Disable handset short-circuit protection */ 1381 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); 1382 1383 /* Enable IBIST */ 1384 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1385 /* Set HP DR bias current optimization, 010: 6uA */ 1386 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1387 /* Set HP & ZCD bias current optimization */ 1388 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1389 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1390 /* Set HS STB enhance circuits */ 1391 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); 1392 1393 /* Disable HP main CMFB loop */ 1394 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1395 /* Select CMFB resistor bulk to AC mode */ 1396 /* Selec HS/LO cap size (6.5pF default) */ 1397 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1398 1399 /* Enable HS driver bias circuits */ 1400 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); 1401 /* Enable HS driver core circuits */ 1402 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); 1403 1404 /* Enable AUD_CLK */ 1405 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1406 0x1, 0x1); 1407 1408 /* Enable Audio DAC */ 1409 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); 1410 /* Enable low-noise mode of DAC */ 1411 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); 1412 /* Switch HS MUX to audio DAC */ 1413 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); 1414 break; 1415 case SND_SOC_DAPM_PRE_PMD: 1416 /* HS mux to open */ 1417 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1418 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT, 1419 RCV_MUX_OPEN); 1420 1421 /* Disable Audio DAC */ 1422 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1423 0x000f, 0x0000); 1424 1425 /* Disable AUD_CLK */ 1426 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1427 0x1, 0x0); 1428 1429 /* decrease HS gain to minimum gain step by step */ 1430 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB); 1431 1432 /* Disable HS driver core circuits */ 1433 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1434 0x1, 0x0); 1435 1436 /* Disable HS driver bias circuits */ 1437 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1438 0x1 << 1, 0x0000); 1439 1440 /* Disable HP aux CMFB loop */ 1441 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1442 0xff << 8, 0x0); 1443 1444 /* Enable HP main CMFB Switch */ 1445 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1446 0xff << 8, 0x2 << 8); 1447 1448 /* Disable IBIST */ 1449 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1450 0x1 << 8, 0x1 << 8); 1451 1452 /* Disable NV regulator (-1.2V) */ 1453 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 1454 0x1, 0x0); 1455 /* Disable cap-less LDOs (1.5V) */ 1456 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1457 0x1055, 0x0); 1458 /* Disable NCP */ 1459 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1460 0x1, 0x1); 1461 break; 1462 default: 1463 break; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static int mt_aif_out_event(struct snd_soc_dapm_widget *w, 1470 struct snd_kcontrol *kcontrol, 1471 int event) 1472 { 1473 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1474 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1475 1476 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", 1477 __func__, event, priv->ul_rate); 1478 1479 switch (event) { 1480 case SND_SOC_DAPM_PRE_PMU: 1481 capture_gpio_set(priv); 1482 break; 1483 case SND_SOC_DAPM_POST_PMD: 1484 capture_gpio_reset(priv); 1485 break; 1486 default: 1487 break; 1488 } 1489 1490 return 0; 1491 } 1492 1493 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w, 1494 struct snd_kcontrol *kcontrol, 1495 int event) 1496 { 1497 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1498 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1499 1500 dev_dbg(priv->dev, "%s(), event 0x%x\n", 1501 __func__, event); 1502 1503 switch (event) { 1504 case SND_SOC_DAPM_PRE_PMU: 1505 /* Enable audio ADC CLKGEN */ 1506 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1507 0x1 << 5, 0x1 << 5); 1508 /* ADC CLK from CLKGEN (13MHz) */ 1509 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 1510 0x0000); 1511 /* Enable LCLDO_ENC 1P8V */ 1512 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1513 0x2500, 0x0100); 1514 /* LCLDO_ENC remote sense */ 1515 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1516 0x2500, 0x2500); 1517 break; 1518 case SND_SOC_DAPM_POST_PMD: 1519 /* LCLDO_ENC remote sense off */ 1520 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1521 0x2500, 0x0100); 1522 /* disable LCLDO_ENC 1P8V */ 1523 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1524 0x2500, 0x0000); 1525 1526 /* ADC CLK from CLKGEN (13MHz) */ 1527 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); 1528 /* disable audio ADC CLKGEN */ 1529 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1530 0x1 << 5, 0x0 << 5); 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 return 0; 1537 } 1538 1539 static int mt6358_amic_enable(struct mt6358_priv *priv) 1540 { 1541 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1542 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1543 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1544 1545 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1546 __func__, mic_type, mux_pga_l, mux_pga_r); 1547 1548 if (IS_DCC_BASE(mic_type)) { 1549 /* DCC 50k CLK (from 26M) */ 1550 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1551 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1552 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1553 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); 1554 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); 1555 } 1556 1557 /* mic bias 0 */ 1558 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 || 1559 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) { 1560 switch (mic_type) { 1561 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1562 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1563 0xff00, 0x7700); 1564 break; 1565 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1566 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1567 0xff00, 0x1100); 1568 break; 1569 default: 1570 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1571 0xff00, 0x0000); 1572 break; 1573 } 1574 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1575 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1576 0xff, 0x21); 1577 } 1578 1579 /* mic bias 1 */ 1580 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) { 1581 /* Enable MICBIAS1, MISBIAS1 = 2P6V */ 1582 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE) 1583 regmap_write(priv->regmap, 1584 MT6358_AUDENC_ANA_CON10, 0x0161); 1585 else 1586 regmap_write(priv->regmap, 1587 MT6358_AUDENC_ANA_CON10, 0x0061); 1588 } 1589 1590 if (IS_DCC_BASE(mic_type)) { 1591 /* Audio L/R preamplifier DCC precharge */ 1592 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1593 0xf8ff, 0x0004); 1594 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1595 0xf8ff, 0x0004); 1596 } else { 1597 /* reset reg */ 1598 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1599 0xf8ff, 0x0000); 1600 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1601 0xf8ff, 0x0000); 1602 } 1603 1604 if (mux_pga_l != PGA_MUX_NONE) { 1605 /* L preamplifier input sel */ 1606 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1607 RG_AUDPREAMPLINPUTSEL_MASK_SFT, 1608 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT); 1609 1610 /* L preamplifier enable */ 1611 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1612 RG_AUDPREAMPLON_MASK_SFT, 1613 0x1 << RG_AUDPREAMPLON_SFT); 1614 1615 if (IS_DCC_BASE(mic_type)) { 1616 /* L preamplifier DCCEN */ 1617 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1618 RG_AUDPREAMPLDCCEN_MASK_SFT, 1619 0x1 << RG_AUDPREAMPLDCCEN_SFT); 1620 } 1621 1622 /* L ADC input sel : L PGA. Enable audio L ADC */ 1623 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1624 RG_AUDADCLINPUTSEL_MASK_SFT, 1625 ADC_MUX_PREAMPLIFIER << 1626 RG_AUDADCLINPUTSEL_SFT); 1627 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1628 RG_AUDADCLPWRUP_MASK_SFT, 1629 0x1 << RG_AUDADCLPWRUP_SFT); 1630 } 1631 1632 if (mux_pga_r != PGA_MUX_NONE) { 1633 /* R preamplifier input sel */ 1634 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1635 RG_AUDPREAMPRINPUTSEL_MASK_SFT, 1636 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT); 1637 1638 /* R preamplifier enable */ 1639 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1640 RG_AUDPREAMPRON_MASK_SFT, 1641 0x1 << RG_AUDPREAMPRON_SFT); 1642 1643 if (IS_DCC_BASE(mic_type)) { 1644 /* R preamplifier DCCEN */ 1645 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1646 RG_AUDPREAMPRDCCEN_MASK_SFT, 1647 0x1 << RG_AUDPREAMPRDCCEN_SFT); 1648 } 1649 1650 /* R ADC input sel : R PGA. Enable audio R ADC */ 1651 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1652 RG_AUDADCRINPUTSEL_MASK_SFT, 1653 ADC_MUX_PREAMPLIFIER << 1654 RG_AUDADCRINPUTSEL_SFT); 1655 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1656 RG_AUDADCRPWRUP_MASK_SFT, 1657 0x1 << RG_AUDADCRPWRUP_SFT); 1658 } 1659 1660 if (IS_DCC_BASE(mic_type)) { 1661 usleep_range(100, 150); 1662 /* Audio L preamplifier DCC precharge off */ 1663 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1664 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); 1665 /* Audio R preamplifier DCC precharge off */ 1666 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1667 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); 1668 1669 /* Short body to ground in PGA */ 1670 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3, 1671 0x1 << 12, 0x0); 1672 } 1673 1674 /* here to set digital part */ 1675 mt6358_mtkaif_tx_enable(priv); 1676 1677 /* UL dmic setting off */ 1678 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); 1679 1680 /* UL turn on */ 1681 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); 1682 1683 return 0; 1684 } 1685 1686 static void mt6358_amic_disable(struct mt6358_priv *priv) 1687 { 1688 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1689 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1690 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1691 1692 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1693 __func__, mic_type, mux_pga_l, mux_pga_r); 1694 1695 /* UL turn off */ 1696 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1697 0x0001, 0x0000); 1698 1699 /* disable aud_pad TX fifos */ 1700 mt6358_mtkaif_tx_disable(priv); 1701 1702 /* L ADC input sel : off, disable L ADC */ 1703 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1704 0xf000, 0x0000); 1705 /* L preamplifier DCCEN */ 1706 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1707 0x1 << 1, 0x0); 1708 /* L preamplifier input sel : off, L PGA 0 dB gain */ 1709 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1710 0xfffb, 0x0000); 1711 1712 /* disable L preamplifier DCC precharge */ 1713 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1714 0x1 << 2, 0x0); 1715 1716 /* R ADC input sel : off, disable R ADC */ 1717 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1718 0xf000, 0x0000); 1719 /* R preamplifier DCCEN */ 1720 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1721 0x1 << 1, 0x0); 1722 /* R preamplifier input sel : off, R PGA 0 dB gain */ 1723 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1724 0x0ffb, 0x0000); 1725 1726 /* disable R preamplifier DCC precharge */ 1727 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1728 0x1 << 2, 0x0); 1729 1730 /* mic bias */ 1731 /* Disable MICBIAS0, MISBIAS0 = 1P7V */ 1732 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1733 1734 /* Disable MICBIAS1 */ 1735 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1736 0x0001, 0x0000); 1737 1738 if (IS_DCC_BASE(mic_type)) { 1739 /* dcclk_gen_on=1'b0 */ 1740 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1741 /* dcclk_pdn=1'b1 */ 1742 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1743 /* dcclk_ref_ck_sel=2'b00 */ 1744 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1745 /* dcclk_div=11'b00100000011 */ 1746 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1747 } 1748 } 1749 1750 static int mt6358_dmic_enable(struct mt6358_priv *priv) 1751 { 1752 dev_info(priv->dev, "%s()\n", __func__); 1753 1754 /* mic bias */ 1755 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1756 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); 1757 1758 /* RG_BANDGAPGEN=1'b0 */ 1759 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1760 0x1 << 12, 0x0); 1761 1762 /* DMIC enable */ 1763 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); 1764 1765 /* here to set digital part */ 1766 mt6358_mtkaif_tx_enable(priv); 1767 1768 /* UL dmic setting */ 1769 if (priv->dmic_one_wire_mode) 1770 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); 1771 else 1772 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); 1773 1774 /* UL turn on */ 1775 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); 1776 1777 /* Prevent pop noise form dmic hw */ 1778 msleep(100); 1779 1780 return 0; 1781 } 1782 1783 static void mt6358_dmic_disable(struct mt6358_priv *priv) 1784 { 1785 dev_info(priv->dev, "%s()\n", __func__); 1786 1787 /* UL turn off */ 1788 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1789 0x0003, 0x0000); 1790 1791 /* disable aud_pad TX fifos */ 1792 mt6358_mtkaif_tx_disable(priv); 1793 1794 /* DMIC disable */ 1795 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); 1796 1797 /* mic bias */ 1798 /* MISBIAS0 = 1P7V */ 1799 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); 1800 1801 /* RG_BANDGAPGEN=1'b0 */ 1802 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1803 0x1 << 12, 0x0); 1804 1805 /* MICBIA0 disable */ 1806 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1807 } 1808 1809 static void mt6358_restore_pga(struct mt6358_priv *priv) 1810 { 1811 unsigned int gain_l, gain_r; 1812 1813 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 1814 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 1815 1816 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1817 RG_AUDPREAMPLGAIN_MASK_SFT, 1818 gain_l << RG_AUDPREAMPLGAIN_SFT); 1819 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1820 RG_AUDPREAMPRGAIN_MASK_SFT, 1821 gain_r << RG_AUDPREAMPRGAIN_SFT); 1822 } 1823 1824 static int mt_mic_type_event(struct snd_soc_dapm_widget *w, 1825 struct snd_kcontrol *kcontrol, 1826 int event) 1827 { 1828 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1829 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1830 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1831 1832 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 1833 __func__, event, mux); 1834 1835 switch (event) { 1836 case SND_SOC_DAPM_WILL_PMU: 1837 priv->mux_select[MUX_MIC_TYPE] = mux; 1838 break; 1839 case SND_SOC_DAPM_PRE_PMU: 1840 switch (mux) { 1841 case MIC_TYPE_MUX_DMIC: 1842 mt6358_dmic_enable(priv); 1843 break; 1844 default: 1845 mt6358_amic_enable(priv); 1846 break; 1847 } 1848 mt6358_restore_pga(priv); 1849 1850 break; 1851 case SND_SOC_DAPM_POST_PMD: 1852 switch (priv->mux_select[MUX_MIC_TYPE]) { 1853 case MIC_TYPE_MUX_DMIC: 1854 mt6358_dmic_disable(priv); 1855 break; 1856 default: 1857 mt6358_amic_disable(priv); 1858 break; 1859 } 1860 1861 priv->mux_select[MUX_MIC_TYPE] = mux; 1862 break; 1863 default: 1864 break; 1865 } 1866 1867 return 0; 1868 } 1869 1870 static int mt_adc_l_event(struct snd_soc_dapm_widget *w, 1871 struct snd_kcontrol *kcontrol, 1872 int event) 1873 { 1874 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1875 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1876 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1877 1878 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1879 __func__, event, mux); 1880 1881 priv->mux_select[MUX_ADC_L] = mux; 1882 1883 return 0; 1884 } 1885 1886 static int mt_adc_r_event(struct snd_soc_dapm_widget *w, 1887 struct snd_kcontrol *kcontrol, 1888 int event) 1889 { 1890 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1891 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1892 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1893 1894 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1895 __func__, event, mux); 1896 1897 priv->mux_select[MUX_ADC_R] = mux; 1898 1899 return 0; 1900 } 1901 1902 static int mt_pga_left_event(struct snd_soc_dapm_widget *w, 1903 struct snd_kcontrol *kcontrol, 1904 int event) 1905 { 1906 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1907 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1908 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1909 1910 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1911 __func__, event, mux); 1912 1913 priv->mux_select[MUX_PGA_L] = mux; 1914 1915 return 0; 1916 } 1917 1918 static int mt_pga_right_event(struct snd_soc_dapm_widget *w, 1919 struct snd_kcontrol *kcontrol, 1920 int event) 1921 { 1922 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1923 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1924 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 1925 1926 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1927 __func__, event, mux); 1928 1929 priv->mux_select[MUX_PGA_R] = mux; 1930 1931 return 0; 1932 } 1933 1934 static int mt_delay_250_event(struct snd_soc_dapm_widget *w, 1935 struct snd_kcontrol *kcontrol, 1936 int event) 1937 { 1938 switch (event) { 1939 case SND_SOC_DAPM_POST_PMU: 1940 usleep_range(250, 270); 1941 break; 1942 case SND_SOC_DAPM_PRE_PMD: 1943 usleep_range(250, 270); 1944 break; 1945 default: 1946 break; 1947 } 1948 1949 return 0; 1950 } 1951 1952 /* DAPM Widgets */ 1953 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = { 1954 /* Global Supply*/ 1955 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF, 1956 MT6358_DCXO_CW14, 1957 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0), 1958 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB, 1959 MT6358_AUDDEC_ANA_CON13, 1960 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0), 1961 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ, 1962 MT6358_AUDENC_ANA_CON6, 1963 RG_CLKSQ_EN_SFT, 0, 1964 mt_clksq_event, 1965 SND_SOC_DAPM_PRE_PMU), 1966 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK, 1967 MT6358_AUD_TOP_CKPDN_CON0, 1968 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0), 1969 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK, 1970 MT6358_AUD_TOP_CKPDN_CON0, 1971 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0), 1972 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, 1973 MT6358_AUD_TOP_CKPDN_CON0, 1974 RG_AUD_CK_PDN_SFT, 1, 1975 mt_delay_250_event, 1976 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1977 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK, 1978 MT6358_AUD_TOP_CKPDN_CON0, 1979 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0), 1980 1981 /* Digital Clock */ 1982 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST, 1983 MT6358_AUDIO_TOP_CON0, 1984 PDN_AFE_CTL_SFT, 1, 1985 mt_delay_250_event, 1986 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1987 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP, 1988 MT6358_AUDIO_TOP_CON0, 1989 PDN_DAC_CTL_SFT, 1, NULL, 0), 1990 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 1991 MT6358_AUDIO_TOP_CON0, 1992 PDN_ADC_CTL_SFT, 1, NULL, 0), 1993 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP, 1994 MT6358_AUDIO_TOP_CON0, 1995 PDN_I2S_DL_CTL_SFT, 1, NULL, 0), 1996 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP, 1997 MT6358_AUDIO_TOP_CON0, 1998 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0), 1999 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP, 2000 MT6358_AUDIO_TOP_CON0, 2001 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0), 2002 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP, 2003 MT6358_AUDIO_TOP_CON0, 2004 PDN_RESERVED_SFT, 1, NULL, 0), 2005 2006 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 2007 0, 0, NULL, 0), 2008 2009 /* AFE ON */ 2010 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE, 2011 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0, 2012 NULL, 0), 2013 2014 /* AIF Rx*/ 2015 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0, 2016 MT6358_AFE_DL_SRC2_CON0_L, 2017 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 2018 mt_aif_in_event, 2019 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2020 2021 /* DL Supply */ 2022 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 2023 0, 0, NULL, 0), 2024 2025 /* DAC */ 2026 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 2027 2028 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 2029 2030 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 2031 2032 /* LOL */ 2033 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control), 2034 2035 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7, 2036 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0), 2037 2038 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7, 2039 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0), 2040 2041 /* Headphone */ 2042 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0, 2043 &hpl_in_mux_control, 2044 mt_hp_event, 2045 SND_SOC_DAPM_PRE_PMU | 2046 SND_SOC_DAPM_PRE_PMD), 2047 2048 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0, 2049 &hpr_in_mux_control, 2050 mt_hp_event, 2051 SND_SOC_DAPM_PRE_PMU | 2052 SND_SOC_DAPM_PRE_PMD), 2053 2054 /* Receiver */ 2055 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0, 2056 &rcv_in_mux_control, 2057 mt_rcv_event, 2058 SND_SOC_DAPM_PRE_PMU | 2059 SND_SOC_DAPM_PRE_PMD), 2060 2061 /* Outputs */ 2062 SND_SOC_DAPM_OUTPUT("Receiver"), 2063 SND_SOC_DAPM_OUTPUT("Headphone L"), 2064 SND_SOC_DAPM_OUTPUT("Headphone R"), 2065 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"), 2066 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"), 2067 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 2068 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"), 2069 2070 /* SGEN */ 2071 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0, 2072 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0), 2073 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0, 2074 SGEN_MUTE_SW_CTL_SFT, 1, 2075 mt_sgen_event, 2076 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2077 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L, 2078 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0), 2079 2080 SND_SOC_DAPM_INPUT("SGEN DL"), 2081 2082 /* Uplinks */ 2083 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0, 2084 SND_SOC_NOPM, 0, 0, 2085 mt_aif_out_event, 2086 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2087 2088 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY, 2089 SND_SOC_NOPM, 0, 0, 2090 mt_adc_supply_event, 2091 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2092 2093 /* Uplinks MUX */ 2094 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 2095 &aif_out_mux_control), 2096 2097 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0, 2098 &mic_type_mux_control, 2099 mt_mic_type_event, 2100 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD | 2101 SND_SOC_DAPM_WILL_PMU), 2102 2103 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0, 2104 &adc_left_mux_control, 2105 mt_adc_l_event, 2106 SND_SOC_DAPM_WILL_PMU), 2107 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0, 2108 &adc_right_mux_control, 2109 mt_adc_r_event, 2110 SND_SOC_DAPM_WILL_PMU), 2111 2112 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2113 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2114 2115 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0, 2116 &pga_left_mux_control, 2117 mt_pga_left_event, 2118 SND_SOC_DAPM_WILL_PMU), 2119 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0, 2120 &pga_right_mux_control, 2121 mt_pga_right_event, 2122 SND_SOC_DAPM_WILL_PMU), 2123 2124 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0), 2125 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0), 2126 2127 /* UL input */ 2128 SND_SOC_DAPM_INPUT("AIN0"), 2129 SND_SOC_DAPM_INPUT("AIN1"), 2130 SND_SOC_DAPM_INPUT("AIN2"), 2131 }; 2132 2133 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = { 2134 /* Capture */ 2135 {"AIF1TX", NULL, "AIF Out Mux"}, 2136 {"AIF1TX", NULL, "CLK_BUF"}, 2137 {"AIF1TX", NULL, "AUDGLB"}, 2138 {"AIF1TX", NULL, "CLKSQ Audio"}, 2139 2140 {"AIF1TX", NULL, "AUD_CK"}, 2141 {"AIF1TX", NULL, "AUDIF_CK"}, 2142 2143 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}, 2144 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}, 2145 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}, 2146 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2147 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"}, 2148 2149 {"AIF1TX", NULL, "AFE_ON"}, 2150 2151 {"AIF Out Mux", NULL, "Mic Type Mux"}, 2152 2153 {"Mic Type Mux", "ACC", "ADC L"}, 2154 {"Mic Type Mux", "ACC", "ADC R"}, 2155 {"Mic Type Mux", "DCC", "ADC L"}, 2156 {"Mic Type Mux", "DCC", "ADC R"}, 2157 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"}, 2158 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"}, 2159 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"}, 2160 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"}, 2161 {"Mic Type Mux", "DMIC", "AIN0"}, 2162 {"Mic Type Mux", "DMIC", "AIN2"}, 2163 2164 {"ADC L", NULL, "ADC L Mux"}, 2165 {"ADC L", NULL, "ADC Supply"}, 2166 {"ADC R", NULL, "ADC R Mux"}, 2167 {"ADC R", NULL, "ADC Supply"}, 2168 2169 {"ADC L Mux", "Left Preamplifier", "PGA L"}, 2170 2171 {"ADC R Mux", "Right Preamplifier", "PGA R"}, 2172 2173 {"PGA L", NULL, "PGA L Mux"}, 2174 {"PGA R", NULL, "PGA R Mux"}, 2175 2176 {"PGA L Mux", "AIN0", "AIN0"}, 2177 {"PGA L Mux", "AIN1", "AIN1"}, 2178 {"PGA L Mux", "AIN2", "AIN2"}, 2179 2180 {"PGA R Mux", "AIN0", "AIN0"}, 2181 {"PGA R Mux", "AIN1", "AIN1"}, 2182 {"PGA R Mux", "AIN2", "AIN2"}, 2183 2184 /* DL Supply */ 2185 {"DL Power Supply", NULL, "CLK_BUF"}, 2186 {"DL Power Supply", NULL, "AUDGLB"}, 2187 {"DL Power Supply", NULL, "CLKSQ Audio"}, 2188 2189 {"DL Power Supply", NULL, "AUDNCP_CK"}, 2190 {"DL Power Supply", NULL, "ZCD13M_CK"}, 2191 {"DL Power Supply", NULL, "AUD_CK"}, 2192 {"DL Power Supply", NULL, "AUDIF_CK"}, 2193 2194 /* DL Digital Supply */ 2195 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 2196 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 2197 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 2198 2199 {"DL Digital Clock", NULL, "AFE_ON"}, 2200 2201 {"AIF_RX", NULL, "DL Digital Clock"}, 2202 2203 /* DL Path */ 2204 {"DAC In Mux", "Normal Path", "AIF_RX"}, 2205 2206 {"DAC In Mux", "Sgen", "SGEN DL"}, 2207 {"SGEN DL", NULL, "SGEN DL SRC"}, 2208 {"SGEN DL", NULL, "SGEN MUTE"}, 2209 {"SGEN DL", NULL, "SGEN DL Enable"}, 2210 {"SGEN DL", NULL, "DL Digital Clock"}, 2211 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"}, 2212 2213 {"DACL", NULL, "DAC In Mux"}, 2214 {"DACL", NULL, "DL Power Supply"}, 2215 2216 {"DACR", NULL, "DAC In Mux"}, 2217 {"DACR", NULL, "DL Power Supply"}, 2218 2219 /* Lineout Path */ 2220 {"LOL Mux", "Playback", "DACL"}, 2221 2222 {"LOL Buffer", NULL, "LOL Mux"}, 2223 {"LOL Buffer", NULL, "LO Stability Enh"}, 2224 2225 {"LINEOUT L", NULL, "LOL Buffer"}, 2226 2227 /* Headphone Path */ 2228 {"HPL Mux", "Audio Playback", "DACL"}, 2229 {"HPR Mux", "Audio Playback", "DACR"}, 2230 {"HPL Mux", "HP Impedance", "DACL"}, 2231 {"HPR Mux", "HP Impedance", "DACR"}, 2232 {"HPL Mux", "LoudSPK Playback", "DACL"}, 2233 {"HPR Mux", "LoudSPK Playback", "DACR"}, 2234 2235 {"Headphone L", NULL, "HPL Mux"}, 2236 {"Headphone R", NULL, "HPR Mux"}, 2237 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"}, 2238 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"}, 2239 {"LINEOUT L HSSPK", NULL, "HPL Mux"}, 2240 2241 /* Receiver Path */ 2242 {"RCV Mux", "Voice Playback", "DACL"}, 2243 {"Receiver", NULL, "RCV Mux"}, 2244 }; 2245 2246 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream, 2247 struct snd_pcm_hw_params *params, 2248 struct snd_soc_dai *dai) 2249 { 2250 struct snd_soc_component *cmpnt = dai->component; 2251 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2252 unsigned int rate = params_rate(params); 2253 2254 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n", 2255 __func__, 2256 substream->stream, 2257 rate, 2258 substream->number); 2259 2260 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2261 priv->dl_rate = rate; 2262 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2263 priv->ul_rate = rate; 2264 2265 return 0; 2266 } 2267 2268 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = { 2269 .hw_params = mt6358_codec_dai_hw_params, 2270 }; 2271 2272 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\ 2273 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\ 2274 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE) 2275 2276 static struct snd_soc_dai_driver mt6358_dai_driver[] = { 2277 { 2278 .name = "mt6358-snd-codec-aif1", 2279 .playback = { 2280 .stream_name = "AIF1 Playback", 2281 .channels_min = 1, 2282 .channels_max = 2, 2283 .rates = SNDRV_PCM_RATE_8000_48000 | 2284 SNDRV_PCM_RATE_96000 | 2285 SNDRV_PCM_RATE_192000, 2286 .formats = MT6358_FORMATS, 2287 }, 2288 .capture = { 2289 .stream_name = "AIF1 Capture", 2290 .channels_min = 1, 2291 .channels_max = 2, 2292 .rates = SNDRV_PCM_RATE_8000 | 2293 SNDRV_PCM_RATE_16000 | 2294 SNDRV_PCM_RATE_32000 | 2295 SNDRV_PCM_RATE_48000, 2296 .formats = MT6358_FORMATS, 2297 }, 2298 .ops = &mt6358_codec_dai_ops, 2299 }, 2300 }; 2301 2302 static void mt6358_codec_init_reg(struct mt6358_priv *priv) 2303 { 2304 /* Disable HeadphoneL/HeadphoneR short circuit protection */ 2305 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2306 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT, 2307 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); 2308 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2309 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT, 2310 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); 2311 /* Disable voice short circuit protection */ 2312 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 2313 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT, 2314 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); 2315 /* disable LO buffer left short circuit protection */ 2316 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 2317 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT, 2318 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); 2319 2320 /* accdet s/w enable */ 2321 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13, 2322 0xFFFF, 0x700E); 2323 2324 /* gpio miso driving set to 4mA */ 2325 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); 2326 2327 /* set gpio */ 2328 playback_gpio_reset(priv); 2329 capture_gpio_reset(priv); 2330 } 2331 2332 static int mt6358_codec_probe(struct snd_soc_component *cmpnt) 2333 { 2334 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2335 int ret; 2336 2337 snd_soc_component_init_regmap(cmpnt, priv->regmap); 2338 2339 mt6358_codec_init_reg(priv); 2340 2341 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd"); 2342 if (IS_ERR(priv->avdd_reg)) { 2343 dev_err(priv->dev, "%s() have no Avdd supply", __func__); 2344 return PTR_ERR(priv->avdd_reg); 2345 } 2346 2347 ret = regulator_enable(priv->avdd_reg); 2348 if (ret) 2349 return ret; 2350 2351 return 0; 2352 } 2353 2354 static const struct snd_soc_component_driver mt6358_soc_component_driver = { 2355 .probe = mt6358_codec_probe, 2356 .controls = mt6358_snd_controls, 2357 .num_controls = ARRAY_SIZE(mt6358_snd_controls), 2358 .dapm_widgets = mt6358_dapm_widgets, 2359 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets), 2360 .dapm_routes = mt6358_dapm_routes, 2361 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes), 2362 .endianness = 1, 2363 }; 2364 2365 static void mt6358_parse_dt(struct mt6358_priv *priv) 2366 { 2367 int ret; 2368 struct device *dev = priv->dev; 2369 2370 ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode", 2371 &priv->dmic_one_wire_mode); 2372 if (ret) { 2373 dev_warn(priv->dev, "%s() failed to read dmic-mode\n", 2374 __func__); 2375 priv->dmic_one_wire_mode = 0; 2376 } 2377 } 2378 2379 static int mt6358_platform_driver_probe(struct platform_device *pdev) 2380 { 2381 struct mt6358_priv *priv; 2382 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 2383 2384 priv = devm_kzalloc(&pdev->dev, 2385 sizeof(struct mt6358_priv), 2386 GFP_KERNEL); 2387 if (!priv) 2388 return -ENOMEM; 2389 2390 dev_set_drvdata(&pdev->dev, priv); 2391 2392 priv->dev = &pdev->dev; 2393 2394 priv->regmap = mt6397->regmap; 2395 if (IS_ERR(priv->regmap)) 2396 return PTR_ERR(priv->regmap); 2397 2398 mt6358_parse_dt(priv); 2399 2400 dev_info(priv->dev, "%s(), dev name %s\n", 2401 __func__, dev_name(&pdev->dev)); 2402 2403 return devm_snd_soc_register_component(&pdev->dev, 2404 &mt6358_soc_component_driver, 2405 mt6358_dai_driver, 2406 ARRAY_SIZE(mt6358_dai_driver)); 2407 } 2408 2409 static const struct of_device_id mt6358_of_match[] = { 2410 {.compatible = "mediatek,mt6358-sound",}, 2411 {.compatible = "mediatek,mt6366-sound",}, 2412 {} 2413 }; 2414 MODULE_DEVICE_TABLE(of, mt6358_of_match); 2415 2416 static struct platform_driver mt6358_platform_driver = { 2417 .driver = { 2418 .name = "mt6358-sound", 2419 .of_match_table = mt6358_of_match, 2420 }, 2421 .probe = mt6358_platform_driver_probe, 2422 }; 2423 2424 module_platform_driver(mt6358_platform_driver) 2425 2426 /* Module information */ 2427 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver"); 2428 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 2429 MODULE_LICENSE("GPL v2"); 2430