1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mt6358.c -- mt6358 ALSA SoC audio codec driver 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/sched.h> 14 #include <linux/mfd/mt6397/core.h> 15 #include <linux/regulator/consumer.h> 16 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 20 #include "mt6358.h" 21 22 enum { 23 AUDIO_ANALOG_VOLUME_HSOUTL, 24 AUDIO_ANALOG_VOLUME_HSOUTR, 25 AUDIO_ANALOG_VOLUME_HPOUTL, 26 AUDIO_ANALOG_VOLUME_HPOUTR, 27 AUDIO_ANALOG_VOLUME_LINEOUTL, 28 AUDIO_ANALOG_VOLUME_LINEOUTR, 29 AUDIO_ANALOG_VOLUME_MICAMP1, 30 AUDIO_ANALOG_VOLUME_MICAMP2, 31 AUDIO_ANALOG_VOLUME_TYPE_MAX 32 }; 33 34 enum { 35 MUX_ADC_L, 36 MUX_ADC_R, 37 MUX_PGA_L, 38 MUX_PGA_R, 39 MUX_MIC_TYPE, 40 MUX_HP_L, 41 MUX_HP_R, 42 MUX_NUM, 43 }; 44 45 enum { 46 DEVICE_HP, 47 DEVICE_LO, 48 DEVICE_RCV, 49 DEVICE_MIC1, 50 DEVICE_MIC2, 51 DEVICE_NUM 52 }; 53 54 /* Supply widget subseq */ 55 enum { 56 /* common */ 57 SUPPLY_SEQ_CLK_BUF, 58 SUPPLY_SEQ_AUD_GLB, 59 SUPPLY_SEQ_CLKSQ, 60 SUPPLY_SEQ_VOW_AUD_LPW, 61 SUPPLY_SEQ_AUD_VOW, 62 SUPPLY_SEQ_VOW_CLK, 63 SUPPLY_SEQ_VOW_LDO, 64 SUPPLY_SEQ_TOP_CK, 65 SUPPLY_SEQ_TOP_CK_LAST, 66 SUPPLY_SEQ_AUD_TOP, 67 SUPPLY_SEQ_AUD_TOP_LAST, 68 SUPPLY_SEQ_AFE, 69 /* capture */ 70 SUPPLY_SEQ_ADC_SUPPLY, 71 }; 72 73 enum { 74 CH_L = 0, 75 CH_R, 76 NUM_CH, 77 }; 78 79 #define REG_STRIDE 2 80 81 struct mt6358_priv { 82 struct device *dev; 83 struct regmap *regmap; 84 85 unsigned int dl_rate; 86 unsigned int ul_rate; 87 88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; 89 unsigned int mux_select[MUX_NUM]; 90 91 int dev_counter[DEVICE_NUM]; 92 93 int mtkaif_protocol; 94 95 struct regulator *avdd_reg; 96 97 int wov_enabled; 98 99 unsigned int dmic_one_wire_mode; 100 }; 101 102 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt, 103 int mtkaif_protocol) 104 { 105 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 106 107 priv->mtkaif_protocol = mtkaif_protocol; 108 return 0; 109 } 110 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol); 111 112 static void playback_gpio_set(struct mt6358_priv *priv) 113 { 114 /* set gpio mosi mode */ 115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 116 0x01f8, 0x01f8); 117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, 118 0xffff, 0x0249); 119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 120 0xffff, 0x0249); 121 } 122 123 static void playback_gpio_reset(struct mt6358_priv *priv) 124 { 125 /* set pad_aud_*_mosi to GPIO mode and dir input 126 * reason: 127 * pad_aud_dat_mosi*, because the pin is used as boot strap 128 * don't clean clk/sync, for mtkaif protocol 2 129 */ 130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 131 0x01f8, 0x01f8); 132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 133 0x01f8, 0x0000); 134 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 135 0xf << 8, 0x0); 136 } 137 138 static void capture_gpio_set(struct mt6358_priv *priv) 139 { 140 /* set gpio miso mode */ 141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 142 0xffff, 0xffff); 143 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET, 144 0xffff, 0x0249); 145 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 146 0xffff, 0x0249); 147 } 148 149 static void capture_gpio_reset(struct mt6358_priv *priv) 150 { 151 /* set pad_aud_*_miso to GPIO mode and dir input 152 * reason: 153 * pad_aud_clk_miso, because when playback only the miso_clk 154 * will also have 26m, so will have power leak 155 * pad_aud_dat_miso*, because the pin is used as boot strap 156 */ 157 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 158 0xffff, 0xffff); 159 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 160 0xffff, 0x0000); 161 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 162 0xf << 12, 0x0); 163 } 164 165 /* use only when not govern by DAPM */ 166 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable) 167 { 168 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 169 0x1 << RG_XO_AUDIO_EN_M_SFT, 170 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); 171 return 0; 172 } 173 174 /* use only when not govern by DAPM */ 175 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable) 176 { 177 /* audio clk source from internal dcxo */ 178 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 179 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 180 0x0); 181 182 /* Enable/disable CLKSQ 26MHz */ 183 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 184 RG_CLKSQ_EN_MASK_SFT, 185 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); 186 return 0; 187 } 188 189 /* use only when not govern by DAPM */ 190 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable) 191 { 192 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 193 RG_AUDGLB_PWRDN_VA28_MASK_SFT, 194 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT); 195 return 0; 196 } 197 198 /* use only when not govern by DAPM */ 199 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable) 200 { 201 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 202 0x0066, enable ? 0x0 : 0x66); 203 return 0; 204 } 205 206 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv) 207 { 208 switch (priv->mtkaif_protocol) { 209 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2: 210 /* MTKAIF TX format setting */ 211 regmap_update_bits(priv->regmap, 212 MT6358_AFE_ADDA_MTKAIF_CFG0, 213 0xffff, 0x0010); 214 /* enable aud_pad TX fifos */ 215 regmap_update_bits(priv->regmap, 216 MT6358_AFE_AUD_PAD_TOP, 217 0xff00, 0x3800); 218 regmap_update_bits(priv->regmap, 219 MT6358_AFE_AUD_PAD_TOP, 220 0xff00, 0x3900); 221 break; 222 case MT6358_MTKAIF_PROTOCOL_2: 223 /* MTKAIF TX format setting */ 224 regmap_update_bits(priv->regmap, 225 MT6358_AFE_ADDA_MTKAIF_CFG0, 226 0xffff, 0x0010); 227 /* enable aud_pad TX fifos */ 228 regmap_update_bits(priv->regmap, 229 MT6358_AFE_AUD_PAD_TOP, 230 0xff00, 0x3100); 231 break; 232 case MT6358_MTKAIF_PROTOCOL_1: 233 default: 234 /* MTKAIF TX format setting */ 235 regmap_update_bits(priv->regmap, 236 MT6358_AFE_ADDA_MTKAIF_CFG0, 237 0xffff, 0x0000); 238 /* enable aud_pad TX fifos */ 239 regmap_update_bits(priv->regmap, 240 MT6358_AFE_AUD_PAD_TOP, 241 0xff00, 0x3100); 242 break; 243 } 244 return 0; 245 } 246 247 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv) 248 { 249 /* disable aud_pad TX fifos */ 250 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP, 251 0xff00, 0x3000); 252 return 0; 253 } 254 255 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt) 256 { 257 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 258 259 playback_gpio_set(priv); 260 capture_gpio_set(priv); 261 mt6358_mtkaif_tx_enable(priv); 262 263 mt6358_set_dcxo(priv, true); 264 mt6358_set_aud_global_bias(priv, true); 265 mt6358_set_clksq(priv, true); 266 mt6358_set_topck(priv, true); 267 268 /* set dat_miso_loopback on */ 269 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 270 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 271 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 272 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 273 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 274 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 275 return 0; 276 } 277 EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_enable); 278 279 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt) 280 { 281 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 282 283 /* set dat_miso_loopback off */ 284 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 285 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 286 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 287 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 288 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 289 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 290 291 mt6358_set_topck(priv, false); 292 mt6358_set_clksq(priv, false); 293 mt6358_set_aud_global_bias(priv, false); 294 mt6358_set_dcxo(priv, false); 295 296 mt6358_mtkaif_tx_disable(priv); 297 playback_gpio_reset(priv); 298 capture_gpio_reset(priv); 299 return 0; 300 } 301 EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_disable); 302 303 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt, 304 int phase_1, int phase_2) 305 { 306 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 307 308 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 309 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT, 310 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT); 311 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 312 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT, 313 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT); 314 return 0; 315 } 316 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_calibration_phase); 317 318 /* dl pga gain */ 319 enum { 320 DL_GAIN_8DB = 0, 321 DL_GAIN_0DB = 8, 322 DL_GAIN_N_1DB = 9, 323 DL_GAIN_N_10DB = 18, 324 DL_GAIN_N_40DB = 0x1f, 325 }; 326 327 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB) 328 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB) 329 #define DL_GAIN_REG_MASK 0x0f9f 330 331 static void hp_zcd_disable(struct mt6358_priv *priv) 332 { 333 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); 334 } 335 336 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up) 337 { 338 int i, stage; 339 int target = 7; 340 341 /* Enable/Reduce HPL/R main output stage step by step */ 342 for (i = 0; i <= target; i++) { 343 stage = up ? i : target - i; 344 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 345 0x7 << 8, stage << 8); 346 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 347 0x7 << 11, stage << 11); 348 usleep_range(100, 150); 349 } 350 } 351 352 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up) 353 { 354 int i, stage; 355 356 /* Reduce HP aux feedback loop gain step by step */ 357 for (i = 0; i <= 0xf; i++) { 358 stage = up ? i : 0xf - i; 359 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 360 0xf << 12, stage << 12); 361 usleep_range(100, 150); 362 } 363 } 364 365 static void hp_pull_down(struct mt6358_priv *priv, bool enable) 366 { 367 int i; 368 369 if (enable) { 370 for (i = 0x0; i <= 0x6; i++) { 371 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 372 0x7, i); 373 usleep_range(600, 700); 374 } 375 } else { 376 for (i = 0x6; i >= 0x1; i--) { 377 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 378 0x7, i); 379 usleep_range(600, 700); 380 } 381 } 382 } 383 384 static bool is_valid_hp_pga_idx(int reg_idx) 385 { 386 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) || 387 reg_idx == DL_GAIN_N_40DB; 388 } 389 390 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to) 391 { 392 int offset = 0, count = 0, reg_idx; 393 394 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) 395 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", 396 __func__, from, to); 397 398 dev_info(priv->dev, "%s(), from %d, to %d\n", 399 __func__, from, to); 400 401 if (to > from) 402 offset = to - from; 403 else 404 offset = from - to; 405 406 while (offset >= 0) { 407 if (to > from) 408 reg_idx = from + count; 409 else 410 reg_idx = from - count; 411 412 if (is_valid_hp_pga_idx(reg_idx)) { 413 regmap_update_bits(priv->regmap, 414 MT6358_ZCD_CON2, 415 DL_GAIN_REG_MASK, 416 (reg_idx << 7) | reg_idx); 417 usleep_range(200, 300); 418 } 419 offset--; 420 count++; 421 } 422 } 423 424 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol, 425 struct snd_ctl_elem_value *ucontrol) 426 { 427 struct snd_soc_component *component = 428 snd_soc_kcontrol_component(kcontrol); 429 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component); 430 struct soc_mixer_control *mc = 431 (struct soc_mixer_control *)kcontrol->private_value; 432 unsigned int reg; 433 int ret; 434 435 ret = snd_soc_put_volsw(kcontrol, ucontrol); 436 if (ret < 0) 437 return ret; 438 439 switch (mc->reg) { 440 case MT6358_ZCD_CON2: 441 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); 442 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 443 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; 444 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 445 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; 446 break; 447 case MT6358_ZCD_CON1: 448 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); 449 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 450 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; 451 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 452 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; 453 break; 454 case MT6358_ZCD_CON3: 455 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®); 456 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = 457 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 458 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] = 459 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 460 break; 461 case MT6358_AUDENC_ANA_CON0: 462 case MT6358_AUDENC_ANA_CON1: 463 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®); 464 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 465 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK; 466 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®); 467 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 468 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK; 469 break; 470 } 471 472 return ret; 473 } 474 475 static void mt6358_restore_pga(struct mt6358_priv *priv); 476 477 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv) 478 { 479 /* analog */ 480 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 481 0xffff, 0x0000); 482 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 483 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 484 0xffff, 0x0800); 485 mt6358_restore_pga(priv); 486 487 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); 488 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 489 0xffff, 0x0025); 490 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 491 0xffff, 0x0005); 492 493 /* digital */ 494 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 495 0xffff, 0x0000); 496 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); 497 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); 498 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); 499 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); 500 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); 501 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); 502 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); 503 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 504 0xffff, 0x0000); 505 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 506 0xffff, 0x0451); 507 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); 508 509 return 0; 510 } 511 512 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv) 513 { 514 /* digital */ 515 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); 516 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 517 0xffff, 0x0450); 518 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 519 0xffff, 0x0c00); 520 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); 521 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); 522 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); 523 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); 524 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); 525 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); 526 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); 527 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 528 0xffff, 0x0000); 529 530 /* analog */ 531 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 532 0xffff, 0x0004); 533 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 534 0xffff, 0x0000); 535 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); 536 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 537 0xffff, 0x0000); 538 mt6358_restore_pga(priv); 539 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 540 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 541 0xffff, 0x0010); 542 543 return 0; 544 } 545 546 static int mt6358_get_wov(struct snd_kcontrol *kcontrol, 547 struct snd_ctl_elem_value *ucontrol) 548 { 549 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol); 550 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 551 552 ucontrol->value.integer.value[0] = priv->wov_enabled; 553 return 0; 554 } 555 556 static int mt6358_put_wov(struct snd_kcontrol *kcontrol, 557 struct snd_ctl_elem_value *ucontrol) 558 { 559 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol); 560 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 561 int enabled = ucontrol->value.integer.value[0]; 562 563 if (priv->wov_enabled != enabled) { 564 if (enabled) 565 mt6358_enable_wov_phase2(priv); 566 else 567 mt6358_disable_wov_phase2(priv); 568 569 priv->wov_enabled = enabled; 570 } 571 572 return 0; 573 } 574 575 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 576 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); 577 578 static const struct snd_kcontrol_new mt6358_snd_controls[] = { 579 /* dl pga gain */ 580 SOC_DOUBLE_EXT_TLV("Headphone Volume", 581 MT6358_ZCD_CON2, 0, 7, 0x12, 1, 582 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 583 SOC_DOUBLE_EXT_TLV("Lineout Volume", 584 MT6358_ZCD_CON1, 0, 7, 0x12, 1, 585 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 586 SOC_SINGLE_EXT_TLV("Handset Volume", 587 MT6358_ZCD_CON3, 0, 0x12, 1, 588 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 589 /* ul pga gain */ 590 SOC_DOUBLE_R_EXT_TLV("PGA Volume", 591 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1, 592 8, 4, 0, 593 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv), 594 595 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0, 596 mt6358_get_wov, mt6358_put_wov), 597 }; 598 599 /* MUX */ 600 /* LOL MUX */ 601 static const char * const lo_in_mux_map[] = { 602 "Open", "Mute", "Playback", "Test Mode" 603 }; 604 605 static int lo_in_mux_map_value[] = { 606 0x0, 0x1, 0x2, 0x3, 607 }; 608 609 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, 610 MT6358_AUDDEC_ANA_CON7, 611 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT, 612 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK, 613 lo_in_mux_map, 614 lo_in_mux_map_value); 615 616 static const struct snd_kcontrol_new lo_in_mux_control = 617 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum); 618 619 /*HP MUX */ 620 enum { 621 HP_MUX_OPEN = 0, 622 HP_MUX_HPSPK, 623 HP_MUX_HP, 624 HP_MUX_TEST_MODE, 625 HP_MUX_HP_IMPEDANCE, 626 HP_MUX_MASK = 0x7, 627 }; 628 629 static const char * const hp_in_mux_map[] = { 630 "Open", 631 "LoudSPK Playback", 632 "Audio Playback", 633 "Test Mode", 634 "HP Impedance", 635 "undefined1", 636 "undefined2", 637 "undefined3", 638 }; 639 640 static int hp_in_mux_map_value[] = { 641 HP_MUX_OPEN, 642 HP_MUX_HPSPK, 643 HP_MUX_HP, 644 HP_MUX_TEST_MODE, 645 HP_MUX_HP_IMPEDANCE, 646 HP_MUX_OPEN, 647 HP_MUX_OPEN, 648 HP_MUX_OPEN, 649 }; 650 651 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, 652 SND_SOC_NOPM, 653 0, 654 HP_MUX_MASK, 655 hp_in_mux_map, 656 hp_in_mux_map_value); 657 658 static const struct snd_kcontrol_new hpl_in_mux_control = 659 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum); 660 661 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, 662 SND_SOC_NOPM, 663 0, 664 HP_MUX_MASK, 665 hp_in_mux_map, 666 hp_in_mux_map_value); 667 668 static const struct snd_kcontrol_new hpr_in_mux_control = 669 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum); 670 671 /* RCV MUX */ 672 enum { 673 RCV_MUX_OPEN = 0, 674 RCV_MUX_MUTE, 675 RCV_MUX_VOICE_PLAYBACK, 676 RCV_MUX_TEST_MODE, 677 RCV_MUX_MASK = 0x3, 678 }; 679 680 static const char * const rcv_in_mux_map[] = { 681 "Open", "Mute", "Voice Playback", "Test Mode" 682 }; 683 684 static int rcv_in_mux_map_value[] = { 685 RCV_MUX_OPEN, 686 RCV_MUX_MUTE, 687 RCV_MUX_VOICE_PLAYBACK, 688 RCV_MUX_TEST_MODE, 689 }; 690 691 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 692 SND_SOC_NOPM, 693 0, 694 RCV_MUX_MASK, 695 rcv_in_mux_map, 696 rcv_in_mux_map_value); 697 698 static const struct snd_kcontrol_new rcv_in_mux_control = 699 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 700 701 /* DAC In MUX */ 702 static const char * const dac_in_mux_map[] = { 703 "Normal Path", "Sgen" 704 }; 705 706 static int dac_in_mux_map_value[] = { 707 0x0, 0x1, 708 }; 709 710 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 711 MT6358_AFE_TOP_CON0, 712 DL_SINE_ON_SFT, 713 DL_SINE_ON_MASK, 714 dac_in_mux_map, 715 dac_in_mux_map_value); 716 717 static const struct snd_kcontrol_new dac_in_mux_control = 718 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 719 720 /* AIF Out MUX */ 721 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 722 MT6358_AFE_TOP_CON0, 723 UL_SINE_ON_SFT, 724 UL_SINE_ON_MASK, 725 dac_in_mux_map, 726 dac_in_mux_map_value); 727 728 static const struct snd_kcontrol_new aif_out_mux_control = 729 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 730 731 /* Mic Type MUX */ 732 enum { 733 MIC_TYPE_MUX_IDLE = 0, 734 MIC_TYPE_MUX_ACC, 735 MIC_TYPE_MUX_DMIC, 736 MIC_TYPE_MUX_DCC, 737 MIC_TYPE_MUX_DCC_ECM_DIFF, 738 MIC_TYPE_MUX_DCC_ECM_SINGLE, 739 MIC_TYPE_MUX_MASK = 0x7, 740 }; 741 742 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \ 743 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \ 744 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE) 745 746 static const char * const mic_type_mux_map[] = { 747 "Idle", 748 "ACC", 749 "DMIC", 750 "DCC", 751 "DCC_ECM_DIFF", 752 "DCC_ECM_SINGLE", 753 }; 754 755 static int mic_type_mux_map_value[] = { 756 MIC_TYPE_MUX_IDLE, 757 MIC_TYPE_MUX_ACC, 758 MIC_TYPE_MUX_DMIC, 759 MIC_TYPE_MUX_DCC, 760 MIC_TYPE_MUX_DCC_ECM_DIFF, 761 MIC_TYPE_MUX_DCC_ECM_SINGLE, 762 }; 763 764 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum, 765 SND_SOC_NOPM, 766 0, 767 MIC_TYPE_MUX_MASK, 768 mic_type_mux_map, 769 mic_type_mux_map_value); 770 771 static const struct snd_kcontrol_new mic_type_mux_control = 772 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum); 773 774 /* ADC L MUX */ 775 enum { 776 ADC_MUX_IDLE = 0, 777 ADC_MUX_AIN0, 778 ADC_MUX_PREAMPLIFIER, 779 ADC_MUX_IDLE1, 780 ADC_MUX_MASK = 0x3, 781 }; 782 783 static const char * const adc_left_mux_map[] = { 784 "Idle", "AIN0", "Left Preamplifier", "Idle_1" 785 }; 786 787 static int adc_mux_map_value[] = { 788 ADC_MUX_IDLE, 789 ADC_MUX_AIN0, 790 ADC_MUX_PREAMPLIFIER, 791 ADC_MUX_IDLE1, 792 }; 793 794 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 795 SND_SOC_NOPM, 796 0, 797 ADC_MUX_MASK, 798 adc_left_mux_map, 799 adc_mux_map_value); 800 801 static const struct snd_kcontrol_new adc_left_mux_control = 802 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 803 804 /* ADC R MUX */ 805 static const char * const adc_right_mux_map[] = { 806 "Idle", "AIN0", "Right Preamplifier", "Idle_1" 807 }; 808 809 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 810 SND_SOC_NOPM, 811 0, 812 ADC_MUX_MASK, 813 adc_right_mux_map, 814 adc_mux_map_value); 815 816 static const struct snd_kcontrol_new adc_right_mux_control = 817 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 818 819 /* PGA L MUX */ 820 enum { 821 PGA_MUX_NONE = 0, 822 PGA_MUX_AIN0, 823 PGA_MUX_AIN1, 824 PGA_MUX_AIN2, 825 PGA_MUX_MASK = 0x3, 826 }; 827 828 static const char * const pga_mux_map[] = { 829 "None", "AIN0", "AIN1", "AIN2" 830 }; 831 832 static int pga_mux_map_value[] = { 833 PGA_MUX_NONE, 834 PGA_MUX_AIN0, 835 PGA_MUX_AIN1, 836 PGA_MUX_AIN2, 837 }; 838 839 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 840 SND_SOC_NOPM, 841 0, 842 PGA_MUX_MASK, 843 pga_mux_map, 844 pga_mux_map_value); 845 846 static const struct snd_kcontrol_new pga_left_mux_control = 847 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 848 849 /* PGA R MUX */ 850 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 851 SND_SOC_NOPM, 852 0, 853 PGA_MUX_MASK, 854 pga_mux_map, 855 pga_mux_map_value); 856 857 static const struct snd_kcontrol_new pga_right_mux_control = 858 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 859 860 static int mt_clksq_event(struct snd_soc_dapm_widget *w, 861 struct snd_kcontrol *kcontrol, 862 int event) 863 { 864 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 865 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 866 867 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 868 869 switch (event) { 870 case SND_SOC_DAPM_PRE_PMU: 871 /* audio clk source from internal dcxo */ 872 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 873 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 874 0x0); 875 break; 876 default: 877 break; 878 } 879 880 return 0; 881 } 882 883 static int mt_sgen_event(struct snd_soc_dapm_widget *w, 884 struct snd_kcontrol *kcontrol, 885 int event) 886 { 887 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 888 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 889 890 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 891 892 switch (event) { 893 case SND_SOC_DAPM_PRE_PMU: 894 /* sdm audio fifo clock power on */ 895 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 896 /* scrambler clock on enable */ 897 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 898 /* sdm power on */ 899 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 900 /* sdm fifo enable */ 901 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 902 903 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0, 904 0xff3f, 905 0x0000); 906 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1, 907 0xffff, 908 0x0001); 909 break; 910 case SND_SOC_DAPM_POST_PMD: 911 /* DL scrambler disabling sequence */ 912 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 913 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 914 break; 915 default: 916 break; 917 } 918 919 return 0; 920 } 921 922 static int mt_aif_in_event(struct snd_soc_dapm_widget *w, 923 struct snd_kcontrol *kcontrol, 924 int event) 925 { 926 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 927 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 928 929 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", 930 __func__, event, priv->dl_rate); 931 932 switch (event) { 933 case SND_SOC_DAPM_PRE_PMU: 934 playback_gpio_set(priv); 935 936 /* sdm audio fifo clock power on */ 937 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 938 /* scrambler clock on enable */ 939 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 940 /* sdm power on */ 941 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 942 /* sdm fifo enable */ 943 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 944 break; 945 case SND_SOC_DAPM_POST_PMD: 946 /* DL scrambler disabling sequence */ 947 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 948 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 949 950 playback_gpio_reset(priv); 951 break; 952 default: 953 break; 954 } 955 956 return 0; 957 } 958 959 static int mtk_hp_enable(struct mt6358_priv *priv) 960 { 961 /* Pull-down HPL/R to AVSS28_AUD */ 962 hp_pull_down(priv, true); 963 /* release HP CMFB gate rstb */ 964 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 965 0x1 << 6, 0x1 << 6); 966 967 /* Reduce ESD resistance of AU_REFN */ 968 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 969 970 /* Set HPR/HPL gain as minimum (~ -40dB) */ 971 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG); 972 973 /* Turn on DA_600K_NCP_VA18 */ 974 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 975 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 976 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 977 /* Toggle RG_DIVCKS_CHG */ 978 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 979 /* Set NCP soft start mode as default mode: 100us */ 980 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 981 /* Enable NCP */ 982 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 983 usleep_range(250, 270); 984 985 /* Enable cap-less LDOs (1.5V) */ 986 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 987 0x1055, 0x1055); 988 /* Enable NV regulator (-1.2V) */ 989 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 990 usleep_range(100, 120); 991 992 /* Disable AUD_ZCD */ 993 hp_zcd_disable(priv); 994 995 /* Disable headphone short-circuit protection */ 996 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 997 998 /* Enable IBIST */ 999 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1000 1001 /* Set HP DR bias current optimization, 010: 6uA */ 1002 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1003 /* Set HP & ZCD bias current optimization */ 1004 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1005 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1006 /* Set HPP/N STB enhance circuits */ 1007 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 1008 1009 /* Enable HP aux output stage */ 1010 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); 1011 /* Enable HP aux feedback loop */ 1012 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); 1013 /* Enable HP aux CMFB loop */ 1014 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 1015 /* Enable HP driver bias circuits */ 1016 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 1017 /* Enable HP driver core circuits */ 1018 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 1019 /* Short HP main output to HP aux output stage */ 1020 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); 1021 1022 /* Enable HP main CMFB loop */ 1023 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 1024 /* Disable HP aux CMFB loop */ 1025 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 1026 1027 /* Select CMFB resistor bulk to AC mode */ 1028 /* Selec HS/LO cap size (6.5pF default) */ 1029 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1030 1031 /* Enable HP main output stage */ 1032 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); 1033 /* Enable HPR/L main output stage step by step */ 1034 hp_main_output_ramp(priv, true); 1035 1036 /* Reduce HP aux feedback loop gain */ 1037 hp_aux_feedback_loop_gain_ramp(priv, true); 1038 /* Disable HP aux feedback loop */ 1039 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1040 1041 /* apply volume setting */ 1042 headset_volume_ramp(priv, 1043 DL_GAIN_N_10DB, 1044 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 1045 1046 /* Disable HP aux output stage */ 1047 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1048 /* Unshort HP main output to HP aux output stage */ 1049 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); 1050 usleep_range(100, 120); 1051 1052 /* Enable AUD_CLK */ 1053 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 1054 /* Enable Audio DAC */ 1055 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); 1056 /* Enable low-noise mode of DAC */ 1057 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); 1058 usleep_range(100, 120); 1059 1060 /* Switch HPL MUX to audio DAC */ 1061 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); 1062 /* Switch HPR MUX to audio DAC */ 1063 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); 1064 1065 /* Disable Pull-down HPL/R to AVSS28_AUD */ 1066 hp_pull_down(priv, false); 1067 1068 return 0; 1069 } 1070 1071 static int mtk_hp_disable(struct mt6358_priv *priv) 1072 { 1073 /* Pull-down HPL/R to AVSS28_AUD */ 1074 hp_pull_down(priv, true); 1075 1076 /* HPR/HPL mux to open */ 1077 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1078 0x0f00, 0x0000); 1079 1080 /* Disable low-noise mode of DAC */ 1081 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1082 0x0001, 0x0000); 1083 1084 /* Disable Audio DAC */ 1085 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1086 0x000f, 0x0000); 1087 1088 /* Disable AUD_CLK */ 1089 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1090 1091 /* Short HP main output to HP aux output stage */ 1092 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1093 /* Enable HP aux output stage */ 1094 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1095 1096 /* decrease HPL/R gain to normal gain step by step */ 1097 headset_volume_ramp(priv, 1098 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1099 DL_GAIN_N_40DB); 1100 1101 /* Enable HP aux feedback loop */ 1102 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1103 1104 /* Reduce HP aux feedback loop gain */ 1105 hp_aux_feedback_loop_gain_ramp(priv, false); 1106 1107 /* decrease HPR/L main output stage step by step */ 1108 hp_main_output_ramp(priv, false); 1109 1110 /* Disable HP main output stage */ 1111 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1112 1113 /* Enable HP aux CMFB loop */ 1114 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 1115 1116 /* Disable HP main CMFB loop */ 1117 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 1118 1119 /* Unshort HP main output to HP aux output stage */ 1120 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1121 0x3 << 6, 0x0); 1122 1123 /* Disable HP driver core circuits */ 1124 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1125 0x3 << 4, 0x0); 1126 1127 /* Disable HP driver bias circuits */ 1128 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1129 0x3 << 6, 0x0); 1130 1131 /* Disable HP aux CMFB loop */ 1132 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1133 1134 /* Disable HP aux feedback loop */ 1135 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1136 0x3 << 4, 0x0); 1137 1138 /* Disable HP aux output stage */ 1139 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1140 0x3 << 2, 0x0); 1141 1142 /* Disable IBIST */ 1143 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1144 0x1 << 8, 0x1 << 8); 1145 1146 /* Disable NV regulator (-1.2V) */ 1147 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1148 /* Disable cap-less LDOs (1.5V) */ 1149 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1150 0x1055, 0x0); 1151 /* Disable NCP */ 1152 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1153 0x1, 0x1); 1154 1155 /* Increase ESD resistance of AU_REFN */ 1156 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2, 1157 0x1 << 14, 0x0); 1158 1159 /* Set HP CMFB gate rstb */ 1160 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1161 0x1 << 6, 0x0); 1162 /* disable Pull-down HPL/R to AVSS28_AUD */ 1163 hp_pull_down(priv, false); 1164 1165 return 0; 1166 } 1167 1168 static int mtk_hp_spk_enable(struct mt6358_priv *priv) 1169 { 1170 /* Pull-down HPL/R to AVSS28_AUD */ 1171 hp_pull_down(priv, true); 1172 /* release HP CMFB gate rstb */ 1173 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1174 0x1 << 6, 0x1 << 6); 1175 1176 /* Reduce ESD resistance of AU_REFN */ 1177 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1178 1179 /* Set HPR/HPL gain to -10dB */ 1180 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG); 1181 1182 /* Turn on DA_600K_NCP_VA18 */ 1183 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1184 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1185 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1186 /* Toggle RG_DIVCKS_CHG */ 1187 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1188 /* Set NCP soft start mode as default mode: 100us */ 1189 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1190 /* Enable NCP */ 1191 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1192 usleep_range(250, 270); 1193 1194 /* Enable cap-less LDOs (1.5V) */ 1195 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1196 0x1055, 0x1055); 1197 /* Enable NV regulator (-1.2V) */ 1198 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1199 usleep_range(100, 120); 1200 1201 /* Disable AUD_ZCD */ 1202 hp_zcd_disable(priv); 1203 1204 /* Disable headphone short-circuit protection */ 1205 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 1206 1207 /* Enable IBIST */ 1208 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1209 1210 /* Set HP DR bias current optimization, 010: 6uA */ 1211 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1212 /* Set HP & ZCD bias current optimization */ 1213 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1214 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1215 /* Set HPP/N STB enhance circuits */ 1216 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 1217 1218 /* Disable Pull-down HPL/R to AVSS28_AUD */ 1219 hp_pull_down(priv, false); 1220 1221 /* Enable HP driver bias circuits */ 1222 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 1223 /* Enable HP driver core circuits */ 1224 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 1225 /* Enable HP main CMFB loop */ 1226 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 1227 1228 /* Select CMFB resistor bulk to AC mode */ 1229 /* Selec HS/LO cap size (6.5pF default) */ 1230 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1231 1232 /* Enable HP main output stage */ 1233 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); 1234 /* Enable HPR/L main output stage step by step */ 1235 hp_main_output_ramp(priv, true); 1236 1237 /* Set LO gain as minimum (~ -40dB) */ 1238 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG); 1239 /* apply volume setting */ 1240 headset_volume_ramp(priv, 1241 DL_GAIN_N_10DB, 1242 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 1243 1244 /* Set LO STB enhance circuits */ 1245 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); 1246 /* Enable LO driver bias circuits */ 1247 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); 1248 /* Enable LO driver core circuits */ 1249 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); 1250 1251 /* Set LOL gain to normal gain step by step */ 1252 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1253 RG_AUDLOLGAIN_MASK_SFT, 1254 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] << 1255 RG_AUDLOLGAIN_SFT); 1256 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1257 RG_AUDLORGAIN_MASK_SFT, 1258 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] << 1259 RG_AUDLORGAIN_SFT); 1260 1261 /* Enable AUD_CLK */ 1262 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 1263 /* Enable Audio DAC */ 1264 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); 1265 /* Enable low-noise mode of DAC */ 1266 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); 1267 /* Switch LOL MUX to audio DAC */ 1268 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); 1269 /* Switch HPL/R MUX to Line-out */ 1270 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); 1271 1272 return 0; 1273 } 1274 1275 static int mtk_hp_spk_disable(struct mt6358_priv *priv) 1276 { 1277 /* HPR/HPL mux to open */ 1278 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1279 0x0f00, 0x0000); 1280 /* LOL mux to open */ 1281 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1282 0x3 << 2, 0x0000); 1283 1284 /* Disable Audio DAC */ 1285 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1286 0x000f, 0x0000); 1287 1288 /* Disable AUD_CLK */ 1289 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1290 1291 /* decrease HPL/R gain to normal gain step by step */ 1292 headset_volume_ramp(priv, 1293 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1294 DL_GAIN_N_40DB); 1295 1296 /* decrease LOL gain to minimum gain step by step */ 1297 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1298 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG); 1299 1300 /* decrease HPR/L main output stage step by step */ 1301 hp_main_output_ramp(priv, false); 1302 1303 /* Disable HP main output stage */ 1304 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1305 1306 /* Short HP main output to HP aux output stage */ 1307 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1308 /* Enable HP aux output stage */ 1309 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1310 1311 /* Enable HP aux feedback loop */ 1312 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1313 1314 /* Reduce HP aux feedback loop gain */ 1315 hp_aux_feedback_loop_gain_ramp(priv, false); 1316 1317 /* Disable HP driver core circuits */ 1318 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1319 0x3 << 4, 0x0); 1320 /* Disable LO driver core circuits */ 1321 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1322 0x1, 0x0); 1323 1324 /* Disable HP driver bias circuits */ 1325 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1326 0x3 << 6, 0x0); 1327 /* Disable LO driver bias circuits */ 1328 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1329 0x1 << 1, 0x0); 1330 1331 /* Disable HP aux CMFB loop */ 1332 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1333 0xff << 8, 0x0000); 1334 1335 /* Disable IBIST */ 1336 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1337 0x1 << 8, 0x1 << 8); 1338 /* Disable NV regulator (-1.2V) */ 1339 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1340 /* Disable cap-less LDOs (1.5V) */ 1341 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); 1342 /* Disable NCP */ 1343 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); 1344 1345 /* Set HP CMFB gate rstb */ 1346 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1347 0x1 << 6, 0x0); 1348 /* disable Pull-down HPL/R to AVSS28_AUD */ 1349 hp_pull_down(priv, false); 1350 1351 return 0; 1352 } 1353 1354 static int mt_hp_event(struct snd_soc_dapm_widget *w, 1355 struct snd_kcontrol *kcontrol, 1356 int event) 1357 { 1358 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1359 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1360 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1361 int device = DEVICE_HP; 1362 1363 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", 1364 __func__, 1365 event, 1366 priv->dev_counter[device], 1367 mux); 1368 1369 switch (event) { 1370 case SND_SOC_DAPM_PRE_PMU: 1371 priv->dev_counter[device]++; 1372 if (priv->dev_counter[device] > 1) 1373 break; /* already enabled, do nothing */ 1374 else if (priv->dev_counter[device] <= 0) 1375 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", 1376 __func__, 1377 priv->dev_counter[device]); 1378 1379 priv->mux_select[MUX_HP_L] = mux; 1380 1381 if (mux == HP_MUX_HP) 1382 mtk_hp_enable(priv); 1383 else if (mux == HP_MUX_HPSPK) 1384 mtk_hp_spk_enable(priv); 1385 break; 1386 case SND_SOC_DAPM_PRE_PMD: 1387 priv->dev_counter[device]--; 1388 if (priv->dev_counter[device] > 0) { 1389 break; /* still being used, don't close */ 1390 } else if (priv->dev_counter[device] < 0) { 1391 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", 1392 __func__, 1393 priv->dev_counter[device]); 1394 priv->dev_counter[device] = 0; 1395 break; 1396 } 1397 1398 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP) 1399 mtk_hp_disable(priv); 1400 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK) 1401 mtk_hp_spk_disable(priv); 1402 1403 priv->mux_select[MUX_HP_L] = mux; 1404 break; 1405 default: 1406 break; 1407 } 1408 1409 return 0; 1410 } 1411 1412 static int mt_rcv_event(struct snd_soc_dapm_widget *w, 1413 struct snd_kcontrol *kcontrol, 1414 int event) 1415 { 1416 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1417 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1418 1419 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", 1420 __func__, 1421 event, 1422 dapm_kcontrol_get_value(w->kcontrols[0])); 1423 1424 switch (event) { 1425 case SND_SOC_DAPM_PRE_PMU: 1426 /* Reduce ESD resistance of AU_REFN */ 1427 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1428 1429 /* Turn on DA_600K_NCP_VA18 */ 1430 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1431 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1432 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1433 /* Toggle RG_DIVCKS_CHG */ 1434 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1435 /* Set NCP soft start mode as default mode: 100us */ 1436 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1437 /* Enable NCP */ 1438 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1439 usleep_range(250, 270); 1440 1441 /* Enable cap-less LDOs (1.5V) */ 1442 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1443 0x1055, 0x1055); 1444 /* Enable NV regulator (-1.2V) */ 1445 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1446 usleep_range(100, 120); 1447 1448 /* Disable AUD_ZCD */ 1449 hp_zcd_disable(priv); 1450 1451 /* Disable handset short-circuit protection */ 1452 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); 1453 1454 /* Enable IBIST */ 1455 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1456 /* Set HP DR bias current optimization, 010: 6uA */ 1457 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1458 /* Set HP & ZCD bias current optimization */ 1459 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1460 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1461 /* Set HS STB enhance circuits */ 1462 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); 1463 1464 /* Disable HP main CMFB loop */ 1465 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1466 /* Select CMFB resistor bulk to AC mode */ 1467 /* Selec HS/LO cap size (6.5pF default) */ 1468 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1469 1470 /* Enable HS driver bias circuits */ 1471 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); 1472 /* Enable HS driver core circuits */ 1473 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); 1474 1475 /* Enable AUD_CLK */ 1476 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1477 0x1, 0x1); 1478 1479 /* Enable Audio DAC */ 1480 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); 1481 /* Enable low-noise mode of DAC */ 1482 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); 1483 /* Switch HS MUX to audio DAC */ 1484 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); 1485 break; 1486 case SND_SOC_DAPM_PRE_PMD: 1487 /* HS mux to open */ 1488 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1489 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT, 1490 RCV_MUX_OPEN); 1491 1492 /* Disable Audio DAC */ 1493 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1494 0x000f, 0x0000); 1495 1496 /* Disable AUD_CLK */ 1497 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1498 0x1, 0x0); 1499 1500 /* decrease HS gain to minimum gain step by step */ 1501 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB); 1502 1503 /* Disable HS driver core circuits */ 1504 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1505 0x1, 0x0); 1506 1507 /* Disable HS driver bias circuits */ 1508 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1509 0x1 << 1, 0x0000); 1510 1511 /* Disable HP aux CMFB loop */ 1512 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1513 0xff << 8, 0x0); 1514 1515 /* Enable HP main CMFB Switch */ 1516 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1517 0xff << 8, 0x2 << 8); 1518 1519 /* Disable IBIST */ 1520 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1521 0x1 << 8, 0x1 << 8); 1522 1523 /* Disable NV regulator (-1.2V) */ 1524 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 1525 0x1, 0x0); 1526 /* Disable cap-less LDOs (1.5V) */ 1527 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1528 0x1055, 0x0); 1529 /* Disable NCP */ 1530 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1531 0x1, 0x1); 1532 break; 1533 default: 1534 break; 1535 } 1536 1537 return 0; 1538 } 1539 1540 static int mt_aif_out_event(struct snd_soc_dapm_widget *w, 1541 struct snd_kcontrol *kcontrol, 1542 int event) 1543 { 1544 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1545 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1546 1547 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", 1548 __func__, event, priv->ul_rate); 1549 1550 switch (event) { 1551 case SND_SOC_DAPM_PRE_PMU: 1552 capture_gpio_set(priv); 1553 break; 1554 case SND_SOC_DAPM_POST_PMD: 1555 capture_gpio_reset(priv); 1556 break; 1557 default: 1558 break; 1559 } 1560 1561 return 0; 1562 } 1563 1564 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w, 1565 struct snd_kcontrol *kcontrol, 1566 int event) 1567 { 1568 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1569 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1570 1571 dev_dbg(priv->dev, "%s(), event 0x%x\n", 1572 __func__, event); 1573 1574 switch (event) { 1575 case SND_SOC_DAPM_PRE_PMU: 1576 /* Enable audio ADC CLKGEN */ 1577 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1578 0x1 << 5, 0x1 << 5); 1579 /* ADC CLK from CLKGEN (13MHz) */ 1580 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 1581 0x0000); 1582 /* Enable LCLDO_ENC 1P8V */ 1583 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1584 0x2500, 0x0100); 1585 /* LCLDO_ENC remote sense */ 1586 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1587 0x2500, 0x2500); 1588 break; 1589 case SND_SOC_DAPM_POST_PMD: 1590 /* LCLDO_ENC remote sense off */ 1591 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1592 0x2500, 0x0100); 1593 /* disable LCLDO_ENC 1P8V */ 1594 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1595 0x2500, 0x0000); 1596 1597 /* ADC CLK from CLKGEN (13MHz) */ 1598 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); 1599 /* disable audio ADC CLKGEN */ 1600 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1601 0x1 << 5, 0x0 << 5); 1602 break; 1603 default: 1604 break; 1605 } 1606 1607 return 0; 1608 } 1609 1610 static int mt6358_amic_enable(struct mt6358_priv *priv) 1611 { 1612 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1613 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1614 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1615 1616 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1617 __func__, mic_type, mux_pga_l, mux_pga_r); 1618 1619 if (IS_DCC_BASE(mic_type)) { 1620 /* DCC 50k CLK (from 26M) */ 1621 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1622 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1623 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1624 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); 1625 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); 1626 } 1627 1628 /* mic bias 0 */ 1629 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 || 1630 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) { 1631 switch (mic_type) { 1632 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1633 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1634 0xff00, 0x7700); 1635 break; 1636 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1637 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1638 0xff00, 0x1100); 1639 break; 1640 default: 1641 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1642 0xff00, 0x0000); 1643 break; 1644 } 1645 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1646 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1647 0xff, 0x21); 1648 } 1649 1650 /* mic bias 1 */ 1651 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) { 1652 /* Enable MICBIAS1, MISBIAS1 = 2P6V */ 1653 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE) 1654 regmap_write(priv->regmap, 1655 MT6358_AUDENC_ANA_CON10, 0x0161); 1656 else 1657 regmap_write(priv->regmap, 1658 MT6358_AUDENC_ANA_CON10, 0x0061); 1659 } 1660 1661 if (IS_DCC_BASE(mic_type)) { 1662 /* Audio L/R preamplifier DCC precharge */ 1663 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1664 0xf8ff, 0x0004); 1665 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1666 0xf8ff, 0x0004); 1667 } else { 1668 /* reset reg */ 1669 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1670 0xf8ff, 0x0000); 1671 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1672 0xf8ff, 0x0000); 1673 } 1674 1675 if (mux_pga_l != PGA_MUX_NONE) { 1676 /* L preamplifier input sel */ 1677 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1678 RG_AUDPREAMPLINPUTSEL_MASK_SFT, 1679 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT); 1680 1681 /* L preamplifier enable */ 1682 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1683 RG_AUDPREAMPLON_MASK_SFT, 1684 0x1 << RG_AUDPREAMPLON_SFT); 1685 1686 if (IS_DCC_BASE(mic_type)) { 1687 /* L preamplifier DCCEN */ 1688 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1689 RG_AUDPREAMPLDCCEN_MASK_SFT, 1690 0x1 << RG_AUDPREAMPLDCCEN_SFT); 1691 } 1692 1693 /* L ADC input sel : L PGA. Enable audio L ADC */ 1694 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1695 RG_AUDADCLINPUTSEL_MASK_SFT, 1696 ADC_MUX_PREAMPLIFIER << 1697 RG_AUDADCLINPUTSEL_SFT); 1698 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1699 RG_AUDADCLPWRUP_MASK_SFT, 1700 0x1 << RG_AUDADCLPWRUP_SFT); 1701 } 1702 1703 if (mux_pga_r != PGA_MUX_NONE) { 1704 /* R preamplifier input sel */ 1705 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1706 RG_AUDPREAMPRINPUTSEL_MASK_SFT, 1707 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT); 1708 1709 /* R preamplifier enable */ 1710 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1711 RG_AUDPREAMPRON_MASK_SFT, 1712 0x1 << RG_AUDPREAMPRON_SFT); 1713 1714 if (IS_DCC_BASE(mic_type)) { 1715 /* R preamplifier DCCEN */ 1716 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1717 RG_AUDPREAMPRDCCEN_MASK_SFT, 1718 0x1 << RG_AUDPREAMPRDCCEN_SFT); 1719 } 1720 1721 /* R ADC input sel : R PGA. Enable audio R ADC */ 1722 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1723 RG_AUDADCRINPUTSEL_MASK_SFT, 1724 ADC_MUX_PREAMPLIFIER << 1725 RG_AUDADCRINPUTSEL_SFT); 1726 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1727 RG_AUDADCRPWRUP_MASK_SFT, 1728 0x1 << RG_AUDADCRPWRUP_SFT); 1729 } 1730 1731 if (IS_DCC_BASE(mic_type)) { 1732 usleep_range(100, 150); 1733 /* Audio L preamplifier DCC precharge off */ 1734 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1735 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); 1736 /* Audio R preamplifier DCC precharge off */ 1737 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1738 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); 1739 1740 /* Short body to ground in PGA */ 1741 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3, 1742 0x1 << 12, 0x0); 1743 } 1744 1745 /* here to set digital part */ 1746 mt6358_mtkaif_tx_enable(priv); 1747 1748 /* UL dmic setting off */ 1749 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); 1750 1751 /* UL turn on */ 1752 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); 1753 1754 return 0; 1755 } 1756 1757 static void mt6358_amic_disable(struct mt6358_priv *priv) 1758 { 1759 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1760 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1761 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1762 1763 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1764 __func__, mic_type, mux_pga_l, mux_pga_r); 1765 1766 /* UL turn off */ 1767 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1768 0x0001, 0x0000); 1769 1770 /* disable aud_pad TX fifos */ 1771 mt6358_mtkaif_tx_disable(priv); 1772 1773 /* L ADC input sel : off, disable L ADC */ 1774 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1775 0xf000, 0x0000); 1776 /* L preamplifier DCCEN */ 1777 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1778 0x1 << 1, 0x0); 1779 /* L preamplifier input sel : off, L PGA 0 dB gain */ 1780 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1781 0xfffb, 0x0000); 1782 1783 /* disable L preamplifier DCC precharge */ 1784 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1785 0x1 << 2, 0x0); 1786 1787 /* R ADC input sel : off, disable R ADC */ 1788 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1789 0xf000, 0x0000); 1790 /* R preamplifier DCCEN */ 1791 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1792 0x1 << 1, 0x0); 1793 /* R preamplifier input sel : off, R PGA 0 dB gain */ 1794 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1795 0x0ffb, 0x0000); 1796 1797 /* disable R preamplifier DCC precharge */ 1798 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1799 0x1 << 2, 0x0); 1800 1801 /* mic bias */ 1802 /* Disable MICBIAS0, MISBIAS0 = 1P7V */ 1803 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1804 1805 /* Disable MICBIAS1 */ 1806 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1807 0x0001, 0x0000); 1808 1809 if (IS_DCC_BASE(mic_type)) { 1810 /* dcclk_gen_on=1'b0 */ 1811 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1812 /* dcclk_pdn=1'b1 */ 1813 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1814 /* dcclk_ref_ck_sel=2'b00 */ 1815 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1816 /* dcclk_div=11'b00100000011 */ 1817 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1818 } 1819 } 1820 1821 static int mt6358_dmic_enable(struct mt6358_priv *priv) 1822 { 1823 dev_info(priv->dev, "%s()\n", __func__); 1824 1825 /* mic bias */ 1826 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1827 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); 1828 1829 /* RG_BANDGAPGEN=1'b0 */ 1830 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1831 0x1 << 12, 0x0); 1832 1833 /* DMIC enable */ 1834 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); 1835 1836 /* here to set digital part */ 1837 mt6358_mtkaif_tx_enable(priv); 1838 1839 /* UL dmic setting */ 1840 if (priv->dmic_one_wire_mode) 1841 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); 1842 else 1843 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); 1844 1845 /* UL turn on */ 1846 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); 1847 1848 /* Prevent pop noise form dmic hw */ 1849 msleep(100); 1850 1851 return 0; 1852 } 1853 1854 static void mt6358_dmic_disable(struct mt6358_priv *priv) 1855 { 1856 dev_info(priv->dev, "%s()\n", __func__); 1857 1858 /* UL turn off */ 1859 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1860 0x0003, 0x0000); 1861 1862 /* disable aud_pad TX fifos */ 1863 mt6358_mtkaif_tx_disable(priv); 1864 1865 /* DMIC disable */ 1866 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); 1867 1868 /* mic bias */ 1869 /* MISBIAS0 = 1P7V */ 1870 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); 1871 1872 /* RG_BANDGAPGEN=1'b0 */ 1873 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1874 0x1 << 12, 0x0); 1875 1876 /* MICBIA0 disable */ 1877 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1878 } 1879 1880 static void mt6358_restore_pga(struct mt6358_priv *priv) 1881 { 1882 unsigned int gain_l, gain_r; 1883 1884 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 1885 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 1886 1887 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1888 RG_AUDPREAMPLGAIN_MASK_SFT, 1889 gain_l << RG_AUDPREAMPLGAIN_SFT); 1890 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1891 RG_AUDPREAMPRGAIN_MASK_SFT, 1892 gain_r << RG_AUDPREAMPRGAIN_SFT); 1893 } 1894 1895 static int mt_mic_type_event(struct snd_soc_dapm_widget *w, 1896 struct snd_kcontrol *kcontrol, 1897 int event) 1898 { 1899 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1900 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1901 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1902 1903 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 1904 __func__, event, mux); 1905 1906 switch (event) { 1907 case SND_SOC_DAPM_WILL_PMU: 1908 priv->mux_select[MUX_MIC_TYPE] = mux; 1909 break; 1910 case SND_SOC_DAPM_PRE_PMU: 1911 switch (mux) { 1912 case MIC_TYPE_MUX_DMIC: 1913 mt6358_dmic_enable(priv); 1914 break; 1915 default: 1916 mt6358_amic_enable(priv); 1917 break; 1918 } 1919 mt6358_restore_pga(priv); 1920 1921 break; 1922 case SND_SOC_DAPM_POST_PMD: 1923 switch (priv->mux_select[MUX_MIC_TYPE]) { 1924 case MIC_TYPE_MUX_DMIC: 1925 mt6358_dmic_disable(priv); 1926 break; 1927 default: 1928 mt6358_amic_disable(priv); 1929 break; 1930 } 1931 1932 priv->mux_select[MUX_MIC_TYPE] = mux; 1933 break; 1934 default: 1935 break; 1936 } 1937 1938 return 0; 1939 } 1940 1941 static int mt_adc_l_event(struct snd_soc_dapm_widget *w, 1942 struct snd_kcontrol *kcontrol, 1943 int event) 1944 { 1945 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1946 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1947 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1948 1949 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1950 __func__, event, mux); 1951 1952 priv->mux_select[MUX_ADC_L] = mux; 1953 1954 return 0; 1955 } 1956 1957 static int mt_adc_r_event(struct snd_soc_dapm_widget *w, 1958 struct snd_kcontrol *kcontrol, 1959 int event) 1960 { 1961 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1962 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1963 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1964 1965 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1966 __func__, event, mux); 1967 1968 priv->mux_select[MUX_ADC_R] = mux; 1969 1970 return 0; 1971 } 1972 1973 static int mt_pga_left_event(struct snd_soc_dapm_widget *w, 1974 struct snd_kcontrol *kcontrol, 1975 int event) 1976 { 1977 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1978 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1979 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1980 1981 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1982 __func__, event, mux); 1983 1984 priv->mux_select[MUX_PGA_L] = mux; 1985 1986 return 0; 1987 } 1988 1989 static int mt_pga_right_event(struct snd_soc_dapm_widget *w, 1990 struct snd_kcontrol *kcontrol, 1991 int event) 1992 { 1993 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1994 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1995 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1996 1997 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1998 __func__, event, mux); 1999 2000 priv->mux_select[MUX_PGA_R] = mux; 2001 2002 return 0; 2003 } 2004 2005 static int mt_delay_250_event(struct snd_soc_dapm_widget *w, 2006 struct snd_kcontrol *kcontrol, 2007 int event) 2008 { 2009 switch (event) { 2010 case SND_SOC_DAPM_POST_PMU: 2011 usleep_range(250, 270); 2012 break; 2013 case SND_SOC_DAPM_PRE_PMD: 2014 usleep_range(250, 270); 2015 break; 2016 default: 2017 break; 2018 } 2019 2020 return 0; 2021 } 2022 2023 /* DAPM Widgets */ 2024 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = { 2025 /* Global Supply*/ 2026 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF, 2027 MT6358_DCXO_CW14, 2028 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0), 2029 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB, 2030 MT6358_AUDDEC_ANA_CON13, 2031 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0), 2032 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ, 2033 MT6358_AUDENC_ANA_CON6, 2034 RG_CLKSQ_EN_SFT, 0, 2035 mt_clksq_event, 2036 SND_SOC_DAPM_PRE_PMU), 2037 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK, 2038 MT6358_AUD_TOP_CKPDN_CON0, 2039 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0), 2040 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK, 2041 MT6358_AUD_TOP_CKPDN_CON0, 2042 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0), 2043 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, 2044 MT6358_AUD_TOP_CKPDN_CON0, 2045 RG_AUD_CK_PDN_SFT, 1, 2046 mt_delay_250_event, 2047 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2048 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK, 2049 MT6358_AUD_TOP_CKPDN_CON0, 2050 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0), 2051 2052 /* Digital Clock */ 2053 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST, 2054 MT6358_AUDIO_TOP_CON0, 2055 PDN_AFE_CTL_SFT, 1, 2056 mt_delay_250_event, 2057 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2058 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP, 2059 MT6358_AUDIO_TOP_CON0, 2060 PDN_DAC_CTL_SFT, 1, NULL, 0), 2061 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 2062 MT6358_AUDIO_TOP_CON0, 2063 PDN_ADC_CTL_SFT, 1, NULL, 0), 2064 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP, 2065 MT6358_AUDIO_TOP_CON0, 2066 PDN_I2S_DL_CTL_SFT, 1, NULL, 0), 2067 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP, 2068 MT6358_AUDIO_TOP_CON0, 2069 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0), 2070 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP, 2071 MT6358_AUDIO_TOP_CON0, 2072 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0), 2073 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP, 2074 MT6358_AUDIO_TOP_CON0, 2075 PDN_RESERVED_SFT, 1, NULL, 0), 2076 2077 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 2078 0, 0, NULL, 0), 2079 2080 /* AFE ON */ 2081 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE, 2082 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0, 2083 NULL, 0), 2084 2085 /* AIF Rx*/ 2086 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0, 2087 MT6358_AFE_DL_SRC2_CON0_L, 2088 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 2089 mt_aif_in_event, 2090 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2091 2092 /* DL Supply */ 2093 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 2094 0, 0, NULL, 0), 2095 2096 /* DAC */ 2097 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 2098 2099 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 2100 2101 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 2102 2103 /* LOL */ 2104 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control), 2105 2106 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7, 2107 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0), 2108 2109 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7, 2110 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0), 2111 2112 /* Headphone */ 2113 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0, 2114 &hpl_in_mux_control, 2115 mt_hp_event, 2116 SND_SOC_DAPM_PRE_PMU | 2117 SND_SOC_DAPM_PRE_PMD), 2118 2119 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0, 2120 &hpr_in_mux_control, 2121 mt_hp_event, 2122 SND_SOC_DAPM_PRE_PMU | 2123 SND_SOC_DAPM_PRE_PMD), 2124 2125 /* Receiver */ 2126 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0, 2127 &rcv_in_mux_control, 2128 mt_rcv_event, 2129 SND_SOC_DAPM_PRE_PMU | 2130 SND_SOC_DAPM_PRE_PMD), 2131 2132 /* Outputs */ 2133 SND_SOC_DAPM_OUTPUT("Receiver"), 2134 SND_SOC_DAPM_OUTPUT("Headphone L"), 2135 SND_SOC_DAPM_OUTPUT("Headphone R"), 2136 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"), 2137 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"), 2138 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 2139 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"), 2140 2141 /* SGEN */ 2142 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0, 2143 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0), 2144 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0, 2145 SGEN_MUTE_SW_CTL_SFT, 1, 2146 mt_sgen_event, 2147 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2148 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L, 2149 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0), 2150 2151 SND_SOC_DAPM_INPUT("SGEN DL"), 2152 2153 /* Uplinks */ 2154 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0, 2155 SND_SOC_NOPM, 0, 0, 2156 mt_aif_out_event, 2157 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2158 2159 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY, 2160 SND_SOC_NOPM, 0, 0, 2161 mt_adc_supply_event, 2162 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2163 2164 /* Uplinks MUX */ 2165 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 2166 &aif_out_mux_control), 2167 2168 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0, 2169 &mic_type_mux_control, 2170 mt_mic_type_event, 2171 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD | 2172 SND_SOC_DAPM_WILL_PMU), 2173 2174 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0, 2175 &adc_left_mux_control, 2176 mt_adc_l_event, 2177 SND_SOC_DAPM_WILL_PMU), 2178 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0, 2179 &adc_right_mux_control, 2180 mt_adc_r_event, 2181 SND_SOC_DAPM_WILL_PMU), 2182 2183 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2184 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2185 2186 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0, 2187 &pga_left_mux_control, 2188 mt_pga_left_event, 2189 SND_SOC_DAPM_WILL_PMU), 2190 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0, 2191 &pga_right_mux_control, 2192 mt_pga_right_event, 2193 SND_SOC_DAPM_WILL_PMU), 2194 2195 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0), 2196 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0), 2197 2198 /* UL input */ 2199 SND_SOC_DAPM_INPUT("AIN0"), 2200 SND_SOC_DAPM_INPUT("AIN1"), 2201 SND_SOC_DAPM_INPUT("AIN2"), 2202 }; 2203 2204 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = { 2205 /* Capture */ 2206 {"AIF1TX", NULL, "AIF Out Mux"}, 2207 {"AIF1TX", NULL, "CLK_BUF"}, 2208 {"AIF1TX", NULL, "AUDGLB"}, 2209 {"AIF1TX", NULL, "CLKSQ Audio"}, 2210 2211 {"AIF1TX", NULL, "AUD_CK"}, 2212 {"AIF1TX", NULL, "AUDIF_CK"}, 2213 2214 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}, 2215 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}, 2216 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}, 2217 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2218 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"}, 2219 2220 {"AIF1TX", NULL, "AFE_ON"}, 2221 2222 {"AIF Out Mux", NULL, "Mic Type Mux"}, 2223 2224 {"Mic Type Mux", "ACC", "ADC L"}, 2225 {"Mic Type Mux", "ACC", "ADC R"}, 2226 {"Mic Type Mux", "DCC", "ADC L"}, 2227 {"Mic Type Mux", "DCC", "ADC R"}, 2228 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"}, 2229 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"}, 2230 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"}, 2231 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"}, 2232 {"Mic Type Mux", "DMIC", "AIN0"}, 2233 {"Mic Type Mux", "DMIC", "AIN2"}, 2234 2235 {"ADC L", NULL, "ADC L Mux"}, 2236 {"ADC L", NULL, "ADC Supply"}, 2237 {"ADC R", NULL, "ADC R Mux"}, 2238 {"ADC R", NULL, "ADC Supply"}, 2239 2240 {"ADC L Mux", "Left Preamplifier", "PGA L"}, 2241 2242 {"ADC R Mux", "Right Preamplifier", "PGA R"}, 2243 2244 {"PGA L", NULL, "PGA L Mux"}, 2245 {"PGA R", NULL, "PGA R Mux"}, 2246 2247 {"PGA L Mux", "AIN0", "AIN0"}, 2248 {"PGA L Mux", "AIN1", "AIN1"}, 2249 {"PGA L Mux", "AIN2", "AIN2"}, 2250 2251 {"PGA R Mux", "AIN0", "AIN0"}, 2252 {"PGA R Mux", "AIN1", "AIN1"}, 2253 {"PGA R Mux", "AIN2", "AIN2"}, 2254 2255 /* DL Supply */ 2256 {"DL Power Supply", NULL, "CLK_BUF"}, 2257 {"DL Power Supply", NULL, "AUDGLB"}, 2258 {"DL Power Supply", NULL, "CLKSQ Audio"}, 2259 2260 {"DL Power Supply", NULL, "AUDNCP_CK"}, 2261 {"DL Power Supply", NULL, "ZCD13M_CK"}, 2262 {"DL Power Supply", NULL, "AUD_CK"}, 2263 {"DL Power Supply", NULL, "AUDIF_CK"}, 2264 2265 /* DL Digital Supply */ 2266 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 2267 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 2268 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 2269 2270 {"DL Digital Clock", NULL, "AFE_ON"}, 2271 2272 {"AIF_RX", NULL, "DL Digital Clock"}, 2273 2274 /* DL Path */ 2275 {"DAC In Mux", "Normal Path", "AIF_RX"}, 2276 2277 {"DAC In Mux", "Sgen", "SGEN DL"}, 2278 {"SGEN DL", NULL, "SGEN DL SRC"}, 2279 {"SGEN DL", NULL, "SGEN MUTE"}, 2280 {"SGEN DL", NULL, "SGEN DL Enable"}, 2281 {"SGEN DL", NULL, "DL Digital Clock"}, 2282 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"}, 2283 2284 {"DACL", NULL, "DAC In Mux"}, 2285 {"DACL", NULL, "DL Power Supply"}, 2286 2287 {"DACR", NULL, "DAC In Mux"}, 2288 {"DACR", NULL, "DL Power Supply"}, 2289 2290 /* Lineout Path */ 2291 {"LOL Mux", "Playback", "DACL"}, 2292 2293 {"LOL Buffer", NULL, "LOL Mux"}, 2294 {"LOL Buffer", NULL, "LO Stability Enh"}, 2295 2296 {"LINEOUT L", NULL, "LOL Buffer"}, 2297 2298 /* Headphone Path */ 2299 {"HPL Mux", "Audio Playback", "DACL"}, 2300 {"HPR Mux", "Audio Playback", "DACR"}, 2301 {"HPL Mux", "HP Impedance", "DACL"}, 2302 {"HPR Mux", "HP Impedance", "DACR"}, 2303 {"HPL Mux", "LoudSPK Playback", "DACL"}, 2304 {"HPR Mux", "LoudSPK Playback", "DACR"}, 2305 2306 {"Headphone L", NULL, "HPL Mux"}, 2307 {"Headphone R", NULL, "HPR Mux"}, 2308 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"}, 2309 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"}, 2310 {"LINEOUT L HSSPK", NULL, "HPL Mux"}, 2311 2312 /* Receiver Path */ 2313 {"RCV Mux", "Voice Playback", "DACL"}, 2314 {"Receiver", NULL, "RCV Mux"}, 2315 }; 2316 2317 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream, 2318 struct snd_pcm_hw_params *params, 2319 struct snd_soc_dai *dai) 2320 { 2321 struct snd_soc_component *cmpnt = dai->component; 2322 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2323 unsigned int rate = params_rate(params); 2324 2325 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n", 2326 __func__, 2327 substream->stream, 2328 rate, 2329 substream->number); 2330 2331 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2332 priv->dl_rate = rate; 2333 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2334 priv->ul_rate = rate; 2335 2336 return 0; 2337 } 2338 2339 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = { 2340 .hw_params = mt6358_codec_dai_hw_params, 2341 }; 2342 2343 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\ 2344 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\ 2345 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\ 2346 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\ 2347 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\ 2348 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE) 2349 2350 static struct snd_soc_dai_driver mt6358_dai_driver[] = { 2351 { 2352 .name = "mt6358-snd-codec-aif1", 2353 .playback = { 2354 .stream_name = "AIF1 Playback", 2355 .channels_min = 1, 2356 .channels_max = 2, 2357 .rates = SNDRV_PCM_RATE_8000_48000 | 2358 SNDRV_PCM_RATE_96000 | 2359 SNDRV_PCM_RATE_192000, 2360 .formats = MT6358_FORMATS, 2361 }, 2362 .capture = { 2363 .stream_name = "AIF1 Capture", 2364 .channels_min = 1, 2365 .channels_max = 2, 2366 .rates = SNDRV_PCM_RATE_8000 | 2367 SNDRV_PCM_RATE_16000 | 2368 SNDRV_PCM_RATE_32000 | 2369 SNDRV_PCM_RATE_48000, 2370 .formats = MT6358_FORMATS, 2371 }, 2372 .ops = &mt6358_codec_dai_ops, 2373 }, 2374 }; 2375 2376 static void mt6358_codec_init_reg(struct mt6358_priv *priv) 2377 { 2378 /* Disable HeadphoneL/HeadphoneR short circuit protection */ 2379 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2380 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT, 2381 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); 2382 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2383 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT, 2384 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); 2385 /* Disable voice short circuit protection */ 2386 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 2387 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT, 2388 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); 2389 /* disable LO buffer left short circuit protection */ 2390 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 2391 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT, 2392 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); 2393 2394 /* accdet s/w enable */ 2395 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13, 2396 0xFFFF, 0x700E); 2397 2398 /* gpio miso driving set to 4mA */ 2399 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); 2400 2401 /* set gpio */ 2402 playback_gpio_reset(priv); 2403 capture_gpio_reset(priv); 2404 } 2405 2406 static int mt6358_codec_probe(struct snd_soc_component *cmpnt) 2407 { 2408 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2409 int ret; 2410 2411 snd_soc_component_init_regmap(cmpnt, priv->regmap); 2412 2413 mt6358_codec_init_reg(priv); 2414 2415 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd"); 2416 if (IS_ERR(priv->avdd_reg)) { 2417 dev_err(priv->dev, "%s() have no Avdd supply", __func__); 2418 return PTR_ERR(priv->avdd_reg); 2419 } 2420 2421 ret = regulator_enable(priv->avdd_reg); 2422 if (ret) 2423 return ret; 2424 2425 return 0; 2426 } 2427 2428 static const struct snd_soc_component_driver mt6358_soc_component_driver = { 2429 .probe = mt6358_codec_probe, 2430 .controls = mt6358_snd_controls, 2431 .num_controls = ARRAY_SIZE(mt6358_snd_controls), 2432 .dapm_widgets = mt6358_dapm_widgets, 2433 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets), 2434 .dapm_routes = mt6358_dapm_routes, 2435 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes), 2436 }; 2437 2438 static void mt6358_parse_dt(struct mt6358_priv *priv) 2439 { 2440 int ret; 2441 struct device *dev = priv->dev; 2442 2443 ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode", 2444 &priv->dmic_one_wire_mode); 2445 if (ret) { 2446 dev_warn(priv->dev, "%s() failed to read dmic-mode\n", 2447 __func__); 2448 priv->dmic_one_wire_mode = 0; 2449 } 2450 } 2451 2452 static int mt6358_platform_driver_probe(struct platform_device *pdev) 2453 { 2454 struct mt6358_priv *priv; 2455 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 2456 2457 priv = devm_kzalloc(&pdev->dev, 2458 sizeof(struct mt6358_priv), 2459 GFP_KERNEL); 2460 if (!priv) 2461 return -ENOMEM; 2462 2463 dev_set_drvdata(&pdev->dev, priv); 2464 2465 priv->dev = &pdev->dev; 2466 2467 priv->regmap = mt6397->regmap; 2468 if (IS_ERR(priv->regmap)) 2469 return PTR_ERR(priv->regmap); 2470 2471 mt6358_parse_dt(priv); 2472 2473 dev_info(priv->dev, "%s(), dev name %s\n", 2474 __func__, dev_name(&pdev->dev)); 2475 2476 return devm_snd_soc_register_component(&pdev->dev, 2477 &mt6358_soc_component_driver, 2478 mt6358_dai_driver, 2479 ARRAY_SIZE(mt6358_dai_driver)); 2480 } 2481 2482 static const struct of_device_id mt6358_of_match[] = { 2483 {.compatible = "mediatek,mt6358-sound",}, 2484 {} 2485 }; 2486 MODULE_DEVICE_TABLE(of, mt6358_of_match); 2487 2488 static struct platform_driver mt6358_platform_driver = { 2489 .driver = { 2490 .name = "mt6358-sound", 2491 .of_match_table = mt6358_of_match, 2492 }, 2493 .probe = mt6358_platform_driver_probe, 2494 }; 2495 2496 module_platform_driver(mt6358_platform_driver) 2497 2498 /* Module information */ 2499 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver"); 2500 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 2501 MODULE_LICENSE("GPL v2"); 2502