1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mt6351.c -- mt6351 ALSA SoC audio codec driver 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/dma-mapping.h> 9 #include <linux/platform_device.h> 10 #include <linux/slab.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 14 #include <sound/core.h> 15 #include <sound/pcm.h> 16 #include <sound/soc.h> 17 #include <sound/tlv.h> 18 19 #include "mt6351.h" 20 21 /* MT6351_TOP_CLKSQ */ 22 #define RG_CLKSQ_EN_AUD_BIT (0) 23 24 /* MT6351_TOP_CKPDN_CON0 */ 25 #define RG_AUDNCP_CK_PDN_BIT (12) 26 #define RG_AUDIF_CK_PDN_BIT (13) 27 #define RG_AUD_CK_PDN_BIT (14) 28 #define RG_ZCD13M_CK_PDN_BIT (15) 29 30 /* MT6351_AUDDEC_ANA_CON0 */ 31 #define RG_AUDDACLPWRUP_VAUDP32_BIT (0) 32 #define RG_AUDDACRPWRUP_VAUDP32_BIT (1) 33 #define RG_AUD_DAC_PWR_UP_VA32_BIT (2) 34 #define RG_AUD_DAC_PWL_UP_VA32_BIT (3) 35 36 #define RG_AUDHSPWRUP_VAUDP32_BIT (4) 37 38 #define RG_AUDHPLPWRUP_VAUDP32_BIT (5) 39 #define RG_AUDHPRPWRUP_VAUDP32_BIT (6) 40 41 #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT (7) 42 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3) 43 44 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT (9) 45 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3) 46 47 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT (11) 48 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3) 49 50 #define RG_AUDHSSCDISABLE_VAUDP32 (13) 51 #define RG_AUDHPLSCDISABLE_VAUDP32_BIT (14) 52 #define RG_AUDHPRSCDISABLE_VAUDP32_BIT (15) 53 54 /* MT6351_AUDDEC_ANA_CON1 */ 55 #define RG_HSOUTPUTSTBENH_VAUDP32_BIT (8) 56 57 /* MT6351_AUDDEC_ANA_CON3 */ 58 #define RG_AUDLOLPWRUP_VAUDP32_BIT (2) 59 60 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT (3) 61 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3) 62 63 #define RG_AUDLOLSCDISABLE_VAUDP32_BIT (5) 64 #define RG_LOOUTPUTSTBENH_VAUDP32_BIT (9) 65 66 /* MT6351_AUDDEC_ANA_CON6 */ 67 #define RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT (8) 68 #define RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT (9) 69 #define RG_ABIDEC_RSVD0_VAUDP32_HS_BIT (10) 70 #define RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT (11) 71 72 /* MT6351_AUDDEC_ANA_CON9 */ 73 #define RG_AUDIBIASPWRDN_VAUDP32_BIT (8) 74 #define RG_RSTB_DECODER_VA32_BIT (9) 75 #define RG_AUDGLB_PWRDN_VA32_BIT (12) 76 77 #define RG_LCLDO_DEC_EN_VA32_BIT (13) 78 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT (15) 79 /* MT6351_AUDDEC_ANA_CON10 */ 80 #define RG_NVREG_EN_VAUDP32_BIT (8) 81 82 #define RG_AUDGLB_LP2_VOW_EN_VA32 10 83 84 /* MT6351_AFE_UL_DL_CON0 */ 85 #define RG_AFE_ON_BIT (0) 86 87 /* MT6351_AFE_DL_SRC2_CON0_L */ 88 #define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0) 89 90 /* MT6351_AFE_UL_SRC_CON0_L */ 91 #define UL_SRC_ON_TMP_CTL (0) 92 93 /* MT6351_AFE_TOP_CON0 */ 94 #define RG_DL_SINE_ON_SFT (0) 95 #define RG_DL_SINE_ON_MASK (0x1) 96 97 #define RG_UL_SINE_ON_SFT (1) 98 #define RG_UL_SINE_ON_MASK (0x1) 99 100 /* MT6351_AUDIO_TOP_CON0 */ 101 #define AUD_TOP_PDN_RESERVED_BIT 0 102 #define AUD_TOP_PWR_CLK_DIS_CTL_BIT 2 103 #define AUD_TOP_PDN_ADC_CTL_BIT 5 104 #define AUD_TOP_PDN_DAC_CTL_BIT 6 105 #define AUD_TOP_PDN_AFE_CTL_BIT 7 106 107 /* MT6351_AFE_SGEN_CFG0 */ 108 #define SGEN_C_MUTE_SW_CTL_BIT 6 109 #define SGEN_C_DAC_EN_CTL_BIT 7 110 111 /* MT6351_AFE_NCP_CFG0 */ 112 #define RG_NCP_ON_BIT 0 113 114 /* MT6351_LDO_VUSB33_CON0 */ 115 #define RG_VUSB33_EN 1 116 #define RG_VUSB33_ON_CTRL 3 117 118 /* MT6351_LDO_VA18_CON0 */ 119 #define RG_VA18_EN 1 120 #define RG_VA18_ON_CTRL 3 121 122 /* MT6351_AUDENC_ANA_CON0 */ 123 #define RG_AUDPREAMPLON 0 124 #define RG_AUDPREAMPLDCCEN 1 125 #define RG_AUDPREAMPLDCPRECHARGE 2 126 127 #define RG_AUDPREAMPLINPUTSEL_SFT (4) 128 #define RG_AUDPREAMPLINPUTSEL_MASK (0x3) 129 130 #define RG_AUDADCLPWRUP 12 131 132 #define RG_AUDADCLINPUTSEL_SFT (13) 133 #define RG_AUDADCLINPUTSEL_MASK (0x3) 134 135 /* MT6351_AUDENC_ANA_CON1 */ 136 #define RG_AUDPREAMPRON 0 137 #define RG_AUDPREAMPRDCCEN 1 138 #define RG_AUDPREAMPRDCPRECHARGE 2 139 140 #define RG_AUDPREAMPRINPUTSEL_SFT (4) 141 #define RG_AUDPREAMPRINPUTSEL_MASK (0x3) 142 143 #define RG_AUDADCRPWRUP 12 144 145 #define RG_AUDADCRINPUTSEL_SFT (13) 146 #define RG_AUDADCRINPUTSEL_MASK (0x3) 147 148 /* MT6351_AUDENC_ANA_CON3 */ 149 #define RG_AUDADCCLKRSTB 6 150 151 /* MT6351_AUDENC_ANA_CON9 */ 152 #define RG_AUDPWDBMICBIAS0 0 153 #define RG_AUDMICBIAS0VREF 4 154 #define RG_AUDMICBIAS0LOWPEN 7 155 156 #define RG_AUDPWDBMICBIAS2 8 157 #define RG_AUDMICBIAS2VREF 12 158 #define RG_AUDMICBIAS2LOWPEN 15 159 160 /* MT6351_AUDENC_ANA_CON10 */ 161 #define RG_AUDPWDBMICBIAS1 0 162 #define RG_AUDMICBIAS1DCSW1NEN 2 163 #define RG_AUDMICBIAS1VREF 4 164 #define RG_AUDMICBIAS1LOWPEN 7 165 166 enum { 167 AUDIO_ANALOG_VOLUME_HSOUTL, 168 AUDIO_ANALOG_VOLUME_HSOUTR, 169 AUDIO_ANALOG_VOLUME_HPOUTL, 170 AUDIO_ANALOG_VOLUME_HPOUTR, 171 AUDIO_ANALOG_VOLUME_LINEOUTL, 172 AUDIO_ANALOG_VOLUME_LINEOUTR, 173 AUDIO_ANALOG_VOLUME_MICAMP1, 174 AUDIO_ANALOG_VOLUME_MICAMP2, 175 AUDIO_ANALOG_VOLUME_TYPE_MAX 176 }; 177 178 /* Supply subseq */ 179 enum { 180 SUPPLY_SUBSEQ_SETTING, 181 SUPPLY_SUBSEQ_ENABLE, 182 SUPPLY_SUBSEQ_MICBIAS, 183 }; 184 185 #define REG_STRIDE 2 186 187 struct mt6351_priv { 188 struct device *dev; 189 struct regmap *regmap; 190 191 unsigned int dl_rate; 192 unsigned int ul_rate; 193 194 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; 195 196 int hp_en_counter; 197 }; 198 199 static void set_hp_gain_zero(struct snd_soc_component *cmpnt) 200 { 201 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, 202 0x1f << 7, 0x8 << 7); 203 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, 204 0x1f << 0, 0x8 << 0); 205 } 206 207 static unsigned int get_cap_reg_val(struct snd_soc_component *cmpnt, 208 unsigned int rate) 209 { 210 switch (rate) { 211 case 8000: 212 return 0; 213 case 16000: 214 return 1; 215 case 32000: 216 return 2; 217 case 48000: 218 return 3; 219 case 96000: 220 return 4; 221 case 192000: 222 return 5; 223 default: 224 dev_warn(cmpnt->dev, "%s(), error rate %d, return 3", 225 __func__, rate); 226 return 3; 227 } 228 } 229 230 static unsigned int get_play_reg_val(struct snd_soc_component *cmpnt, 231 unsigned int rate) 232 { 233 switch (rate) { 234 case 8000: 235 return 0; 236 case 11025: 237 return 1; 238 case 12000: 239 return 2; 240 case 16000: 241 return 3; 242 case 22050: 243 return 4; 244 case 24000: 245 return 5; 246 case 32000: 247 return 6; 248 case 44100: 249 return 7; 250 case 48000: 251 case 96000: 252 case 192000: 253 return 8; 254 default: 255 dev_warn(cmpnt->dev, "%s(), error rate %d, return 8", 256 __func__, rate); 257 return 8; 258 } 259 } 260 261 static int mt6351_codec_dai_hw_params(struct snd_pcm_substream *substream, 262 struct snd_pcm_hw_params *params, 263 struct snd_soc_dai *dai) 264 { 265 struct snd_soc_component *cmpnt = dai->component; 266 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); 267 unsigned int rate = params_rate(params); 268 269 dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n", 270 __func__, substream->stream, rate); 271 272 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 273 priv->dl_rate = rate; 274 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 275 priv->ul_rate = rate; 276 277 return 0; 278 } 279 280 static const struct snd_soc_dai_ops mt6351_codec_dai_ops = { 281 .hw_params = mt6351_codec_dai_hw_params, 282 }; 283 284 #define MT6351_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\ 285 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\ 286 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE) 287 288 static struct snd_soc_dai_driver mt6351_dai_driver[] = { 289 { 290 .name = "mt6351-snd-codec-aif1", 291 .playback = { 292 .stream_name = "AIF1 Playback", 293 .channels_min = 1, 294 .channels_max = 2, 295 .rates = SNDRV_PCM_RATE_8000_48000 | 296 SNDRV_PCM_RATE_96000 | 297 SNDRV_PCM_RATE_192000, 298 .formats = MT6351_FORMATS, 299 }, 300 .capture = { 301 .stream_name = "AIF1 Capture", 302 .channels_min = 1, 303 .channels_max = 2, 304 .rates = SNDRV_PCM_RATE_8000 | 305 SNDRV_PCM_RATE_16000 | 306 SNDRV_PCM_RATE_32000 | 307 SNDRV_PCM_RATE_48000 | 308 SNDRV_PCM_RATE_96000 | 309 SNDRV_PCM_RATE_192000, 310 .formats = MT6351_FORMATS, 311 }, 312 .ops = &mt6351_codec_dai_ops, 313 }, 314 }; 315 316 enum { 317 HP_GAIN_SET_ZERO, 318 HP_GAIN_RESTORE, 319 }; 320 321 static void hp_gain_ramp_set(struct snd_soc_component *cmpnt, int hp_gain_ctl) 322 { 323 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); 324 int idx, old_idx, offset, reg_idx; 325 326 if (hp_gain_ctl == HP_GAIN_SET_ZERO) { 327 idx = 8; /* 0dB */ 328 old_idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; 329 } else { 330 idx = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; 331 old_idx = 8; /* 0dB */ 332 } 333 dev_dbg(priv->dev, "%s(), idx %d, old_idx %d\n", 334 __func__, idx, old_idx); 335 336 if (idx > old_idx) 337 offset = idx - old_idx; 338 else 339 offset = old_idx - idx; 340 341 reg_idx = old_idx; 342 343 while (offset > 0) { 344 reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1; 345 346 /* check valid range, and set value */ 347 if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) { 348 regmap_update_bits(cmpnt->regmap, 349 MT6351_ZCD_CON2, 350 0xf9f, 351 (reg_idx << 7) | reg_idx); 352 usleep_range(100, 120); 353 } 354 offset--; 355 } 356 } 357 358 static void hp_zcd_enable(struct snd_soc_component *cmpnt) 359 { 360 /* Enable ZCD, for minimize pop noise */ 361 /* when adjust gain during HP buffer on */ 362 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8); 363 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7); 364 365 /* timeout, 1=5ms, 0=30ms */ 366 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6); 367 368 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4); 369 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1); 370 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0); 371 } 372 373 static void hp_zcd_disable(struct snd_soc_component *cmpnt) 374 { 375 regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000); 376 } 377 378 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 379 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); 380 381 static const struct snd_kcontrol_new mt6351_snd_controls[] = { 382 /* dl pga gain */ 383 SOC_DOUBLE_TLV("Headphone Volume", 384 MT6351_ZCD_CON2, 0, 7, 0x12, 1, 385 playback_tlv), 386 SOC_DOUBLE_TLV("Lineout Volume", 387 MT6351_ZCD_CON1, 0, 7, 0x12, 1, 388 playback_tlv), 389 SOC_SINGLE_TLV("Handset Volume", 390 MT6351_ZCD_CON3, 0, 0x12, 1, 391 playback_tlv), 392 /* ul pga gain */ 393 SOC_DOUBLE_R_TLV("PGA Volume", 394 MT6351_AUDENC_ANA_CON0, MT6351_AUDENC_ANA_CON1, 395 8, 4, 0, 396 pga_tlv), 397 }; 398 399 /* MUX */ 400 401 /* LOL MUX */ 402 static const char *const lo_in_mux_map[] = { 403 "Open", "Mute", "Playback", "Test Mode", 404 }; 405 406 static int lo_in_mux_map_value[] = { 407 0x0, 0x1, 0x2, 0x3, 408 }; 409 410 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, 411 MT6351_AUDDEC_ANA_CON3, 412 RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT, 413 RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK, 414 lo_in_mux_map, 415 lo_in_mux_map_value); 416 417 static const struct snd_kcontrol_new lo_in_mux_control = 418 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum); 419 420 /*HP MUX */ 421 static const char *const hp_in_mux_map[] = { 422 "Open", "LoudSPK Playback", "Audio Playback", "Test Mode", 423 }; 424 425 static int hp_in_mux_map_value[] = { 426 0x0, 0x1, 0x2, 0x3, 427 }; 428 429 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, 430 MT6351_AUDDEC_ANA_CON0, 431 RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT, 432 RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK, 433 hp_in_mux_map, 434 hp_in_mux_map_value); 435 436 static const struct snd_kcontrol_new hpl_in_mux_control = 437 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum); 438 439 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, 440 MT6351_AUDDEC_ANA_CON0, 441 RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT, 442 RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK, 443 hp_in_mux_map, 444 hp_in_mux_map_value); 445 446 static const struct snd_kcontrol_new hpr_in_mux_control = 447 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum); 448 449 /* RCV MUX */ 450 static const char *const rcv_in_mux_map[] = { 451 "Open", "Mute", "Voice Playback", "Test Mode", 452 }; 453 454 static int rcv_in_mux_map_value[] = { 455 0x0, 0x1, 0x2, 0x3, 456 }; 457 458 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 459 MT6351_AUDDEC_ANA_CON0, 460 RG_AUDHSMUXINPUTSEL_VAUDP32_SFT, 461 RG_AUDHSMUXINPUTSEL_VAUDP32_MASK, 462 rcv_in_mux_map, 463 rcv_in_mux_map_value); 464 465 static const struct snd_kcontrol_new rcv_in_mux_control = 466 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 467 468 /* DAC In MUX */ 469 static const char *const dac_in_mux_map[] = { 470 "Normal Path", "Sgen", 471 }; 472 473 static int dac_in_mux_map_value[] = { 474 0x0, 0x1, 475 }; 476 477 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 478 MT6351_AFE_TOP_CON0, 479 RG_DL_SINE_ON_SFT, 480 RG_DL_SINE_ON_MASK, 481 dac_in_mux_map, 482 dac_in_mux_map_value); 483 484 static const struct snd_kcontrol_new dac_in_mux_control = 485 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 486 487 /* AIF Out MUX */ 488 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 489 MT6351_AFE_TOP_CON0, 490 RG_UL_SINE_ON_SFT, 491 RG_UL_SINE_ON_MASK, 492 dac_in_mux_map, 493 dac_in_mux_map_value); 494 495 static const struct snd_kcontrol_new aif_out_mux_control = 496 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 497 498 /* ADC L MUX */ 499 static const char *const adc_left_mux_map[] = { 500 "Idle", "AIN0", "Left Preamplifier", "Idle_1", 501 }; 502 503 static int adc_left_mux_map_value[] = { 504 0x0, 0x1, 0x2, 0x3, 505 }; 506 507 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 508 MT6351_AUDENC_ANA_CON0, 509 RG_AUDADCLINPUTSEL_SFT, 510 RG_AUDADCLINPUTSEL_MASK, 511 adc_left_mux_map, 512 adc_left_mux_map_value); 513 514 static const struct snd_kcontrol_new adc_left_mux_control = 515 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 516 517 /* ADC R MUX */ 518 static const char *const adc_right_mux_map[] = { 519 "Idle", "AIN0", "Right Preamplifier", "Idle_1", 520 }; 521 522 static int adc_right_mux_map_value[] = { 523 0x0, 0x1, 0x2, 0x3, 524 }; 525 526 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 527 MT6351_AUDENC_ANA_CON1, 528 RG_AUDADCRINPUTSEL_SFT, 529 RG_AUDADCRINPUTSEL_MASK, 530 adc_right_mux_map, 531 adc_right_mux_map_value); 532 533 static const struct snd_kcontrol_new adc_right_mux_control = 534 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 535 536 /* PGA L MUX */ 537 static const char *const pga_left_mux_map[] = { 538 "None", "AIN0", "AIN1", "AIN2", 539 }; 540 541 static int pga_left_mux_map_value[] = { 542 0x0, 0x1, 0x2, 0x3, 543 }; 544 545 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 546 MT6351_AUDENC_ANA_CON0, 547 RG_AUDPREAMPLINPUTSEL_SFT, 548 RG_AUDPREAMPLINPUTSEL_MASK, 549 pga_left_mux_map, 550 pga_left_mux_map_value); 551 552 static const struct snd_kcontrol_new pga_left_mux_control = 553 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 554 555 /* PGA R MUX */ 556 static const char *const pga_right_mux_map[] = { 557 "None", "AIN0", "AIN3", "AIN2", 558 }; 559 560 static int pga_right_mux_map_value[] = { 561 0x0, 0x1, 0x2, 0x3, 562 }; 563 564 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 565 MT6351_AUDENC_ANA_CON1, 566 RG_AUDPREAMPRINPUTSEL_SFT, 567 RG_AUDPREAMPRINPUTSEL_MASK, 568 pga_right_mux_map, 569 pga_right_mux_map_value); 570 571 static const struct snd_kcontrol_new pga_right_mux_control = 572 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 573 574 static int mt_reg_set_clr_event(struct snd_soc_dapm_widget *w, 575 struct snd_kcontrol *kcontrol, 576 int event) 577 { 578 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 579 580 switch (event) { 581 case SND_SOC_DAPM_POST_PMU: 582 if (w->on_val) { 583 /* SET REG */ 584 regmap_update_bits(cmpnt->regmap, 585 w->reg + REG_STRIDE, 586 0x1 << w->shift, 587 0x1 << w->shift); 588 } else { 589 /* CLR REG */ 590 regmap_update_bits(cmpnt->regmap, 591 w->reg + REG_STRIDE * 2, 592 0x1 << w->shift, 593 0x1 << w->shift); 594 } 595 break; 596 case SND_SOC_DAPM_PRE_PMD: 597 if (w->off_val) { 598 /* SET REG */ 599 regmap_update_bits(cmpnt->regmap, 600 w->reg + REG_STRIDE, 601 0x1 << w->shift, 602 0x1 << w->shift); 603 } else { 604 /* CLR REG */ 605 regmap_update_bits(cmpnt->regmap, 606 w->reg + REG_STRIDE * 2, 607 0x1 << w->shift, 608 0x1 << w->shift); 609 } 610 break; 611 default: 612 break; 613 } 614 615 return 0; 616 } 617 618 static int mt_ncp_event(struct snd_soc_dapm_widget *w, 619 struct snd_kcontrol *kcontrol, 620 int event) 621 { 622 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 623 624 switch (event) { 625 case SND_SOC_DAPM_PRE_PMU: 626 regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG1, 627 0xffff, 0x1515); 628 /* NCP: ck1 and ck2 clock frequecy adjust configure */ 629 regmap_update_bits(cmpnt->regmap, MT6351_AFE_NCP_CFG0, 630 0xfffe, 0x8C00); 631 break; 632 case SND_SOC_DAPM_POST_PMU: 633 usleep_range(250, 270); 634 break; 635 default: 636 break; 637 } 638 639 return 0; 640 } 641 642 static int mt_sgen_event(struct snd_soc_dapm_widget *w, 643 struct snd_kcontrol *kcontrol, 644 int event) 645 { 646 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 647 648 switch (event) { 649 case SND_SOC_DAPM_PRE_PMU: 650 regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG0, 651 0xffef, 0x0008); 652 regmap_update_bits(cmpnt->regmap, MT6351_AFE_SGEN_CFG1, 653 0xffff, 0x0101); 654 break; 655 default: 656 break; 657 } 658 659 return 0; 660 } 661 662 static int mt_aif_in_event(struct snd_soc_dapm_widget *w, 663 struct snd_kcontrol *kcontrol, 664 int event) 665 { 666 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 667 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); 668 669 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", 670 __func__, event, priv->dl_rate); 671 672 switch (event) { 673 case SND_SOC_DAPM_PRE_PMU: 674 /* sdm audio fifo clock power on */ 675 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2, 676 0xffff, 0x0006); 677 /* scrambler clock on enable */ 678 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON0, 679 0xffff, 0xC3A1); 680 /* sdm power on */ 681 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2, 682 0xffff, 0x0003); 683 /* sdm fifo enable */ 684 regmap_update_bits(cmpnt->regmap, MT6351_AFUNC_AUD_CON2, 685 0xffff, 0x000B); 686 /* set attenuation gain */ 687 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DL_SDM_CON1, 688 0xffff, 0x001E); 689 690 regmap_write(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG0, 691 (get_play_reg_val(cmpnt, priv->dl_rate) << 12) | 692 0x330); 693 regmap_write(cmpnt->regmap, MT6351_AFE_DL_SRC2_CON0_H, 694 (get_play_reg_val(cmpnt, priv->dl_rate) << 12) | 695 0x300); 696 697 regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2, 698 0x8000, 0x8000); 699 break; 700 default: 701 break; 702 } 703 704 return 0; 705 } 706 707 static int mt_hp_event(struct snd_soc_dapm_widget *w, 708 struct snd_kcontrol *kcontrol, 709 int event) 710 { 711 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 712 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); 713 int reg; 714 715 dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n", 716 __func__, event, priv->hp_en_counter); 717 718 switch (event) { 719 case SND_SOC_DAPM_PRE_PMU: 720 priv->hp_en_counter++; 721 if (priv->hp_en_counter > 1) 722 break; /* already enabled, do nothing */ 723 else if (priv->hp_en_counter <= 0) 724 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", 725 __func__, 726 priv->hp_en_counter); 727 728 hp_zcd_disable(cmpnt); 729 730 /* from yoyo HQA script */ 731 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6, 732 0x0700, 0x0700); 733 734 /* save target gain to restore after hardware open complete */ 735 regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, ®); 736 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f; 737 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f; 738 739 /* Set HPR/HPL gain as minimum (~ -40dB) */ 740 regmap_update_bits(cmpnt->regmap, 741 MT6351_ZCD_CON2, 0xffff, 0x0F9F); 742 /* Set HS gain as minimum (~ -40dB) */ 743 regmap_update_bits(cmpnt->regmap, 744 MT6351_ZCD_CON3, 0xffff, 0x001F); 745 /* De_OSC of HP */ 746 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON2, 747 0x0001, 0x0001); 748 /* enable output STBENH */ 749 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, 750 0xffff, 0x2000); 751 /* De_OSC of voice, enable output STBENH */ 752 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, 753 0xffff, 0x2100); 754 /* Enable voice driver */ 755 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0, 756 0x0010, 0xE090); 757 /* Enable pre-charge buffer */ 758 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, 759 0xffff, 0x2140); 760 761 usleep_range(50, 60); 762 763 /* Apply digital DC compensation value to DAC */ 764 set_hp_gain_zero(cmpnt); 765 766 /* Enable HPR/HPL */ 767 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, 768 0xffff, 0x2100); 769 /* Disable pre-charge buffer */ 770 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON1, 771 0xffff, 0x2000); 772 /* Disable De_OSC of voice */ 773 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0, 774 0x0010, 0xF4EF); 775 /* Disable voice buffer */ 776 777 /* from yoyo HQ */ 778 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON6, 779 0x0700, 0x0300); 780 781 /* Enable ZCD, for minimize pop noise */ 782 /* when adjust gain during HP buffer on */ 783 hp_zcd_enable(cmpnt); 784 785 /* apply volume setting */ 786 hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE); 787 788 break; 789 case SND_SOC_DAPM_PRE_PMD: 790 priv->hp_en_counter--; 791 if (priv->hp_en_counter > 0) 792 break; /* still being used, don't close */ 793 else if (priv->hp_en_counter < 0) 794 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", 795 __func__, 796 priv->hp_en_counter); 797 798 /* Disable AUD_ZCD */ 799 hp_zcd_disable(cmpnt); 800 801 /* Set HPR/HPL gain as -1dB, step by step */ 802 hp_gain_ramp_set(cmpnt, HP_GAIN_SET_ZERO); 803 804 set_hp_gain_zero(cmpnt); 805 break; 806 case SND_SOC_DAPM_POST_PMD: 807 if (priv->hp_en_counter > 0) 808 break; /* still being used, don't close */ 809 else if (priv->hp_en_counter < 0) 810 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", 811 __func__, 812 priv->hp_en_counter); 813 814 /* reset*/ 815 regmap_update_bits(cmpnt->regmap, 816 MT6351_AUDDEC_ANA_CON6, 817 0x0700, 818 0x0000); 819 /* De_OSC of HP */ 820 regmap_update_bits(cmpnt->regmap, 821 MT6351_AUDDEC_ANA_CON2, 822 0x0001, 823 0x0000); 824 825 /* apply volume setting */ 826 hp_gain_ramp_set(cmpnt, HP_GAIN_RESTORE); 827 break; 828 default: 829 break; 830 } 831 832 return 0; 833 } 834 835 static int mt_aif_out_event(struct snd_soc_dapm_widget *w, 836 struct snd_kcontrol *kcontrol, 837 int event) 838 { 839 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 840 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); 841 842 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", 843 __func__, event, priv->ul_rate); 844 845 switch (event) { 846 case SND_SOC_DAPM_PRE_PMU: 847 /* dcclk_div=11'b00100000011, dcclk_ref_ck_sel=2'b00 */ 848 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0, 849 0xffff, 0x2062); 850 /* dcclk_pdn=1'b0 */ 851 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0, 852 0xffff, 0x2060); 853 /* dcclk_gen_on=1'b1 */ 854 regmap_update_bits(cmpnt->regmap, MT6351_AFE_DCCLK_CFG0, 855 0xffff, 0x2061); 856 857 /* UL sample rate and mode configure */ 858 regmap_update_bits(cmpnt->regmap, MT6351_AFE_UL_SRC_CON0_H, 859 0x000E, 860 get_cap_reg_val(cmpnt, priv->ul_rate) << 1); 861 862 /* fixed 260k path for 8/16/32/48 */ 863 if (priv->ul_rate <= 48000) { 864 /* anc ul path src on */ 865 regmap_update_bits(cmpnt->regmap, 866 MT6351_AFE_HPANC_CFG0, 867 0x1 << 1, 868 0x1 << 1); 869 /* ANC clk pdn release */ 870 regmap_update_bits(cmpnt->regmap, 871 MT6351_AFE_HPANC_CFG0, 872 0x1 << 0, 873 0x0 << 0); 874 } 875 break; 876 case SND_SOC_DAPM_PRE_PMD: 877 /* fixed 260k path for 8/16/32/48 */ 878 if (priv->ul_rate <= 48000) { 879 /* anc ul path src on */ 880 regmap_update_bits(cmpnt->regmap, 881 MT6351_AFE_HPANC_CFG0, 882 0x1 << 1, 883 0x0 << 1); 884 /* ANC clk pdn release */ 885 regmap_update_bits(cmpnt->regmap, 886 MT6351_AFE_HPANC_CFG0, 887 0x1 << 0, 888 0x1 << 0); 889 } 890 break; 891 default: 892 break; 893 } 894 895 return 0; 896 } 897 898 static int mt_adc_clkgen_event(struct snd_soc_dapm_widget *w, 899 struct snd_kcontrol *kcontrol, 900 int event) 901 { 902 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 903 904 switch (event) { 905 case SND_SOC_DAPM_PRE_PMU: 906 /* Audio ADC clock gen. mode: 00_divided by 2 (Normal) */ 907 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3, 908 0x3 << 4, 0x0); 909 break; 910 case SND_SOC_DAPM_POST_PMU: 911 /* ADC CLK from: 00_13MHz from CLKSQ (Default) */ 912 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON3, 913 0x3 << 2, 0x0); 914 break; 915 default: 916 break; 917 } 918 return 0; 919 } 920 921 static int mt_pga_left_event(struct snd_soc_dapm_widget *w, 922 struct snd_kcontrol *kcontrol, 923 int event) 924 { 925 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 926 927 switch (event) { 928 case SND_SOC_DAPM_PRE_PMU: 929 /* Audio L PGA precharge on */ 930 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0, 931 0x3 << RG_AUDPREAMPLDCPRECHARGE, 932 0x1 << RG_AUDPREAMPLDCPRECHARGE); 933 /* Audio L PGA mode: 1_DCC */ 934 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0, 935 0x3 << RG_AUDPREAMPLDCCEN, 936 0x1 << RG_AUDPREAMPLDCCEN); 937 break; 938 case SND_SOC_DAPM_POST_PMU: 939 usleep_range(100, 120); 940 /* Audio L PGA precharge off */ 941 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON0, 942 0x3 << RG_AUDPREAMPLDCPRECHARGE, 943 0x0 << RG_AUDPREAMPLDCPRECHARGE); 944 break; 945 default: 946 break; 947 } 948 return 0; 949 } 950 951 static int mt_pga_right_event(struct snd_soc_dapm_widget *w, 952 struct snd_kcontrol *kcontrol, 953 int event) 954 { 955 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 956 957 switch (event) { 958 case SND_SOC_DAPM_PRE_PMU: 959 /* Audio R PGA precharge on */ 960 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1, 961 0x3 << RG_AUDPREAMPRDCPRECHARGE, 962 0x1 << RG_AUDPREAMPRDCPRECHARGE); 963 /* Audio R PGA mode: 1_DCC */ 964 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1, 965 0x3 << RG_AUDPREAMPRDCCEN, 966 0x1 << RG_AUDPREAMPRDCCEN); 967 break; 968 case SND_SOC_DAPM_POST_PMU: 969 usleep_range(100, 120); 970 /* Audio R PGA precharge off */ 971 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON1, 972 0x3 << RG_AUDPREAMPRDCPRECHARGE, 973 0x0 << RG_AUDPREAMPRDCPRECHARGE); 974 break; 975 default: 976 break; 977 } 978 return 0; 979 } 980 981 static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w, 982 struct snd_kcontrol *kcontrol, 983 int event) 984 { 985 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 986 987 switch (event) { 988 case SND_SOC_DAPM_PRE_PMU: 989 /* MIC Bias 0 LowPower: 0_Normal */ 990 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, 991 0x3 << RG_AUDMICBIAS0LOWPEN, 0x0); 992 /* MISBIAS0 = 1P9V */ 993 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, 994 0x7 << RG_AUDMICBIAS0VREF, 995 0x2 << RG_AUDMICBIAS0VREF); 996 break; 997 case SND_SOC_DAPM_POST_PMD: 998 /* MISBIAS0 = 1P97 */ 999 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, 1000 0x7 << RG_AUDMICBIAS0VREF, 1001 0x0 << RG_AUDMICBIAS0VREF); 1002 break; 1003 default: 1004 break; 1005 } 1006 return 0; 1007 } 1008 1009 static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w, 1010 struct snd_kcontrol *kcontrol, 1011 int event) 1012 { 1013 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1014 1015 switch (event) { 1016 case SND_SOC_DAPM_PRE_PMU: 1017 /* MIC Bias 1 LowPower: 0_Normal */ 1018 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10, 1019 0x3 << RG_AUDMICBIAS1LOWPEN, 0x0); 1020 /* MISBIAS1 = 2P7V */ 1021 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10, 1022 0x7 << RG_AUDMICBIAS1VREF, 1023 0x7 << RG_AUDMICBIAS1VREF); 1024 break; 1025 case SND_SOC_DAPM_POST_PMD: 1026 /* MISBIAS1 = 1P7V */ 1027 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON10, 1028 0x7 << RG_AUDMICBIAS1VREF, 1029 0x0 << RG_AUDMICBIAS1VREF); 1030 break; 1031 default: 1032 break; 1033 } 1034 return 0; 1035 } 1036 1037 static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w, 1038 struct snd_kcontrol *kcontrol, 1039 int event) 1040 { 1041 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1042 1043 switch (event) { 1044 case SND_SOC_DAPM_PRE_PMU: 1045 /* MIC Bias 2 LowPower: 0_Normal */ 1046 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, 1047 0x3 << RG_AUDMICBIAS2LOWPEN, 0x0); 1048 /* MISBIAS2 = 1P9V */ 1049 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, 1050 0x7 << RG_AUDMICBIAS2VREF, 1051 0x2 << RG_AUDMICBIAS2VREF); 1052 break; 1053 case SND_SOC_DAPM_POST_PMD: 1054 /* MISBIAS2 = 1P97 */ 1055 regmap_update_bits(cmpnt->regmap, MT6351_AUDENC_ANA_CON9, 1056 0x7 << RG_AUDMICBIAS2VREF, 1057 0x0 << RG_AUDMICBIAS2VREF); 1058 break; 1059 default: 1060 break; 1061 } 1062 return 0; 1063 } 1064 1065 /* DAPM Widgets */ 1066 static const struct snd_soc_dapm_widget mt6351_dapm_widgets[] = { 1067 /* Digital Clock */ 1068 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_AFE_CTL", MT6351_AUDIO_TOP_CON0, 1069 AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0), 1070 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_DAC_CTL", MT6351_AUDIO_TOP_CON0, 1071 AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0), 1072 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_ADC_CTL", MT6351_AUDIO_TOP_CON0, 1073 AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0), 1074 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PWR_CLK", MT6351_AUDIO_TOP_CON0, 1075 AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0), 1076 SND_SOC_DAPM_SUPPLY("AUDIO_TOP_PDN_RESERVED", MT6351_AUDIO_TOP_CON0, 1077 AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0), 1078 1079 SND_SOC_DAPM_SUPPLY("NCP", MT6351_AFE_NCP_CFG0, 1080 RG_NCP_ON_BIT, 0, 1081 mt_ncp_event, 1082 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1083 1084 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 1085 0, 0, NULL, 0), 1086 1087 /* Global Supply*/ 1088 SND_SOC_DAPM_SUPPLY("AUDGLB", MT6351_AUDDEC_ANA_CON9, 1089 RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0), 1090 SND_SOC_DAPM_SUPPLY("CLKSQ Audio", MT6351_TOP_CLKSQ, 1091 RG_CLKSQ_EN_AUD_BIT, 0, 1092 mt_reg_set_clr_event, 1093 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1094 SND_SOC_DAPM_SUPPLY("ZCD13M_CK", MT6351_TOP_CKPDN_CON0, 1095 RG_ZCD13M_CK_PDN_BIT, 1, 1096 mt_reg_set_clr_event, 1097 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1098 SND_SOC_DAPM_SUPPLY("AUD_CK", MT6351_TOP_CKPDN_CON0, 1099 RG_AUD_CK_PDN_BIT, 1, 1100 mt_reg_set_clr_event, 1101 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1102 SND_SOC_DAPM_SUPPLY("AUDIF_CK", MT6351_TOP_CKPDN_CON0, 1103 RG_AUDIF_CK_PDN_BIT, 1, 1104 mt_reg_set_clr_event, 1105 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1106 SND_SOC_DAPM_SUPPLY("AUDNCP_CK", MT6351_TOP_CKPDN_CON0, 1107 RG_AUDNCP_CK_PDN_BIT, 1, 1108 mt_reg_set_clr_event, 1109 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1110 1111 SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0, 1112 NULL, 0), 1113 1114 /* AIF Rx*/ 1115 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0, 1116 MT6351_AFE_DL_SRC2_CON0_L, 1117 RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, 1118 mt_aif_in_event, SND_SOC_DAPM_PRE_PMU), 1119 1120 /* DL Supply */ 1121 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 1122 0, 0, NULL, 0), 1123 SND_SOC_DAPM_SUPPLY("NV Regulator", MT6351_AUDDEC_ANA_CON10, 1124 RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0), 1125 SND_SOC_DAPM_SUPPLY("AUD_CLK", MT6351_AUDDEC_ANA_CON9, 1126 RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0), 1127 SND_SOC_DAPM_SUPPLY("IBIST", MT6351_AUDDEC_ANA_CON9, 1128 RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0), 1129 SND_SOC_DAPM_SUPPLY("LDO", MT6351_AUDDEC_ANA_CON9, 1130 RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0), 1131 SND_SOC_DAPM_SUPPLY("LDO_REMOTE_SENSE", MT6351_AUDDEC_ANA_CON9, 1132 RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0), 1133 1134 /* DAC */ 1135 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 1136 1137 SND_SOC_DAPM_DAC("DACL", NULL, MT6351_AUDDEC_ANA_CON0, 1138 RG_AUDDACLPWRUP_VAUDP32_BIT, 0), 1139 SND_SOC_DAPM_SUPPLY("DACL_BIASGEN", MT6351_AUDDEC_ANA_CON0, 1140 RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0), 1141 1142 SND_SOC_DAPM_DAC("DACR", NULL, MT6351_AUDDEC_ANA_CON0, 1143 RG_AUDDACRPWRUP_VAUDP32_BIT, 0), 1144 SND_SOC_DAPM_SUPPLY("DACR_BIASGEN", MT6351_AUDDEC_ANA_CON0, 1145 RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0), 1146 /* LOL */ 1147 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control), 1148 1149 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6351_AUDDEC_ANA_CON3, 1150 RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0), 1151 SND_SOC_DAPM_SUPPLY("LOL Bias Gen", MT6351_AUDDEC_ANA_CON6, 1152 RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0), 1153 1154 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6351_AUDDEC_ANA_CON3, 1155 RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0), 1156 1157 /* Headphone */ 1158 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control), 1159 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control), 1160 1161 SND_SOC_DAPM_OUT_DRV_E("HPL Power", MT6351_AUDDEC_ANA_CON0, 1162 RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0, 1163 mt_hp_event, 1164 SND_SOC_DAPM_PRE_PMU | 1165 SND_SOC_DAPM_PRE_PMD | 1166 SND_SOC_DAPM_POST_PMD), 1167 SND_SOC_DAPM_OUT_DRV_E("HPR Power", MT6351_AUDDEC_ANA_CON0, 1168 RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0, 1169 mt_hp_event, 1170 SND_SOC_DAPM_PRE_PMU | 1171 SND_SOC_DAPM_PRE_PMD | 1172 SND_SOC_DAPM_POST_PMD), 1173 1174 /* Receiver */ 1175 SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control), 1176 1177 SND_SOC_DAPM_SUPPLY("RCV Stability Enh", MT6351_AUDDEC_ANA_CON1, 1178 RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0), 1179 SND_SOC_DAPM_SUPPLY("RCV Bias Gen", MT6351_AUDDEC_ANA_CON6, 1180 RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0), 1181 1182 SND_SOC_DAPM_OUT_DRV("RCV Buffer", MT6351_AUDDEC_ANA_CON0, 1183 RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0), 1184 1185 /* Outputs */ 1186 SND_SOC_DAPM_OUTPUT("Receiver"), 1187 SND_SOC_DAPM_OUTPUT("Headphone L"), 1188 SND_SOC_DAPM_OUTPUT("Headphone R"), 1189 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 1190 1191 /* SGEN */ 1192 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6351_AFE_SGEN_CFG0, 1193 SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0), 1194 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6351_AFE_SGEN_CFG0, 1195 SGEN_C_MUTE_SW_CTL_BIT, 1, 1196 mt_sgen_event, SND_SOC_DAPM_PRE_PMU), 1197 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6351_AFE_DL_SRC2_CON0_L, 1198 RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0), 1199 1200 SND_SOC_DAPM_INPUT("SGEN DL"), 1201 1202 /* Uplinks */ 1203 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0, 1204 MT6351_AFE_UL_SRC_CON0_L, 1205 UL_SRC_ON_TMP_CTL, 0, 1206 mt_aif_out_event, 1207 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1208 1209 SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO", SUPPLY_SUBSEQ_ENABLE, 1210 MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0, 1211 NULL, 0), 1212 SND_SOC_DAPM_SUPPLY_S("VUSB33_LDO_CTRL", SUPPLY_SUBSEQ_SETTING, 1213 MT6351_LDO_VUSB33_CON0, RG_VUSB33_ON_CTRL, 1, 1214 NULL, 0), 1215 1216 SND_SOC_DAPM_SUPPLY_S("VA18_LDO", SUPPLY_SUBSEQ_ENABLE, 1217 MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0), 1218 SND_SOC_DAPM_SUPPLY_S("VA18_LDO_CTRL", SUPPLY_SUBSEQ_SETTING, 1219 MT6351_LDO_VA18_CON0, RG_VA18_ON_CTRL, 1, 1220 NULL, 0), 1221 1222 SND_SOC_DAPM_SUPPLY_S("ADC CLKGEN", SUPPLY_SUBSEQ_ENABLE, 1223 MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0, 1224 mt_adc_clkgen_event, 1225 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1226 1227 /* Uplinks MUX */ 1228 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 1229 &aif_out_mux_control), 1230 1231 SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0, 1232 &adc_left_mux_control), 1233 SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0, 1234 &adc_right_mux_control), 1235 1236 SND_SOC_DAPM_ADC("ADC L", NULL, 1237 MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0), 1238 SND_SOC_DAPM_ADC("ADC R", NULL, 1239 MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0), 1240 1241 SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0, 1242 &pga_left_mux_control), 1243 SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0, 1244 &pga_right_mux_control), 1245 1246 SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0, 1247 NULL, 0, 1248 mt_pga_left_event, 1249 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1250 SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0, 1251 NULL, 0, 1252 mt_pga_right_event, 1253 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1254 1255 /* main mic mic bias */ 1256 SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS, 1257 MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0, 1258 mt_mic_bias_0_event, 1259 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1260 /* ref mic mic bias */ 1261 SND_SOC_DAPM_SUPPLY_S("Mic Bias 2", SUPPLY_SUBSEQ_MICBIAS, 1262 MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0, 1263 mt_mic_bias_2_event, 1264 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1265 /* headset mic1/2 mic bias */ 1266 SND_SOC_DAPM_SUPPLY_S("Mic Bias 1", SUPPLY_SUBSEQ_MICBIAS, 1267 MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0, 1268 mt_mic_bias_1_event, 1269 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1270 SND_SOC_DAPM_SUPPLY_S("Mic Bias 1 DCC pull high", SUPPLY_SUBSEQ_MICBIAS, 1271 MT6351_AUDENC_ANA_CON10, 1272 RG_AUDMICBIAS1DCSW1NEN, 0, 1273 NULL, 0), 1274 1275 /* UL input */ 1276 SND_SOC_DAPM_INPUT("AIN0"), 1277 SND_SOC_DAPM_INPUT("AIN1"), 1278 SND_SOC_DAPM_INPUT("AIN2"), 1279 SND_SOC_DAPM_INPUT("AIN3"), 1280 }; 1281 1282 static const struct snd_soc_dapm_route mt6351_dapm_routes[] = { 1283 /* Capture */ 1284 {"AIF1TX", NULL, "AIF Out Mux"}, 1285 {"AIF1TX", NULL, "VUSB33_LDO"}, 1286 {"VUSB33_LDO", NULL, "VUSB33_LDO_CTRL"}, 1287 {"AIF1TX", NULL, "VA18_LDO"}, 1288 {"VA18_LDO", NULL, "VA18_LDO_CTRL"}, 1289 1290 {"AIF1TX", NULL, "AUDGLB"}, 1291 {"AIF1TX", NULL, "CLKSQ Audio"}, 1292 1293 {"AIF1TX", NULL, "AFE_ON"}, 1294 1295 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}, 1296 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}, 1297 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}, 1298 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"}, 1299 1300 {"AIF Out Mux", "Normal Path", "ADC L"}, 1301 {"AIF Out Mux", "Normal Path", "ADC R"}, 1302 1303 {"ADC L", NULL, "ADC L Mux"}, 1304 {"ADC L", NULL, "AUD_CK"}, 1305 {"ADC L", NULL, "AUDIF_CK"}, 1306 {"ADC L", NULL, "ADC CLKGEN"}, 1307 {"ADC R", NULL, "ADC R Mux"}, 1308 {"ADC R", NULL, "AUD_CK"}, 1309 {"ADC R", NULL, "AUDIF_CK"}, 1310 {"ADC R", NULL, "ADC CLKGEN"}, 1311 1312 {"ADC L Mux", "AIN0", "AIN0"}, 1313 {"ADC L Mux", "Left Preamplifier", "PGA L"}, 1314 1315 {"ADC R Mux", "AIN0", "AIN0"}, 1316 {"ADC R Mux", "Right Preamplifier", "PGA R"}, 1317 1318 {"PGA L", NULL, "PGA L Mux"}, 1319 {"PGA R", NULL, "PGA R Mux"}, 1320 1321 {"PGA L Mux", "AIN0", "AIN0"}, 1322 {"PGA L Mux", "AIN1", "AIN1"}, 1323 {"PGA L Mux", "AIN2", "AIN2"}, 1324 1325 {"PGA R Mux", "AIN0", "AIN0"}, 1326 {"PGA R Mux", "AIN3", "AIN3"}, 1327 {"PGA R Mux", "AIN2", "AIN2"}, 1328 1329 {"AIN0", NULL, "Mic Bias 0"}, 1330 {"AIN2", NULL, "Mic Bias 2"}, 1331 1332 {"AIN1", NULL, "Mic Bias 1"}, 1333 {"AIN1", NULL, "Mic Bias 1 DCC pull high"}, 1334 1335 /* DL Supply */ 1336 {"DL Power Supply", NULL, "AUDGLB"}, 1337 {"DL Power Supply", NULL, "CLKSQ Audio"}, 1338 {"DL Power Supply", NULL, "ZCD13M_CK"}, 1339 {"DL Power Supply", NULL, "AUD_CK"}, 1340 {"DL Power Supply", NULL, "AUDIF_CK"}, 1341 {"DL Power Supply", NULL, "AUDNCP_CK"}, 1342 1343 {"DL Power Supply", NULL, "NV Regulator"}, 1344 {"DL Power Supply", NULL, "AUD_CLK"}, 1345 {"DL Power Supply", NULL, "IBIST"}, 1346 {"DL Power Supply", NULL, "LDO"}, 1347 {"LDO", NULL, "LDO_REMOTE_SENSE"}, 1348 1349 /* DL Digital Supply */ 1350 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 1351 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 1352 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 1353 {"DL Digital Clock", NULL, "AUDIO_TOP_PDN_RESERVED"}, 1354 {"DL Digital Clock", NULL, "NCP"}, 1355 {"DL Digital Clock", NULL, "AFE_ON"}, 1356 1357 {"AIF_RX", NULL, "DL Digital Clock"}, 1358 1359 /* DL Path */ 1360 {"DAC In Mux", "Normal Path", "AIF_RX"}, 1361 1362 {"DAC In Mux", "Sgen", "SGEN DL"}, 1363 {"SGEN DL", NULL, "SGEN DL SRC"}, 1364 {"SGEN DL", NULL, "SGEN MUTE"}, 1365 {"SGEN DL", NULL, "SGEN DL Enable"}, 1366 {"SGEN DL", NULL, "DL Digital Clock"}, 1367 1368 {"DACL", NULL, "DAC In Mux"}, 1369 {"DACL", NULL, "DL Power Supply"}, 1370 {"DACL", NULL, "DACL_BIASGEN"}, 1371 1372 {"DACR", NULL, "DAC In Mux"}, 1373 {"DACR", NULL, "DL Power Supply"}, 1374 {"DACR", NULL, "DACR_BIASGEN"}, 1375 1376 {"LOL Mux", "Playback", "DACL"}, 1377 1378 {"LOL Buffer", NULL, "LOL Mux"}, 1379 {"LOL Buffer", NULL, "LO Stability Enh"}, 1380 {"LOL Buffer", NULL, "LOL Bias Gen"}, 1381 1382 {"LINEOUT L", NULL, "LOL Buffer"}, 1383 1384 /* Headphone Path */ 1385 {"HPL Mux", "Audio Playback", "DACL"}, 1386 {"HPR Mux", "Audio Playback", "DACR"}, 1387 1388 {"HPL Mux", "LoudSPK Playback", "DACL"}, 1389 {"HPR Mux", "LoudSPK Playback", "DACR"}, 1390 1391 {"HPL Power", NULL, "HPL Mux"}, 1392 {"HPR Power", NULL, "HPR Mux"}, 1393 1394 {"Headphone L", NULL, "HPL Power"}, 1395 {"Headphone R", NULL, "HPR Power"}, 1396 1397 /* Receiver Path */ 1398 {"RCV Mux", "Voice Playback", "DACL"}, 1399 1400 {"RCV Buffer", NULL, "RCV Mux"}, 1401 {"RCV Buffer", NULL, "RCV Stability Enh"}, 1402 {"RCV Buffer", NULL, "RCV Bias Gen"}, 1403 1404 {"Receiver", NULL, "RCV Buffer"}, 1405 }; 1406 1407 static int mt6351_codec_init_reg(struct snd_soc_component *cmpnt) 1408 { 1409 /* Disable CLKSQ 26MHz */ 1410 regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0); 1411 /* disable AUDGLB */ 1412 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON9, 1413 0x1000, 0x1000); 1414 /* Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M */ 1415 regmap_update_bits(cmpnt->regmap, MT6351_TOP_CKPDN_CON0_SET, 1416 0x3800, 0x3800); 1417 /* Disable HeadphoneL/HeadphoneR/voice short circuit protection */ 1418 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON0, 1419 0xe000, 0xe000); 1420 /* [5] = 1, disable LO buffer left short circuit protection */ 1421 regmap_update_bits(cmpnt->regmap, MT6351_AUDDEC_ANA_CON3, 1422 0x20, 0x20); 1423 /* Reverse the PMIC clock*/ 1424 regmap_update_bits(cmpnt->regmap, MT6351_AFE_PMIC_NEWIF_CFG2, 1425 0x8000, 0x8000); 1426 return 0; 1427 } 1428 1429 static int mt6351_codec_probe(struct snd_soc_component *cmpnt) 1430 { 1431 struct mt6351_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1432 1433 snd_soc_component_init_regmap(cmpnt, priv->regmap); 1434 1435 mt6351_codec_init_reg(cmpnt); 1436 return 0; 1437 } 1438 1439 static const struct snd_soc_component_driver mt6351_soc_component_driver = { 1440 .probe = mt6351_codec_probe, 1441 .controls = mt6351_snd_controls, 1442 .num_controls = ARRAY_SIZE(mt6351_snd_controls), 1443 .dapm_widgets = mt6351_dapm_widgets, 1444 .num_dapm_widgets = ARRAY_SIZE(mt6351_dapm_widgets), 1445 .dapm_routes = mt6351_dapm_routes, 1446 .num_dapm_routes = ARRAY_SIZE(mt6351_dapm_routes), 1447 .endianness = 1, 1448 }; 1449 1450 static int mt6351_codec_driver_probe(struct platform_device *pdev) 1451 { 1452 struct mt6351_priv *priv; 1453 1454 priv = devm_kzalloc(&pdev->dev, 1455 sizeof(struct mt6351_priv), 1456 GFP_KERNEL); 1457 if (!priv) 1458 return -ENOMEM; 1459 1460 dev_set_drvdata(&pdev->dev, priv); 1461 1462 priv->dev = &pdev->dev; 1463 1464 priv->regmap = dev_get_regmap(pdev->dev.parent, NULL); 1465 if (!priv->regmap) 1466 return -ENODEV; 1467 1468 dev_dbg(priv->dev, "%s(), dev name %s\n", 1469 __func__, dev_name(&pdev->dev)); 1470 1471 return devm_snd_soc_register_component(&pdev->dev, 1472 &mt6351_soc_component_driver, 1473 mt6351_dai_driver, 1474 ARRAY_SIZE(mt6351_dai_driver)); 1475 } 1476 1477 static const struct of_device_id mt6351_of_match[] = { 1478 {.compatible = "mediatek,mt6351-sound",}, 1479 {} 1480 }; 1481 1482 static struct platform_driver mt6351_codec_driver = { 1483 .driver = { 1484 .name = "mt6351-sound", 1485 .of_match_table = mt6351_of_match, 1486 }, 1487 .probe = mt6351_codec_driver_probe, 1488 }; 1489 1490 module_platform_driver(mt6351_codec_driver) 1491 1492 /* Module information */ 1493 MODULE_DESCRIPTION("MT6351 ALSA SoC codec driver"); 1494 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 1495 MODULE_LICENSE("GPL v2"); 1496