1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2022, Analog Devices Inc. 3 4 #include <linux/i2c.h> 5 #include <linux/module.h> 6 #include <sound/pcm_params.h> 7 #include <sound/soc.h> 8 #include <linux/gpio.h> 9 #include <sound/tlv.h> 10 #include "max98396.h" 11 12 static struct reg_default max98396_reg[] = { 13 {MAX98396_R2000_SW_RESET, 0x00}, 14 {MAX98396_R2001_INT_RAW1, 0x00}, 15 {MAX98396_R2002_INT_RAW2, 0x00}, 16 {MAX98396_R2003_INT_RAW3, 0x00}, 17 {MAX98396_R2004_INT_RAW4, 0x00}, 18 {MAX98396_R2006_INT_STATE1, 0x00}, 19 {MAX98396_R2007_INT_STATE2, 0x00}, 20 {MAX98396_R2008_INT_STATE3, 0x00}, 21 {MAX98396_R2009_INT_STATE4, 0x00}, 22 {MAX98396_R200B_INT_FLAG1, 0x00}, 23 {MAX98396_R200C_INT_FLAG2, 0x00}, 24 {MAX98396_R200D_INT_FLAG3, 0x00}, 25 {MAX98396_R200E_INT_FLAG4, 0x00}, 26 {MAX98396_R2010_INT_EN1, 0x02}, 27 {MAX98396_R2011_INT_EN2, 0x00}, 28 {MAX98396_R2012_INT_EN3, 0x00}, 29 {MAX98396_R2013_INT_EN4, 0x00}, 30 {MAX98396_R2015_INT_FLAG_CLR1, 0x00}, 31 {MAX98396_R2016_INT_FLAG_CLR2, 0x00}, 32 {MAX98396_R2017_INT_FLAG_CLR3, 0x00}, 33 {MAX98396_R2018_INT_FLAG_CLR4, 0x00}, 34 {MAX98396_R201F_IRQ_CTRL, 0x00}, 35 {MAX98396_R2020_THERM_WARN_THRESH, 0x46}, 36 {MAX98396_R2021_THERM_WARN_THRESH2, 0x46}, 37 {MAX98396_R2022_THERM_SHDN_THRESH, 0x64}, 38 {MAX98396_R2023_THERM_HYSTERESIS, 0x02}, 39 {MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5}, 40 {MAX98396_R2027_THERM_FOLDBACK_EN, 0x01}, 41 {MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32}, 42 {MAX98396_R2033_NOISEGATE_MODE_EN, 0x00}, 43 {MAX98396_R2038_CLK_MON_CTRL, 0x00}, 44 {MAX98396_R2039_DATA_MON_CTRL, 0x00}, 45 {MAX98396_R203F_ENABLE_CTRLS, 0x0F}, 46 {MAX98396_R2040_PIN_CFG, 0x55}, 47 {MAX98396_R2041_PCM_MODE_CFG, 0xC0}, 48 {MAX98396_R2042_PCM_CLK_SETUP, 0x04}, 49 {MAX98396_R2043_PCM_SR_SETUP, 0x88}, 50 {MAX98396_R2044_PCM_TX_CTRL_1, 0x00}, 51 {MAX98396_R2045_PCM_TX_CTRL_2, 0x00}, 52 {MAX98396_R2046_PCM_TX_CTRL_3, 0x00}, 53 {MAX98396_R2047_PCM_TX_CTRL_4, 0x00}, 54 {MAX98396_R2048_PCM_TX_CTRL_5, 0x00}, 55 {MAX98396_R2049_PCM_TX_CTRL_6, 0x00}, 56 {MAX98396_R204A_PCM_TX_CTRL_7, 0x00}, 57 {MAX98396_R204B_PCM_TX_CTRL_8, 0x00}, 58 {MAX98396_R204C_PCM_TX_HIZ_CTRL_1, 0xFF}, 59 {MAX98396_R204D_PCM_TX_HIZ_CTRL_2, 0xFF}, 60 {MAX98396_R204E_PCM_TX_HIZ_CTRL_3, 0xFF}, 61 {MAX98396_R204F_PCM_TX_HIZ_CTRL_4, 0xFF}, 62 {MAX98396_R2050_PCM_TX_HIZ_CTRL_5, 0xFF}, 63 {MAX98396_R2051_PCM_TX_HIZ_CTRL_6, 0xFF}, 64 {MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 0xFF}, 65 {MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 0xFF}, 66 {MAX98396_R2055_PCM_RX_SRC1, 0x00}, 67 {MAX98396_R2056_PCM_RX_SRC2, 0x00}, 68 {MAX98396_R2058_PCM_BYPASS_SRC, 0x00}, 69 {MAX98396_R205D_PCM_TX_SRC_EN, 0x00}, 70 {MAX98396_R205E_PCM_RX_EN, 0x00}, 71 {MAX98396_R205F_PCM_TX_EN, 0x00}, 72 {MAX98396_R2070_ICC_RX_EN_A, 0x00}, 73 {MAX98396_R2071_ICC_RX_EN_B, 0x00}, 74 {MAX98396_R2072_ICC_TX_CTRL, 0x00}, 75 {MAX98396_R207F_ICC_EN, 0x00}, 76 {MAX98396_R2083_TONE_GEN_DC_CFG, 0x04}, 77 {MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00}, 78 {MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00}, 79 {MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00}, 80 {MAX98396_R208F_TONE_GEN_EN, 0x00}, 81 {MAX98396_R2090_AMP_VOL_CTRL, 0x00}, 82 {MAX98396_R2091_AMP_PATH_GAIN, 0x0B}, 83 {MAX98396_R2092_AMP_DSP_CFG, 0x23}, 84 {MAX98396_R2093_SSM_CFG, 0x0D}, 85 {MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12}, 86 {MAX98396_R2095_SPK_CLS_DG_HDR, 0x17}, 87 {MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17}, 88 {MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00}, 89 {MAX98396_R2098_SPK_CLS_DG_MODE, 0x00}, 90 {MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03}, 91 {MAX98396_R209A_SPK_EDGE_CTRL, 0x00}, 92 {MAX98396_R209C_SPK_EDGE_CTRL1, 0x0A}, 93 {MAX98396_R209D_SPK_EDGE_CTRL2, 0xAA}, 94 {MAX98396_R209E_AMP_CLIP_GAIN, 0x00}, 95 {MAX98396_R209F_BYPASS_PATH_CFG, 0x00}, 96 {MAX98396_R20A0_AMP_SUPPLY_CTL, 0x00}, 97 {MAX98396_R20AF_AMP_EN, 0x00}, 98 {MAX98396_R20B0_ADC_SR, 0x30}, 99 {MAX98396_R20B1_ADC_PVDD_CFG, 0x00}, 100 {MAX98396_R20B2_ADC_VBAT_CFG, 0x00}, 101 {MAX98396_R20B3_ADC_THERMAL_CFG, 0x00}, 102 {MAX98396_R20B4_ADC_READBACK_CTRL1, 0x00}, 103 {MAX98396_R20B5_ADC_READBACK_CTRL2, 0x00}, 104 {MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0x00}, 105 {MAX98396_R20B7_ADC_PVDD_READBACK_LSB, 0x00}, 106 {MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0x00}, 107 {MAX98396_R20B9_ADC_VBAT_READBACK_LSB, 0x00}, 108 {MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0x00}, 109 {MAX98396_R20BB_ADC_TEMP_READBACK_LSB, 0x00}, 110 {MAX98396_R20BC_ADC_LO_PVDD_READBACK_MSB, 0x00}, 111 {MAX98396_R20BD_ADC_LO_PVDD_READBACK_LSB, 0x00}, 112 {MAX98396_R20BE_ADC_LO_VBAT_READBACK_MSB, 0x00}, 113 {MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00}, 114 {MAX98396_R20C7_ADC_CFG, 0x00}, 115 {MAX98396_R20D0_DHT_CFG1, 0x00}, 116 {MAX98396_R20D1_LIMITER_CFG1, 0x08}, 117 {MAX98396_R20D2_LIMITER_CFG2, 0x00}, 118 {MAX98396_R20D3_DHT_CFG2, 0x14}, 119 {MAX98396_R20D4_DHT_CFG3, 0x02}, 120 {MAX98396_R20D5_DHT_CFG4, 0x04}, 121 {MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07}, 122 {MAX98396_R20DF_DHT_EN, 0x00}, 123 {MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04}, 124 {MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00}, 125 {MAX98396_R20E5_BPE_STATE, 0x00}, 126 {MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00}, 127 {MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00}, 128 {MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00}, 129 {MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00}, 130 {MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00}, 131 {MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00}, 132 {MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00}, 133 {MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00}, 134 {MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00}, 135 {MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00}, 136 {MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00}, 137 {MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00}, 138 {MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00}, 139 {MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00}, 140 {MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00}, 141 {MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00}, 142 {MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00}, 143 {MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00}, 144 {MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00}, 145 {MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00}, 146 {MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00}, 147 {MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00}, 148 {MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00}, 149 {MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00}, 150 {MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00}, 151 {MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00}, 152 {MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00}, 153 {MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00}, 154 {MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00}, 155 {MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00}, 156 {MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00}, 157 {MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00}, 158 {MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00}, 159 {MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00}, 160 {MAX98396_R2108_BPE_SUPPLY_SRC, 0x00}, 161 {MAX98396_R2109_BPE_LOW_STATE, 0x00}, 162 {MAX98396_R210A_BPE_LOW_GAIN, 0x00}, 163 {MAX98396_R210B_BPE_LOW_LIMITER, 0x00}, 164 {MAX98396_R210D_BPE_EN, 0x00}, 165 {MAX98396_R210E_AUTO_RESTART, 0x00}, 166 {MAX98396_R210F_GLOBAL_EN, 0x00}, 167 {MAX98396_R21FF_REVISION_ID, 0x00}, 168 }; 169 170 static struct reg_default max98397_reg[] = { 171 {MAX98396_R2000_SW_RESET, 0x00}, 172 {MAX98396_R2001_INT_RAW1, 0x00}, 173 {MAX98396_R2002_INT_RAW2, 0x00}, 174 {MAX98396_R2003_INT_RAW3, 0x00}, 175 {MAX98396_R2004_INT_RAW4, 0x00}, 176 {MAX98396_R2006_INT_STATE1, 0x00}, 177 {MAX98396_R2007_INT_STATE2, 0x00}, 178 {MAX98396_R2008_INT_STATE3, 0x00}, 179 {MAX98396_R2009_INT_STATE4, 0x00}, 180 {MAX98396_R200B_INT_FLAG1, 0x00}, 181 {MAX98396_R200C_INT_FLAG2, 0x00}, 182 {MAX98396_R200D_INT_FLAG3, 0x00}, 183 {MAX98396_R200E_INT_FLAG4, 0x00}, 184 {MAX98396_R2010_INT_EN1, 0x02}, 185 {MAX98396_R2011_INT_EN2, 0x00}, 186 {MAX98396_R2012_INT_EN3, 0x00}, 187 {MAX98396_R2013_INT_EN4, 0x00}, 188 {MAX98396_R2015_INT_FLAG_CLR1, 0x00}, 189 {MAX98396_R2016_INT_FLAG_CLR2, 0x00}, 190 {MAX98396_R2017_INT_FLAG_CLR3, 0x00}, 191 {MAX98396_R2018_INT_FLAG_CLR4, 0x00}, 192 {MAX98396_R201F_IRQ_CTRL, 0x00}, 193 {MAX98396_R2020_THERM_WARN_THRESH, 0x46}, 194 {MAX98396_R2021_THERM_WARN_THRESH2, 0x46}, 195 {MAX98396_R2022_THERM_SHDN_THRESH, 0x64}, 196 {MAX98396_R2023_THERM_HYSTERESIS, 0x02}, 197 {MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5}, 198 {MAX98396_R2027_THERM_FOLDBACK_EN, 0x01}, 199 {MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32}, 200 {MAX98396_R2033_NOISEGATE_MODE_EN, 0x00}, 201 {MAX98396_R2038_CLK_MON_CTRL, 0x00}, 202 {MAX98396_R2039_DATA_MON_CTRL, 0x00}, 203 {MAX98397_R203A_SPK_MON_THRESH, 0x03}, 204 {MAX98396_R203F_ENABLE_CTRLS, 0x0F}, 205 {MAX98396_R2040_PIN_CFG, 0x55}, 206 {MAX98396_R2041_PCM_MODE_CFG, 0xC0}, 207 {MAX98396_R2042_PCM_CLK_SETUP, 0x04}, 208 {MAX98396_R2043_PCM_SR_SETUP, 0x88}, 209 {MAX98396_R2044_PCM_TX_CTRL_1, 0x00}, 210 {MAX98396_R2045_PCM_TX_CTRL_2, 0x00}, 211 {MAX98396_R2046_PCM_TX_CTRL_3, 0x00}, 212 {MAX98396_R2047_PCM_TX_CTRL_4, 0x00}, 213 {MAX98396_R2048_PCM_TX_CTRL_5, 0x00}, 214 {MAX98396_R2049_PCM_TX_CTRL_6, 0x00}, 215 {MAX98396_R204A_PCM_TX_CTRL_7, 0x00}, 216 {MAX98396_R204B_PCM_TX_CTRL_8, 0x00}, 217 {MAX98397_R204C_PCM_TX_CTRL_9, 0x00}, 218 {MAX98397_R204D_PCM_TX_HIZ_CTRL_1, 0xFF}, 219 {MAX98397_R204E_PCM_TX_HIZ_CTRL_2, 0xFF}, 220 {MAX98397_R204F_PCM_TX_HIZ_CTRL_3, 0xFF}, 221 {MAX98397_R2050_PCM_TX_HIZ_CTRL_4, 0xFF}, 222 {MAX98397_R2051_PCM_TX_HIZ_CTRL_5, 0xFF}, 223 {MAX98397_R2052_PCM_TX_HIZ_CTRL_6, 0xFF}, 224 {MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 0xFF}, 225 {MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 0xFF}, 226 {MAX98397_R2056_PCM_RX_SRC1, 0x00}, 227 {MAX98397_R2057_PCM_RX_SRC2, 0x00}, 228 {MAX98396_R2058_PCM_BYPASS_SRC, 0x00}, 229 {MAX98396_R205D_PCM_TX_SRC_EN, 0x00}, 230 {MAX98396_R205E_PCM_RX_EN, 0x00}, 231 {MAX98396_R205F_PCM_TX_EN, 0x00}, 232 {MAX98397_R2060_PCM_TX_SUPPLY_SEL, 0x00}, 233 {MAX98396_R2070_ICC_RX_EN_A, 0x00}, 234 {MAX98396_R2071_ICC_RX_EN_B, 0x00}, 235 {MAX98396_R2072_ICC_TX_CTRL, 0x00}, 236 {MAX98396_R207F_ICC_EN, 0x00}, 237 {MAX98396_R2083_TONE_GEN_DC_CFG, 0x04}, 238 {MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00}, 239 {MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00}, 240 {MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00}, 241 {MAX98396_R208F_TONE_GEN_EN, 0x00}, 242 {MAX98396_R2090_AMP_VOL_CTRL, 0x00}, 243 {MAX98396_R2091_AMP_PATH_GAIN, 0x12}, 244 {MAX98396_R2092_AMP_DSP_CFG, 0x22}, 245 {MAX98396_R2093_SSM_CFG, 0x08}, 246 {MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12}, 247 {MAX98396_R2095_SPK_CLS_DG_HDR, 0x17}, 248 {MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17}, 249 {MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00}, 250 {MAX98396_R2098_SPK_CLS_DG_MODE, 0x00}, 251 {MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03}, 252 {MAX98396_R209A_SPK_EDGE_CTRL, 0x00}, 253 {MAX98397_R209B_SPK_PATH_WB_ONLY, 0x00}, 254 {MAX98396_R209C_SPK_EDGE_CTRL1, 0x03}, 255 {MAX98396_R209D_SPK_EDGE_CTRL2, 0xFC}, 256 {MAX98396_R209E_AMP_CLIP_GAIN, 0x00}, 257 {MAX98396_R209F_BYPASS_PATH_CFG, 0x00}, 258 {MAX98396_R20AF_AMP_EN, 0x00}, 259 {MAX98396_R20B0_ADC_SR, 0x30}, 260 {MAX98396_R20B1_ADC_PVDD_CFG, 0x00}, 261 {MAX98396_R20B2_ADC_VBAT_CFG, 0x00}, 262 {MAX98396_R20B3_ADC_THERMAL_CFG, 0x00}, 263 {MAX98397_R20B4_ADC_VDDH_CFG, 0x00}, 264 {MAX98397_R20B5_ADC_READBACK_CTRL1, 0x00}, 265 {MAX98397_R20B6_ADC_READBACK_CTRL2, 0x00}, 266 {MAX98397_R20B7_ADC_PVDD_READBACK_MSB, 0x00}, 267 {MAX98397_R20B8_ADC_PVDD_READBACK_LSB, 0x00}, 268 {MAX98397_R20B9_ADC_VBAT_READBACK_MSB, 0x00}, 269 {MAX98397_R20BA_ADC_VBAT_READBACK_LSB, 0x00}, 270 {MAX98397_R20BB_ADC_TEMP_READBACK_MSB, 0x00}, 271 {MAX98397_R20BC_ADC_TEMP_READBACK_LSB, 0x00}, 272 {MAX98397_R20BD_ADC_VDDH__READBACK_MSB, 0x00}, 273 {MAX98397_R20BE_ADC_VDDH_READBACK_LSB, 0x00}, 274 {MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00}, 275 {MAX98397_R20C3_ADC_LO_VDDH_READBACK_MSB, 0x00}, 276 {MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB, 0x00}, 277 {MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE, 0x04}, 278 {MAX98396_R20C7_ADC_CFG, 0x00}, 279 {MAX98396_R20D0_DHT_CFG1, 0x00}, 280 {MAX98396_R20D1_LIMITER_CFG1, 0x08}, 281 {MAX98396_R20D2_LIMITER_CFG2, 0x00}, 282 {MAX98396_R20D3_DHT_CFG2, 0x14}, 283 {MAX98396_R20D4_DHT_CFG3, 0x02}, 284 {MAX98396_R20D5_DHT_CFG4, 0x04}, 285 {MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07}, 286 {MAX98396_R20DF_DHT_EN, 0x00}, 287 {MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04}, 288 {MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00}, 289 {MAX98396_R20E5_BPE_STATE, 0x00}, 290 {MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00}, 291 {MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00}, 292 {MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00}, 293 {MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00}, 294 {MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00}, 295 {MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00}, 296 {MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00}, 297 {MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00}, 298 {MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00}, 299 {MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00}, 300 {MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00}, 301 {MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00}, 302 {MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00}, 303 {MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00}, 304 {MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00}, 305 {MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00}, 306 {MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00}, 307 {MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00}, 308 {MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00}, 309 {MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00}, 310 {MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00}, 311 {MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00}, 312 {MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00}, 313 {MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00}, 314 {MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00}, 315 {MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00}, 316 {MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00}, 317 {MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00}, 318 {MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00}, 319 {MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00}, 320 {MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00}, 321 {MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00}, 322 {MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00}, 323 {MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00}, 324 {MAX98396_R2108_BPE_SUPPLY_SRC, 0x00}, 325 {MAX98396_R2109_BPE_LOW_STATE, 0x00}, 326 {MAX98396_R210A_BPE_LOW_GAIN, 0x00}, 327 {MAX98396_R210B_BPE_LOW_LIMITER, 0x00}, 328 {MAX98396_R210D_BPE_EN, 0x00}, 329 {MAX98396_R210E_AUTO_RESTART, 0x00}, 330 {MAX98396_R210F_GLOBAL_EN, 0x00}, 331 {MAX98397_R22FF_REVISION_ID, 0x00}, 332 }; 333 334 static void max98396_global_enable_onoff(struct regmap *regmap, bool onoff) 335 { 336 regmap_write(regmap, MAX98396_R210F_GLOBAL_EN, onoff ? 1 : 0); 337 usleep_range(11000, 12000); 338 } 339 340 static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 341 { 342 struct snd_soc_component *component = codec_dai->component; 343 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 344 unsigned int format = 0; 345 unsigned int bclk_pol = 0; 346 int ret, status; 347 int reg; 348 bool update = false; 349 350 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 351 352 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 353 case SND_SOC_DAIFMT_NB_NF: 354 break; 355 case SND_SOC_DAIFMT_NB_IF: 356 format = MAX98396_PCM_MODE_CFG_LRCLKEDGE; 357 break; 358 case SND_SOC_DAIFMT_IB_NF: 359 bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE; 360 break; 361 case SND_SOC_DAIFMT_IB_IF: 362 bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE; 363 format = MAX98396_PCM_MODE_CFG_LRCLKEDGE; 364 break; 365 366 default: 367 dev_err(component->dev, "DAI invert mode unsupported\n"); 368 return -EINVAL; 369 } 370 371 /* interface format */ 372 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 373 case SND_SOC_DAIFMT_I2S: 374 format |= MAX98396_PCM_FORMAT_I2S; 375 break; 376 case SND_SOC_DAIFMT_LEFT_J: 377 format |= MAX98396_PCM_FORMAT_LJ; 378 break; 379 case SND_SOC_DAIFMT_DSP_A: 380 format |= MAX98396_PCM_FORMAT_TDM_MODE1; 381 break; 382 case SND_SOC_DAIFMT_DSP_B: 383 format |= MAX98396_PCM_FORMAT_TDM_MODE0; 384 break; 385 default: 386 return -EINVAL; 387 } 388 389 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 390 if (ret < 0) 391 return -EINVAL; 392 393 if (status) { 394 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 395 if (ret < 0) 396 return -EINVAL; 397 if (format != (reg & MAX98396_PCM_BCLKEDGE_BSEL_MASK)) { 398 update = true; 399 } else { 400 ret = regmap_read(max98396->regmap, 401 MAX98396_R2042_PCM_CLK_SETUP, ®); 402 if (ret < 0) 403 return -EINVAL; 404 if (bclk_pol != (reg & MAX98396_PCM_MODE_CFG_BCLKEDGE)) 405 update = true; 406 } 407 /* GLOBAL_EN OFF prior to pcm mode, clock configuration change */ 408 if (update) 409 max98396_global_enable_onoff(max98396->regmap, false); 410 } 411 412 regmap_update_bits(max98396->regmap, 413 MAX98396_R2041_PCM_MODE_CFG, 414 MAX98396_PCM_BCLKEDGE_BSEL_MASK, 415 format); 416 417 regmap_update_bits(max98396->regmap, 418 MAX98396_R2042_PCM_CLK_SETUP, 419 MAX98396_PCM_MODE_CFG_BCLKEDGE, 420 bclk_pol); 421 422 if (status && update) 423 max98396_global_enable_onoff(max98396->regmap, true); 424 425 return 0; 426 } 427 428 /* BCLKs per LRCLK */ 429 static const int bclk_sel_table[] = { 430 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 431 }; 432 433 static int max98396_get_bclk_sel(int bclk) 434 { 435 int i; 436 /* match BCLKs per LRCLK */ 437 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 438 if (bclk_sel_table[i] == bclk) 439 return i + 2; 440 } 441 return 0; 442 } 443 444 static int max98396_set_clock(struct snd_soc_component *component, 445 struct snd_pcm_hw_params *params) 446 { 447 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 448 /* BCLK/LRCLK ratio calculation */ 449 int blr_clk_ratio = params_channels(params) * max98396->ch_size; 450 int value; 451 452 if (!max98396->tdm_mode) { 453 /* BCLK configuration */ 454 value = max98396_get_bclk_sel(blr_clk_ratio); 455 if (!value) { 456 dev_err(component->dev, "format unsupported %d\n", 457 params_format(params)); 458 return -EINVAL; 459 } 460 461 regmap_update_bits(max98396->regmap, 462 MAX98396_R2042_PCM_CLK_SETUP, 463 MAX98396_PCM_CLK_SETUP_BSEL_MASK, 464 value); 465 } 466 467 return 0; 468 } 469 470 static int max98396_dai_hw_params(struct snd_pcm_substream *substream, 471 struct snd_pcm_hw_params *params, 472 struct snd_soc_dai *dai) 473 { 474 struct snd_soc_component *component = dai->component; 475 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 476 unsigned int sampling_rate = 0; 477 unsigned int chan_sz = 0; 478 int ret, reg; 479 int status; 480 bool update = false; 481 482 /* pcm mode configuration */ 483 switch (snd_pcm_format_width(params_format(params))) { 484 case 16: 485 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16; 486 break; 487 case 24: 488 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24; 489 break; 490 case 32: 491 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32; 492 break; 493 default: 494 dev_err(component->dev, "format unsupported %d\n", 495 params_format(params)); 496 goto err; 497 } 498 499 max98396->ch_size = snd_pcm_format_width(params_format(params)); 500 501 dev_dbg(component->dev, "format supported %d", 502 params_format(params)); 503 504 /* sampling rate configuration */ 505 switch (params_rate(params)) { 506 case 8000: 507 sampling_rate = MAX98396_PCM_SR_8000; 508 break; 509 case 11025: 510 sampling_rate = MAX98396_PCM_SR_11025; 511 break; 512 case 12000: 513 sampling_rate = MAX98396_PCM_SR_12000; 514 break; 515 case 16000: 516 sampling_rate = MAX98396_PCM_SR_16000; 517 break; 518 case 22050: 519 sampling_rate = MAX98396_PCM_SR_22050; 520 break; 521 case 24000: 522 sampling_rate = MAX98396_PCM_SR_24000; 523 break; 524 case 32000: 525 sampling_rate = MAX98396_PCM_SR_32000; 526 break; 527 case 44100: 528 sampling_rate = MAX98396_PCM_SR_44100; 529 break; 530 case 48000: 531 sampling_rate = MAX98396_PCM_SR_48000; 532 break; 533 case 88200: 534 sampling_rate = MAX98396_PCM_SR_88200; 535 break; 536 case 96000: 537 sampling_rate = MAX98396_PCM_SR_96000; 538 break; 539 case 192000: 540 sampling_rate = MAX98396_PCM_SR_192000; 541 break; 542 default: 543 dev_err(component->dev, "rate %d not supported\n", 544 params_rate(params)); 545 goto err; 546 } 547 548 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 549 if (ret < 0) 550 goto err; 551 552 if (status) { 553 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 554 if (ret < 0) 555 goto err; 556 if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK)) { 557 update = true; 558 } else { 559 ret = regmap_read(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP, ®); 560 if (ret < 0) 561 goto err; 562 if (sampling_rate != (reg & MAX98396_PCM_SR_MASK)) 563 update = true; 564 } 565 566 /* GLOBAL_EN OFF prior to channel size and sampling rate change */ 567 if (update) 568 max98396_global_enable_onoff(max98396->regmap, false); 569 } 570 571 /* set channel size */ 572 regmap_update_bits(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, 573 MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 574 575 /* set DAI_SR to correct LRCLK frequency */ 576 regmap_update_bits(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP, 577 MAX98396_PCM_SR_MASK, sampling_rate); 578 579 /* set sampling rate of IV */ 580 if (max98396->interleave_mode && 581 sampling_rate > MAX98396_PCM_SR_16000) 582 regmap_update_bits(max98396->regmap, 583 MAX98396_R2043_PCM_SR_SETUP, 584 MAX98396_IVADC_SR_MASK, 585 (sampling_rate - 3) 586 << MAX98396_IVADC_SR_SHIFT); 587 else 588 regmap_update_bits(max98396->regmap, 589 MAX98396_R2043_PCM_SR_SETUP, 590 MAX98396_IVADC_SR_MASK, 591 sampling_rate << MAX98396_IVADC_SR_SHIFT); 592 593 ret = max98396_set_clock(component, params); 594 595 if (status && update) 596 max98396_global_enable_onoff(max98396->regmap, true); 597 598 return ret; 599 600 err: 601 return -EINVAL; 602 } 603 604 static int max98396_dai_tdm_slot(struct snd_soc_dai *dai, 605 unsigned int tx_mask, unsigned int rx_mask, 606 int slots, int slot_width) 607 { 608 struct snd_soc_component *component = dai->component; 609 struct max98396_priv *max98396 = 610 snd_soc_component_get_drvdata(component); 611 int bsel; 612 unsigned int chan_sz = 0; 613 int ret, status; 614 int reg; 615 bool update = false; 616 617 if (!tx_mask && !rx_mask && !slots && !slot_width) 618 max98396->tdm_mode = false; 619 else 620 max98396->tdm_mode = true; 621 622 /* BCLK configuration */ 623 bsel = max98396_get_bclk_sel(slots * slot_width); 624 if (bsel == 0) { 625 dev_err(component->dev, "BCLK %d not supported\n", 626 slots * slot_width); 627 return -EINVAL; 628 } 629 630 /* Channel size configuration */ 631 switch (slot_width) { 632 case 16: 633 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16; 634 break; 635 case 24: 636 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24; 637 break; 638 case 32: 639 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32; 640 break; 641 default: 642 dev_err(component->dev, "format unsupported %d\n", 643 slot_width); 644 return -EINVAL; 645 } 646 647 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 648 if (ret < 0) 649 return -EINVAL; 650 651 if (status) { 652 ret = regmap_read(max98396->regmap, MAX98396_R2042_PCM_CLK_SETUP, ®); 653 if (ret < 0) 654 return -EINVAL; 655 if (bsel != (reg & MAX98396_PCM_CLK_SETUP_BSEL_MASK)) { 656 update = true; 657 } else { 658 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 659 if (ret < 0) 660 return -EINVAL; 661 if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK)) 662 update = true; 663 } 664 665 /* GLOBAL_EN OFF prior to channel size and BCLK per LRCLK change */ 666 if (update) 667 max98396_global_enable_onoff(max98396->regmap, false); 668 } 669 670 regmap_update_bits(max98396->regmap, 671 MAX98396_R2042_PCM_CLK_SETUP, 672 MAX98396_PCM_CLK_SETUP_BSEL_MASK, 673 bsel); 674 675 regmap_update_bits(max98396->regmap, 676 MAX98396_R2041_PCM_MODE_CFG, 677 MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 678 679 /* Rx slot configuration */ 680 if (max98396->device_id == CODEC_TYPE_MAX98396) { 681 regmap_update_bits(max98396->regmap, 682 MAX98396_R2056_PCM_RX_SRC2, 683 MAX98396_PCM_DMIX_CH0_SRC_MASK, 684 rx_mask); 685 regmap_update_bits(max98396->regmap, 686 MAX98396_R2056_PCM_RX_SRC2, 687 MAX98396_PCM_DMIX_CH1_SRC_MASK, 688 rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT); 689 } else { 690 regmap_update_bits(max98396->regmap, 691 MAX98397_R2057_PCM_RX_SRC2, 692 MAX98396_PCM_DMIX_CH0_SRC_MASK, 693 rx_mask); 694 regmap_update_bits(max98396->regmap, 695 MAX98397_R2057_PCM_RX_SRC2, 696 MAX98396_PCM_DMIX_CH1_SRC_MASK, 697 rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT); 698 } 699 700 /* Tx slot Hi-Z configuration */ 701 if (max98396->device_id == CODEC_TYPE_MAX98396) { 702 regmap_write(max98396->regmap, 703 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 704 ~tx_mask & 0xFF); 705 regmap_write(max98396->regmap, 706 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 707 (~tx_mask & 0xFF00) >> 8); 708 } else { 709 regmap_write(max98396->regmap, 710 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 711 ~tx_mask & 0xFF); 712 regmap_write(max98396->regmap, 713 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 714 (~tx_mask & 0xFF00) >> 8); 715 } 716 717 if (status && update) 718 max98396_global_enable_onoff(max98396->regmap, true); 719 720 return 0; 721 } 722 723 #define MAX98396_RATES SNDRV_PCM_RATE_8000_192000 724 725 #define MAX98396_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 726 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 727 728 static const struct snd_soc_dai_ops max98396_dai_ops = { 729 .set_fmt = max98396_dai_set_fmt, 730 .hw_params = max98396_dai_hw_params, 731 .set_tdm_slot = max98396_dai_tdm_slot, 732 }; 733 734 static int max98396_dac_event(struct snd_soc_dapm_widget *w, 735 struct snd_kcontrol *kcontrol, int event) 736 { 737 struct snd_soc_component *component = 738 snd_soc_dapm_to_component(w->dapm); 739 struct max98396_priv *max98396 = 740 snd_soc_component_get_drvdata(component); 741 742 switch (event) { 743 case SND_SOC_DAPM_POST_PMU: 744 max98396_global_enable_onoff(max98396->regmap, true); 745 break; 746 case SND_SOC_DAPM_PRE_PMD: 747 max98396_global_enable_onoff(max98396->regmap, false); 748 749 max98396->tdm_mode = false; 750 break; 751 default: 752 return 0; 753 } 754 return 0; 755 } 756 757 static bool max98396_readable_register(struct device *dev, unsigned int reg) 758 { 759 switch (reg) { 760 case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4: 761 case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4: 762 case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4: 763 case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4: 764 case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4: 765 case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET: 766 case MAX98396_R2027_THERM_FOLDBACK_EN: 767 case MAX98396_R2030_NOISEGATE_MODE_CTRL: 768 case MAX98396_R2033_NOISEGATE_MODE_EN: 769 case MAX98396_R2038_CLK_MON_CTRL ... MAX98396_R2039_DATA_MON_CTRL: 770 case MAX98396_R203F_ENABLE_CTRLS ... MAX98396_R2053_PCM_TX_HIZ_CTRL_8: 771 case MAX98396_R2055_PCM_RX_SRC1 ... MAX98396_R2056_PCM_RX_SRC2: 772 case MAX98396_R2058_PCM_BYPASS_SRC: 773 case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98396_R205F_PCM_TX_EN: 774 case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL: 775 case MAX98396_R207F_ICC_EN: 776 case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3: 777 case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209A_SPK_EDGE_CTRL: 778 case MAX98396_R209C_SPK_EDGE_CTRL1 ... MAX98396_R20A0_AMP_SUPPLY_CTL: 779 case MAX98396_R20AF_AMP_EN ... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB: 780 case MAX98396_R20C7_ADC_CFG: 781 case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG: 782 case MAX98396_R20DF_DHT_EN: 783 case MAX98396_R20E0_IV_SENSE_PATH_CFG: 784 case MAX98396_R20E4_IV_SENSE_PATH_EN 785 ... MAX98396_R2106_BPE_THRESH_HYSTERESIS: 786 case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER: 787 case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN: 788 case MAX98396_R21FF_REVISION_ID: 789 return true; 790 default: 791 return false; 792 } 793 }; 794 795 static bool max98396_volatile_reg(struct device *dev, unsigned int reg) 796 { 797 switch (reg) { 798 case MAX98396_R2000_SW_RESET: 799 case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4: 800 case MAX98396_R2041_PCM_MODE_CFG: 801 case MAX98396_R20B6_ADC_PVDD_READBACK_MSB 802 ... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB: 803 case MAX98396_R20E5_BPE_STATE: 804 case MAX98396_R2109_BPE_LOW_STATE 805 ... MAX98396_R210B_BPE_LOW_LIMITER: 806 case MAX98396_R210F_GLOBAL_EN: 807 case MAX98396_R21FF_REVISION_ID: 808 return true; 809 default: 810 return false; 811 } 812 } 813 814 static bool max98397_readable_register(struct device *dev, unsigned int reg) 815 { 816 switch (reg) { 817 case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4: 818 case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4: 819 case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4: 820 case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4: 821 case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4: 822 case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET: 823 case MAX98396_R2027_THERM_FOLDBACK_EN: 824 case MAX98396_R2030_NOISEGATE_MODE_CTRL: 825 case MAX98396_R2033_NOISEGATE_MODE_EN: 826 case MAX98396_R2038_CLK_MON_CTRL ... MAX98397_R203A_SPK_MON_THRESH: 827 case MAX98396_R203F_ENABLE_CTRLS ... MAX98397_R2054_PCM_TX_HIZ_CTRL_8: 828 case MAX98397_R2056_PCM_RX_SRC1... MAX98396_R2058_PCM_BYPASS_SRC: 829 case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98397_R2060_PCM_TX_SUPPLY_SEL: 830 case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL: 831 case MAX98396_R207F_ICC_EN: 832 case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3: 833 case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209F_BYPASS_PATH_CFG: 834 case MAX98396_R20AF_AMP_EN ... MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE: 835 case MAX98396_R20C7_ADC_CFG: 836 case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG: 837 case MAX98396_R20DF_DHT_EN: 838 case MAX98396_R20E0_IV_SENSE_PATH_CFG: 839 case MAX98396_R20E4_IV_SENSE_PATH_EN 840 ... MAX98396_R2106_BPE_THRESH_HYSTERESIS: 841 case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER: 842 case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN: 843 case MAX98397_R22FF_REVISION_ID: 844 return true; 845 default: 846 return false; 847 } 848 }; 849 850 static bool max98397_volatile_reg(struct device *dev, unsigned int reg) 851 { 852 switch (reg) { 853 case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4: 854 case MAX98396_R2041_PCM_MODE_CFG: 855 case MAX98397_R20B7_ADC_PVDD_READBACK_MSB 856 ... MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB: 857 case MAX98396_R20E5_BPE_STATE: 858 case MAX98396_R2109_BPE_LOW_STATE 859 ... MAX98396_R210B_BPE_LOW_LIMITER: 860 case MAX98396_R210F_GLOBAL_EN: 861 case MAX98397_R22FF_REVISION_ID: 862 return true; 863 default: 864 return false; 865 } 866 } 867 868 static const char * const max98396_op_mod_text[] = { 869 "DG", "PVDD", "VBAT", 870 }; 871 872 static SOC_ENUM_SINGLE_DECL(max98396_op_mod_enum, 873 MAX98396_R2098_SPK_CLS_DG_MODE, 874 0, max98396_op_mod_text); 875 876 static DECLARE_TLV_DB_SCALE(max98396_digital_tlv, -6350, 50, 1); 877 static const DECLARE_TLV_DB_RANGE(max98396_spk_tlv, 878 0, 0x11, TLV_DB_SCALE_ITEM(400, 100, 0), 879 ); 880 static DECLARE_TLV_DB_RANGE(max98397_digital_tlv, 881 0, 0x4A, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 882 0x4B, 0xFF, TLV_DB_SCALE_ITEM(-9000, 50, 0), 883 ); 884 static const DECLARE_TLV_DB_RANGE(max98397_spk_tlv, 885 0, 0x15, TLV_DB_SCALE_ITEM(600, 100, 0), 886 ); 887 888 static int max98396_mux_get(struct snd_kcontrol *kcontrol, 889 struct snd_ctl_elem_value *ucontrol) 890 { 891 struct snd_soc_component *component = 892 snd_soc_dapm_kcontrol_component(kcontrol); 893 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 894 int reg, val; 895 896 if (max98396->device_id == CODEC_TYPE_MAX98396) 897 reg = MAX98396_R2055_PCM_RX_SRC1; 898 else 899 reg = MAX98397_R2056_PCM_RX_SRC1; 900 901 regmap_read(max98396->regmap, reg, &val); 902 903 ucontrol->value.enumerated.item[0] = val; 904 905 return 0; 906 } 907 908 static int max98396_mux_put(struct snd_kcontrol *kcontrol, 909 struct snd_ctl_elem_value *ucontrol) 910 { 911 struct snd_soc_component *component = 912 snd_soc_dapm_kcontrol_component(kcontrol); 913 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); 914 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 915 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 916 unsigned int *item = ucontrol->value.enumerated.item; 917 int reg, val; 918 int change; 919 920 if (item[0] >= e->items) 921 return -EINVAL; 922 923 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 924 925 if (max98396->device_id == CODEC_TYPE_MAX98396) 926 reg = MAX98396_R2055_PCM_RX_SRC1; 927 else 928 reg = MAX98397_R2056_PCM_RX_SRC1; 929 930 change = snd_soc_component_test_bits(component, reg, 931 MAX98396_PCM_RX_MASK, val); 932 933 if (change) 934 regmap_update_bits(max98396->regmap, reg, 935 MAX98396_PCM_RX_MASK, val); 936 937 snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL); 938 939 return change; 940 } 941 942 static const char * const max98396_switch_text[] = { 943 "Left", "Right", "LeftRight"}; 944 945 static SOC_ENUM_SINGLE_DECL(dai_sel_enum, SND_SOC_NOPM, 0, 946 max98396_switch_text); 947 948 static const struct snd_kcontrol_new max98396_dai_mux = 949 SOC_DAPM_ENUM_EXT("DAI Sel Mux", dai_sel_enum, 950 max98396_mux_get, max98396_mux_put); 951 952 static const struct snd_kcontrol_new max98396_vi_control = 953 SOC_DAPM_SINGLE("Switch", MAX98396_R205F_PCM_TX_EN, 0, 1, 0); 954 955 static const struct snd_soc_dapm_widget max98396_dapm_widgets[] = { 956 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 957 MAX98396_R20AF_AMP_EN, 0, 0, max98396_dac_event, 958 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 959 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 960 &max98396_dai_mux), 961 SND_SOC_DAPM_OUTPUT("BE_OUT"), 962 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 963 MAX98396_R20E4_IV_SENSE_PATH_EN, 0, 0), 964 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 965 MAX98396_R20E4_IV_SENSE_PATH_EN, 1, 0), 966 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 967 &max98396_vi_control), 968 SND_SOC_DAPM_SIGGEN("VMON"), 969 SND_SOC_DAPM_SIGGEN("IMON"), 970 SND_SOC_DAPM_SIGGEN("FBMON"), 971 }; 972 973 static const char * const max98396_thermal_thresh_text[] = { 974 "50C", "51C", "52C", "53C", "54C", "55C", "56C", "57C", 975 "58C", "59C", "60C", "61C", "62C", "63C", "64C", "65C", 976 "66C", "67C", "68C", "69C", "70C", "71C", "72C", "73C", 977 "74C", "75C", "76C", "77C", "78C", "79C", "80C", "81C", 978 "82C", "83C", "84C", "85C", "86C", "87C", "88C", "89C", 979 "90C", "91C", "92C", "93C", "94C", "95C", "96C", "97C", 980 "98C", "99C", "100C", "101C", "102C", "103C", "104C", "105C", 981 "106C", "107C", "108C", "109C", "110C", "111C", "112C", "113C", 982 "114C", "115C", "116C", "117C", "118C", "119C", "120C", "121C", 983 "122C", "123C", "124C", "125C", "126C", "127C", "128C", "129C", 984 "130C", "131C", "132C", "133C", "134C", "135C", "136C", "137C", 985 "138C", "139C", "140C", "141C", "142C", "143C", "144C", "145C", 986 "146C", "147C", "148C", "149C", "150C" 987 }; 988 989 static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh1_enum, 990 MAX98396_R2020_THERM_WARN_THRESH, 0, 991 max98396_thermal_thresh_text); 992 993 static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh2_enum, 994 MAX98396_R2021_THERM_WARN_THRESH2, 0, 995 max98396_thermal_thresh_text); 996 997 static SOC_ENUM_SINGLE_DECL(max98396_thermal_shdn_thresh_enum, 998 MAX98396_R2022_THERM_SHDN_THRESH, 0, 999 max98396_thermal_thresh_text); 1000 1001 static const char * const max98396_thermal_hyteresis_text[] = { 1002 "2C", "5C", "7C", "10C" 1003 }; 1004 1005 static SOC_ENUM_SINGLE_DECL(max98396_thermal_hysteresis_enum, 1006 MAX98396_R2023_THERM_HYSTERESIS, 0, 1007 max98396_thermal_hyteresis_text); 1008 1009 static const char * const max98396_foldback_slope_text[] = { 1010 "0.25", "0.5", "1.0", "2.0" 1011 }; 1012 1013 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope1_enum, 1014 MAX98396_R2024_THERM_FOLDBACK_SET, 1015 MAX98396_THERM_FB_SLOPE1_SHIFT, 1016 max98396_foldback_slope_text); 1017 1018 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope2_enum, 1019 MAX98396_R2024_THERM_FOLDBACK_SET, 1020 MAX98396_THERM_FB_SLOPE2_SHIFT, 1021 max98396_foldback_slope_text); 1022 1023 static const char * const max98396_foldback_reltime_text[] = { 1024 "3ms", "10ms", "100ms", "300ms" 1025 }; 1026 1027 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_reltime_enum, 1028 MAX98396_R2024_THERM_FOLDBACK_SET, 1029 MAX98396_THERM_FB_REL_SHIFT, 1030 max98396_foldback_reltime_text); 1031 1032 static const char * const max98396_foldback_holdtime_text[] = { 1033 "0ms", "20ms", "40ms", "80ms" 1034 }; 1035 1036 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_holdtime_enum, 1037 MAX98396_R2024_THERM_FOLDBACK_SET, 1038 MAX98396_THERM_FB_HOLD_SHIFT, 1039 max98396_foldback_holdtime_text); 1040 1041 static int max98396_adc_value_get(struct snd_kcontrol *kcontrol, 1042 struct snd_ctl_elem_value *ucontrol) 1043 { 1044 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1045 struct soc_mixer_control *mc = 1046 (struct soc_mixer_control *)kcontrol->private_value; 1047 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 1048 int ret; 1049 u8 val[2]; 1050 int reg = mc->reg; 1051 1052 /* ADC value is not available if the device is powered down */ 1053 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 1054 goto exit; 1055 1056 if (max98396->device_id == CODEC_TYPE_MAX98397) { 1057 switch (mc->reg) { 1058 case MAX98396_R20B6_ADC_PVDD_READBACK_MSB: 1059 reg = MAX98397_R20B7_ADC_PVDD_READBACK_MSB; 1060 break; 1061 case MAX98396_R20B8_ADC_VBAT_READBACK_MSB: 1062 reg = MAX98397_R20B9_ADC_VBAT_READBACK_MSB; 1063 break; 1064 case MAX98396_R20BA_ADC_TEMP_READBACK_MSB: 1065 reg = MAX98397_R20BB_ADC_TEMP_READBACK_MSB; 1066 break; 1067 default: 1068 goto exit; 1069 } 1070 } 1071 1072 ret = regmap_raw_read(max98396->regmap, reg, &val, 2); 1073 if (ret) 1074 goto exit; 1075 1076 /* ADC readback bits[8:0] rearrangement */ 1077 ucontrol->value.integer.value[0] = (val[0] << 1) | (val[1] & 1); 1078 return 0; 1079 1080 exit: 1081 ucontrol->value.integer.value[0] = 0; 1082 return 0; 1083 } 1084 1085 static const struct snd_kcontrol_new max98396_snd_controls[] = { 1086 /* Volume */ 1087 SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL, 1088 0, 0x7F, 1, max98396_digital_tlv), 1089 SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN, 1090 0, 0x11, 0, max98396_spk_tlv), 1091 /* Volume Ramp Up/Down Enable*/ 1092 SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG, 1093 MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0), 1094 SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG, 1095 MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0), 1096 /* Clock Monitor Enable */ 1097 SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS, 1098 MAX98396_CTRL_CMON_EN_SHIFT, 1, 0), 1099 /* Dither Enable */ 1100 SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG, 1101 MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0), 1102 SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1103 MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0), 1104 /* DC Blocker Enable */ 1105 SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG, 1106 MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0), 1107 SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1108 MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0), 1109 /* Speaker Safe Mode Enable */ 1110 SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG, 1111 MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0), 1112 /* Wideband Filter Enable */ 1113 SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG, 1114 MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0), 1115 SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1116 MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0), 1117 /* Dynamic Headroom Tracking */ 1118 SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0), 1119 /* Brownout Protection Engine */ 1120 SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0), 1121 SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0), 1122 /* Bypass Path Enable */ 1123 SOC_SINGLE("Bypass Path Switch", 1124 MAX98396_R205E_PCM_RX_EN, 1, 1, 0), 1125 /* Speaker Operation Mode */ 1126 SOC_ENUM("OP Mode", max98396_op_mod_enum), 1127 /* Auto Restart functions */ 1128 SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL, 1129 MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0), 1130 SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1131 MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0), 1132 SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1133 MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0), 1134 SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1135 MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0), 1136 SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1137 MAX98396_OVC_RESTART_SHFT, 1, 0), 1138 /* Thermal Threshold */ 1139 SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum), 1140 SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum), 1141 SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum), 1142 SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum), 1143 SOC_SINGLE("THERM Foldback Switch", 1144 MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0), 1145 SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum), 1146 SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum), 1147 SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum), 1148 SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum), 1149 /* ADC */ 1150 SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0, 1151 max98396_adc_value_get, NULL), 1152 SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0, 1153 max98396_adc_value_get, NULL), 1154 SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0, 1155 max98396_adc_value_get, NULL), 1156 }; 1157 1158 static const struct snd_kcontrol_new max98397_snd_controls[] = { 1159 /* Volume */ 1160 SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL, 1161 0, 0xFF, 1, max98397_digital_tlv), 1162 SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN, 1163 0, 0x15, 0, max98397_spk_tlv), 1164 /* Volume Ramp Up/Down Enable*/ 1165 SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG, 1166 MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0), 1167 SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG, 1168 MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0), 1169 /* Clock Monitor Enable */ 1170 SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS, 1171 MAX98396_CTRL_CMON_EN_SHIFT, 1, 0), 1172 /* Dither Enable */ 1173 SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG, 1174 MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0), 1175 SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1176 MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0), 1177 /* DC Blocker Enable */ 1178 SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG, 1179 MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0), 1180 SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1181 MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0), 1182 /* Speaker Safe Mode Enable */ 1183 SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG, 1184 MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0), 1185 /* Wideband Filter Enable */ 1186 SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG, 1187 MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0), 1188 SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1189 MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0), 1190 /* Dynamic Headroom Tracking */ 1191 SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0), 1192 /* Brownout Protection Engine */ 1193 SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0), 1194 SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0), 1195 /* Bypass Path Enable */ 1196 SOC_SINGLE("Bypass Path Switch", 1197 MAX98396_R205E_PCM_RX_EN, 1, 1, 0), 1198 /* Speaker Operation Mode */ 1199 SOC_ENUM("OP Mode", max98396_op_mod_enum), 1200 /* Auto Restart functions */ 1201 SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL, 1202 MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0), 1203 SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1204 MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0), 1205 SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1206 MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0), 1207 SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1208 MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0), 1209 SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1210 MAX98396_OVC_RESTART_SHFT, 1, 0), 1211 /* Thermal Threshold */ 1212 SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum), 1213 SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum), 1214 SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum), 1215 SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum), 1216 SOC_SINGLE("THERM Foldback Switch", 1217 MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0), 1218 SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum), 1219 SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum), 1220 SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum), 1221 SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum), 1222 /* ADC */ 1223 SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0, 1224 max98396_adc_value_get, NULL), 1225 SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0, 1226 max98396_adc_value_get, NULL), 1227 SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0, 1228 max98396_adc_value_get, NULL), 1229 }; 1230 1231 static const struct snd_soc_dapm_route max98396_audio_map[] = { 1232 /* Plabyack */ 1233 {"DAI Sel Mux", "Left", "Amp Enable"}, 1234 {"DAI Sel Mux", "Right", "Amp Enable"}, 1235 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 1236 {"BE_OUT", NULL, "DAI Sel Mux"}, 1237 /* Capture */ 1238 { "VI Sense", "Switch", "VMON" }, 1239 { "VI Sense", "Switch", "IMON" }, 1240 { "Voltage Sense", NULL, "VI Sense" }, 1241 { "Current Sense", NULL, "VI Sense" }, 1242 }; 1243 1244 static struct snd_soc_dai_driver max98396_dai[] = { 1245 { 1246 .name = "max98396-aif1", 1247 .playback = { 1248 .stream_name = "HiFi Playback", 1249 .channels_min = 1, 1250 .channels_max = 2, 1251 .rates = MAX98396_RATES, 1252 .formats = MAX98396_FORMATS, 1253 }, 1254 .capture = { 1255 .stream_name = "HiFi Capture", 1256 .channels_min = 1, 1257 .channels_max = 2, 1258 .rates = MAX98396_RATES, 1259 .formats = MAX98396_FORMATS, 1260 }, 1261 .ops = &max98396_dai_ops, 1262 } 1263 }; 1264 1265 static struct snd_soc_dai_driver max98397_dai[] = { 1266 { 1267 .name = "max98397-aif1", 1268 .playback = { 1269 .stream_name = "HiFi Playback", 1270 .channels_min = 1, 1271 .channels_max = 2, 1272 .rates = MAX98396_RATES, 1273 .formats = MAX98396_FORMATS, 1274 }, 1275 .capture = { 1276 .stream_name = "HiFi Capture", 1277 .channels_min = 1, 1278 .channels_max = 2, 1279 .rates = MAX98396_RATES, 1280 .formats = MAX98396_FORMATS, 1281 }, 1282 .ops = &max98396_dai_ops, 1283 } 1284 }; 1285 1286 static void max98396_reset(struct max98396_priv *max98396, struct device *dev) 1287 { 1288 int ret, reg, count; 1289 1290 /* Software Reset */ 1291 ret = regmap_write(max98396->regmap, 1292 MAX98396_R2000_SW_RESET, 1); 1293 if (ret) 1294 dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 1295 1296 count = 0; 1297 while (count < 3) { 1298 usleep_range(5000, 6000); 1299 /* Software Reset Verification */ 1300 ret = regmap_read(max98396->regmap, 1301 GET_REG_ADDR_REV_ID(max98396->device_id), ®); 1302 if (!ret) { 1303 dev_info(dev, "Reset completed (retry:%d)\n", count); 1304 return; 1305 } 1306 count++; 1307 } 1308 dev_err(dev, "Reset failed. (ret:%d)\n", ret); 1309 } 1310 1311 static int max98396_probe(struct snd_soc_component *component) 1312 { 1313 struct max98396_priv *max98396 = 1314 snd_soc_component_get_drvdata(component); 1315 1316 /* Software Reset */ 1317 max98396_reset(max98396, component->dev); 1318 1319 /* L/R mix configuration */ 1320 if (max98396->device_id == CODEC_TYPE_MAX98396) { 1321 regmap_write(max98396->regmap, 1322 MAX98396_R2055_PCM_RX_SRC1, 0x02); 1323 regmap_write(max98396->regmap, 1324 MAX98396_R2056_PCM_RX_SRC2, 0x10); 1325 } else { 1326 regmap_write(max98396->regmap, 1327 MAX98397_R2056_PCM_RX_SRC1, 0x02); 1328 regmap_write(max98396->regmap, 1329 MAX98397_R2057_PCM_RX_SRC2, 0x10); 1330 } 1331 /* Enable DC blocker */ 1332 regmap_update_bits(max98396->regmap, 1333 MAX98396_R2092_AMP_DSP_CFG, 1, 1); 1334 /* Enable IV Monitor DC blocker */ 1335 regmap_update_bits(max98396->regmap, 1336 MAX98396_R20E0_IV_SENSE_PATH_CFG, 1337 MAX98396_IV_SENSE_DCBLK_EN_MASK, 1338 MAX98396_IV_SENSE_DCBLK_EN_MASK); 1339 /* Configure default data output sources */ 1340 regmap_write(max98396->regmap, 1341 MAX98396_R205D_PCM_TX_SRC_EN, 3); 1342 /* Enable Wideband Filter */ 1343 regmap_update_bits(max98396->regmap, 1344 MAX98396_R2092_AMP_DSP_CFG, 0x40, 0x40); 1345 /* Enable IV Wideband Filter */ 1346 regmap_update_bits(max98396->regmap, 1347 MAX98396_R20E0_IV_SENSE_PATH_CFG, 8, 8); 1348 1349 /* Enable Bypass Source */ 1350 regmap_write(max98396->regmap, 1351 MAX98396_R2058_PCM_BYPASS_SRC, 1352 max98396->bypass_slot); 1353 /* Voltage, current slot configuration */ 1354 regmap_write(max98396->regmap, 1355 MAX98396_R2044_PCM_TX_CTRL_1, 1356 max98396->v_slot); 1357 regmap_write(max98396->regmap, 1358 MAX98396_R2045_PCM_TX_CTRL_2, 1359 max98396->i_slot); 1360 1361 if (max98396->v_slot < 8) 1362 if (max98396->device_id == CODEC_TYPE_MAX98396) 1363 regmap_update_bits(max98396->regmap, 1364 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 1365 1 << max98396->v_slot, 0); 1366 else 1367 regmap_update_bits(max98396->regmap, 1368 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 1369 1 << max98396->v_slot, 0); 1370 else 1371 if (max98396->device_id == CODEC_TYPE_MAX98396) 1372 regmap_update_bits(max98396->regmap, 1373 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 1374 1 << (max98396->v_slot - 8), 0); 1375 else 1376 regmap_update_bits(max98396->regmap, 1377 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 1378 1 << (max98396->v_slot - 8), 0); 1379 1380 if (max98396->i_slot < 8) 1381 if (max98396->device_id == CODEC_TYPE_MAX98396) 1382 regmap_update_bits(max98396->regmap, 1383 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 1384 1 << max98396->i_slot, 0); 1385 else 1386 regmap_update_bits(max98396->regmap, 1387 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 1388 1 << max98396->i_slot, 0); 1389 else 1390 if (max98396->device_id == CODEC_TYPE_MAX98396) 1391 regmap_update_bits(max98396->regmap, 1392 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 1393 1 << (max98396->i_slot - 8), 0); 1394 else 1395 regmap_update_bits(max98396->regmap, 1396 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 1397 1 << (max98396->i_slot - 8), 0); 1398 1399 /* Set interleave mode */ 1400 if (max98396->interleave_mode) 1401 regmap_update_bits(max98396->regmap, 1402 MAX98396_R2041_PCM_MODE_CFG, 1403 MAX98396_PCM_TX_CH_INTERLEAVE_MASK, 1404 MAX98396_PCM_TX_CH_INTERLEAVE_MASK); 1405 1406 regmap_update_bits(max98396->regmap, 1407 MAX98396_R2038_CLK_MON_CTRL, 1408 MAX98396_CLK_MON_AUTO_RESTART_MASK, 1409 MAX98396_CLK_MON_AUTO_RESTART_MASK); 1410 1411 /* Speaker Amplifier PCM RX Enable by default */ 1412 regmap_update_bits(max98396->regmap, 1413 MAX98396_R205E_PCM_RX_EN, 1414 MAX98396_PCM_RX_EN_MASK, 1); 1415 1416 return 0; 1417 } 1418 1419 #ifdef CONFIG_PM_SLEEP 1420 static int max98396_suspend(struct device *dev) 1421 { 1422 struct max98396_priv *max98396 = dev_get_drvdata(dev); 1423 1424 regcache_cache_only(max98396->regmap, true); 1425 regcache_mark_dirty(max98396->regmap); 1426 return 0; 1427 } 1428 1429 static int max98396_resume(struct device *dev) 1430 { 1431 struct max98396_priv *max98396 = dev_get_drvdata(dev); 1432 1433 regcache_cache_only(max98396->regmap, false); 1434 max98396_reset(max98396, dev); 1435 regcache_sync(max98396->regmap); 1436 return 0; 1437 } 1438 #endif 1439 1440 static const struct dev_pm_ops max98396_pm = { 1441 SET_SYSTEM_SLEEP_PM_OPS(max98396_suspend, max98396_resume) 1442 }; 1443 1444 static const struct snd_soc_component_driver soc_codec_dev_max98396 = { 1445 .probe = max98396_probe, 1446 .controls = max98396_snd_controls, 1447 .num_controls = ARRAY_SIZE(max98396_snd_controls), 1448 .dapm_widgets = max98396_dapm_widgets, 1449 .num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets), 1450 .dapm_routes = max98396_audio_map, 1451 .num_dapm_routes = ARRAY_SIZE(max98396_audio_map), 1452 .idle_bias_on = 1, 1453 .use_pmdown_time = 1, 1454 .endianness = 1, 1455 .non_legacy_dai_naming = 1, 1456 }; 1457 1458 static const struct snd_soc_component_driver soc_codec_dev_max98397 = { 1459 .probe = max98396_probe, 1460 .controls = max98397_snd_controls, 1461 .num_controls = ARRAY_SIZE(max98397_snd_controls), 1462 .dapm_widgets = max98396_dapm_widgets, 1463 .num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets), 1464 .dapm_routes = max98396_audio_map, 1465 .num_dapm_routes = ARRAY_SIZE(max98396_audio_map), 1466 .idle_bias_on = 1, 1467 .use_pmdown_time = 1, 1468 .endianness = 1, 1469 .non_legacy_dai_naming = 1, 1470 }; 1471 1472 static const struct regmap_config max98396_regmap = { 1473 .reg_bits = 16, 1474 .val_bits = 8, 1475 .max_register = MAX98396_R21FF_REVISION_ID, 1476 .reg_defaults = max98396_reg, 1477 .num_reg_defaults = ARRAY_SIZE(max98396_reg), 1478 .readable_reg = max98396_readable_register, 1479 .volatile_reg = max98396_volatile_reg, 1480 .cache_type = REGCACHE_RBTREE, 1481 }; 1482 1483 static const struct regmap_config max98397_regmap = { 1484 .reg_bits = 16, 1485 .val_bits = 8, 1486 .max_register = MAX98397_R22FF_REVISION_ID, 1487 .reg_defaults = max98397_reg, 1488 .num_reg_defaults = ARRAY_SIZE(max98397_reg), 1489 .readable_reg = max98397_readable_register, 1490 .volatile_reg = max98397_volatile_reg, 1491 .cache_type = REGCACHE_RBTREE, 1492 }; 1493 1494 static void max98396_read_device_property(struct device *dev, 1495 struct max98396_priv *max98396) 1496 { 1497 int value; 1498 1499 if (!device_property_read_u32(dev, "adi,vmon-slot-no", &value)) 1500 max98396->v_slot = value & 0xF; 1501 else 1502 max98396->v_slot = 0; 1503 1504 if (!device_property_read_u32(dev, "adi,imon-slot-no", &value)) 1505 max98396->i_slot = value & 0xF; 1506 else 1507 max98396->i_slot = 1; 1508 1509 if (!device_property_read_u32(dev, "adi,bypass-slot-no", &value)) 1510 max98396->bypass_slot = value & 0xF; 1511 else 1512 max98396->bypass_slot = 0; 1513 } 1514 1515 static int max98396_i2c_probe(struct i2c_client *i2c, 1516 const struct i2c_device_id *id) 1517 { 1518 struct max98396_priv *max98396 = NULL; 1519 int ret, reg; 1520 1521 max98396 = devm_kzalloc(&i2c->dev, sizeof(*max98396), GFP_KERNEL); 1522 1523 if (!max98396) { 1524 ret = -ENOMEM; 1525 return ret; 1526 } 1527 i2c_set_clientdata(i2c, max98396); 1528 1529 max98396->device_id = id->driver_data; 1530 1531 /* regmap initialization */ 1532 if (max98396->device_id == CODEC_TYPE_MAX98396) 1533 max98396->regmap = devm_regmap_init_i2c(i2c, &max98396_regmap); 1534 1535 else 1536 max98396->regmap = devm_regmap_init_i2c(i2c, &max98397_regmap); 1537 1538 if (IS_ERR(max98396->regmap)) { 1539 ret = PTR_ERR(max98396->regmap); 1540 dev_err(&i2c->dev, 1541 "Failed to allocate regmap: %d\n", ret); 1542 return ret; 1543 } 1544 1545 /* update interleave mode info */ 1546 if (device_property_read_bool(&i2c->dev, "adi,interleave_mode")) 1547 max98396->interleave_mode = true; 1548 else 1549 max98396->interleave_mode = false; 1550 1551 /* voltage/current slot & gpio configuration */ 1552 max98396_read_device_property(&i2c->dev, max98396); 1553 1554 /* Reset the Device */ 1555 max98396->reset_gpio = devm_gpiod_get_optional(&i2c->dev, 1556 "reset", GPIOD_OUT_HIGH); 1557 if (IS_ERR(max98396->reset_gpio)) { 1558 ret = PTR_ERR(max98396->reset_gpio); 1559 dev_err(&i2c->dev, "Unable to request GPIO pin: %d.\n", ret); 1560 return ret; 1561 } 1562 1563 if (max98396->reset_gpio) { 1564 usleep_range(5000, 6000); 1565 gpiod_set_value_cansleep(max98396->reset_gpio, 0); 1566 /* Wait for the hw reset done */ 1567 usleep_range(5000, 6000); 1568 } 1569 1570 ret = regmap_read(max98396->regmap, 1571 GET_REG_ADDR_REV_ID(max98396->device_id), ®); 1572 if (ret < 0) { 1573 dev_err(&i2c->dev, "%s: failed to read revision of the device.\n", id->name); 1574 return ret; 1575 } 1576 dev_info(&i2c->dev, "%s revision ID: 0x%02X\n", id->name, reg); 1577 1578 /* codec registration */ 1579 if (max98396->device_id == CODEC_TYPE_MAX98396) 1580 ret = devm_snd_soc_register_component(&i2c->dev, 1581 &soc_codec_dev_max98396, 1582 max98396_dai, 1583 ARRAY_SIZE(max98396_dai)); 1584 else 1585 ret = devm_snd_soc_register_component(&i2c->dev, 1586 &soc_codec_dev_max98397, 1587 max98397_dai, 1588 ARRAY_SIZE(max98397_dai)); 1589 if (ret < 0) 1590 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 1591 1592 return ret; 1593 } 1594 1595 static const struct i2c_device_id max98396_i2c_id[] = { 1596 { "max98396", CODEC_TYPE_MAX98396}, 1597 { "max98397", CODEC_TYPE_MAX98397}, 1598 { }, 1599 }; 1600 1601 MODULE_DEVICE_TABLE(i2c, max98396_i2c_id); 1602 1603 #if defined(CONFIG_OF) 1604 static const struct of_device_id max98396_of_match[] = { 1605 { .compatible = "adi,max98396", }, 1606 { .compatible = "adi,max98397", }, 1607 { } 1608 }; 1609 MODULE_DEVICE_TABLE(of, max98396_of_match); 1610 #endif 1611 1612 #ifdef CONFIG_ACPI 1613 static const struct acpi_device_id max98396_acpi_match[] = { 1614 { "ADS8396", 0 }, 1615 { "ADS8397", 0 }, 1616 {}, 1617 }; 1618 MODULE_DEVICE_TABLE(acpi, max98396_acpi_match); 1619 #endif 1620 1621 static struct i2c_driver max98396_i2c_driver = { 1622 .driver = { 1623 .name = "max98396", 1624 .of_match_table = of_match_ptr(max98396_of_match), 1625 .acpi_match_table = ACPI_PTR(max98396_acpi_match), 1626 .pm = &max98396_pm, 1627 }, 1628 .probe = max98396_i2c_probe, 1629 .id_table = max98396_i2c_id, 1630 }; 1631 1632 module_i2c_driver(max98396_i2c_driver) 1633 1634 MODULE_DESCRIPTION("ALSA SoC MAX98396 driver"); 1635 MODULE_AUTHOR("Ryan Lee <ryans.lee@analog.com>"); 1636 MODULE_LICENSE("GPL"); 1637