1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/i2c.h> 7 #include <linux/module.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/regmap.h> 10 #include <linux/slab.h> 11 #include <linux/cdev.h> 12 #include <sound/pcm.h> 13 #include <sound/pcm_params.h> 14 #include <sound/soc.h> 15 #include <linux/gpio.h> 16 #include <linux/of.h> 17 #include <linux/of_gpio.h> 18 #include <sound/tlv.h> 19 #include "max98373.h" 20 21 static int max98373_dac_event(struct snd_soc_dapm_widget *w, 22 struct snd_kcontrol *kcontrol, int event) 23 { 24 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 25 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 26 27 switch (event) { 28 case SND_SOC_DAPM_POST_PMU: 29 regmap_update_bits(max98373->regmap, 30 MAX98373_R20FF_GLOBAL_SHDN, 31 MAX98373_GLOBAL_EN_MASK, 1); 32 usleep_range(30000, 31000); 33 break; 34 case SND_SOC_DAPM_POST_PMD: 35 regmap_update_bits(max98373->regmap, 36 MAX98373_R20FF_GLOBAL_SHDN, 37 MAX98373_GLOBAL_EN_MASK, 0); 38 usleep_range(30000, 31000); 39 max98373->tdm_mode = false; 40 break; 41 default: 42 return 0; 43 } 44 return 0; 45 } 46 47 static const char * const max98373_switch_text[] = { 48 "Left", "Right", "LeftRight"}; 49 50 static const struct soc_enum dai_sel_enum = 51 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 52 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 53 3, max98373_switch_text); 54 55 static const struct snd_kcontrol_new max98373_dai_controls = 56 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 57 58 static const struct snd_kcontrol_new max98373_vi_control = 59 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0); 60 61 static const struct snd_kcontrol_new max98373_spkfb_control = 62 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0); 63 64 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = { 65 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 66 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event, 67 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 68 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 69 &max98373_dai_controls), 70 SND_SOC_DAPM_OUTPUT("BE_OUT"), 71 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 72 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0), 73 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 74 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0), 75 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0, 76 SND_SOC_NOPM, 0, 0), 77 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 78 &max98373_vi_control), 79 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0, 80 &max98373_spkfb_control), 81 SND_SOC_DAPM_SIGGEN("VMON"), 82 SND_SOC_DAPM_SIGGEN("IMON"), 83 SND_SOC_DAPM_SIGGEN("FBMON"), 84 }; 85 86 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1); 87 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv, 88 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0), 89 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0), 90 ); 91 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv, 92 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 93 ); 94 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv, 95 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0), 96 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0), 97 ); 98 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv, 99 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 100 ); 101 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv, 102 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0), 103 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0), 104 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0), 105 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0), 106 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0), 107 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0), 108 ); 109 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv, 110 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0), 111 ); 112 113 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv, 114 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0), 115 ); 116 117 static const char * const max98373_output_voltage_lvl_text[] = { 118 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V", 119 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V" 120 }; 121 122 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum, 123 MAX98373_R203E_AMP_PATH_GAIN, 0, 124 max98373_output_voltage_lvl_text); 125 126 static const char * const max98373_dht_attack_rate_text[] = { 127 "17.5us", "35us", "70us", "140us", 128 "280us", "560us", "1120us", "2240us" 129 }; 130 131 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum, 132 MAX98373_R20D2_DHT_ATTACK_CFG, 0, 133 max98373_dht_attack_rate_text); 134 135 static const char * const max98373_dht_release_rate_text[] = { 136 "45ms", "225ms", "450ms", "1150ms", 137 "2250ms", "3100ms", "4500ms", "6750ms" 138 }; 139 140 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum, 141 MAX98373_R20D3_DHT_RELEASE_CFG, 0, 142 max98373_dht_release_rate_text); 143 144 static const char * const max98373_limiter_attack_rate_text[] = { 145 "10us", "20us", "40us", "80us", 146 "160us", "320us", "640us", "1.28ms", 147 "2.56ms", "5.12ms", "10.24ms", "20.48ms", 148 "40.96ms", "81.92ms", "16.384ms", "32.768ms" 149 }; 150 151 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum, 152 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4, 153 max98373_limiter_attack_rate_text); 154 155 static const char * const max98373_limiter_release_rate_text[] = { 156 "40us", "80us", "160us", "320us", 157 "640us", "1.28ms", "2.56ms", "5.120ms", 158 "10.24ms", "20.48ms", "40.96ms", "81.92ms", 159 "163.84ms", "327.68ms", "655.36ms", "1310.72ms" 160 }; 161 162 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum, 163 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0, 164 max98373_limiter_release_rate_text); 165 166 static const char * const max98373_ADC_samplerate_text[] = { 167 "333kHz", "192kHz", "64kHz", "48kHz" 168 }; 169 170 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum, 171 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0, 172 max98373_ADC_samplerate_text); 173 174 static int max98373_feedback_get(struct snd_kcontrol *kcontrol, 175 struct snd_ctl_elem_value *ucontrol) 176 { 177 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 178 struct soc_mixer_control *mc = 179 (struct soc_mixer_control *)kcontrol->private_value; 180 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 181 int i; 182 183 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 184 /* 185 * Register values will be cached before suspend. The cached value 186 * will be a valid value and userspace will happy with that. 187 */ 188 for (i = 0; i < max98373->cache_num; i++) { 189 if (mc->reg == max98373->cache[i].reg) { 190 ucontrol->value.integer.value[0] = max98373->cache[i].val; 191 return 0; 192 } 193 } 194 } 195 196 return snd_soc_get_volsw(kcontrol, ucontrol); 197 } 198 199 static const struct snd_kcontrol_new max98373_snd_controls[] = { 200 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG, 201 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 202 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG, 203 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 204 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG, 205 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0), 206 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG, 207 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0), 208 /* Speaker Amplifier Overcurrent Automatic Restart Enable */ 209 SOC_SINGLE("OVC Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 210 MAX98373_OVC_AUTORESTART_SHIFT, 1, 0), 211 /* Thermal Shutdown Automatic Restart Enable */ 212 SOC_SINGLE("THERM Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 213 MAX98373_THERM_AUTORESTART_SHIFT, 1, 0), 214 /* Clock Monitor Automatic Restart Enable */ 215 SOC_SINGLE("CMON Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 216 MAX98373_CMON_AUTORESTART_SHIFT, 1, 0), 217 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 218 MAX98373_CLOCK_MON_SHIFT, 1, 0), 219 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG, 220 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0), 221 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG, 222 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0), 223 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL, 224 0, 0x7F, 1, max98373_digital_tlv), 225 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN, 226 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv), 227 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN, 228 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv), 229 SOC_ENUM("Output Voltage", max98373_out_volt_enum), 230 /* Dynamic Headroom Tracking */ 231 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN, 232 MAX98373_DHT_EN_SHIFT, 1, 0), 233 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG, 234 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv), 235 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG, 236 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv), 237 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG, 238 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 239 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG, 240 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 241 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum), 242 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum), 243 /* ADC configuration */ 244 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0), 245 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 246 MAX98373_FLT_EN_SHIFT, 1, 0), 247 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 248 MAX98373_FLT_EN_SHIFT, 1, 0), 249 SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0, 250 max98373_feedback_get, NULL), 251 SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0, 252 max98373_feedback_get, NULL), 253 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 254 0, 0x3, 0), 255 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 256 0, 0x3, 0), 257 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum), 258 /* Brownout Detection Engine */ 259 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0), 260 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2, 261 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0), 262 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2, 263 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0), 264 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0), 265 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0), 266 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0), 267 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0), 268 SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0, 269 max98373_feedback_get, NULL), 270 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0), 271 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0), 272 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0), 273 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0), 274 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0), 275 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2, 276 0, 0x3C, 1, max98373_bde_gain_tlv), 277 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2, 278 0, 0x3C, 1, max98373_bde_gain_tlv), 279 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2, 280 0, 0x3C, 1, max98373_bde_gain_tlv), 281 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2, 282 0, 0x3C, 1, max98373_bde_gain_tlv), 283 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3, 284 0, 0x3C, 1, max98373_bde_gain_tlv), 285 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3, 286 0, 0x3C, 1, max98373_bde_gain_tlv), 287 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3, 288 0, 0x3C, 1, max98373_bde_gain_tlv), 289 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3, 290 0, 0x3C, 1, max98373_bde_gain_tlv), 291 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1, 292 0, 0xF, 1, max98373_limiter_thresh_tlv), 293 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1, 294 0, 0xF, 1, max98373_limiter_thresh_tlv), 295 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1, 296 0, 0xF, 1, max98373_limiter_thresh_tlv), 297 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1, 298 0, 0xF, 1, max98373_limiter_thresh_tlv), 299 /* Limiter */ 300 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN, 301 MAX98373_LIMITER_EN_SHIFT, 1, 0), 302 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG, 303 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0), 304 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG, 305 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv), 306 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum), 307 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum), 308 }; 309 310 static const struct snd_soc_dapm_route max98373_audio_map[] = { 311 /* Plabyack */ 312 {"DAI Sel Mux", "Left", "Amp Enable"}, 313 {"DAI Sel Mux", "Right", "Amp Enable"}, 314 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 315 {"BE_OUT", NULL, "DAI Sel Mux"}, 316 /* Capture */ 317 { "VI Sense", "Switch", "VMON" }, 318 { "VI Sense", "Switch", "IMON" }, 319 { "SpkFB Sense", "Switch", "FBMON" }, 320 { "Voltage Sense", NULL, "VI Sense" }, 321 { "Current Sense", NULL, "VI Sense" }, 322 { "Speaker FB Sense", NULL, "SpkFB Sense" }, 323 }; 324 325 void max98373_reset(struct max98373_priv *max98373, struct device *dev) 326 { 327 int ret, reg, count; 328 329 /* Software Reset */ 330 ret = regmap_update_bits(max98373->regmap, 331 MAX98373_R2000_SW_RESET, 332 MAX98373_SOFT_RESET, 333 MAX98373_SOFT_RESET); 334 if (ret) 335 dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 336 337 count = 0; 338 while (count < 3) { 339 usleep_range(10000, 11000); 340 /* Software Reset Verification */ 341 ret = regmap_read(max98373->regmap, 342 MAX98373_R21FF_REV_ID, ®); 343 if (!ret) { 344 dev_info(dev, "Reset completed (retry:%d)\n", count); 345 return; 346 } 347 count++; 348 } 349 dev_err(dev, "Reset failed. (ret:%d)\n", ret); 350 } 351 EXPORT_SYMBOL_GPL(max98373_reset); 352 353 static int max98373_probe(struct snd_soc_component *component) 354 { 355 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 356 357 /* Software Reset */ 358 max98373_reset(max98373, component->dev); 359 360 /* IV default slot configuration */ 361 regmap_write(max98373->regmap, 362 MAX98373_R2020_PCM_TX_HIZ_EN_1, 363 0xFF); 364 regmap_write(max98373->regmap, 365 MAX98373_R2021_PCM_TX_HIZ_EN_2, 366 0xFF); 367 /* L/R mix configuration */ 368 regmap_write(max98373->regmap, 369 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 370 0x80); 371 regmap_write(max98373->regmap, 372 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 373 0x1); 374 /* Enable DC blocker */ 375 regmap_write(max98373->regmap, 376 MAX98373_R203F_AMP_DSP_CFG, 377 0x3); 378 /* Enable IMON VMON DC blocker */ 379 regmap_write(max98373->regmap, 380 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 381 0x7); 382 /* voltage, current slot configuration */ 383 regmap_write(max98373->regmap, 384 MAX98373_R2022_PCM_TX_SRC_1, 385 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 386 max98373->v_slot) & 0xFF); 387 if (max98373->v_slot < 8) 388 regmap_update_bits(max98373->regmap, 389 MAX98373_R2020_PCM_TX_HIZ_EN_1, 390 1 << max98373->v_slot, 0); 391 else 392 regmap_update_bits(max98373->regmap, 393 MAX98373_R2021_PCM_TX_HIZ_EN_2, 394 1 << (max98373->v_slot - 8), 0); 395 396 if (max98373->i_slot < 8) 397 regmap_update_bits(max98373->regmap, 398 MAX98373_R2020_PCM_TX_HIZ_EN_1, 399 1 << max98373->i_slot, 0); 400 else 401 regmap_update_bits(max98373->regmap, 402 MAX98373_R2021_PCM_TX_HIZ_EN_2, 403 1 << (max98373->i_slot - 8), 0); 404 405 /* enable auto restart function by default */ 406 regmap_write(max98373->regmap, 407 MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 408 0xF); 409 410 /* speaker feedback slot configuration */ 411 regmap_write(max98373->regmap, 412 MAX98373_R2023_PCM_TX_SRC_2, 413 max98373->spkfb_slot & 0xFF); 414 415 /* Set interleave mode */ 416 if (max98373->interleave_mode) 417 regmap_update_bits(max98373->regmap, 418 MAX98373_R2024_PCM_DATA_FMT_CFG, 419 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 420 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 421 422 /* Speaker enable */ 423 regmap_update_bits(max98373->regmap, 424 MAX98373_R2043_AMP_EN, 425 MAX98373_SPK_EN_MASK, 1); 426 427 return 0; 428 } 429 430 const struct snd_soc_component_driver soc_codec_dev_max98373 = { 431 .probe = max98373_probe, 432 .controls = max98373_snd_controls, 433 .num_controls = ARRAY_SIZE(max98373_snd_controls), 434 .dapm_widgets = max98373_dapm_widgets, 435 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 436 .dapm_routes = max98373_audio_map, 437 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 438 .use_pmdown_time = 1, 439 .endianness = 1, 440 }; 441 EXPORT_SYMBOL_GPL(soc_codec_dev_max98373); 442 443 static int max98373_sdw_probe(struct snd_soc_component *component) 444 { 445 int ret; 446 447 ret = pm_runtime_resume(component->dev); 448 if (ret < 0 && ret != -EACCES) 449 return ret; 450 451 return 0; 452 } 453 454 const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = { 455 .probe = max98373_sdw_probe, 456 .controls = max98373_snd_controls, 457 .num_controls = ARRAY_SIZE(max98373_snd_controls), 458 .dapm_widgets = max98373_dapm_widgets, 459 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 460 .dapm_routes = max98373_audio_map, 461 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 462 .use_pmdown_time = 1, 463 .endianness = 1, 464 }; 465 EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw); 466 467 void max98373_slot_config(struct device *dev, 468 struct max98373_priv *max98373) 469 { 470 int value; 471 472 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value)) 473 max98373->v_slot = value & 0xF; 474 else 475 max98373->v_slot = 0; 476 477 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value)) 478 max98373->i_slot = value & 0xF; 479 else 480 max98373->i_slot = 1; 481 if (dev->of_node) { 482 max98373->reset_gpio = of_get_named_gpio(dev->of_node, 483 "maxim,reset-gpio", 0); 484 if (!gpio_is_valid(max98373->reset_gpio)) { 485 dev_err(dev, "Looking up %s property in node %s failed %d\n", 486 "maxim,reset-gpio", dev->of_node->full_name, 487 max98373->reset_gpio); 488 } else { 489 dev_dbg(dev, "maxim,reset-gpio=%d", 490 max98373->reset_gpio); 491 } 492 } else { 493 /* this makes reset_gpio as invalid */ 494 max98373->reset_gpio = -1; 495 } 496 497 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value)) 498 max98373->spkfb_slot = value & 0xF; 499 else 500 max98373->spkfb_slot = 2; 501 } 502 EXPORT_SYMBOL_GPL(max98373_slot_config); 503 504 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 505 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 506 MODULE_LICENSE("GPL"); 507