1 /* 2 * max98095.c -- MAX98095 ALSA SoC Audio driver 3 * 4 * Copyright 2011 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/mutex.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/initval.h> 25 #include <sound/tlv.h> 26 #include <linux/slab.h> 27 #include <asm/div64.h> 28 #include <sound/max98095.h> 29 #include <sound/jack.h> 30 #include "max98095.h" 31 32 enum max98095_type { 33 MAX98095, 34 }; 35 36 struct max98095_cdata { 37 unsigned int rate; 38 unsigned int fmt; 39 int eq_sel; 40 int bq_sel; 41 }; 42 43 struct max98095_priv { 44 struct regmap *regmap; 45 enum max98095_type devtype; 46 struct max98095_pdata *pdata; 47 struct clk *mclk; 48 unsigned int sysclk; 49 struct max98095_cdata dai[3]; 50 const char **eq_texts; 51 const char **bq_texts; 52 struct soc_enum eq_enum; 53 struct soc_enum bq_enum; 54 int eq_textcnt; 55 int bq_textcnt; 56 u8 lin_state; 57 unsigned int mic1pre; 58 unsigned int mic2pre; 59 struct snd_soc_jack *headphone_jack; 60 struct snd_soc_jack *mic_jack; 61 struct mutex lock; 62 }; 63 64 static const struct reg_default max98095_reg_def[] = { 65 { 0xf, 0x00 }, /* 0F */ 66 { 0x10, 0x00 }, /* 10 */ 67 { 0x11, 0x00 }, /* 11 */ 68 { 0x12, 0x00 }, /* 12 */ 69 { 0x13, 0x00 }, /* 13 */ 70 { 0x14, 0x00 }, /* 14 */ 71 { 0x15, 0x00 }, /* 15 */ 72 { 0x16, 0x00 }, /* 16 */ 73 { 0x17, 0x00 }, /* 17 */ 74 { 0x18, 0x00 }, /* 18 */ 75 { 0x19, 0x00 }, /* 19 */ 76 { 0x1a, 0x00 }, /* 1A */ 77 { 0x1b, 0x00 }, /* 1B */ 78 { 0x1c, 0x00 }, /* 1C */ 79 { 0x1d, 0x00 }, /* 1D */ 80 { 0x1e, 0x00 }, /* 1E */ 81 { 0x1f, 0x00 }, /* 1F */ 82 { 0x20, 0x00 }, /* 20 */ 83 { 0x21, 0x00 }, /* 21 */ 84 { 0x22, 0x00 }, /* 22 */ 85 { 0x23, 0x00 }, /* 23 */ 86 { 0x24, 0x00 }, /* 24 */ 87 { 0x25, 0x00 }, /* 25 */ 88 { 0x26, 0x00 }, /* 26 */ 89 { 0x27, 0x00 }, /* 27 */ 90 { 0x28, 0x00 }, /* 28 */ 91 { 0x29, 0x00 }, /* 29 */ 92 { 0x2a, 0x00 }, /* 2A */ 93 { 0x2b, 0x00 }, /* 2B */ 94 { 0x2c, 0x00 }, /* 2C */ 95 { 0x2d, 0x00 }, /* 2D */ 96 { 0x2e, 0x00 }, /* 2E */ 97 { 0x2f, 0x00 }, /* 2F */ 98 { 0x30, 0x00 }, /* 30 */ 99 { 0x31, 0x00 }, /* 31 */ 100 { 0x32, 0x00 }, /* 32 */ 101 { 0x33, 0x00 }, /* 33 */ 102 { 0x34, 0x00 }, /* 34 */ 103 { 0x35, 0x00 }, /* 35 */ 104 { 0x36, 0x00 }, /* 36 */ 105 { 0x37, 0x00 }, /* 37 */ 106 { 0x38, 0x00 }, /* 38 */ 107 { 0x39, 0x00 }, /* 39 */ 108 { 0x3a, 0x00 }, /* 3A */ 109 { 0x3b, 0x00 }, /* 3B */ 110 { 0x3c, 0x00 }, /* 3C */ 111 { 0x3d, 0x00 }, /* 3D */ 112 { 0x3e, 0x00 }, /* 3E */ 113 { 0x3f, 0x00 }, /* 3F */ 114 { 0x40, 0x00 }, /* 40 */ 115 { 0x41, 0x00 }, /* 41 */ 116 { 0x42, 0x00 }, /* 42 */ 117 { 0x43, 0x00 }, /* 43 */ 118 { 0x44, 0x00 }, /* 44 */ 119 { 0x45, 0x00 }, /* 45 */ 120 { 0x46, 0x00 }, /* 46 */ 121 { 0x47, 0x00 }, /* 47 */ 122 { 0x48, 0x00 }, /* 48 */ 123 { 0x49, 0x00 }, /* 49 */ 124 { 0x4a, 0x00 }, /* 4A */ 125 { 0x4b, 0x00 }, /* 4B */ 126 { 0x4c, 0x00 }, /* 4C */ 127 { 0x4d, 0x00 }, /* 4D */ 128 { 0x4e, 0x00 }, /* 4E */ 129 { 0x4f, 0x00 }, /* 4F */ 130 { 0x50, 0x00 }, /* 50 */ 131 { 0x51, 0x00 }, /* 51 */ 132 { 0x52, 0x00 }, /* 52 */ 133 { 0x53, 0x00 }, /* 53 */ 134 { 0x54, 0x00 }, /* 54 */ 135 { 0x55, 0x00 }, /* 55 */ 136 { 0x56, 0x00 }, /* 56 */ 137 { 0x57, 0x00 }, /* 57 */ 138 { 0x58, 0x00 }, /* 58 */ 139 { 0x59, 0x00 }, /* 59 */ 140 { 0x5a, 0x00 }, /* 5A */ 141 { 0x5b, 0x00 }, /* 5B */ 142 { 0x5c, 0x00 }, /* 5C */ 143 { 0x5d, 0x00 }, /* 5D */ 144 { 0x5e, 0x00 }, /* 5E */ 145 { 0x5f, 0x00 }, /* 5F */ 146 { 0x60, 0x00 }, /* 60 */ 147 { 0x61, 0x00 }, /* 61 */ 148 { 0x62, 0x00 }, /* 62 */ 149 { 0x63, 0x00 }, /* 63 */ 150 { 0x64, 0x00 }, /* 64 */ 151 { 0x65, 0x00 }, /* 65 */ 152 { 0x66, 0x00 }, /* 66 */ 153 { 0x67, 0x00 }, /* 67 */ 154 { 0x68, 0x00 }, /* 68 */ 155 { 0x69, 0x00 }, /* 69 */ 156 { 0x6a, 0x00 }, /* 6A */ 157 { 0x6b, 0x00 }, /* 6B */ 158 { 0x6c, 0x00 }, /* 6C */ 159 { 0x6d, 0x00 }, /* 6D */ 160 { 0x6e, 0x00 }, /* 6E */ 161 { 0x6f, 0x00 }, /* 6F */ 162 { 0x70, 0x00 }, /* 70 */ 163 { 0x71, 0x00 }, /* 71 */ 164 { 0x72, 0x00 }, /* 72 */ 165 { 0x73, 0x00 }, /* 73 */ 166 { 0x74, 0x00 }, /* 74 */ 167 { 0x75, 0x00 }, /* 75 */ 168 { 0x76, 0x00 }, /* 76 */ 169 { 0x77, 0x00 }, /* 77 */ 170 { 0x78, 0x00 }, /* 78 */ 171 { 0x79, 0x00 }, /* 79 */ 172 { 0x7a, 0x00 }, /* 7A */ 173 { 0x7b, 0x00 }, /* 7B */ 174 { 0x7c, 0x00 }, /* 7C */ 175 { 0x7d, 0x00 }, /* 7D */ 176 { 0x7e, 0x00 }, /* 7E */ 177 { 0x7f, 0x00 }, /* 7F */ 178 { 0x80, 0x00 }, /* 80 */ 179 { 0x81, 0x00 }, /* 81 */ 180 { 0x82, 0x00 }, /* 82 */ 181 { 0x83, 0x00 }, /* 83 */ 182 { 0x84, 0x00 }, /* 84 */ 183 { 0x85, 0x00 }, /* 85 */ 184 { 0x86, 0x00 }, /* 86 */ 185 { 0x87, 0x00 }, /* 87 */ 186 { 0x88, 0x00 }, /* 88 */ 187 { 0x89, 0x00 }, /* 89 */ 188 { 0x8a, 0x00 }, /* 8A */ 189 { 0x8b, 0x00 }, /* 8B */ 190 { 0x8c, 0x00 }, /* 8C */ 191 { 0x8d, 0x00 }, /* 8D */ 192 { 0x8e, 0x00 }, /* 8E */ 193 { 0x8f, 0x00 }, /* 8F */ 194 { 0x90, 0x00 }, /* 90 */ 195 { 0x91, 0x00 }, /* 91 */ 196 { 0x92, 0x30 }, /* 92 */ 197 { 0x93, 0xF0 }, /* 93 */ 198 { 0x94, 0x00 }, /* 94 */ 199 { 0x95, 0x00 }, /* 95 */ 200 { 0x96, 0x3F }, /* 96 */ 201 { 0x97, 0x00 }, /* 97 */ 202 { 0xff, 0x00 }, /* FF */ 203 }; 204 205 static struct { 206 int readable; 207 int writable; 208 } max98095_access[M98095_REG_CNT] = { 209 { 0x00, 0x00 }, /* 00 */ 210 { 0xFF, 0x00 }, /* 01 */ 211 { 0xFF, 0x00 }, /* 02 */ 212 { 0xFF, 0x00 }, /* 03 */ 213 { 0xFF, 0x00 }, /* 04 */ 214 { 0xFF, 0x00 }, /* 05 */ 215 { 0xFF, 0x00 }, /* 06 */ 216 { 0xFF, 0x00 }, /* 07 */ 217 { 0xFF, 0x00 }, /* 08 */ 218 { 0xFF, 0x00 }, /* 09 */ 219 { 0xFF, 0x00 }, /* 0A */ 220 { 0xFF, 0x00 }, /* 0B */ 221 { 0xFF, 0x00 }, /* 0C */ 222 { 0xFF, 0x00 }, /* 0D */ 223 { 0xFF, 0x00 }, /* 0E */ 224 { 0xFF, 0x9F }, /* 0F */ 225 { 0xFF, 0xFF }, /* 10 */ 226 { 0xFF, 0xFF }, /* 11 */ 227 { 0xFF, 0xFF }, /* 12 */ 228 { 0xFF, 0xFF }, /* 13 */ 229 { 0xFF, 0xFF }, /* 14 */ 230 { 0xFF, 0xFF }, /* 15 */ 231 { 0xFF, 0xFF }, /* 16 */ 232 { 0xFF, 0xFF }, /* 17 */ 233 { 0xFF, 0xFF }, /* 18 */ 234 { 0xFF, 0xFF }, /* 19 */ 235 { 0xFF, 0xFF }, /* 1A */ 236 { 0xFF, 0xFF }, /* 1B */ 237 { 0xFF, 0xFF }, /* 1C */ 238 { 0xFF, 0xFF }, /* 1D */ 239 { 0xFF, 0x77 }, /* 1E */ 240 { 0xFF, 0x77 }, /* 1F */ 241 { 0xFF, 0x77 }, /* 20 */ 242 { 0xFF, 0x77 }, /* 21 */ 243 { 0xFF, 0x77 }, /* 22 */ 244 { 0xFF, 0x77 }, /* 23 */ 245 { 0xFF, 0xFF }, /* 24 */ 246 { 0xFF, 0x7F }, /* 25 */ 247 { 0xFF, 0x31 }, /* 26 */ 248 { 0xFF, 0xFF }, /* 27 */ 249 { 0xFF, 0xFF }, /* 28 */ 250 { 0xFF, 0xFF }, /* 29 */ 251 { 0xFF, 0xF7 }, /* 2A */ 252 { 0xFF, 0x2F }, /* 2B */ 253 { 0xFF, 0xEF }, /* 2C */ 254 { 0xFF, 0xFF }, /* 2D */ 255 { 0xFF, 0xFF }, /* 2E */ 256 { 0xFF, 0xFF }, /* 2F */ 257 { 0xFF, 0xFF }, /* 30 */ 258 { 0xFF, 0xFF }, /* 31 */ 259 { 0xFF, 0xFF }, /* 32 */ 260 { 0xFF, 0xFF }, /* 33 */ 261 { 0xFF, 0xF7 }, /* 34 */ 262 { 0xFF, 0x2F }, /* 35 */ 263 { 0xFF, 0xCF }, /* 36 */ 264 { 0xFF, 0xFF }, /* 37 */ 265 { 0xFF, 0xFF }, /* 38 */ 266 { 0xFF, 0xFF }, /* 39 */ 267 { 0xFF, 0xFF }, /* 3A */ 268 { 0xFF, 0xFF }, /* 3B */ 269 { 0xFF, 0xFF }, /* 3C */ 270 { 0xFF, 0xFF }, /* 3D */ 271 { 0xFF, 0xF7 }, /* 3E */ 272 { 0xFF, 0x2F }, /* 3F */ 273 { 0xFF, 0xCF }, /* 40 */ 274 { 0xFF, 0xFF }, /* 41 */ 275 { 0xFF, 0x77 }, /* 42 */ 276 { 0xFF, 0xFF }, /* 43 */ 277 { 0xFF, 0xFF }, /* 44 */ 278 { 0xFF, 0xFF }, /* 45 */ 279 { 0xFF, 0xFF }, /* 46 */ 280 { 0xFF, 0xFF }, /* 47 */ 281 { 0xFF, 0xFF }, /* 48 */ 282 { 0xFF, 0x0F }, /* 49 */ 283 { 0xFF, 0xFF }, /* 4A */ 284 { 0xFF, 0xFF }, /* 4B */ 285 { 0xFF, 0x3F }, /* 4C */ 286 { 0xFF, 0x3F }, /* 4D */ 287 { 0xFF, 0x3F }, /* 4E */ 288 { 0xFF, 0xFF }, /* 4F */ 289 { 0xFF, 0x7F }, /* 50 */ 290 { 0xFF, 0x7F }, /* 51 */ 291 { 0xFF, 0x0F }, /* 52 */ 292 { 0xFF, 0x3F }, /* 53 */ 293 { 0xFF, 0x3F }, /* 54 */ 294 { 0xFF, 0x3F }, /* 55 */ 295 { 0xFF, 0xFF }, /* 56 */ 296 { 0xFF, 0xFF }, /* 57 */ 297 { 0xFF, 0xBF }, /* 58 */ 298 { 0xFF, 0x1F }, /* 59 */ 299 { 0xFF, 0xBF }, /* 5A */ 300 { 0xFF, 0x1F }, /* 5B */ 301 { 0xFF, 0xBF }, /* 5C */ 302 { 0xFF, 0x3F }, /* 5D */ 303 { 0xFF, 0x3F }, /* 5E */ 304 { 0xFF, 0x7F }, /* 5F */ 305 { 0xFF, 0x7F }, /* 60 */ 306 { 0xFF, 0x47 }, /* 61 */ 307 { 0xFF, 0x9F }, /* 62 */ 308 { 0xFF, 0x9F }, /* 63 */ 309 { 0xFF, 0x9F }, /* 64 */ 310 { 0xFF, 0x9F }, /* 65 */ 311 { 0xFF, 0x9F }, /* 66 */ 312 { 0xFF, 0xBF }, /* 67 */ 313 { 0xFF, 0xBF }, /* 68 */ 314 { 0xFF, 0xFF }, /* 69 */ 315 { 0xFF, 0xFF }, /* 6A */ 316 { 0xFF, 0x7F }, /* 6B */ 317 { 0xFF, 0xF7 }, /* 6C */ 318 { 0xFF, 0xFF }, /* 6D */ 319 { 0xFF, 0xFF }, /* 6E */ 320 { 0xFF, 0x1F }, /* 6F */ 321 { 0xFF, 0xF7 }, /* 70 */ 322 { 0xFF, 0xFF }, /* 71 */ 323 { 0xFF, 0xFF }, /* 72 */ 324 { 0xFF, 0x1F }, /* 73 */ 325 { 0xFF, 0xF7 }, /* 74 */ 326 { 0xFF, 0xFF }, /* 75 */ 327 { 0xFF, 0xFF }, /* 76 */ 328 { 0xFF, 0x1F }, /* 77 */ 329 { 0xFF, 0xF7 }, /* 78 */ 330 { 0xFF, 0xFF }, /* 79 */ 331 { 0xFF, 0xFF }, /* 7A */ 332 { 0xFF, 0x1F }, /* 7B */ 333 { 0xFF, 0xF7 }, /* 7C */ 334 { 0xFF, 0xFF }, /* 7D */ 335 { 0xFF, 0xFF }, /* 7E */ 336 { 0xFF, 0x1F }, /* 7F */ 337 { 0xFF, 0xF7 }, /* 80 */ 338 { 0xFF, 0xFF }, /* 81 */ 339 { 0xFF, 0xFF }, /* 82 */ 340 { 0xFF, 0x1F }, /* 83 */ 341 { 0xFF, 0x7F }, /* 84 */ 342 { 0xFF, 0x0F }, /* 85 */ 343 { 0xFF, 0xD8 }, /* 86 */ 344 { 0xFF, 0xFF }, /* 87 */ 345 { 0xFF, 0xEF }, /* 88 */ 346 { 0xFF, 0xFE }, /* 89 */ 347 { 0xFF, 0xFE }, /* 8A */ 348 { 0xFF, 0xFF }, /* 8B */ 349 { 0xFF, 0xFF }, /* 8C */ 350 { 0xFF, 0x3F }, /* 8D */ 351 { 0xFF, 0xFF }, /* 8E */ 352 { 0xFF, 0x3F }, /* 8F */ 353 { 0xFF, 0x8F }, /* 90 */ 354 { 0xFF, 0xFF }, /* 91 */ 355 { 0xFF, 0x3F }, /* 92 */ 356 { 0xFF, 0xFF }, /* 93 */ 357 { 0xFF, 0xFF }, /* 94 */ 358 { 0xFF, 0x0F }, /* 95 */ 359 { 0xFF, 0x3F }, /* 96 */ 360 { 0xFF, 0x8C }, /* 97 */ 361 { 0x00, 0x00 }, /* 98 */ 362 { 0x00, 0x00 }, /* 99 */ 363 { 0x00, 0x00 }, /* 9A */ 364 { 0x00, 0x00 }, /* 9B */ 365 { 0x00, 0x00 }, /* 9C */ 366 { 0x00, 0x00 }, /* 9D */ 367 { 0x00, 0x00 }, /* 9E */ 368 { 0x00, 0x00 }, /* 9F */ 369 { 0x00, 0x00 }, /* A0 */ 370 { 0x00, 0x00 }, /* A1 */ 371 { 0x00, 0x00 }, /* A2 */ 372 { 0x00, 0x00 }, /* A3 */ 373 { 0x00, 0x00 }, /* A4 */ 374 { 0x00, 0x00 }, /* A5 */ 375 { 0x00, 0x00 }, /* A6 */ 376 { 0x00, 0x00 }, /* A7 */ 377 { 0x00, 0x00 }, /* A8 */ 378 { 0x00, 0x00 }, /* A9 */ 379 { 0x00, 0x00 }, /* AA */ 380 { 0x00, 0x00 }, /* AB */ 381 { 0x00, 0x00 }, /* AC */ 382 { 0x00, 0x00 }, /* AD */ 383 { 0x00, 0x00 }, /* AE */ 384 { 0x00, 0x00 }, /* AF */ 385 { 0x00, 0x00 }, /* B0 */ 386 { 0x00, 0x00 }, /* B1 */ 387 { 0x00, 0x00 }, /* B2 */ 388 { 0x00, 0x00 }, /* B3 */ 389 { 0x00, 0x00 }, /* B4 */ 390 { 0x00, 0x00 }, /* B5 */ 391 { 0x00, 0x00 }, /* B6 */ 392 { 0x00, 0x00 }, /* B7 */ 393 { 0x00, 0x00 }, /* B8 */ 394 { 0x00, 0x00 }, /* B9 */ 395 { 0x00, 0x00 }, /* BA */ 396 { 0x00, 0x00 }, /* BB */ 397 { 0x00, 0x00 }, /* BC */ 398 { 0x00, 0x00 }, /* BD */ 399 { 0x00, 0x00 }, /* BE */ 400 { 0x00, 0x00 }, /* BF */ 401 { 0x00, 0x00 }, /* C0 */ 402 { 0x00, 0x00 }, /* C1 */ 403 { 0x00, 0x00 }, /* C2 */ 404 { 0x00, 0x00 }, /* C3 */ 405 { 0x00, 0x00 }, /* C4 */ 406 { 0x00, 0x00 }, /* C5 */ 407 { 0x00, 0x00 }, /* C6 */ 408 { 0x00, 0x00 }, /* C7 */ 409 { 0x00, 0x00 }, /* C8 */ 410 { 0x00, 0x00 }, /* C9 */ 411 { 0x00, 0x00 }, /* CA */ 412 { 0x00, 0x00 }, /* CB */ 413 { 0x00, 0x00 }, /* CC */ 414 { 0x00, 0x00 }, /* CD */ 415 { 0x00, 0x00 }, /* CE */ 416 { 0x00, 0x00 }, /* CF */ 417 { 0x00, 0x00 }, /* D0 */ 418 { 0x00, 0x00 }, /* D1 */ 419 { 0x00, 0x00 }, /* D2 */ 420 { 0x00, 0x00 }, /* D3 */ 421 { 0x00, 0x00 }, /* D4 */ 422 { 0x00, 0x00 }, /* D5 */ 423 { 0x00, 0x00 }, /* D6 */ 424 { 0x00, 0x00 }, /* D7 */ 425 { 0x00, 0x00 }, /* D8 */ 426 { 0x00, 0x00 }, /* D9 */ 427 { 0x00, 0x00 }, /* DA */ 428 { 0x00, 0x00 }, /* DB */ 429 { 0x00, 0x00 }, /* DC */ 430 { 0x00, 0x00 }, /* DD */ 431 { 0x00, 0x00 }, /* DE */ 432 { 0x00, 0x00 }, /* DF */ 433 { 0x00, 0x00 }, /* E0 */ 434 { 0x00, 0x00 }, /* E1 */ 435 { 0x00, 0x00 }, /* E2 */ 436 { 0x00, 0x00 }, /* E3 */ 437 { 0x00, 0x00 }, /* E4 */ 438 { 0x00, 0x00 }, /* E5 */ 439 { 0x00, 0x00 }, /* E6 */ 440 { 0x00, 0x00 }, /* E7 */ 441 { 0x00, 0x00 }, /* E8 */ 442 { 0x00, 0x00 }, /* E9 */ 443 { 0x00, 0x00 }, /* EA */ 444 { 0x00, 0x00 }, /* EB */ 445 { 0x00, 0x00 }, /* EC */ 446 { 0x00, 0x00 }, /* ED */ 447 { 0x00, 0x00 }, /* EE */ 448 { 0x00, 0x00 }, /* EF */ 449 { 0x00, 0x00 }, /* F0 */ 450 { 0x00, 0x00 }, /* F1 */ 451 { 0x00, 0x00 }, /* F2 */ 452 { 0x00, 0x00 }, /* F3 */ 453 { 0x00, 0x00 }, /* F4 */ 454 { 0x00, 0x00 }, /* F5 */ 455 { 0x00, 0x00 }, /* F6 */ 456 { 0x00, 0x00 }, /* F7 */ 457 { 0x00, 0x00 }, /* F8 */ 458 { 0x00, 0x00 }, /* F9 */ 459 { 0x00, 0x00 }, /* FA */ 460 { 0x00, 0x00 }, /* FB */ 461 { 0x00, 0x00 }, /* FC */ 462 { 0x00, 0x00 }, /* FD */ 463 { 0x00, 0x00 }, /* FE */ 464 { 0xFF, 0x00 }, /* FF */ 465 }; 466 467 static bool max98095_readable(struct device *dev, unsigned int reg) 468 { 469 if (reg >= M98095_REG_CNT) 470 return 0; 471 return max98095_access[reg].readable != 0; 472 } 473 474 static bool max98095_volatile(struct device *dev, unsigned int reg) 475 { 476 if (reg > M98095_REG_MAX_CACHED) 477 return 1; 478 479 switch (reg) { 480 case M98095_000_HOST_DATA: 481 case M98095_001_HOST_INT_STS: 482 case M98095_002_HOST_RSP_STS: 483 case M98095_003_HOST_CMD_STS: 484 case M98095_004_CODEC_STS: 485 case M98095_005_DAI1_ALC_STS: 486 case M98095_006_DAI2_ALC_STS: 487 case M98095_007_JACK_AUTO_STS: 488 case M98095_008_JACK_MANUAL_STS: 489 case M98095_009_JACK_VBAT_STS: 490 case M98095_00A_ACC_ADC_STS: 491 case M98095_00B_MIC_NG_AGC_STS: 492 case M98095_00C_SPK_L_VOLT_STS: 493 case M98095_00D_SPK_R_VOLT_STS: 494 case M98095_00E_TEMP_SENSOR_STS: 495 return 1; 496 } 497 498 return 0; 499 } 500 501 static const struct regmap_config max98095_regmap = { 502 .reg_bits = 8, 503 .val_bits = 8, 504 505 .reg_defaults = max98095_reg_def, 506 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def), 507 .max_register = M98095_0FF_REV_ID, 508 .cache_type = REGCACHE_RBTREE, 509 510 .readable_reg = max98095_readable, 511 .volatile_reg = max98095_volatile, 512 }; 513 514 /* 515 * Load equalizer DSP coefficient configurations registers 516 */ 517 static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, 518 unsigned int band, u16 *coefs) 519 { 520 unsigned int eq_reg; 521 unsigned int i; 522 523 if (WARN_ON(band > 4) || 524 WARN_ON(dai > 1)) 525 return; 526 527 /* Load the base register address */ 528 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; 529 530 /* Add the band address offset, note adjustment for word address */ 531 eq_reg += band * (M98095_COEFS_PER_BAND << 1); 532 533 /* Step through the registers and coefs */ 534 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 535 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); 536 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); 537 } 538 } 539 540 /* 541 * Load biquad filter coefficient configurations registers 542 */ 543 static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, 544 unsigned int band, u16 *coefs) 545 { 546 unsigned int bq_reg; 547 unsigned int i; 548 549 if (WARN_ON(band > 1) || 550 WARN_ON(dai > 1)) 551 return; 552 553 /* Load the base register address */ 554 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; 555 556 /* Add the band address offset, note adjustment for word address */ 557 bq_reg += band * (M98095_COEFS_PER_BAND << 1); 558 559 /* Step through the registers and coefs */ 560 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 561 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); 562 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); 563 } 564 } 565 566 static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; 567 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum, 568 M98095_02E_DAI1_FILTERS, 7, 569 max98095_fltr_mode); 570 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum, 571 M98095_038_DAI2_FILTERS, 7, 572 max98095_fltr_mode); 573 574 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; 575 576 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum, 577 M98095_087_CFG_MIC, 0, 578 max98095_extmic_text); 579 580 static const struct snd_kcontrol_new max98095_extmic_mux = 581 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); 582 583 static const char * const max98095_linein_text[] = { "INA", "INB" }; 584 585 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum, 586 M98095_086_CFG_LINE, 6, 587 max98095_linein_text); 588 589 static const struct snd_kcontrol_new max98095_linein_mux = 590 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); 591 592 static const char * const max98095_line_mode_text[] = { 593 "Stereo", "Differential"}; 594 595 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum, 596 M98095_086_CFG_LINE, 7, 597 max98095_line_mode_text); 598 599 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum, 600 M98095_086_CFG_LINE, 4, 601 max98095_line_mode_text); 602 603 static const char * const max98095_dai_fltr[] = { 604 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", 605 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; 606 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum, 607 M98095_02E_DAI1_FILTERS, 0, 608 max98095_dai_fltr); 609 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum, 610 M98095_038_DAI2_FILTERS, 0, 611 max98095_dai_fltr); 612 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum, 613 M98095_042_DAI3_FILTERS, 0, 614 max98095_dai_fltr); 615 616 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, 617 struct snd_ctl_elem_value *ucontrol) 618 { 619 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 620 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 621 unsigned int sel = ucontrol->value.integer.value[0]; 622 623 max98095->mic1pre = sel; 624 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, 625 (1+sel)<<M98095_MICPRE_SHIFT); 626 627 return 0; 628 } 629 630 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, 631 struct snd_ctl_elem_value *ucontrol) 632 { 633 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 634 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 635 636 ucontrol->value.integer.value[0] = max98095->mic1pre; 637 return 0; 638 } 639 640 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, 641 struct snd_ctl_elem_value *ucontrol) 642 { 643 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 644 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 645 unsigned int sel = ucontrol->value.integer.value[0]; 646 647 max98095->mic2pre = sel; 648 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, 649 (1+sel)<<M98095_MICPRE_SHIFT); 650 651 return 0; 652 } 653 654 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, 655 struct snd_ctl_elem_value *ucontrol) 656 { 657 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 658 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 659 660 ucontrol->value.integer.value[0] = max98095->mic2pre; 661 return 0; 662 } 663 664 static const unsigned int max98095_micboost_tlv[] = { 665 TLV_DB_RANGE_HEAD(2), 666 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 667 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 668 }; 669 670 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); 671 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); 672 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); 673 674 static const unsigned int max98095_hp_tlv[] = { 675 TLV_DB_RANGE_HEAD(5), 676 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 677 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 678 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 679 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 680 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 681 }; 682 683 static const unsigned int max98095_spk_tlv[] = { 684 TLV_DB_RANGE_HEAD(4), 685 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), 686 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), 687 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), 688 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0), 689 }; 690 691 static const unsigned int max98095_rcv_lout_tlv[] = { 692 TLV_DB_RANGE_HEAD(5), 693 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 694 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 695 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 696 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 697 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 698 }; 699 700 static const unsigned int max98095_lin_tlv[] = { 701 TLV_DB_RANGE_HEAD(3), 702 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), 703 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), 704 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), 705 }; 706 707 static const struct snd_kcontrol_new max98095_snd_controls[] = { 708 709 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, 710 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), 711 712 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, 713 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), 714 715 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, 716 0, 31, 0, max98095_rcv_lout_tlv), 717 718 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, 719 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), 720 721 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, 722 M98095_065_LVL_HP_R, 7, 1, 1), 723 724 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, 725 M98095_068_LVL_SPK_R, 7, 1, 1), 726 727 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), 728 729 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, 730 M98095_063_LVL_LINEOUT2, 7, 1, 1), 731 732 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, 733 max98095_mic_tlv), 734 735 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, 736 max98095_mic_tlv), 737 738 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 739 M98095_05F_LVL_MIC1, 5, 2, 0, 740 max98095_mic1pre_get, max98095_mic1pre_set, 741 max98095_micboost_tlv), 742 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 743 M98095_060_LVL_MIC2, 5, 2, 0, 744 max98095_mic2pre_get, max98095_mic2pre_set, 745 max98095_micboost_tlv), 746 747 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, 748 max98095_lin_tlv), 749 750 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, 751 max98095_adc_tlv), 752 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, 753 max98095_adc_tlv), 754 755 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, 756 max98095_adcboost_tlv), 757 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, 758 max98095_adcboost_tlv), 759 760 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), 761 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), 762 763 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), 764 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), 765 766 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), 767 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), 768 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), 769 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), 770 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), 771 772 SOC_ENUM("Linein Mode", max98095_linein_mode_enum), 773 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), 774 }; 775 776 /* Left speaker mixer switch */ 777 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { 778 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), 779 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), 780 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 781 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 782 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), 783 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), 784 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), 785 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), 786 }; 787 788 /* Right speaker mixer switch */ 789 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { 790 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), 791 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), 792 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 793 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 794 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), 795 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), 796 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), 797 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), 798 }; 799 800 /* Left headphone mixer switch */ 801 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { 802 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), 803 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), 804 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), 805 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), 806 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), 807 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), 808 }; 809 810 /* Right headphone mixer switch */ 811 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { 812 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), 813 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), 814 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), 815 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), 816 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), 817 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), 818 }; 819 820 /* Receiver earpiece mixer switch */ 821 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { 822 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), 823 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), 824 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), 825 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), 826 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), 827 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), 828 }; 829 830 /* Left lineout mixer switch */ 831 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { 832 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), 833 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), 834 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), 835 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), 836 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), 837 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), 838 }; 839 840 /* Right lineout mixer switch */ 841 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { 842 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), 843 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), 844 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), 845 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), 846 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), 847 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), 848 }; 849 850 /* Left ADC mixer switch */ 851 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { 852 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), 853 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), 854 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), 855 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), 856 }; 857 858 /* Right ADC mixer switch */ 859 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { 860 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), 861 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), 862 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), 863 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), 864 }; 865 866 static int max98095_mic_event(struct snd_soc_dapm_widget *w, 867 struct snd_kcontrol *kcontrol, int event) 868 { 869 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 870 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 871 872 switch (event) { 873 case SND_SOC_DAPM_POST_PMU: 874 if (w->reg == M98095_05F_LVL_MIC1) { 875 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 876 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); 877 } else { 878 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 879 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); 880 } 881 break; 882 case SND_SOC_DAPM_POST_PMD: 883 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); 884 break; 885 default: 886 return -EINVAL; 887 } 888 889 return 0; 890 } 891 892 /* 893 * The line inputs are stereo inputs with the left and right 894 * channels sharing a common PGA power control signal. 895 */ 896 static int max98095_line_pga(struct snd_soc_dapm_widget *w, 897 int event, u8 channel) 898 { 899 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 900 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 901 u8 *state; 902 903 if (WARN_ON(!(channel == 1 || channel == 2))) 904 return -EINVAL; 905 906 state = &max98095->lin_state; 907 908 switch (event) { 909 case SND_SOC_DAPM_POST_PMU: 910 *state |= channel; 911 snd_soc_update_bits(codec, w->reg, 912 (1 << w->shift), (1 << w->shift)); 913 break; 914 case SND_SOC_DAPM_POST_PMD: 915 *state &= ~channel; 916 if (*state == 0) { 917 snd_soc_update_bits(codec, w->reg, 918 (1 << w->shift), 0); 919 } 920 break; 921 default: 922 return -EINVAL; 923 } 924 925 return 0; 926 } 927 928 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, 929 struct snd_kcontrol *k, int event) 930 { 931 return max98095_line_pga(w, event, 1); 932 } 933 934 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, 935 struct snd_kcontrol *k, int event) 936 { 937 return max98095_line_pga(w, event, 2); 938 } 939 940 /* 941 * The stereo line out mixer outputs to two stereo line outs. 942 * The 2nd pair has a separate set of enables. 943 */ 944 static int max98095_lineout_event(struct snd_soc_dapm_widget *w, 945 struct snd_kcontrol *kcontrol, int event) 946 { 947 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 948 949 switch (event) { 950 case SND_SOC_DAPM_POST_PMU: 951 snd_soc_update_bits(codec, w->reg, 952 (1 << (w->shift+2)), (1 << (w->shift+2))); 953 break; 954 case SND_SOC_DAPM_POST_PMD: 955 snd_soc_update_bits(codec, w->reg, 956 (1 << (w->shift+2)), 0); 957 break; 958 default: 959 return -EINVAL; 960 } 961 962 return 0; 963 } 964 965 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { 966 967 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), 968 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), 969 970 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 971 M98095_091_PWR_EN_OUT, 0, 0), 972 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 973 M98095_091_PWR_EN_OUT, 1, 0), 974 SND_SOC_DAPM_DAC("DACM2", "Aux Playback", 975 M98095_091_PWR_EN_OUT, 2, 0), 976 SND_SOC_DAPM_DAC("DACM3", "Voice Playback", 977 M98095_091_PWR_EN_OUT, 2, 0), 978 979 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, 980 6, 0, NULL, 0), 981 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, 982 7, 0, NULL, 0), 983 984 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, 985 4, 0, NULL, 0), 986 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, 987 5, 0, NULL, 0), 988 989 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, 990 3, 0, NULL, 0), 991 992 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, 993 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 994 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, 995 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 996 997 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 998 &max98095_extmic_mux), 999 1000 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, 1001 &max98095_linein_mux), 1002 1003 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1004 &max98095_left_hp_mixer_controls[0], 1005 ARRAY_SIZE(max98095_left_hp_mixer_controls)), 1006 1007 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1008 &max98095_right_hp_mixer_controls[0], 1009 ARRAY_SIZE(max98095_right_hp_mixer_controls)), 1010 1011 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1012 &max98095_left_speaker_mixer_controls[0], 1013 ARRAY_SIZE(max98095_left_speaker_mixer_controls)), 1014 1015 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1016 &max98095_right_speaker_mixer_controls[0], 1017 ARRAY_SIZE(max98095_right_speaker_mixer_controls)), 1018 1019 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, 1020 &max98095_mono_rcv_mixer_controls[0], 1021 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), 1022 1023 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, 1024 &max98095_left_lineout_mixer_controls[0], 1025 ARRAY_SIZE(max98095_left_lineout_mixer_controls)), 1026 1027 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, 1028 &max98095_right_lineout_mixer_controls[0], 1029 ARRAY_SIZE(max98095_right_lineout_mixer_controls)), 1030 1031 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1032 &max98095_left_ADC_mixer_controls[0], 1033 ARRAY_SIZE(max98095_left_ADC_mixer_controls)), 1034 1035 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1036 &max98095_right_ADC_mixer_controls[0], 1037 ARRAY_SIZE(max98095_right_ADC_mixer_controls)), 1038 1039 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, 1040 5, 0, NULL, 0, max98095_mic_event, 1041 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1042 1043 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, 1044 5, 0, NULL, 0, max98095_mic_event, 1045 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1046 1047 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, 1048 7, 0, NULL, 0, max98095_pga_in1_event, 1049 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1050 1051 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, 1052 7, 0, NULL, 0, max98095_pga_in2_event, 1053 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1054 1055 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), 1056 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), 1057 1058 SND_SOC_DAPM_OUTPUT("HPL"), 1059 SND_SOC_DAPM_OUTPUT("HPR"), 1060 SND_SOC_DAPM_OUTPUT("SPKL"), 1061 SND_SOC_DAPM_OUTPUT("SPKR"), 1062 SND_SOC_DAPM_OUTPUT("RCV"), 1063 SND_SOC_DAPM_OUTPUT("OUT1"), 1064 SND_SOC_DAPM_OUTPUT("OUT2"), 1065 SND_SOC_DAPM_OUTPUT("OUT3"), 1066 SND_SOC_DAPM_OUTPUT("OUT4"), 1067 1068 SND_SOC_DAPM_INPUT("MIC1"), 1069 SND_SOC_DAPM_INPUT("MIC2"), 1070 SND_SOC_DAPM_INPUT("INA1"), 1071 SND_SOC_DAPM_INPUT("INA2"), 1072 SND_SOC_DAPM_INPUT("INB1"), 1073 SND_SOC_DAPM_INPUT("INB2"), 1074 }; 1075 1076 static const struct snd_soc_dapm_route max98095_audio_map[] = { 1077 /* Left headphone output mixer */ 1078 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 1079 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 1080 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1081 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1082 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, 1083 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, 1084 1085 /* Right headphone output mixer */ 1086 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 1087 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 1088 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1089 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1090 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, 1091 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, 1092 1093 /* Left speaker output mixer */ 1094 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 1095 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 1096 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 1097 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 1098 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1099 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1100 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, 1101 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, 1102 1103 /* Right speaker output mixer */ 1104 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 1105 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 1106 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 1107 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 1108 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1109 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1110 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, 1111 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, 1112 1113 /* Earpiece/Receiver output mixer */ 1114 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, 1115 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, 1116 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1117 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1118 {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, 1119 {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, 1120 1121 /* Left Lineout output mixer */ 1122 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 1123 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 1124 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 1125 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 1126 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, 1127 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, 1128 1129 /* Right lineout output mixer */ 1130 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 1131 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 1132 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 1133 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 1134 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, 1135 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, 1136 1137 {"HP Left Out", NULL, "Left Headphone Mixer"}, 1138 {"HP Right Out", NULL, "Right Headphone Mixer"}, 1139 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1140 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1141 {"RCV Mono Out", NULL, "Receiver Mixer"}, 1142 {"LINE Left Out", NULL, "Left Lineout Mixer"}, 1143 {"LINE Right Out", NULL, "Right Lineout Mixer"}, 1144 1145 {"HPL", NULL, "HP Left Out"}, 1146 {"HPR", NULL, "HP Right Out"}, 1147 {"SPKL", NULL, "SPK Left Out"}, 1148 {"SPKR", NULL, "SPK Right Out"}, 1149 {"RCV", NULL, "RCV Mono Out"}, 1150 {"OUT1", NULL, "LINE Left Out"}, 1151 {"OUT2", NULL, "LINE Right Out"}, 1152 {"OUT3", NULL, "LINE Left Out"}, 1153 {"OUT4", NULL, "LINE Right Out"}, 1154 1155 /* Left ADC input mixer */ 1156 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1157 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1158 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, 1159 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, 1160 1161 /* Right ADC input mixer */ 1162 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1163 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1164 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, 1165 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, 1166 1167 /* Inputs */ 1168 {"ADCL", NULL, "Left ADC Mixer"}, 1169 {"ADCR", NULL, "Right ADC Mixer"}, 1170 1171 {"IN1 Input", NULL, "INA1"}, 1172 {"IN2 Input", NULL, "INA2"}, 1173 1174 {"MIC1 Input", NULL, "MIC1"}, 1175 {"MIC2 Input", NULL, "MIC2"}, 1176 }; 1177 1178 /* codec mclk clock divider coefficients */ 1179 static const struct { 1180 u32 rate; 1181 u8 sr; 1182 } rate_table[] = { 1183 {8000, 0x01}, 1184 {11025, 0x02}, 1185 {16000, 0x03}, 1186 {22050, 0x04}, 1187 {24000, 0x05}, 1188 {32000, 0x06}, 1189 {44100, 0x07}, 1190 {48000, 0x08}, 1191 {88200, 0x09}, 1192 {96000, 0x0A}, 1193 }; 1194 1195 static int rate_value(int rate, u8 *value) 1196 { 1197 int i; 1198 1199 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 1200 if (rate_table[i].rate >= rate) { 1201 *value = rate_table[i].sr; 1202 return 0; 1203 } 1204 } 1205 *value = rate_table[0].sr; 1206 return -EINVAL; 1207 } 1208 1209 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, 1210 struct snd_pcm_hw_params *params, 1211 struct snd_soc_dai *dai) 1212 { 1213 struct snd_soc_codec *codec = dai->codec; 1214 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1215 struct max98095_cdata *cdata; 1216 unsigned long long ni; 1217 unsigned int rate; 1218 u8 regval; 1219 1220 cdata = &max98095->dai[0]; 1221 1222 rate = params_rate(params); 1223 1224 switch (params_width(params)) { 1225 case 16: 1226 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1227 M98095_DAI_WS, 0); 1228 break; 1229 case 24: 1230 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1231 M98095_DAI_WS, M98095_DAI_WS); 1232 break; 1233 default: 1234 return -EINVAL; 1235 } 1236 1237 if (rate_value(rate, ®val)) 1238 return -EINVAL; 1239 1240 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, 1241 M98095_CLKMODE_MASK, regval); 1242 cdata->rate = rate; 1243 1244 /* Configure NI when operating as master */ 1245 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { 1246 if (max98095->sysclk == 0) { 1247 dev_err(codec->dev, "Invalid system clock frequency\n"); 1248 return -EINVAL; 1249 } 1250 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1251 * (unsigned long long int)rate; 1252 do_div(ni, (unsigned long long int)max98095->sysclk); 1253 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 1254 (ni >> 8) & 0x7F); 1255 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 1256 ni & 0xFF); 1257 } 1258 1259 /* Update sample rate mode */ 1260 if (rate < 50000) 1261 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 1262 M98095_DAI_DHF, 0); 1263 else 1264 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 1265 M98095_DAI_DHF, M98095_DAI_DHF); 1266 1267 return 0; 1268 } 1269 1270 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, 1271 struct snd_pcm_hw_params *params, 1272 struct snd_soc_dai *dai) 1273 { 1274 struct snd_soc_codec *codec = dai->codec; 1275 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1276 struct max98095_cdata *cdata; 1277 unsigned long long ni; 1278 unsigned int rate; 1279 u8 regval; 1280 1281 cdata = &max98095->dai[1]; 1282 1283 rate = params_rate(params); 1284 1285 switch (params_width(params)) { 1286 case 16: 1287 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1288 M98095_DAI_WS, 0); 1289 break; 1290 case 24: 1291 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1292 M98095_DAI_WS, M98095_DAI_WS); 1293 break; 1294 default: 1295 return -EINVAL; 1296 } 1297 1298 if (rate_value(rate, ®val)) 1299 return -EINVAL; 1300 1301 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, 1302 M98095_CLKMODE_MASK, regval); 1303 cdata->rate = rate; 1304 1305 /* Configure NI when operating as master */ 1306 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { 1307 if (max98095->sysclk == 0) { 1308 dev_err(codec->dev, "Invalid system clock frequency\n"); 1309 return -EINVAL; 1310 } 1311 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1312 * (unsigned long long int)rate; 1313 do_div(ni, (unsigned long long int)max98095->sysclk); 1314 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1315 (ni >> 8) & 0x7F); 1316 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1317 ni & 0xFF); 1318 } 1319 1320 /* Update sample rate mode */ 1321 if (rate < 50000) 1322 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1323 M98095_DAI_DHF, 0); 1324 else 1325 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1326 M98095_DAI_DHF, M98095_DAI_DHF); 1327 1328 return 0; 1329 } 1330 1331 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, 1332 struct snd_pcm_hw_params *params, 1333 struct snd_soc_dai *dai) 1334 { 1335 struct snd_soc_codec *codec = dai->codec; 1336 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1337 struct max98095_cdata *cdata; 1338 unsigned long long ni; 1339 unsigned int rate; 1340 u8 regval; 1341 1342 cdata = &max98095->dai[2]; 1343 1344 rate = params_rate(params); 1345 1346 switch (params_width(params)) { 1347 case 16: 1348 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1349 M98095_DAI_WS, 0); 1350 break; 1351 case 24: 1352 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1353 M98095_DAI_WS, M98095_DAI_WS); 1354 break; 1355 default: 1356 return -EINVAL; 1357 } 1358 1359 if (rate_value(rate, ®val)) 1360 return -EINVAL; 1361 1362 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, 1363 M98095_CLKMODE_MASK, regval); 1364 cdata->rate = rate; 1365 1366 /* Configure NI when operating as master */ 1367 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { 1368 if (max98095->sysclk == 0) { 1369 dev_err(codec->dev, "Invalid system clock frequency\n"); 1370 return -EINVAL; 1371 } 1372 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1373 * (unsigned long long int)rate; 1374 do_div(ni, (unsigned long long int)max98095->sysclk); 1375 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1376 (ni >> 8) & 0x7F); 1377 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1378 ni & 0xFF); 1379 } 1380 1381 /* Update sample rate mode */ 1382 if (rate < 50000) 1383 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1384 M98095_DAI_DHF, 0); 1385 else 1386 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1387 M98095_DAI_DHF, M98095_DAI_DHF); 1388 1389 return 0; 1390 } 1391 1392 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, 1393 int clk_id, unsigned int freq, int dir) 1394 { 1395 struct snd_soc_codec *codec = dai->codec; 1396 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1397 1398 /* Requested clock frequency is already setup */ 1399 if (freq == max98095->sysclk) 1400 return 0; 1401 1402 if (!IS_ERR(max98095->mclk)) { 1403 freq = clk_round_rate(max98095->mclk, freq); 1404 clk_set_rate(max98095->mclk, freq); 1405 } 1406 1407 /* Setup clocks for slave mode, and using the PLL 1408 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1409 * 0x02 (when master clk is 20MHz to 40MHz).. 1410 * 0x03 (when master clk is 40MHz to 60MHz).. 1411 */ 1412 if ((freq >= 10000000) && (freq < 20000000)) { 1413 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); 1414 } else if ((freq >= 20000000) && (freq < 40000000)) { 1415 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); 1416 } else if ((freq >= 40000000) && (freq < 60000000)) { 1417 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); 1418 } else { 1419 dev_err(codec->dev, "Invalid master clock frequency\n"); 1420 return -EINVAL; 1421 } 1422 1423 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1424 1425 max98095->sysclk = freq; 1426 return 0; 1427 } 1428 1429 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1430 unsigned int fmt) 1431 { 1432 struct snd_soc_codec *codec = codec_dai->codec; 1433 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1434 struct max98095_cdata *cdata; 1435 u8 regval = 0; 1436 1437 cdata = &max98095->dai[0]; 1438 1439 if (fmt != cdata->fmt) { 1440 cdata->fmt = fmt; 1441 1442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1443 case SND_SOC_DAIFMT_CBS_CFS: 1444 /* Slave mode PLL */ 1445 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 1446 0x80); 1447 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 1448 0x00); 1449 break; 1450 case SND_SOC_DAIFMT_CBM_CFM: 1451 /* Set to master mode */ 1452 regval |= M98095_DAI_MAS; 1453 break; 1454 case SND_SOC_DAIFMT_CBS_CFM: 1455 case SND_SOC_DAIFMT_CBM_CFS: 1456 default: 1457 dev_err(codec->dev, "Clock mode unsupported"); 1458 return -EINVAL; 1459 } 1460 1461 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1462 case SND_SOC_DAIFMT_I2S: 1463 regval |= M98095_DAI_DLY; 1464 break; 1465 case SND_SOC_DAIFMT_LEFT_J: 1466 break; 1467 default: 1468 return -EINVAL; 1469 } 1470 1471 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1472 case SND_SOC_DAIFMT_NB_NF: 1473 break; 1474 case SND_SOC_DAIFMT_NB_IF: 1475 regval |= M98095_DAI_WCI; 1476 break; 1477 case SND_SOC_DAIFMT_IB_NF: 1478 regval |= M98095_DAI_BCI; 1479 break; 1480 case SND_SOC_DAIFMT_IB_IF: 1481 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1482 break; 1483 default: 1484 return -EINVAL; 1485 } 1486 1487 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1488 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1489 M98095_DAI_WCI, regval); 1490 1491 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); 1492 } 1493 1494 return 0; 1495 } 1496 1497 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1498 unsigned int fmt) 1499 { 1500 struct snd_soc_codec *codec = codec_dai->codec; 1501 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1502 struct max98095_cdata *cdata; 1503 u8 regval = 0; 1504 1505 cdata = &max98095->dai[1]; 1506 1507 if (fmt != cdata->fmt) { 1508 cdata->fmt = fmt; 1509 1510 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1511 case SND_SOC_DAIFMT_CBS_CFS: 1512 /* Slave mode PLL */ 1513 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1514 0x80); 1515 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1516 0x00); 1517 break; 1518 case SND_SOC_DAIFMT_CBM_CFM: 1519 /* Set to master mode */ 1520 regval |= M98095_DAI_MAS; 1521 break; 1522 case SND_SOC_DAIFMT_CBS_CFM: 1523 case SND_SOC_DAIFMT_CBM_CFS: 1524 default: 1525 dev_err(codec->dev, "Clock mode unsupported"); 1526 return -EINVAL; 1527 } 1528 1529 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1530 case SND_SOC_DAIFMT_I2S: 1531 regval |= M98095_DAI_DLY; 1532 break; 1533 case SND_SOC_DAIFMT_LEFT_J: 1534 break; 1535 default: 1536 return -EINVAL; 1537 } 1538 1539 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1540 case SND_SOC_DAIFMT_NB_NF: 1541 break; 1542 case SND_SOC_DAIFMT_NB_IF: 1543 regval |= M98095_DAI_WCI; 1544 break; 1545 case SND_SOC_DAIFMT_IB_NF: 1546 regval |= M98095_DAI_BCI; 1547 break; 1548 case SND_SOC_DAIFMT_IB_IF: 1549 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1550 break; 1551 default: 1552 return -EINVAL; 1553 } 1554 1555 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1556 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1557 M98095_DAI_WCI, regval); 1558 1559 snd_soc_write(codec, M98095_035_DAI2_CLOCK, 1560 M98095_DAI_BSEL64); 1561 } 1562 1563 return 0; 1564 } 1565 1566 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, 1567 unsigned int fmt) 1568 { 1569 struct snd_soc_codec *codec = codec_dai->codec; 1570 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1571 struct max98095_cdata *cdata; 1572 u8 regval = 0; 1573 1574 cdata = &max98095->dai[2]; 1575 1576 if (fmt != cdata->fmt) { 1577 cdata->fmt = fmt; 1578 1579 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1580 case SND_SOC_DAIFMT_CBS_CFS: 1581 /* Slave mode PLL */ 1582 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1583 0x80); 1584 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1585 0x00); 1586 break; 1587 case SND_SOC_DAIFMT_CBM_CFM: 1588 /* Set to master mode */ 1589 regval |= M98095_DAI_MAS; 1590 break; 1591 case SND_SOC_DAIFMT_CBS_CFM: 1592 case SND_SOC_DAIFMT_CBM_CFS: 1593 default: 1594 dev_err(codec->dev, "Clock mode unsupported"); 1595 return -EINVAL; 1596 } 1597 1598 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1599 case SND_SOC_DAIFMT_I2S: 1600 regval |= M98095_DAI_DLY; 1601 break; 1602 case SND_SOC_DAIFMT_LEFT_J: 1603 break; 1604 default: 1605 return -EINVAL; 1606 } 1607 1608 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1609 case SND_SOC_DAIFMT_NB_NF: 1610 break; 1611 case SND_SOC_DAIFMT_NB_IF: 1612 regval |= M98095_DAI_WCI; 1613 break; 1614 case SND_SOC_DAIFMT_IB_NF: 1615 regval |= M98095_DAI_BCI; 1616 break; 1617 case SND_SOC_DAIFMT_IB_IF: 1618 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1619 break; 1620 default: 1621 return -EINVAL; 1622 } 1623 1624 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1625 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1626 M98095_DAI_WCI, regval); 1627 1628 snd_soc_write(codec, M98095_03F_DAI3_CLOCK, 1629 M98095_DAI_BSEL64); 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int max98095_set_bias_level(struct snd_soc_codec *codec, 1636 enum snd_soc_bias_level level) 1637 { 1638 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1639 int ret; 1640 1641 switch (level) { 1642 case SND_SOC_BIAS_ON: 1643 break; 1644 1645 case SND_SOC_BIAS_PREPARE: 1646 /* 1647 * SND_SOC_BIAS_PREPARE is called while preparing for a 1648 * transition to ON or away from ON. If current bias_level 1649 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1650 * away from ON. Disable the clock in that case, otherwise 1651 * enable it. 1652 */ 1653 if (!IS_ERR(max98095->mclk)) { 1654 if (codec->dapm.bias_level == SND_SOC_BIAS_ON) 1655 clk_disable_unprepare(max98095->mclk); 1656 else 1657 clk_prepare_enable(max98095->mclk); 1658 } 1659 break; 1660 1661 case SND_SOC_BIAS_STANDBY: 1662 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1663 ret = regcache_sync(max98095->regmap); 1664 1665 if (ret != 0) { 1666 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1667 return ret; 1668 } 1669 } 1670 1671 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1672 M98095_MBEN, M98095_MBEN); 1673 break; 1674 1675 case SND_SOC_BIAS_OFF: 1676 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1677 M98095_MBEN, 0); 1678 regcache_mark_dirty(max98095->regmap); 1679 break; 1680 } 1681 codec->dapm.bias_level = level; 1682 return 0; 1683 } 1684 1685 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 1686 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1687 1688 static const struct snd_soc_dai_ops max98095_dai1_ops = { 1689 .set_sysclk = max98095_dai_set_sysclk, 1690 .set_fmt = max98095_dai1_set_fmt, 1691 .hw_params = max98095_dai1_hw_params, 1692 }; 1693 1694 static const struct snd_soc_dai_ops max98095_dai2_ops = { 1695 .set_sysclk = max98095_dai_set_sysclk, 1696 .set_fmt = max98095_dai2_set_fmt, 1697 .hw_params = max98095_dai2_hw_params, 1698 }; 1699 1700 static const struct snd_soc_dai_ops max98095_dai3_ops = { 1701 .set_sysclk = max98095_dai_set_sysclk, 1702 .set_fmt = max98095_dai3_set_fmt, 1703 .hw_params = max98095_dai3_hw_params, 1704 }; 1705 1706 static struct snd_soc_dai_driver max98095_dai[] = { 1707 { 1708 .name = "HiFi", 1709 .playback = { 1710 .stream_name = "HiFi Playback", 1711 .channels_min = 1, 1712 .channels_max = 2, 1713 .rates = MAX98095_RATES, 1714 .formats = MAX98095_FORMATS, 1715 }, 1716 .capture = { 1717 .stream_name = "HiFi Capture", 1718 .channels_min = 1, 1719 .channels_max = 2, 1720 .rates = MAX98095_RATES, 1721 .formats = MAX98095_FORMATS, 1722 }, 1723 .ops = &max98095_dai1_ops, 1724 }, 1725 { 1726 .name = "Aux", 1727 .playback = { 1728 .stream_name = "Aux Playback", 1729 .channels_min = 1, 1730 .channels_max = 1, 1731 .rates = MAX98095_RATES, 1732 .formats = MAX98095_FORMATS, 1733 }, 1734 .ops = &max98095_dai2_ops, 1735 }, 1736 { 1737 .name = "Voice", 1738 .playback = { 1739 .stream_name = "Voice Playback", 1740 .channels_min = 1, 1741 .channels_max = 1, 1742 .rates = MAX98095_RATES, 1743 .formats = MAX98095_FORMATS, 1744 }, 1745 .ops = &max98095_dai3_ops, 1746 } 1747 1748 }; 1749 1750 static int max98095_get_eq_channel(const char *name) 1751 { 1752 if (strcmp(name, "EQ1 Mode") == 0) 1753 return 0; 1754 if (strcmp(name, "EQ2 Mode") == 0) 1755 return 1; 1756 return -EINVAL; 1757 } 1758 1759 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, 1760 struct snd_ctl_elem_value *ucontrol) 1761 { 1762 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1763 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1764 struct max98095_pdata *pdata = max98095->pdata; 1765 int channel = max98095_get_eq_channel(kcontrol->id.name); 1766 struct max98095_cdata *cdata; 1767 unsigned int sel = ucontrol->value.integer.value[0]; 1768 struct max98095_eq_cfg *coef_set; 1769 int fs, best, best_val, i; 1770 int regmask, regsave; 1771 1772 if (WARN_ON(channel > 1)) 1773 return -EINVAL; 1774 1775 if (!pdata || !max98095->eq_textcnt) 1776 return 0; 1777 1778 if (sel >= pdata->eq_cfgcnt) 1779 return -EINVAL; 1780 1781 cdata = &max98095->dai[channel]; 1782 cdata->eq_sel = sel; 1783 fs = cdata->rate; 1784 1785 /* Find the selected configuration with nearest sample rate */ 1786 best = 0; 1787 best_val = INT_MAX; 1788 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1789 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && 1790 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1791 best = i; 1792 best_val = abs(pdata->eq_cfg[i].rate - fs); 1793 } 1794 } 1795 1796 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1797 pdata->eq_cfg[best].name, 1798 pdata->eq_cfg[best].rate, fs); 1799 1800 coef_set = &pdata->eq_cfg[best]; 1801 1802 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; 1803 1804 /* Disable filter while configuring, and save current on/off state */ 1805 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 1806 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 1807 1808 mutex_lock(&max98095->lock); 1809 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 1810 m98095_eq_band(codec, channel, 0, coef_set->band1); 1811 m98095_eq_band(codec, channel, 1, coef_set->band2); 1812 m98095_eq_band(codec, channel, 2, coef_set->band3); 1813 m98095_eq_band(codec, channel, 3, coef_set->band4); 1814 m98095_eq_band(codec, channel, 4, coef_set->band5); 1815 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 1816 mutex_unlock(&max98095->lock); 1817 1818 /* Restore the original on/off state */ 1819 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 1820 return 0; 1821 } 1822 1823 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, 1824 struct snd_ctl_elem_value *ucontrol) 1825 { 1826 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1827 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1828 int channel = max98095_get_eq_channel(kcontrol->id.name); 1829 struct max98095_cdata *cdata; 1830 1831 cdata = &max98095->dai[channel]; 1832 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1833 1834 return 0; 1835 } 1836 1837 static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) 1838 { 1839 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1840 struct max98095_pdata *pdata = max98095->pdata; 1841 struct max98095_eq_cfg *cfg; 1842 unsigned int cfgcnt; 1843 int i, j; 1844 const char **t; 1845 int ret; 1846 1847 struct snd_kcontrol_new controls[] = { 1848 SOC_ENUM_EXT("EQ1 Mode", 1849 max98095->eq_enum, 1850 max98095_get_eq_enum, 1851 max98095_put_eq_enum), 1852 SOC_ENUM_EXT("EQ2 Mode", 1853 max98095->eq_enum, 1854 max98095_get_eq_enum, 1855 max98095_put_eq_enum), 1856 }; 1857 1858 cfg = pdata->eq_cfg; 1859 cfgcnt = pdata->eq_cfgcnt; 1860 1861 /* Setup an array of texts for the equalizer enum. 1862 * This is based on Mark Brown's equalizer driver code. 1863 */ 1864 max98095->eq_textcnt = 0; 1865 max98095->eq_texts = NULL; 1866 for (i = 0; i < cfgcnt; i++) { 1867 for (j = 0; j < max98095->eq_textcnt; j++) { 1868 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) 1869 break; 1870 } 1871 1872 if (j != max98095->eq_textcnt) 1873 continue; 1874 1875 /* Expand the array */ 1876 t = krealloc(max98095->eq_texts, 1877 sizeof(char *) * (max98095->eq_textcnt + 1), 1878 GFP_KERNEL); 1879 if (t == NULL) 1880 continue; 1881 1882 /* Store the new entry */ 1883 t[max98095->eq_textcnt] = cfg[i].name; 1884 max98095->eq_textcnt++; 1885 max98095->eq_texts = t; 1886 } 1887 1888 /* Now point the soc_enum to .texts array items */ 1889 max98095->eq_enum.texts = max98095->eq_texts; 1890 max98095->eq_enum.items = max98095->eq_textcnt; 1891 1892 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 1893 if (ret != 0) 1894 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); 1895 } 1896 1897 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; 1898 1899 static int max98095_get_bq_channel(struct snd_soc_codec *codec, 1900 const char *name) 1901 { 1902 int i; 1903 1904 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) 1905 if (strcmp(name, bq_mode_name[i]) == 0) 1906 return i; 1907 1908 /* Shouldn't happen */ 1909 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name); 1910 return -EINVAL; 1911 } 1912 1913 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, 1914 struct snd_ctl_elem_value *ucontrol) 1915 { 1916 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1917 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1918 struct max98095_pdata *pdata = max98095->pdata; 1919 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 1920 struct max98095_cdata *cdata; 1921 unsigned int sel = ucontrol->value.integer.value[0]; 1922 struct max98095_biquad_cfg *coef_set; 1923 int fs, best, best_val, i; 1924 int regmask, regsave; 1925 1926 if (channel < 0) 1927 return channel; 1928 1929 if (!pdata || !max98095->bq_textcnt) 1930 return 0; 1931 1932 if (sel >= pdata->bq_cfgcnt) 1933 return -EINVAL; 1934 1935 cdata = &max98095->dai[channel]; 1936 cdata->bq_sel = sel; 1937 fs = cdata->rate; 1938 1939 /* Find the selected configuration with nearest sample rate */ 1940 best = 0; 1941 best_val = INT_MAX; 1942 for (i = 0; i < pdata->bq_cfgcnt; i++) { 1943 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && 1944 abs(pdata->bq_cfg[i].rate - fs) < best_val) { 1945 best = i; 1946 best_val = abs(pdata->bq_cfg[i].rate - fs); 1947 } 1948 } 1949 1950 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1951 pdata->bq_cfg[best].name, 1952 pdata->bq_cfg[best].rate, fs); 1953 1954 coef_set = &pdata->bq_cfg[best]; 1955 1956 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; 1957 1958 /* Disable filter while configuring, and save current on/off state */ 1959 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 1960 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 1961 1962 mutex_lock(&max98095->lock); 1963 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 1964 m98095_biquad_band(codec, channel, 0, coef_set->band1); 1965 m98095_biquad_band(codec, channel, 1, coef_set->band2); 1966 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 1967 mutex_unlock(&max98095->lock); 1968 1969 /* Restore the original on/off state */ 1970 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 1971 return 0; 1972 } 1973 1974 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, 1975 struct snd_ctl_elem_value *ucontrol) 1976 { 1977 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1978 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1979 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 1980 struct max98095_cdata *cdata; 1981 1982 if (channel < 0) 1983 return channel; 1984 1985 cdata = &max98095->dai[channel]; 1986 ucontrol->value.enumerated.item[0] = cdata->bq_sel; 1987 1988 return 0; 1989 } 1990 1991 static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) 1992 { 1993 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1994 struct max98095_pdata *pdata = max98095->pdata; 1995 struct max98095_biquad_cfg *cfg; 1996 unsigned int cfgcnt; 1997 int i, j; 1998 const char **t; 1999 int ret; 2000 2001 struct snd_kcontrol_new controls[] = { 2002 SOC_ENUM_EXT((char *)bq_mode_name[0], 2003 max98095->bq_enum, 2004 max98095_get_bq_enum, 2005 max98095_put_bq_enum), 2006 SOC_ENUM_EXT((char *)bq_mode_name[1], 2007 max98095->bq_enum, 2008 max98095_get_bq_enum, 2009 max98095_put_bq_enum), 2010 }; 2011 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); 2012 2013 cfg = pdata->bq_cfg; 2014 cfgcnt = pdata->bq_cfgcnt; 2015 2016 /* Setup an array of texts for the biquad enum. 2017 * This is based on Mark Brown's equalizer driver code. 2018 */ 2019 max98095->bq_textcnt = 0; 2020 max98095->bq_texts = NULL; 2021 for (i = 0; i < cfgcnt; i++) { 2022 for (j = 0; j < max98095->bq_textcnt; j++) { 2023 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) 2024 break; 2025 } 2026 2027 if (j != max98095->bq_textcnt) 2028 continue; 2029 2030 /* Expand the array */ 2031 t = krealloc(max98095->bq_texts, 2032 sizeof(char *) * (max98095->bq_textcnt + 1), 2033 GFP_KERNEL); 2034 if (t == NULL) 2035 continue; 2036 2037 /* Store the new entry */ 2038 t[max98095->bq_textcnt] = cfg[i].name; 2039 max98095->bq_textcnt++; 2040 max98095->bq_texts = t; 2041 } 2042 2043 /* Now point the soc_enum to .texts array items */ 2044 max98095->bq_enum.texts = max98095->bq_texts; 2045 max98095->bq_enum.items = max98095->bq_textcnt; 2046 2047 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 2048 if (ret != 0) 2049 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); 2050 } 2051 2052 static void max98095_handle_pdata(struct snd_soc_codec *codec) 2053 { 2054 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2055 struct max98095_pdata *pdata = max98095->pdata; 2056 u8 regval = 0; 2057 2058 if (!pdata) { 2059 dev_dbg(codec->dev, "No platform data\n"); 2060 return; 2061 } 2062 2063 /* Configure mic for analog/digital mic mode */ 2064 if (pdata->digmic_left_mode) 2065 regval |= M98095_DIGMIC_L; 2066 2067 if (pdata->digmic_right_mode) 2068 regval |= M98095_DIGMIC_R; 2069 2070 snd_soc_write(codec, M98095_087_CFG_MIC, regval); 2071 2072 /* Configure equalizers */ 2073 if (pdata->eq_cfgcnt) 2074 max98095_handle_eq_pdata(codec); 2075 2076 /* Configure bi-quad filters */ 2077 if (pdata->bq_cfgcnt) 2078 max98095_handle_bq_pdata(codec); 2079 } 2080 2081 static irqreturn_t max98095_report_jack(int irq, void *data) 2082 { 2083 struct snd_soc_codec *codec = data; 2084 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2085 unsigned int value; 2086 int hp_report = 0; 2087 int mic_report = 0; 2088 2089 /* Read the Jack Status Register */ 2090 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS); 2091 2092 /* If ddone is not set, then detection isn't finished yet */ 2093 if ((value & M98095_DDONE) == 0) 2094 return IRQ_NONE; 2095 2096 /* if hp, check its bit, and if set, clear it */ 2097 if ((value & M98095_HP_IN || value & M98095_LO_IN) && 2098 max98095->headphone_jack) 2099 hp_report |= SND_JACK_HEADPHONE; 2100 2101 /* if mic, check its bit, and if set, clear it */ 2102 if ((value & M98095_MIC_IN) && max98095->mic_jack) 2103 mic_report |= SND_JACK_MICROPHONE; 2104 2105 if (max98095->headphone_jack == max98095->mic_jack) { 2106 snd_soc_jack_report(max98095->headphone_jack, 2107 hp_report | mic_report, 2108 SND_JACK_HEADSET); 2109 } else { 2110 if (max98095->headphone_jack) 2111 snd_soc_jack_report(max98095->headphone_jack, 2112 hp_report, SND_JACK_HEADPHONE); 2113 if (max98095->mic_jack) 2114 snd_soc_jack_report(max98095->mic_jack, 2115 mic_report, SND_JACK_MICROPHONE); 2116 } 2117 2118 return IRQ_HANDLED; 2119 } 2120 2121 static int max98095_jack_detect_enable(struct snd_soc_codec *codec) 2122 { 2123 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2124 int ret = 0; 2125 int detect_enable = M98095_JDEN; 2126 unsigned int slew = M98095_DEFAULT_SLEW_DELAY; 2127 2128 if (max98095->pdata->jack_detect_pin5en) 2129 detect_enable |= M98095_PIN5EN; 2130 2131 if (max98095->pdata->jack_detect_delay) 2132 slew = max98095->pdata->jack_detect_delay; 2133 2134 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew); 2135 if (ret < 0) { 2136 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); 2137 return ret; 2138 } 2139 2140 /* configure auto detection to be enabled */ 2141 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable); 2142 if (ret < 0) { 2143 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); 2144 return ret; 2145 } 2146 2147 return ret; 2148 } 2149 2150 static int max98095_jack_detect_disable(struct snd_soc_codec *codec) 2151 { 2152 int ret = 0; 2153 2154 /* configure auto detection to be disabled */ 2155 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0); 2156 if (ret < 0) { 2157 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); 2158 return ret; 2159 } 2160 2161 return ret; 2162 } 2163 2164 int max98095_jack_detect(struct snd_soc_codec *codec, 2165 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack) 2166 { 2167 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2168 struct i2c_client *client = to_i2c_client(codec->dev); 2169 int ret = 0; 2170 2171 max98095->headphone_jack = hp_jack; 2172 max98095->mic_jack = mic_jack; 2173 2174 /* only progress if we have at least 1 jack pointer */ 2175 if (!hp_jack && !mic_jack) 2176 return -EINVAL; 2177 2178 max98095_jack_detect_enable(codec); 2179 2180 /* enable interrupts for headphone jack detection */ 2181 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN, 2182 M98095_IDDONE, M98095_IDDONE); 2183 if (ret < 0) { 2184 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret); 2185 return ret; 2186 } 2187 2188 max98095_report_jack(client->irq, codec); 2189 return 0; 2190 } 2191 EXPORT_SYMBOL_GPL(max98095_jack_detect); 2192 2193 #ifdef CONFIG_PM 2194 static int max98095_suspend(struct snd_soc_codec *codec) 2195 { 2196 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2197 2198 if (max98095->headphone_jack || max98095->mic_jack) 2199 max98095_jack_detect_disable(codec); 2200 2201 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); 2202 2203 return 0; 2204 } 2205 2206 static int max98095_resume(struct snd_soc_codec *codec) 2207 { 2208 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2209 struct i2c_client *client = to_i2c_client(codec->dev); 2210 2211 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2212 2213 if (max98095->headphone_jack || max98095->mic_jack) { 2214 max98095_jack_detect_enable(codec); 2215 max98095_report_jack(client->irq, codec); 2216 } 2217 2218 return 0; 2219 } 2220 #else 2221 #define max98095_suspend NULL 2222 #define max98095_resume NULL 2223 #endif 2224 2225 static int max98095_reset(struct snd_soc_codec *codec) 2226 { 2227 int i, ret; 2228 2229 /* Gracefully reset the DSP core and the codec hardware 2230 * in a proper sequence */ 2231 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); 2232 if (ret < 0) { 2233 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); 2234 return ret; 2235 } 2236 2237 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); 2238 if (ret < 0) { 2239 dev_err(codec->dev, "Failed to reset codec: %d\n", ret); 2240 return ret; 2241 } 2242 2243 /* Reset to hardware default for registers, as there is not 2244 * a soft reset hardware control register */ 2245 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 2246 ret = snd_soc_write(codec, i, snd_soc_read(codec, i)); 2247 if (ret < 0) { 2248 dev_err(codec->dev, "Failed to reset: %d\n", ret); 2249 return ret; 2250 } 2251 } 2252 2253 return ret; 2254 } 2255 2256 static int max98095_probe(struct snd_soc_codec *codec) 2257 { 2258 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2259 struct max98095_cdata *cdata; 2260 struct i2c_client *client; 2261 int ret = 0; 2262 2263 max98095->mclk = devm_clk_get(codec->dev, "mclk"); 2264 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER) 2265 return -EPROBE_DEFER; 2266 2267 /* reset the codec, the DSP core, and disable all interrupts */ 2268 max98095_reset(codec); 2269 2270 client = to_i2c_client(codec->dev); 2271 2272 /* initialize private data */ 2273 2274 max98095->sysclk = (unsigned)-1; 2275 max98095->eq_textcnt = 0; 2276 max98095->bq_textcnt = 0; 2277 2278 cdata = &max98095->dai[0]; 2279 cdata->rate = (unsigned)-1; 2280 cdata->fmt = (unsigned)-1; 2281 cdata->eq_sel = 0; 2282 cdata->bq_sel = 0; 2283 2284 cdata = &max98095->dai[1]; 2285 cdata->rate = (unsigned)-1; 2286 cdata->fmt = (unsigned)-1; 2287 cdata->eq_sel = 0; 2288 cdata->bq_sel = 0; 2289 2290 cdata = &max98095->dai[2]; 2291 cdata->rate = (unsigned)-1; 2292 cdata->fmt = (unsigned)-1; 2293 cdata->eq_sel = 0; 2294 cdata->bq_sel = 0; 2295 2296 max98095->lin_state = 0; 2297 max98095->mic1pre = 0; 2298 max98095->mic2pre = 0; 2299 2300 if (client->irq) { 2301 /* register an audio interrupt */ 2302 ret = request_threaded_irq(client->irq, NULL, 2303 max98095_report_jack, 2304 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 2305 "max98095", codec); 2306 if (ret) { 2307 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret); 2308 goto err_access; 2309 } 2310 } 2311 2312 ret = snd_soc_read(codec, M98095_0FF_REV_ID); 2313 if (ret < 0) { 2314 dev_err(codec->dev, "Failure reading hardware revision: %d\n", 2315 ret); 2316 goto err_irq; 2317 } 2318 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); 2319 2320 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); 2321 2322 snd_soc_write(codec, M98095_048_MIX_DAC_LR, 2323 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); 2324 2325 snd_soc_write(codec, M98095_049_MIX_DAC_M, 2326 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); 2327 2328 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); 2329 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); 2330 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); 2331 2332 snd_soc_write(codec, M98095_02C_DAI1_IOCFG, 2333 M98095_S1NORMAL|M98095_SDATA); 2334 2335 snd_soc_write(codec, M98095_036_DAI2_IOCFG, 2336 M98095_S2NORMAL|M98095_SDATA); 2337 2338 snd_soc_write(codec, M98095_040_DAI3_IOCFG, 2339 M98095_S3NORMAL|M98095_SDATA); 2340 2341 max98095_handle_pdata(codec); 2342 2343 /* take the codec out of the shut down */ 2344 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, 2345 M98095_SHDNRUN); 2346 2347 return 0; 2348 2349 err_irq: 2350 if (client->irq) 2351 free_irq(client->irq, codec); 2352 err_access: 2353 return ret; 2354 } 2355 2356 static int max98095_remove(struct snd_soc_codec *codec) 2357 { 2358 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2359 struct i2c_client *client = to_i2c_client(codec->dev); 2360 2361 if (max98095->headphone_jack || max98095->mic_jack) 2362 max98095_jack_detect_disable(codec); 2363 2364 if (client->irq) 2365 free_irq(client->irq, codec); 2366 2367 return 0; 2368 } 2369 2370 static struct snd_soc_codec_driver soc_codec_dev_max98095 = { 2371 .probe = max98095_probe, 2372 .remove = max98095_remove, 2373 .suspend = max98095_suspend, 2374 .resume = max98095_resume, 2375 .set_bias_level = max98095_set_bias_level, 2376 .controls = max98095_snd_controls, 2377 .num_controls = ARRAY_SIZE(max98095_snd_controls), 2378 .dapm_widgets = max98095_dapm_widgets, 2379 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), 2380 .dapm_routes = max98095_audio_map, 2381 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), 2382 }; 2383 2384 static int max98095_i2c_probe(struct i2c_client *i2c, 2385 const struct i2c_device_id *id) 2386 { 2387 struct max98095_priv *max98095; 2388 int ret; 2389 2390 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv), 2391 GFP_KERNEL); 2392 if (max98095 == NULL) 2393 return -ENOMEM; 2394 2395 mutex_init(&max98095->lock); 2396 2397 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap); 2398 if (IS_ERR(max98095->regmap)) { 2399 ret = PTR_ERR(max98095->regmap); 2400 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2401 return ret; 2402 } 2403 2404 max98095->devtype = id->driver_data; 2405 i2c_set_clientdata(i2c, max98095); 2406 max98095->pdata = i2c->dev.platform_data; 2407 2408 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, 2409 max98095_dai, ARRAY_SIZE(max98095_dai)); 2410 return ret; 2411 } 2412 2413 static int max98095_i2c_remove(struct i2c_client *client) 2414 { 2415 snd_soc_unregister_codec(&client->dev); 2416 return 0; 2417 } 2418 2419 static const struct i2c_device_id max98095_i2c_id[] = { 2420 { "max98095", MAX98095 }, 2421 { } 2422 }; 2423 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); 2424 2425 static const struct of_device_id max98095_of_match[] = { 2426 { .compatible = "maxim,max98095", }, 2427 { } 2428 }; 2429 MODULE_DEVICE_TABLE(of, max98095_of_match); 2430 2431 static struct i2c_driver max98095_i2c_driver = { 2432 .driver = { 2433 .name = "max98095", 2434 .owner = THIS_MODULE, 2435 .of_match_table = of_match_ptr(max98095_of_match), 2436 }, 2437 .probe = max98095_i2c_probe, 2438 .remove = max98095_i2c_remove, 2439 .id_table = max98095_i2c_id, 2440 }; 2441 2442 module_i2c_driver(max98095_i2c_driver); 2443 2444 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); 2445 MODULE_AUTHOR("Peter Hsiang"); 2446 MODULE_LICENSE("GPL"); 2447