1 /* 2 * max98090.c -- MAX98090 ALSA SoC Audio driver 3 * 4 * Copyright 2011-2012 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/pm.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/acpi.h> 19 #include <sound/jack.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <sound/max98090.h> 25 #include "max98090.h" 26 27 #define DEBUG 28 #define EXTMIC_METHOD 29 #define EXTMIC_METHOD_TEST 30 31 /* Allows for sparsely populated register maps */ 32 static struct reg_default max98090_reg[] = { 33 { 0x00, 0x00 }, /* 00 Software Reset */ 34 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 35 { 0x04, 0x00 }, /* 04 System Clock Quick */ 36 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 37 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 38 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 39 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 40 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 41 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 42 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 43 { 0x0C, 0x00 }, /* 0C Reserved */ 44 { 0x0D, 0x00 }, /* 0D Input Config */ 45 { 0x0E, 0x1B }, /* 0E Line Input Level */ 46 { 0x0F, 0x00 }, /* 0F Line Config */ 47 48 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 49 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 50 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 51 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 52 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 53 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 54 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 55 { 0x17, 0x03 }, /* 17 Left ADC Level */ 56 { 0x18, 0x03 }, /* 18 Right ADC Level */ 57 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 58 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 59 { 0x1B, 0x00 }, /* 1B System Clock */ 60 { 0x1C, 0x00 }, /* 1C Clock Mode */ 61 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 62 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 63 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 64 65 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 66 { 0x21, 0x00 }, /* 21 Master Mode */ 67 { 0x22, 0x00 }, /* 22 Interface Format */ 68 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 69 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 70 { 0x25, 0x00 }, /* 25 I/O Configuration */ 71 { 0x26, 0x80 }, /* 26 Filter Config */ 72 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 73 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 74 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 75 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 76 { 0x2B, 0x00 }, /* 2B HP Control */ 77 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 78 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 79 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 80 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 81 82 { 0x30, 0x00 }, /* 30 Spk Control */ 83 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 84 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 85 { 0x33, 0x00 }, /* 33 ALC Timing */ 86 { 0x34, 0x00 }, /* 34 ALC Compressor */ 87 { 0x35, 0x00 }, /* 35 ALC Expander */ 88 { 0x36, 0x00 }, /* 36 ALC Gain */ 89 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 90 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 91 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 92 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 93 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 94 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 95 { 0x3D, 0x00 }, /* 3D Jack Detect */ 96 { 0x3E, 0x00 }, /* 3E Input Enable */ 97 { 0x3F, 0x00 }, /* 3F Output Enable */ 98 99 { 0x40, 0x00 }, /* 40 Level Control */ 100 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 101 { 0x42, 0x00 }, /* 42 Bias Control */ 102 { 0x43, 0x00 }, /* 43 DAC Control */ 103 { 0x44, 0x06 }, /* 44 ADC Control */ 104 { 0x45, 0x00 }, /* 45 Device Shutdown */ 105 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 106 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 107 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 108 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 109 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 110 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 111 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 112 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 113 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 114 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 115 116 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 117 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 118 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 119 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 120 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 121 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 122 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 123 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 124 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 125 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 126 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 127 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 128 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 129 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 130 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 131 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 132 133 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 134 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 135 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 136 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 137 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 138 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 139 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 140 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 141 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 142 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 143 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 144 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 145 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 146 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 147 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 148 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 149 150 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 151 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 152 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 153 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 154 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 155 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 156 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 157 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 158 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 159 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 160 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 161 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 162 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 163 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 164 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 165 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 166 167 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 168 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 169 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 170 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 171 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 172 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 173 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 174 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 175 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 176 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 177 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 178 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 179 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 180 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 181 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 182 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 183 184 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 185 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 186 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 187 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 188 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 189 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 190 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 191 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 192 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 193 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 194 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 195 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 196 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 197 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 198 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 199 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 200 201 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 202 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 203 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 204 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 205 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 206 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 207 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 208 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 209 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 210 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 211 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 212 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 213 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 214 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 215 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 216 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 217 218 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 219 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 220 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 221 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 222 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 223 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 224 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 225 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 226 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 227 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 228 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 229 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 230 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 231 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 232 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 233 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 234 235 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 236 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 237 { 0xC2, 0x00 }, /* C2 Sample Rate */ 238 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 239 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 240 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 241 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 242 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 243 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 244 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 245 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 246 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 247 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 248 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 249 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 250 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 251 252 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 253 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 254 }; 255 256 static bool max98090_volatile_register(struct device *dev, unsigned int reg) 257 { 258 switch (reg) { 259 case M98090_REG_DEVICE_STATUS: 260 case M98090_REG_JACK_STATUS: 261 case M98090_REG_REVISION_ID: 262 return true; 263 default: 264 return false; 265 } 266 } 267 268 static bool max98090_readable_register(struct device *dev, unsigned int reg) 269 { 270 switch (reg) { 271 case M98090_REG_DEVICE_STATUS: 272 case M98090_REG_JACK_STATUS: 273 case M98090_REG_INTERRUPT_S: 274 case M98090_REG_RESERVED: 275 case M98090_REG_LINE_INPUT_CONFIG: 276 case M98090_REG_LINE_INPUT_LEVEL: 277 case M98090_REG_INPUT_MODE: 278 case M98090_REG_MIC1_INPUT_LEVEL: 279 case M98090_REG_MIC2_INPUT_LEVEL: 280 case M98090_REG_MIC_BIAS_VOLTAGE: 281 case M98090_REG_DIGITAL_MIC_ENABLE: 282 case M98090_REG_DIGITAL_MIC_CONFIG: 283 case M98090_REG_LEFT_ADC_MIXER: 284 case M98090_REG_RIGHT_ADC_MIXER: 285 case M98090_REG_LEFT_ADC_LEVEL: 286 case M98090_REG_RIGHT_ADC_LEVEL: 287 case M98090_REG_ADC_BIQUAD_LEVEL: 288 case M98090_REG_ADC_SIDETONE: 289 case M98090_REG_SYSTEM_CLOCK: 290 case M98090_REG_CLOCK_MODE: 291 case M98090_REG_CLOCK_RATIO_NI_MSB: 292 case M98090_REG_CLOCK_RATIO_NI_LSB: 293 case M98090_REG_CLOCK_RATIO_MI_MSB: 294 case M98090_REG_CLOCK_RATIO_MI_LSB: 295 case M98090_REG_MASTER_MODE: 296 case M98090_REG_INTERFACE_FORMAT: 297 case M98090_REG_TDM_CONTROL: 298 case M98090_REG_TDM_FORMAT: 299 case M98090_REG_IO_CONFIGURATION: 300 case M98090_REG_FILTER_CONFIG: 301 case M98090_REG_DAI_PLAYBACK_LEVEL: 302 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: 303 case M98090_REG_LEFT_HP_MIXER: 304 case M98090_REG_RIGHT_HP_MIXER: 305 case M98090_REG_HP_CONTROL: 306 case M98090_REG_LEFT_HP_VOLUME: 307 case M98090_REG_RIGHT_HP_VOLUME: 308 case M98090_REG_LEFT_SPK_MIXER: 309 case M98090_REG_RIGHT_SPK_MIXER: 310 case M98090_REG_SPK_CONTROL: 311 case M98090_REG_LEFT_SPK_VOLUME: 312 case M98090_REG_RIGHT_SPK_VOLUME: 313 case M98090_REG_DRC_TIMING: 314 case M98090_REG_DRC_COMPRESSOR: 315 case M98090_REG_DRC_EXPANDER: 316 case M98090_REG_DRC_GAIN: 317 case M98090_REG_RCV_LOUTL_MIXER: 318 case M98090_REG_RCV_LOUTL_CONTROL: 319 case M98090_REG_RCV_LOUTL_VOLUME: 320 case M98090_REG_LOUTR_MIXER: 321 case M98090_REG_LOUTR_CONTROL: 322 case M98090_REG_LOUTR_VOLUME: 323 case M98090_REG_JACK_DETECT: 324 case M98090_REG_INPUT_ENABLE: 325 case M98090_REG_OUTPUT_ENABLE: 326 case M98090_REG_LEVEL_CONTROL: 327 case M98090_REG_DSP_FILTER_ENABLE: 328 case M98090_REG_BIAS_CONTROL: 329 case M98090_REG_DAC_CONTROL: 330 case M98090_REG_ADC_CONTROL: 331 case M98090_REG_DEVICE_SHUTDOWN: 332 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: 333 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: 334 case M98090_REG_DMIC3_VOLUME: 335 case M98090_REG_DMIC4_VOLUME: 336 case M98090_REG_DMIC34_BQ_PREATTEN: 337 case M98090_REG_RECORD_TDM_SLOT: 338 case M98090_REG_SAMPLE_RATE: 339 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: 340 case M98090_REG_REVISION_ID: 341 return true; 342 default: 343 return false; 344 } 345 } 346 347 static int max98090_reset(struct max98090_priv *max98090) 348 { 349 int ret; 350 351 /* Reset the codec by writing to this write-only reset register */ 352 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 353 M98090_SWRESET_MASK); 354 if (ret < 0) { 355 dev_err(max98090->codec->dev, 356 "Failed to reset codec: %d\n", ret); 357 return ret; 358 } 359 360 msleep(20); 361 return ret; 362 } 363 364 static const unsigned int max98090_micboost_tlv[] = { 365 TLV_DB_RANGE_HEAD(2), 366 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 367 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 368 }; 369 370 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 371 372 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 373 -600, 600, 0); 374 375 static const unsigned int max98090_line_tlv[] = { 376 TLV_DB_RANGE_HEAD(2), 377 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 378 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), 379 }; 380 381 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 382 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 383 384 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 385 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 386 387 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0); 388 389 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0); 390 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 391 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 392 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 393 394 static const unsigned int max98090_mixout_tlv[] = { 395 TLV_DB_RANGE_HEAD(2), 396 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 397 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), 398 }; 399 400 static const unsigned int max98090_hp_tlv[] = { 401 TLV_DB_RANGE_HEAD(5), 402 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 403 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 404 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 405 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 406 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 407 }; 408 409 static const unsigned int max98090_spk_tlv[] = { 410 TLV_DB_RANGE_HEAD(5), 411 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 412 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 413 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 414 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 415 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0), 416 }; 417 418 static const unsigned int max98090_rcv_lout_tlv[] = { 419 TLV_DB_RANGE_HEAD(5), 420 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 421 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 422 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 423 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 424 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 425 }; 426 427 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 428 struct snd_ctl_elem_value *ucontrol) 429 { 430 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 431 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 432 struct soc_mixer_control *mc = 433 (struct soc_mixer_control *)kcontrol->private_value; 434 unsigned int mask = (1 << fls(mc->max)) - 1; 435 unsigned int val = snd_soc_read(codec, mc->reg); 436 unsigned int *select; 437 438 switch (mc->reg) { 439 case M98090_REG_MIC1_INPUT_LEVEL: 440 select = &(max98090->pa1en); 441 break; 442 case M98090_REG_MIC2_INPUT_LEVEL: 443 select = &(max98090->pa2en); 444 break; 445 case M98090_REG_ADC_SIDETONE: 446 select = &(max98090->sidetone); 447 break; 448 default: 449 return -EINVAL; 450 } 451 452 val = (val >> mc->shift) & mask; 453 454 if (val >= 1) { 455 /* If on, return the volume */ 456 val = val - 1; 457 *select = val; 458 } else { 459 /* If off, return last stored value */ 460 val = *select; 461 } 462 463 ucontrol->value.integer.value[0] = val; 464 return 0; 465 } 466 467 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 468 struct snd_ctl_elem_value *ucontrol) 469 { 470 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 471 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 472 struct soc_mixer_control *mc = 473 (struct soc_mixer_control *)kcontrol->private_value; 474 unsigned int mask = (1 << fls(mc->max)) - 1; 475 unsigned int sel = ucontrol->value.integer.value[0]; 476 unsigned int val = snd_soc_read(codec, mc->reg); 477 unsigned int *select; 478 479 switch (mc->reg) { 480 case M98090_REG_MIC1_INPUT_LEVEL: 481 select = &(max98090->pa1en); 482 break; 483 case M98090_REG_MIC2_INPUT_LEVEL: 484 select = &(max98090->pa2en); 485 break; 486 case M98090_REG_ADC_SIDETONE: 487 select = &(max98090->sidetone); 488 break; 489 default: 490 return -EINVAL; 491 } 492 493 val = (val >> mc->shift) & mask; 494 495 *select = sel; 496 497 /* Setting a volume is only valid if it is already On */ 498 if (val >= 1) { 499 sel = sel + 1; 500 } else { 501 /* Write what was already there */ 502 sel = val; 503 } 504 505 snd_soc_update_bits(codec, mc->reg, 506 mask << mc->shift, 507 sel << mc->shift); 508 509 return 0; 510 } 511 512 static const char *max98090_perf_pwr_text[] = 513 { "High Performance", "Low Power" }; 514 static const char *max98090_pwr_perf_text[] = 515 { "Low Power", "High Performance" }; 516 517 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, 518 M98090_REG_BIAS_CONTROL, 519 M98090_VCM_MODE_SHIFT, 520 max98090_pwr_perf_text); 521 522 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 523 524 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, 525 M98090_REG_ADC_CONTROL, 526 M98090_OSR128_SHIFT, 527 max98090_osr128_text); 528 529 static const char *max98090_mode_text[] = { "Voice", "Music" }; 530 531 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, 532 M98090_REG_FILTER_CONFIG, 533 M98090_MODE_SHIFT, 534 max98090_mode_text); 535 536 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, 537 M98090_REG_FILTER_CONFIG, 538 M98090_FLT_DMIC34MODE_SHIFT, 539 max98090_mode_text); 540 541 static const char *max98090_drcatk_text[] = 542 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 543 544 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, 545 M98090_REG_DRC_TIMING, 546 M98090_DRCATK_SHIFT, 547 max98090_drcatk_text); 548 549 static const char *max98090_drcrls_text[] = 550 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 551 552 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, 553 M98090_REG_DRC_TIMING, 554 M98090_DRCRLS_SHIFT, 555 max98090_drcrls_text); 556 557 static const char *max98090_alccmp_text[] = 558 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 559 560 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, 561 M98090_REG_DRC_COMPRESSOR, 562 M98090_DRCCMP_SHIFT, 563 max98090_alccmp_text); 564 565 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 566 567 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, 568 M98090_REG_DRC_EXPANDER, 569 M98090_DRCEXP_SHIFT, 570 max98090_drcexp_text); 571 572 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, 573 M98090_REG_DAC_CONTROL, 574 M98090_PERFMODE_SHIFT, 575 max98090_perf_pwr_text); 576 577 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, 578 M98090_REG_DAC_CONTROL, 579 M98090_DACHP_SHIFT, 580 max98090_pwr_perf_text); 581 582 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, 583 M98090_REG_ADC_CONTROL, 584 M98090_ADCHP_SHIFT, 585 max98090_pwr_perf_text); 586 587 static const struct snd_kcontrol_new max98090_snd_controls[] = { 588 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 589 590 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 591 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 592 593 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 594 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 595 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 596 max98090_put_enab_tlv, max98090_micboost_tlv), 597 598 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 599 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 600 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 601 max98090_put_enab_tlv, max98090_micboost_tlv), 602 603 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 604 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 605 max98090_mic_tlv), 606 607 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 608 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 609 max98090_mic_tlv), 610 611 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 612 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 613 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 614 615 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 616 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 617 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 618 619 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 620 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 621 max98090_line_tlv), 622 623 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 624 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 625 max98090_line_tlv), 626 627 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 628 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 629 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 630 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 631 632 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 633 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 634 max98090_avg_tlv), 635 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 636 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 637 max98090_avg_tlv), 638 639 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 640 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 641 max98090_av_tlv), 642 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 643 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 644 max98090_av_tlv), 645 646 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 647 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 648 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 649 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 650 651 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 652 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 653 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 654 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 655 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 656 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 657 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 658 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 659 SOC_ENUM("Filter Mode", max98090_mode_enum), 660 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 661 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 662 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 663 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 664 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 665 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 666 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 667 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 668 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 669 max98090_put_enab_tlv, max98090_micboost_tlv), 670 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 671 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 672 max98090_dvg_tlv), 673 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 674 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 675 max98090_dv_tlv), 676 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 677 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 678 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 679 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 680 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 681 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 682 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 683 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 684 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 685 1), 686 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 687 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 688 max98090_dv_tlv), 689 690 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 691 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 692 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 693 SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 694 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 695 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 696 max98090_alcmakeup_tlv), 697 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 698 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 699 SOC_SINGLE_TLV("ALC Compression Threshold Volume", 700 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 701 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 702 SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 703 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 704 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 705 706 SOC_ENUM("DAC HP Playback Performance Mode", 707 max98090_dac_perfmode_enum), 708 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 709 710 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 711 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 712 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 713 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 714 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 715 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 716 717 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 718 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 719 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 720 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 721 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 722 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 723 724 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 725 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 726 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 727 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 728 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 729 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 730 731 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 732 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 733 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 734 735 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 736 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 737 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 738 0, max98090_spk_tlv), 739 740 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 741 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 742 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 743 744 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 745 M98090_HPLM_SHIFT, 1, 1), 746 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 747 M98090_HPRM_SHIFT, 1, 1), 748 749 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 750 M98090_SPLM_SHIFT, 1, 1), 751 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 752 M98090_SPRM_SHIFT, 1, 1), 753 754 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 755 M98090_RCVLM_SHIFT, 1, 1), 756 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 757 M98090_RCVRM_SHIFT, 1, 1), 758 759 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 760 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 761 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 762 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 763 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 764 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 765 766 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 767 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 768 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 769 }; 770 771 static const struct snd_kcontrol_new max98091_snd_controls[] = { 772 773 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 774 M98090_DMIC34_ZEROPAD_SHIFT, 775 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 776 777 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 778 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 779 M98090_FLT_DMIC34HPF_SHIFT, 780 M98090_FLT_DMIC34HPF_NUM - 1, 0), 781 782 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 783 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 784 max98090_avg_tlv), 785 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 786 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 787 max98090_avg_tlv), 788 789 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 790 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 791 max98090_av_tlv), 792 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 793 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 794 max98090_av_tlv), 795 796 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 797 M98090_REG_DMIC34_BIQUAD_BASE, 15), 798 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 799 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 800 801 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 802 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 803 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 804 }; 805 806 static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 807 struct snd_kcontrol *kcontrol, int event) 808 { 809 struct snd_soc_codec *codec = w->codec; 810 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 811 812 unsigned int val = snd_soc_read(codec, w->reg); 813 814 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 815 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 816 else 817 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 818 819 820 if (val >= 1) { 821 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 822 max98090->pa1en = val - 1; /* Update for volatile */ 823 } else { 824 max98090->pa2en = val - 1; /* Update for volatile */ 825 } 826 } 827 828 switch (event) { 829 case SND_SOC_DAPM_POST_PMU: 830 /* If turning on, set to most recently selected volume */ 831 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 832 val = max98090->pa1en + 1; 833 else 834 val = max98090->pa2en + 1; 835 break; 836 case SND_SOC_DAPM_POST_PMD: 837 /* If turning off, turn off */ 838 val = 0; 839 break; 840 default: 841 return -EINVAL; 842 } 843 844 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 845 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK, 846 val << M98090_MIC_PA1EN_SHIFT); 847 else 848 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK, 849 val << M98090_MIC_PA2EN_SHIFT); 850 851 return 0; 852 } 853 854 static const char *mic1_mux_text[] = { "IN12", "IN56" }; 855 856 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, 857 M98090_REG_INPUT_MODE, 858 M98090_EXTMIC1_SHIFT, 859 mic1_mux_text); 860 861 static const struct snd_kcontrol_new max98090_mic1_mux = 862 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 863 864 static const char *mic2_mux_text[] = { "IN34", "IN56" }; 865 866 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, 867 M98090_REG_INPUT_MODE, 868 M98090_EXTMIC2_SHIFT, 869 mic2_mux_text); 870 871 static const struct snd_kcontrol_new max98090_mic2_mux = 872 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 873 874 static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 875 876 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 877 878 static const struct snd_kcontrol_new max98090_dmic_mux = 879 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum); 880 881 static const char *max98090_micpre_text[] = { "Off", "On" }; 882 883 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum, 884 M98090_REG_MIC1_INPUT_LEVEL, 885 M98090_MIC_PA1EN_SHIFT, 886 max98090_micpre_text); 887 888 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum, 889 M98090_REG_MIC2_INPUT_LEVEL, 890 M98090_MIC_PA2EN_SHIFT, 891 max98090_micpre_text); 892 893 /* LINEA mixer switch */ 894 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 895 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 896 M98090_IN1SEEN_SHIFT, 1, 0), 897 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 898 M98090_IN3SEEN_SHIFT, 1, 0), 899 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 900 M98090_IN5SEEN_SHIFT, 1, 0), 901 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 902 M98090_IN34DIFF_SHIFT, 1, 0), 903 }; 904 905 /* LINEB mixer switch */ 906 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 907 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 908 M98090_IN2SEEN_SHIFT, 1, 0), 909 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 910 M98090_IN4SEEN_SHIFT, 1, 0), 911 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 912 M98090_IN6SEEN_SHIFT, 1, 0), 913 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 914 M98090_IN56DIFF_SHIFT, 1, 0), 915 }; 916 917 /* Left ADC mixer switch */ 918 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 919 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 920 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 921 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 922 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 923 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 924 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 925 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 926 M98090_MIXADL_LINEA_SHIFT, 1, 0), 927 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 928 M98090_MIXADL_LINEB_SHIFT, 1, 0), 929 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 930 M98090_MIXADL_MIC1_SHIFT, 1, 0), 931 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 932 M98090_MIXADL_MIC2_SHIFT, 1, 0), 933 }; 934 935 /* Right ADC mixer switch */ 936 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 937 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 938 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 939 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 940 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 941 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 942 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 943 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 944 M98090_MIXADR_LINEA_SHIFT, 1, 0), 945 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 946 M98090_MIXADR_LINEB_SHIFT, 1, 0), 947 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 948 M98090_MIXADR_MIC1_SHIFT, 1, 0), 949 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 950 M98090_MIXADR_MIC2_SHIFT, 1, 0), 951 }; 952 953 static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 954 955 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, 956 M98090_REG_IO_CONFIGURATION, 957 M98090_LTEN_SHIFT, 958 lten_mux_text); 959 960 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, 961 M98090_REG_IO_CONFIGURATION, 962 M98090_LTEN_SHIFT, 963 lten_mux_text); 964 965 static const struct snd_kcontrol_new max98090_ltenl_mux = 966 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 967 968 static const struct snd_kcontrol_new max98090_ltenr_mux = 969 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 970 971 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 972 973 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, 974 M98090_REG_IO_CONFIGURATION, 975 M98090_LBEN_SHIFT, 976 lben_mux_text); 977 978 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, 979 M98090_REG_IO_CONFIGURATION, 980 M98090_LBEN_SHIFT, 981 lben_mux_text); 982 983 static const struct snd_kcontrol_new max98090_lbenl_mux = 984 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 985 986 static const struct snd_kcontrol_new max98090_lbenr_mux = 987 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 988 989 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 990 991 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 992 993 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, 994 M98090_REG_ADC_SIDETONE, 995 M98090_DSTSL_SHIFT, 996 stenl_mux_text); 997 998 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, 999 M98090_REG_ADC_SIDETONE, 1000 M98090_DSTSR_SHIFT, 1001 stenr_mux_text); 1002 1003 static const struct snd_kcontrol_new max98090_stenl_mux = 1004 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 1005 1006 static const struct snd_kcontrol_new max98090_stenr_mux = 1007 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 1008 1009 /* Left speaker mixer switch */ 1010 static const struct 1011 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 1012 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1013 M98090_MIXSPL_DACL_SHIFT, 1, 0), 1014 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1015 M98090_MIXSPL_DACR_SHIFT, 1, 0), 1016 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 1017 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 1018 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 1019 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 1020 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 1021 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 1022 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 1023 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 1024 }; 1025 1026 /* Right speaker mixer switch */ 1027 static const struct 1028 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 1029 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1030 M98090_MIXSPR_DACL_SHIFT, 1, 0), 1031 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1032 M98090_MIXSPR_DACR_SHIFT, 1, 0), 1033 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 1034 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 1035 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 1036 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 1037 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 1038 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 1039 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 1040 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 1041 }; 1042 1043 /* Left headphone mixer switch */ 1044 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 1045 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 1046 M98090_MIXHPL_DACL_SHIFT, 1, 0), 1047 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 1048 M98090_MIXHPL_DACR_SHIFT, 1, 0), 1049 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 1050 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 1051 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 1052 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 1053 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 1054 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 1055 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 1056 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 1057 }; 1058 1059 /* Right headphone mixer switch */ 1060 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 1061 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1062 M98090_MIXHPR_DACL_SHIFT, 1, 0), 1063 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1064 M98090_MIXHPR_DACR_SHIFT, 1, 0), 1065 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 1066 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 1067 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 1068 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 1069 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 1070 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 1071 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 1072 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 1073 }; 1074 1075 /* Left receiver mixer switch */ 1076 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1077 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1078 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1079 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1080 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1081 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1082 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1083 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1084 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1085 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1086 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1087 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1088 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1089 }; 1090 1091 /* Right receiver mixer switch */ 1092 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1093 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1094 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1095 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1096 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1097 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1098 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1099 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1100 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1101 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1102 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1103 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1104 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1105 }; 1106 1107 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1108 1109 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, 1110 M98090_REG_LOUTR_MIXER, 1111 M98090_LINMOD_SHIFT, 1112 linmod_mux_text); 1113 1114 static const struct snd_kcontrol_new max98090_linmod_mux = 1115 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1116 1117 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1118 1119 /* 1120 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1121 */ 1122 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, 1123 M98090_REG_HP_CONTROL, 1124 M98090_MIXHPLSEL_SHIFT, 1125 mixhpsel_mux_text); 1126 1127 static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1128 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1129 1130 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, 1131 M98090_REG_HP_CONTROL, 1132 M98090_MIXHPRSEL_SHIFT, 1133 mixhpsel_mux_text); 1134 1135 static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1136 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1137 1138 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1139 1140 SND_SOC_DAPM_INPUT("MIC1"), 1141 SND_SOC_DAPM_INPUT("MIC2"), 1142 SND_SOC_DAPM_INPUT("DMICL"), 1143 SND_SOC_DAPM_INPUT("DMICR"), 1144 SND_SOC_DAPM_INPUT("IN1"), 1145 SND_SOC_DAPM_INPUT("IN2"), 1146 SND_SOC_DAPM_INPUT("IN3"), 1147 SND_SOC_DAPM_INPUT("IN4"), 1148 SND_SOC_DAPM_INPUT("IN5"), 1149 SND_SOC_DAPM_INPUT("IN6"), 1150 SND_SOC_DAPM_INPUT("IN12"), 1151 SND_SOC_DAPM_INPUT("IN34"), 1152 SND_SOC_DAPM_INPUT("IN56"), 1153 1154 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1155 M98090_MBEN_SHIFT, 0, NULL, 0), 1156 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1157 M98090_SHDNN_SHIFT, 0, NULL, 0), 1158 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1159 M98090_SDIEN_SHIFT, 0, NULL, 0), 1160 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1161 M98090_SDOEN_SHIFT, 0, NULL, 0), 1162 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1163 M98090_DIGMICL_SHIFT, 0, NULL, 0), 1164 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1165 M98090_DIGMICR_SHIFT, 0, NULL, 0), 1166 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1167 M98090_AHPF_SHIFT, 0, NULL, 0), 1168 1169 /* 1170 * Note: Sysclk and misc power supplies are taken care of by SHDN 1171 */ 1172 1173 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1174 0, 0, &max98090_mic1_mux), 1175 1176 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1177 0, 0, &max98090_mic2_mux), 1178 1179 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM, 1180 0, 0, &max98090_dmic_mux), 1181 1182 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1183 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1184 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1185 1186 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1187 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1188 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1189 1190 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1191 &max98090_linea_mixer_controls[0], 1192 ARRAY_SIZE(max98090_linea_mixer_controls)), 1193 1194 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1195 &max98090_lineb_mixer_controls[0], 1196 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1197 1198 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1199 M98090_LINEAEN_SHIFT, 0, NULL, 0), 1200 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1201 M98090_LINEBEN_SHIFT, 0, NULL, 0), 1202 1203 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1204 &max98090_left_adc_mixer_controls[0], 1205 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1206 1207 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1208 &max98090_right_adc_mixer_controls[0], 1209 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1210 1211 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1212 M98090_ADLEN_SHIFT, 0), 1213 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1214 M98090_ADREN_SHIFT, 0), 1215 1216 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1217 SND_SOC_NOPM, 0, 0), 1218 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, 1219 SND_SOC_NOPM, 0, 0), 1220 1221 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1222 0, 0, &max98090_lbenl_mux), 1223 1224 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1225 0, 0, &max98090_lbenr_mux), 1226 1227 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1228 0, 0, &max98090_ltenl_mux), 1229 1230 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1231 0, 0, &max98090_ltenr_mux), 1232 1233 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1234 0, 0, &max98090_stenl_mux), 1235 1236 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1237 0, 0, &max98090_stenr_mux), 1238 1239 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1240 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1241 1242 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1243 M98090_DALEN_SHIFT, 0), 1244 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1245 M98090_DAREN_SHIFT, 0), 1246 1247 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1248 &max98090_left_hp_mixer_controls[0], 1249 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1250 1251 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1252 &max98090_right_hp_mixer_controls[0], 1253 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1254 1255 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1256 &max98090_left_speaker_mixer_controls[0], 1257 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1258 1259 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1260 &max98090_right_speaker_mixer_controls[0], 1261 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1262 1263 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1264 &max98090_left_rcv_mixer_controls[0], 1265 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1266 1267 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1268 &max98090_right_rcv_mixer_controls[0], 1269 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1270 1271 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER, 1272 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux), 1273 1274 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL, 1275 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux), 1276 1277 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL, 1278 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux), 1279 1280 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1281 M98090_HPLEN_SHIFT, 0, NULL, 0), 1282 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1283 M98090_HPREN_SHIFT, 0, NULL, 0), 1284 1285 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1286 M98090_SPLEN_SHIFT, 0, NULL, 0), 1287 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1288 M98090_SPREN_SHIFT, 0, NULL, 0), 1289 1290 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1291 M98090_RCVLEN_SHIFT, 0, NULL, 0), 1292 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1293 M98090_RCVREN_SHIFT, 0, NULL, 0), 1294 1295 SND_SOC_DAPM_OUTPUT("HPL"), 1296 SND_SOC_DAPM_OUTPUT("HPR"), 1297 SND_SOC_DAPM_OUTPUT("SPKL"), 1298 SND_SOC_DAPM_OUTPUT("SPKR"), 1299 SND_SOC_DAPM_OUTPUT("RCVL"), 1300 SND_SOC_DAPM_OUTPUT("RCVR"), 1301 }; 1302 1303 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1304 1305 SND_SOC_DAPM_INPUT("DMIC3"), 1306 SND_SOC_DAPM_INPUT("DMIC4"), 1307 1308 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1309 M98090_DIGMIC3_SHIFT, 0, NULL, 0), 1310 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1311 M98090_DIGMIC4_SHIFT, 0, NULL, 0), 1312 }; 1313 1314 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1315 1316 {"MIC1 Input", NULL, "MIC1"}, 1317 {"MIC2 Input", NULL, "MIC2"}, 1318 1319 {"DMICL", NULL, "DMICL_ENA"}, 1320 {"DMICR", NULL, "DMICR_ENA"}, 1321 {"DMICL", NULL, "AHPF"}, 1322 {"DMICR", NULL, "AHPF"}, 1323 1324 /* MIC1 input mux */ 1325 {"MIC1 Mux", "IN12", "IN12"}, 1326 {"MIC1 Mux", "IN56", "IN56"}, 1327 1328 /* MIC2 input mux */ 1329 {"MIC2 Mux", "IN34", "IN34"}, 1330 {"MIC2 Mux", "IN56", "IN56"}, 1331 1332 {"MIC1 Input", NULL, "MIC1 Mux"}, 1333 {"MIC2 Input", NULL, "MIC2 Mux"}, 1334 1335 /* Left ADC input mixer */ 1336 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1337 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1338 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1339 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1340 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1341 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1342 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1343 1344 /* Right ADC input mixer */ 1345 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1346 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1347 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1348 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1349 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1350 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1351 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1352 1353 /* Line A input mixer */ 1354 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1355 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1356 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1357 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1358 1359 /* Line B input mixer */ 1360 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1361 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1362 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1363 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1364 1365 {"LINEA Input", NULL, "LINEA Mixer"}, 1366 {"LINEB Input", NULL, "LINEB Mixer"}, 1367 1368 /* Inputs */ 1369 {"ADCL", NULL, "Left ADC Mixer"}, 1370 {"ADCR", NULL, "Right ADC Mixer"}, 1371 {"ADCL", NULL, "SHDN"}, 1372 {"ADCR", NULL, "SHDN"}, 1373 1374 {"DMIC Mux", "ADC", "ADCL"}, 1375 {"DMIC Mux", "ADC", "ADCR"}, 1376 {"DMIC Mux", "DMIC", "DMICL"}, 1377 {"DMIC Mux", "DMIC", "DMICR"}, 1378 1379 {"LBENL Mux", "Normal", "DMIC Mux"}, 1380 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1381 {"LBENR Mux", "Normal", "DMIC Mux"}, 1382 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1383 1384 {"AIFOUTL", NULL, "LBENL Mux"}, 1385 {"AIFOUTR", NULL, "LBENR Mux"}, 1386 {"AIFOUTL", NULL, "SHDN"}, 1387 {"AIFOUTR", NULL, "SHDN"}, 1388 {"AIFOUTL", NULL, "SDOEN"}, 1389 {"AIFOUTR", NULL, "SDOEN"}, 1390 1391 {"LTENL Mux", "Normal", "AIFINL"}, 1392 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1393 {"LTENR Mux", "Normal", "AIFINR"}, 1394 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1395 1396 {"DACL", NULL, "LTENL Mux"}, 1397 {"DACR", NULL, "LTENR Mux"}, 1398 1399 {"STENL Mux", "Sidetone Left", "ADCL"}, 1400 {"STENL Mux", "Sidetone Left", "DMICL"}, 1401 {"STENR Mux", "Sidetone Right", "ADCR"}, 1402 {"STENR Mux", "Sidetone Right", "DMICR"}, 1403 {"DACL", "NULL", "STENL Mux"}, 1404 {"DACR", "NULL", "STENL Mux"}, 1405 1406 {"AIFINL", NULL, "SHDN"}, 1407 {"AIFINR", NULL, "SHDN"}, 1408 {"AIFINL", NULL, "SDIEN"}, 1409 {"AIFINR", NULL, "SDIEN"}, 1410 {"DACL", NULL, "SHDN"}, 1411 {"DACR", NULL, "SHDN"}, 1412 1413 /* Left headphone output mixer */ 1414 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1415 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1416 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1417 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1418 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1419 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1420 1421 /* Right headphone output mixer */ 1422 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1423 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1424 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1425 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1426 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1427 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1428 1429 /* Left speaker output mixer */ 1430 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1431 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1432 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1433 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1434 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1435 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1436 1437 /* Right speaker output mixer */ 1438 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1439 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1440 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1441 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1442 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1443 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1444 1445 /* Left Receiver output mixer */ 1446 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1447 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1448 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1449 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1450 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1451 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1452 1453 /* Right Receiver output mixer */ 1454 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1455 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1456 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1457 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1458 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1459 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1460 1461 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1462 1463 /* 1464 * Disable this for lowest power if bypassing 1465 * the DAC with an analog signal 1466 */ 1467 {"HP Left Out", NULL, "DACL"}, 1468 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1469 1470 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1471 1472 /* 1473 * Disable this for lowest power if bypassing 1474 * the DAC with an analog signal 1475 */ 1476 {"HP Right Out", NULL, "DACR"}, 1477 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1478 1479 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1480 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1481 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1482 1483 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1484 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1485 {"RCV Right Out", NULL, "LINMOD Mux"}, 1486 1487 {"HPL", NULL, "HP Left Out"}, 1488 {"HPR", NULL, "HP Right Out"}, 1489 {"SPKL", NULL, "SPK Left Out"}, 1490 {"SPKR", NULL, "SPK Right Out"}, 1491 {"RCVL", NULL, "RCV Left Out"}, 1492 {"RCVR", NULL, "RCV Right Out"}, 1493 1494 }; 1495 1496 static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1497 1498 /* DMIC inputs */ 1499 {"DMIC3", NULL, "DMIC3_ENA"}, 1500 {"DMIC4", NULL, "DMIC4_ENA"}, 1501 {"DMIC3", NULL, "AHPF"}, 1502 {"DMIC4", NULL, "AHPF"}, 1503 1504 }; 1505 1506 static int max98090_add_widgets(struct snd_soc_codec *codec) 1507 { 1508 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1509 struct snd_soc_dapm_context *dapm = &codec->dapm; 1510 1511 snd_soc_add_codec_controls(codec, max98090_snd_controls, 1512 ARRAY_SIZE(max98090_snd_controls)); 1513 1514 if (max98090->devtype == MAX98091) { 1515 snd_soc_add_codec_controls(codec, max98091_snd_controls, 1516 ARRAY_SIZE(max98091_snd_controls)); 1517 } 1518 1519 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1520 ARRAY_SIZE(max98090_dapm_widgets)); 1521 1522 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1523 ARRAY_SIZE(max98090_dapm_routes)); 1524 1525 if (max98090->devtype == MAX98091) { 1526 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1527 ARRAY_SIZE(max98091_dapm_widgets)); 1528 1529 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1530 ARRAY_SIZE(max98091_dapm_routes)); 1531 1532 } 1533 1534 return 0; 1535 } 1536 1537 static const int pclk_rates[] = { 1538 12000000, 12000000, 13000000, 13000000, 1539 16000000, 16000000, 19200000, 19200000 1540 }; 1541 1542 static const int lrclk_rates[] = { 1543 8000, 16000, 8000, 16000, 1544 8000, 16000, 8000, 16000 1545 }; 1546 1547 static const int user_pclk_rates[] = { 1548 13000000, 13000000, 19200000, 19200000, 1549 }; 1550 1551 static const int user_lrclk_rates[] = { 1552 44100, 48000, 44100, 48000, 1553 }; 1554 1555 static const unsigned long long ni_value[] = { 1556 3528, 768, 441, 8 1557 }; 1558 1559 static const unsigned long long mi_value[] = { 1560 8125, 1625, 1500, 25 1561 }; 1562 1563 static void max98090_configure_bclk(struct snd_soc_codec *codec) 1564 { 1565 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1566 unsigned long long ni; 1567 int i; 1568 1569 if (!max98090->sysclk) { 1570 dev_err(codec->dev, "No SYSCLK configured\n"); 1571 return; 1572 } 1573 1574 if (!max98090->bclk || !max98090->lrclk) { 1575 dev_err(codec->dev, "No audio clocks configured\n"); 1576 return; 1577 } 1578 1579 /* Skip configuration when operating as slave */ 1580 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) & 1581 M98090_MAS_MASK)) { 1582 return; 1583 } 1584 1585 /* Check for supported PCLK to LRCLK ratios */ 1586 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1587 if ((pclk_rates[i] == max98090->sysclk) && 1588 (lrclk_rates[i] == max98090->lrclk)) { 1589 dev_dbg(codec->dev, 1590 "Found supported PCLK to LRCLK rates 0x%x\n", 1591 i + 0x8); 1592 1593 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1594 M98090_FREQ_MASK, 1595 (i + 0x8) << M98090_FREQ_SHIFT); 1596 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1597 M98090_USE_M1_MASK, 0); 1598 return; 1599 } 1600 } 1601 1602 /* Check for user calculated MI and NI ratios */ 1603 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1604 if ((user_pclk_rates[i] == max98090->sysclk) && 1605 (user_lrclk_rates[i] == max98090->lrclk)) { 1606 dev_dbg(codec->dev, 1607 "Found user supported PCLK to LRCLK rates\n"); 1608 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n", 1609 i, ni_value[i], mi_value[i]); 1610 1611 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1612 M98090_FREQ_MASK, 0); 1613 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1614 M98090_USE_M1_MASK, 1615 1 << M98090_USE_M1_SHIFT); 1616 1617 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1618 (ni_value[i] >> 8) & 0x7F); 1619 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, 1620 ni_value[i] & 0xFF); 1621 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB, 1622 (mi_value[i] >> 8) & 0x7F); 1623 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB, 1624 mi_value[i] & 0xFF); 1625 1626 return; 1627 } 1628 } 1629 1630 /* 1631 * Calculate based on MI = 65536 (not as good as either method above) 1632 */ 1633 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1634 M98090_FREQ_MASK, 0); 1635 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1636 M98090_USE_M1_MASK, 0); 1637 1638 /* 1639 * Configure NI when operating as master 1640 * Note: There is a small, but significant audio quality improvement 1641 * by calculating ni and mi. 1642 */ 1643 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1644 * (unsigned long long int)max98090->lrclk; 1645 do_div(ni, (unsigned long long int)max98090->sysclk); 1646 dev_info(codec->dev, "No better method found\n"); 1647 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni); 1648 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1649 (ni >> 8) & 0x7F); 1650 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1651 } 1652 1653 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1654 unsigned int fmt) 1655 { 1656 struct snd_soc_codec *codec = codec_dai->codec; 1657 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1658 struct max98090_cdata *cdata; 1659 u8 regval; 1660 1661 max98090->dai_fmt = fmt; 1662 cdata = &max98090->dai[0]; 1663 1664 if (fmt != cdata->fmt) { 1665 cdata->fmt = fmt; 1666 1667 regval = 0; 1668 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1669 case SND_SOC_DAIFMT_CBS_CFS: 1670 /* Set to slave mode PLL - MAS mode off */ 1671 snd_soc_write(codec, 1672 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1673 snd_soc_write(codec, 1674 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1675 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1676 M98090_USE_M1_MASK, 0); 1677 max98090->master = false; 1678 break; 1679 case SND_SOC_DAIFMT_CBM_CFM: 1680 /* Set to master mode */ 1681 if (max98090->tdm_slots == 4) { 1682 /* TDM */ 1683 regval |= M98090_MAS_MASK | 1684 M98090_BSEL_64; 1685 } else if (max98090->tdm_slots == 3) { 1686 /* TDM */ 1687 regval |= M98090_MAS_MASK | 1688 M98090_BSEL_48; 1689 } else { 1690 /* Few TDM slots, or No TDM */ 1691 regval |= M98090_MAS_MASK | 1692 M98090_BSEL_32; 1693 } 1694 max98090->master = true; 1695 break; 1696 case SND_SOC_DAIFMT_CBS_CFM: 1697 case SND_SOC_DAIFMT_CBM_CFS: 1698 default: 1699 dev_err(codec->dev, "DAI clock mode unsupported"); 1700 return -EINVAL; 1701 } 1702 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval); 1703 1704 regval = 0; 1705 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1706 case SND_SOC_DAIFMT_I2S: 1707 regval |= M98090_DLY_MASK; 1708 break; 1709 case SND_SOC_DAIFMT_LEFT_J: 1710 break; 1711 case SND_SOC_DAIFMT_RIGHT_J: 1712 regval |= M98090_RJ_MASK; 1713 break; 1714 case SND_SOC_DAIFMT_DSP_A: 1715 /* Not supported mode */ 1716 default: 1717 dev_err(codec->dev, "DAI format unsupported"); 1718 return -EINVAL; 1719 } 1720 1721 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1722 case SND_SOC_DAIFMT_NB_NF: 1723 break; 1724 case SND_SOC_DAIFMT_NB_IF: 1725 regval |= M98090_WCI_MASK; 1726 break; 1727 case SND_SOC_DAIFMT_IB_NF: 1728 regval |= M98090_BCI_MASK; 1729 break; 1730 case SND_SOC_DAIFMT_IB_IF: 1731 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1732 break; 1733 default: 1734 dev_err(codec->dev, "DAI invert mode unsupported"); 1735 return -EINVAL; 1736 } 1737 1738 /* 1739 * This accommodates an inverted logic in the MAX98090 chip 1740 * for Bit Clock Invert (BCI). The inverted logic is only 1741 * seen for the case of TDM mode. The remaining cases have 1742 * normal logic. 1743 */ 1744 if (max98090->tdm_slots > 1) 1745 regval ^= M98090_BCI_MASK; 1746 1747 snd_soc_write(codec, 1748 M98090_REG_INTERFACE_FORMAT, regval); 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1755 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1756 { 1757 struct snd_soc_codec *codec = codec_dai->codec; 1758 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1759 struct max98090_cdata *cdata; 1760 cdata = &max98090->dai[0]; 1761 1762 if (slots < 0 || slots > 4) 1763 return -EINVAL; 1764 1765 max98090->tdm_slots = slots; 1766 max98090->tdm_width = slot_width; 1767 1768 if (max98090->tdm_slots > 1) { 1769 /* SLOTL SLOTR SLOTDLY */ 1770 snd_soc_write(codec, M98090_REG_TDM_FORMAT, 1771 0 << M98090_TDM_SLOTL_SHIFT | 1772 1 << M98090_TDM_SLOTR_SHIFT | 1773 0 << M98090_TDM_SLOTDLY_SHIFT); 1774 1775 /* FSW TDM */ 1776 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL, 1777 M98090_TDM_MASK, 1778 M98090_TDM_MASK); 1779 } 1780 1781 /* 1782 * Normally advisable to set TDM first, but this permits either order 1783 */ 1784 cdata->fmt = 0; 1785 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); 1786 1787 return 0; 1788 } 1789 1790 static int max98090_set_bias_level(struct snd_soc_codec *codec, 1791 enum snd_soc_bias_level level) 1792 { 1793 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1794 int ret; 1795 1796 switch (level) { 1797 case SND_SOC_BIAS_ON: 1798 break; 1799 1800 case SND_SOC_BIAS_PREPARE: 1801 break; 1802 1803 case SND_SOC_BIAS_STANDBY: 1804 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1805 ret = regcache_sync(max98090->regmap); 1806 if (ret != 0) { 1807 dev_err(codec->dev, 1808 "Failed to sync cache: %d\n", ret); 1809 return ret; 1810 } 1811 } 1812 break; 1813 1814 case SND_SOC_BIAS_OFF: 1815 /* Set internal pull-up to lowest power mode */ 1816 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1817 M98090_JDWK_MASK, M98090_JDWK_MASK); 1818 regcache_mark_dirty(max98090->regmap); 1819 break; 1820 } 1821 codec->dapm.bias_level = level; 1822 return 0; 1823 } 1824 1825 static const int comp_pclk_rates[] = { 1826 11289600, 12288000, 12000000, 13000000, 19200000 1827 }; 1828 1829 static const int dmic_micclk[] = { 1830 2, 2, 2, 2, 4, 2 1831 }; 1832 1833 static const int comp_lrclk_rates[] = { 1834 8000, 16000, 32000, 44100, 48000, 96000 1835 }; 1836 1837 static const int dmic_comp[6][6] = { 1838 {7, 8, 3, 3, 3, 3}, 1839 {7, 8, 3, 3, 3, 3}, 1840 {7, 8, 3, 3, 3, 3}, 1841 {7, 8, 3, 1, 1, 1}, 1842 {7, 8, 3, 1, 2, 2}, 1843 {7, 8, 3, 3, 3, 3} 1844 }; 1845 1846 static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1847 struct snd_pcm_hw_params *params, 1848 struct snd_soc_dai *dai) 1849 { 1850 struct snd_soc_codec *codec = dai->codec; 1851 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1852 struct max98090_cdata *cdata; 1853 int i, j; 1854 1855 cdata = &max98090->dai[0]; 1856 max98090->bclk = snd_soc_params_to_bclk(params); 1857 if (params_channels(params) == 1) 1858 max98090->bclk *= 2; 1859 1860 max98090->lrclk = params_rate(params); 1861 1862 switch (params_width(params)) { 1863 case 16: 1864 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT, 1865 M98090_WS_MASK, 0); 1866 break; 1867 default: 1868 return -EINVAL; 1869 } 1870 1871 if (max98090->master) 1872 max98090_configure_bclk(codec); 1873 1874 cdata->rate = max98090->lrclk; 1875 1876 /* Update filter mode */ 1877 if (max98090->lrclk < 24000) 1878 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1879 M98090_MODE_MASK, 0); 1880 else 1881 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1882 M98090_MODE_MASK, M98090_MODE_MASK); 1883 1884 /* Update sample rate mode */ 1885 if (max98090->lrclk < 50000) 1886 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1887 M98090_DHF_MASK, 0); 1888 else 1889 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1890 M98090_DHF_MASK, M98090_DHF_MASK); 1891 1892 /* Check for supported PCLK to LRCLK ratios */ 1893 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) { 1894 if (comp_pclk_rates[j] == max98090->sysclk) { 1895 break; 1896 } 1897 } 1898 1899 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 1900 if (max98090->lrclk <= (comp_lrclk_rates[i] + 1901 comp_lrclk_rates[i + 1]) / 2) { 1902 break; 1903 } 1904 } 1905 1906 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE, 1907 M98090_MICCLK_MASK, 1908 dmic_micclk[j] << M98090_MICCLK_SHIFT); 1909 1910 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG, 1911 M98090_DMIC_COMP_MASK, 1912 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT); 1913 1914 return 0; 1915 } 1916 1917 /* 1918 * PLL / Sysclk 1919 */ 1920 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1921 int clk_id, unsigned int freq, int dir) 1922 { 1923 struct snd_soc_codec *codec = dai->codec; 1924 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1925 1926 /* Requested clock frequency is already setup */ 1927 if (freq == max98090->sysclk) 1928 return 0; 1929 1930 /* Setup clocks for slave mode, and using the PLL 1931 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1932 * 0x02 (when master clk is 20MHz to 40MHz).. 1933 * 0x03 (when master clk is 40MHz to 60MHz).. 1934 */ 1935 if ((freq >= 10000000) && (freq < 20000000)) { 1936 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1937 M98090_PSCLK_DIV1); 1938 } else if ((freq >= 20000000) && (freq < 40000000)) { 1939 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1940 M98090_PSCLK_DIV2); 1941 } else if ((freq >= 40000000) && (freq < 60000000)) { 1942 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1943 M98090_PSCLK_DIV4); 1944 } else { 1945 dev_err(codec->dev, "Invalid master clock frequency\n"); 1946 return -EINVAL; 1947 } 1948 1949 max98090->sysclk = freq; 1950 1951 return 0; 1952 } 1953 1954 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1955 { 1956 struct snd_soc_codec *codec = codec_dai->codec; 1957 int regval; 1958 1959 regval = mute ? M98090_DVM_MASK : 0; 1960 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL, 1961 M98090_DVM_MASK, regval); 1962 1963 return 0; 1964 } 1965 1966 static void max98090_jack_work(struct work_struct *work) 1967 { 1968 struct max98090_priv *max98090 = container_of(work, 1969 struct max98090_priv, 1970 jack_work.work); 1971 struct snd_soc_codec *codec = max98090->codec; 1972 struct snd_soc_dapm_context *dapm = &codec->dapm; 1973 int status = 0; 1974 int reg; 1975 1976 /* Read a second time */ 1977 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 1978 1979 /* Strong pull up allows mic detection */ 1980 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1981 M98090_JDWK_MASK, 0); 1982 1983 msleep(50); 1984 1985 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1986 1987 /* Weak pull up allows only insertion detection */ 1988 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1989 M98090_JDWK_MASK, M98090_JDWK_MASK); 1990 } else { 1991 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1992 } 1993 1994 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1995 1996 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 1997 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 1998 dev_dbg(codec->dev, "No Headset Detected\n"); 1999 2000 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2001 2002 status |= 0; 2003 2004 break; 2005 2006 case 0: 2007 if (max98090->jack_state == 2008 M98090_JACK_STATE_HEADSET) { 2009 2010 dev_dbg(codec->dev, 2011 "Headset Button Down Detected\n"); 2012 2013 /* 2014 * max98090_headset_button_event(codec) 2015 * could be defined, then called here. 2016 */ 2017 2018 status |= SND_JACK_HEADSET; 2019 status |= SND_JACK_BTN_0; 2020 2021 break; 2022 } 2023 2024 /* Line is reported as Headphone */ 2025 /* Nokia Headset is reported as Headphone */ 2026 /* Mono Headphone is reported as Headphone */ 2027 dev_dbg(codec->dev, "Headphone Detected\n"); 2028 2029 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2030 2031 status |= SND_JACK_HEADPHONE; 2032 2033 break; 2034 2035 case M98090_JKSNS_MASK: 2036 dev_dbg(codec->dev, "Headset Detected\n"); 2037 2038 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2039 2040 status |= SND_JACK_HEADSET; 2041 2042 break; 2043 2044 default: 2045 dev_dbg(codec->dev, "Unrecognized Jack Status\n"); 2046 break; 2047 } 2048 2049 snd_soc_jack_report(max98090->jack, status, 2050 SND_JACK_HEADSET | SND_JACK_BTN_0); 2051 2052 snd_soc_dapm_sync(dapm); 2053 } 2054 2055 static irqreturn_t max98090_interrupt(int irq, void *data) 2056 { 2057 struct snd_soc_codec *codec = data; 2058 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2059 int ret; 2060 unsigned int mask; 2061 unsigned int active; 2062 2063 dev_dbg(codec->dev, "***** max98090_interrupt *****\n"); 2064 2065 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2066 2067 if (ret != 0) { 2068 dev_err(codec->dev, 2069 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2070 ret); 2071 return IRQ_NONE; 2072 } 2073 2074 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2075 2076 if (ret != 0) { 2077 dev_err(codec->dev, 2078 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2079 ret); 2080 return IRQ_NONE; 2081 } 2082 2083 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2084 active, mask, active & mask); 2085 2086 active &= mask; 2087 2088 if (!active) 2089 return IRQ_NONE; 2090 2091 if (active & M98090_CLD_MASK) 2092 dev_err(codec->dev, "M98090_CLD_MASK\n"); 2093 2094 if (active & M98090_SLD_MASK) 2095 dev_dbg(codec->dev, "M98090_SLD_MASK\n"); 2096 2097 if (active & M98090_ULK_MASK) 2098 dev_err(codec->dev, "M98090_ULK_MASK\n"); 2099 2100 if (active & M98090_JDET_MASK) { 2101 dev_dbg(codec->dev, "M98090_JDET_MASK\n"); 2102 2103 pm_wakeup_event(codec->dev, 100); 2104 2105 queue_delayed_work(system_power_efficient_wq, 2106 &max98090->jack_work, 2107 msecs_to_jiffies(100)); 2108 } 2109 2110 if (active & M98090_DRCACT_MASK) 2111 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n"); 2112 2113 if (active & M98090_DRCCLP_MASK) 2114 dev_err(codec->dev, "M98090_DRCCLP_MASK\n"); 2115 2116 return IRQ_HANDLED; 2117 } 2118 2119 /** 2120 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2121 * 2122 * @codec: MAX98090 codec 2123 * @jack: jack to report detection events on 2124 * 2125 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2126 * being used to bring out signals to the processor then only platform 2127 * data configuration is needed for MAX98090 and processor GPIOs should 2128 * be configured using snd_soc_jack_add_gpios() instead. 2129 * 2130 * If no jack is supplied detection will be disabled. 2131 */ 2132 int max98090_mic_detect(struct snd_soc_codec *codec, 2133 struct snd_soc_jack *jack) 2134 { 2135 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2136 2137 dev_dbg(codec->dev, "max98090_mic_detect\n"); 2138 2139 max98090->jack = jack; 2140 if (jack) { 2141 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2142 M98090_IJDET_MASK, 2143 1 << M98090_IJDET_SHIFT); 2144 } else { 2145 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2146 M98090_IJDET_MASK, 2147 0); 2148 } 2149 2150 /* Send an initial empty report */ 2151 snd_soc_jack_report(max98090->jack, 0, 2152 SND_JACK_HEADSET | SND_JACK_BTN_0); 2153 2154 queue_delayed_work(system_power_efficient_wq, 2155 &max98090->jack_work, 2156 msecs_to_jiffies(100)); 2157 2158 return 0; 2159 } 2160 EXPORT_SYMBOL_GPL(max98090_mic_detect); 2161 2162 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2163 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2164 2165 static struct snd_soc_dai_ops max98090_dai_ops = { 2166 .set_sysclk = max98090_dai_set_sysclk, 2167 .set_fmt = max98090_dai_set_fmt, 2168 .set_tdm_slot = max98090_set_tdm_slot, 2169 .hw_params = max98090_dai_hw_params, 2170 .digital_mute = max98090_dai_digital_mute, 2171 }; 2172 2173 static struct snd_soc_dai_driver max98090_dai[] = { 2174 { 2175 .name = "HiFi", 2176 .playback = { 2177 .stream_name = "HiFi Playback", 2178 .channels_min = 2, 2179 .channels_max = 2, 2180 .rates = MAX98090_RATES, 2181 .formats = MAX98090_FORMATS, 2182 }, 2183 .capture = { 2184 .stream_name = "HiFi Capture", 2185 .channels_min = 1, 2186 .channels_max = 2, 2187 .rates = MAX98090_RATES, 2188 .formats = MAX98090_FORMATS, 2189 }, 2190 .ops = &max98090_dai_ops, 2191 } 2192 }; 2193 2194 static void max98090_handle_pdata(struct snd_soc_codec *codec) 2195 { 2196 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2197 struct max98090_pdata *pdata = max98090->pdata; 2198 2199 if (!pdata) { 2200 dev_err(codec->dev, "No platform data\n"); 2201 return; 2202 } 2203 2204 } 2205 2206 static int max98090_probe(struct snd_soc_codec *codec) 2207 { 2208 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2209 struct max98090_cdata *cdata; 2210 int ret = 0; 2211 2212 dev_dbg(codec->dev, "max98090_probe\n"); 2213 2214 max98090->codec = codec; 2215 2216 /* Reset the codec, the DSP core, and disable all interrupts */ 2217 max98090_reset(max98090); 2218 2219 /* Initialize private data */ 2220 2221 max98090->sysclk = (unsigned)-1; 2222 max98090->master = false; 2223 2224 cdata = &max98090->dai[0]; 2225 cdata->rate = (unsigned)-1; 2226 cdata->fmt = (unsigned)-1; 2227 2228 max98090->lin_state = 0; 2229 max98090->pa1en = 0; 2230 max98090->pa2en = 0; 2231 max98090->extmic_mux = 0; 2232 2233 ret = snd_soc_read(codec, M98090_REG_REVISION_ID); 2234 if (ret < 0) { 2235 dev_err(codec->dev, "Failed to read device revision: %d\n", 2236 ret); 2237 goto err_access; 2238 } 2239 2240 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2241 max98090->devtype = MAX98090; 2242 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret); 2243 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2244 max98090->devtype = MAX98091; 2245 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret); 2246 } else { 2247 max98090->devtype = MAX98090; 2248 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret); 2249 } 2250 2251 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2252 2253 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2254 2255 /* Enable jack detection */ 2256 snd_soc_write(codec, M98090_REG_JACK_DETECT, 2257 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2258 2259 /* Register for interrupts */ 2260 dev_dbg(codec->dev, "irq = %d\n", max98090->irq); 2261 2262 ret = request_threaded_irq(max98090->irq, NULL, 2263 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2264 "max98090_interrupt", codec); 2265 if (ret < 0) { 2266 dev_err(codec->dev, "request_irq failed: %d\n", 2267 ret); 2268 } 2269 2270 /* 2271 * Clear any old interrupts. 2272 * An old interrupt ocurring prior to installing the ISR 2273 * can keep a new interrupt from generating a trigger. 2274 */ 2275 snd_soc_read(codec, M98090_REG_DEVICE_STATUS); 2276 2277 /* High Performance is default */ 2278 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2279 M98090_DACHP_MASK, 2280 1 << M98090_DACHP_SHIFT); 2281 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2282 M98090_PERFMODE_MASK, 2283 0 << M98090_PERFMODE_SHIFT); 2284 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL, 2285 M98090_ADCHP_MASK, 2286 1 << M98090_ADCHP_SHIFT); 2287 2288 /* Turn on VCM bandgap reference */ 2289 snd_soc_write(codec, M98090_REG_BIAS_CONTROL, 2290 M98090_VCM_MODE_MASK); 2291 2292 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE, 2293 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8); 2294 2295 max98090_handle_pdata(codec); 2296 2297 max98090_add_widgets(codec); 2298 2299 err_access: 2300 return ret; 2301 } 2302 2303 static int max98090_remove(struct snd_soc_codec *codec) 2304 { 2305 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2306 2307 cancel_delayed_work_sync(&max98090->jack_work); 2308 2309 return 0; 2310 } 2311 2312 static struct snd_soc_codec_driver soc_codec_dev_max98090 = { 2313 .probe = max98090_probe, 2314 .remove = max98090_remove, 2315 .set_bias_level = max98090_set_bias_level, 2316 }; 2317 2318 static const struct regmap_config max98090_regmap = { 2319 .reg_bits = 8, 2320 .val_bits = 8, 2321 2322 .max_register = MAX98090_MAX_REGISTER, 2323 .reg_defaults = max98090_reg, 2324 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2325 .volatile_reg = max98090_volatile_register, 2326 .readable_reg = max98090_readable_register, 2327 .cache_type = REGCACHE_RBTREE, 2328 }; 2329 2330 static int max98090_i2c_probe(struct i2c_client *i2c, 2331 const struct i2c_device_id *i2c_id) 2332 { 2333 struct max98090_priv *max98090; 2334 const struct acpi_device_id *acpi_id; 2335 kernel_ulong_t driver_data = 0; 2336 int ret; 2337 2338 pr_debug("max98090_i2c_probe\n"); 2339 2340 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2341 GFP_KERNEL); 2342 if (max98090 == NULL) 2343 return -ENOMEM; 2344 2345 if (ACPI_HANDLE(&i2c->dev)) { 2346 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, 2347 &i2c->dev); 2348 if (!acpi_id) { 2349 dev_err(&i2c->dev, "No driver data\n"); 2350 return -EINVAL; 2351 } 2352 driver_data = acpi_id->driver_data; 2353 } else if (i2c_id) { 2354 driver_data = i2c_id->driver_data; 2355 } 2356 2357 max98090->devtype = driver_data; 2358 i2c_set_clientdata(i2c, max98090); 2359 max98090->pdata = i2c->dev.platform_data; 2360 max98090->irq = i2c->irq; 2361 2362 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2363 if (IS_ERR(max98090->regmap)) { 2364 ret = PTR_ERR(max98090->regmap); 2365 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2366 goto err_enable; 2367 } 2368 2369 ret = snd_soc_register_codec(&i2c->dev, 2370 &soc_codec_dev_max98090, max98090_dai, 2371 ARRAY_SIZE(max98090_dai)); 2372 err_enable: 2373 return ret; 2374 } 2375 2376 static int max98090_i2c_remove(struct i2c_client *client) 2377 { 2378 snd_soc_unregister_codec(&client->dev); 2379 return 0; 2380 } 2381 2382 #ifdef CONFIG_PM_RUNTIME 2383 static int max98090_runtime_resume(struct device *dev) 2384 { 2385 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2386 2387 regcache_cache_only(max98090->regmap, false); 2388 2389 regcache_sync(max98090->regmap); 2390 2391 return 0; 2392 } 2393 2394 static int max98090_runtime_suspend(struct device *dev) 2395 { 2396 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2397 2398 regcache_cache_only(max98090->regmap, true); 2399 2400 return 0; 2401 } 2402 #endif 2403 2404 static const struct dev_pm_ops max98090_pm = { 2405 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2406 max98090_runtime_resume, NULL) 2407 }; 2408 2409 static const struct i2c_device_id max98090_i2c_id[] = { 2410 { "max98090", MAX98090 }, 2411 { } 2412 }; 2413 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2414 2415 static const struct of_device_id max98090_of_match[] = { 2416 { .compatible = "maxim,max98090", }, 2417 { } 2418 }; 2419 MODULE_DEVICE_TABLE(of, max98090_of_match); 2420 2421 #ifdef CONFIG_ACPI 2422 static struct acpi_device_id max98090_acpi_match[] = { 2423 { "193C9890", MAX98090 }, 2424 { } 2425 }; 2426 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); 2427 #endif 2428 2429 static struct i2c_driver max98090_i2c_driver = { 2430 .driver = { 2431 .name = "max98090", 2432 .owner = THIS_MODULE, 2433 .pm = &max98090_pm, 2434 .of_match_table = of_match_ptr(max98090_of_match), 2435 .acpi_match_table = ACPI_PTR(max98090_acpi_match), 2436 }, 2437 .probe = max98090_i2c_probe, 2438 .remove = max98090_i2c_remove, 2439 .id_table = max98090_i2c_id, 2440 }; 2441 2442 module_i2c_driver(max98090_i2c_driver); 2443 2444 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2445 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2446 MODULE_LICENSE("GPL"); 2447