1 /* 2 * max98090.c -- MAX98090 ALSA SoC Audio driver 3 * 4 * Copyright 2011-2012 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <sound/jack.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/tlv.h> 25 #include <sound/max98090.h> 26 #include "max98090.h" 27 28 #define DEBUG 29 #define EXTMIC_METHOD 30 #define EXTMIC_METHOD_TEST 31 32 /* Allows for sparsely populated register maps */ 33 static struct reg_default max98090_reg[] = { 34 { 0x00, 0x00 }, /* 00 Software Reset */ 35 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 36 { 0x04, 0x00 }, /* 04 System Clock Quick */ 37 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 38 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 39 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 40 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 41 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 42 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 43 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 44 { 0x0C, 0x00 }, /* 0C Reserved */ 45 { 0x0D, 0x00 }, /* 0D Input Config */ 46 { 0x0E, 0x1B }, /* 0E Line Input Level */ 47 { 0x0F, 0x00 }, /* 0F Line Config */ 48 49 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 50 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 51 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 52 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 53 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 54 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 55 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 56 { 0x17, 0x03 }, /* 17 Left ADC Level */ 57 { 0x18, 0x03 }, /* 18 Right ADC Level */ 58 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 59 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 60 { 0x1B, 0x00 }, /* 1B System Clock */ 61 { 0x1C, 0x00 }, /* 1C Clock Mode */ 62 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 63 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 64 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 65 66 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 67 { 0x21, 0x00 }, /* 21 Master Mode */ 68 { 0x22, 0x00 }, /* 22 Interface Format */ 69 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 70 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 71 { 0x25, 0x00 }, /* 25 I/O Configuration */ 72 { 0x26, 0x80 }, /* 26 Filter Config */ 73 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 74 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 75 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 76 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 77 { 0x2B, 0x00 }, /* 2B HP Control */ 78 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 79 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 80 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 81 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 82 83 { 0x30, 0x00 }, /* 30 Spk Control */ 84 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 85 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 86 { 0x33, 0x00 }, /* 33 ALC Timing */ 87 { 0x34, 0x00 }, /* 34 ALC Compressor */ 88 { 0x35, 0x00 }, /* 35 ALC Expander */ 89 { 0x36, 0x00 }, /* 36 ALC Gain */ 90 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 91 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 92 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 93 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 94 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 95 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 96 { 0x3D, 0x00 }, /* 3D Jack Detect */ 97 { 0x3E, 0x00 }, /* 3E Input Enable */ 98 { 0x3F, 0x00 }, /* 3F Output Enable */ 99 100 { 0x40, 0x00 }, /* 40 Level Control */ 101 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 102 { 0x42, 0x00 }, /* 42 Bias Control */ 103 { 0x43, 0x00 }, /* 43 DAC Control */ 104 { 0x44, 0x06 }, /* 44 ADC Control */ 105 { 0x45, 0x00 }, /* 45 Device Shutdown */ 106 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 107 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 108 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 109 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 110 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 111 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 112 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 113 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 114 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 115 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 116 117 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 118 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 119 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 120 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 121 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 122 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 123 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 124 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 125 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 126 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 127 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 128 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 129 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 130 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 131 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 132 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 133 134 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 135 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 136 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 137 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 138 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 139 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 140 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 141 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 142 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 143 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 144 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 145 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 146 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 147 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 148 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 149 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 150 151 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 152 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 153 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 154 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 155 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 156 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 157 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 158 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 159 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 160 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 161 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 162 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 163 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 164 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 165 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 166 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 167 168 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 169 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 170 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 171 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 172 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 173 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 174 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 175 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 176 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 177 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 178 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 179 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 180 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 181 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 182 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 183 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 184 185 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 186 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 187 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 188 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 189 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 190 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 191 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 192 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 193 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 194 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 195 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 196 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 197 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 198 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 199 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 200 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 201 202 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 203 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 204 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 205 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 206 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 207 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 208 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 209 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 210 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 211 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 212 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 213 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 214 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 215 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 216 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 217 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 218 219 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 220 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 221 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 222 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 223 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 224 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 225 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 226 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 227 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 228 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 229 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 230 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 231 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 232 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 233 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 234 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 235 236 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 237 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 238 { 0xC2, 0x00 }, /* C2 Sample Rate */ 239 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 240 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 241 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 242 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 243 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 244 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 245 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 246 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 247 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 248 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 249 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 250 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 251 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 252 253 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 254 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 255 }; 256 257 static bool max98090_volatile_register(struct device *dev, unsigned int reg) 258 { 259 switch (reg) { 260 case M98090_REG_SOFTWARE_RESET: 261 case M98090_REG_DEVICE_STATUS: 262 case M98090_REG_JACK_STATUS: 263 case M98090_REG_REVISION_ID: 264 return true; 265 default: 266 return false; 267 } 268 } 269 270 static bool max98090_readable_register(struct device *dev, unsigned int reg) 271 { 272 switch (reg) { 273 case M98090_REG_DEVICE_STATUS: 274 case M98090_REG_JACK_STATUS: 275 case M98090_REG_INTERRUPT_S: 276 case M98090_REG_RESERVED: 277 case M98090_REG_LINE_INPUT_CONFIG: 278 case M98090_REG_LINE_INPUT_LEVEL: 279 case M98090_REG_INPUT_MODE: 280 case M98090_REG_MIC1_INPUT_LEVEL: 281 case M98090_REG_MIC2_INPUT_LEVEL: 282 case M98090_REG_MIC_BIAS_VOLTAGE: 283 case M98090_REG_DIGITAL_MIC_ENABLE: 284 case M98090_REG_DIGITAL_MIC_CONFIG: 285 case M98090_REG_LEFT_ADC_MIXER: 286 case M98090_REG_RIGHT_ADC_MIXER: 287 case M98090_REG_LEFT_ADC_LEVEL: 288 case M98090_REG_RIGHT_ADC_LEVEL: 289 case M98090_REG_ADC_BIQUAD_LEVEL: 290 case M98090_REG_ADC_SIDETONE: 291 case M98090_REG_SYSTEM_CLOCK: 292 case M98090_REG_CLOCK_MODE: 293 case M98090_REG_CLOCK_RATIO_NI_MSB: 294 case M98090_REG_CLOCK_RATIO_NI_LSB: 295 case M98090_REG_CLOCK_RATIO_MI_MSB: 296 case M98090_REG_CLOCK_RATIO_MI_LSB: 297 case M98090_REG_MASTER_MODE: 298 case M98090_REG_INTERFACE_FORMAT: 299 case M98090_REG_TDM_CONTROL: 300 case M98090_REG_TDM_FORMAT: 301 case M98090_REG_IO_CONFIGURATION: 302 case M98090_REG_FILTER_CONFIG: 303 case M98090_REG_DAI_PLAYBACK_LEVEL: 304 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: 305 case M98090_REG_LEFT_HP_MIXER: 306 case M98090_REG_RIGHT_HP_MIXER: 307 case M98090_REG_HP_CONTROL: 308 case M98090_REG_LEFT_HP_VOLUME: 309 case M98090_REG_RIGHT_HP_VOLUME: 310 case M98090_REG_LEFT_SPK_MIXER: 311 case M98090_REG_RIGHT_SPK_MIXER: 312 case M98090_REG_SPK_CONTROL: 313 case M98090_REG_LEFT_SPK_VOLUME: 314 case M98090_REG_RIGHT_SPK_VOLUME: 315 case M98090_REG_DRC_TIMING: 316 case M98090_REG_DRC_COMPRESSOR: 317 case M98090_REG_DRC_EXPANDER: 318 case M98090_REG_DRC_GAIN: 319 case M98090_REG_RCV_LOUTL_MIXER: 320 case M98090_REG_RCV_LOUTL_CONTROL: 321 case M98090_REG_RCV_LOUTL_VOLUME: 322 case M98090_REG_LOUTR_MIXER: 323 case M98090_REG_LOUTR_CONTROL: 324 case M98090_REG_LOUTR_VOLUME: 325 case M98090_REG_JACK_DETECT: 326 case M98090_REG_INPUT_ENABLE: 327 case M98090_REG_OUTPUT_ENABLE: 328 case M98090_REG_LEVEL_CONTROL: 329 case M98090_REG_DSP_FILTER_ENABLE: 330 case M98090_REG_BIAS_CONTROL: 331 case M98090_REG_DAC_CONTROL: 332 case M98090_REG_ADC_CONTROL: 333 case M98090_REG_DEVICE_SHUTDOWN: 334 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: 335 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: 336 case M98090_REG_DMIC3_VOLUME: 337 case M98090_REG_DMIC4_VOLUME: 338 case M98090_REG_DMIC34_BQ_PREATTEN: 339 case M98090_REG_RECORD_TDM_SLOT: 340 case M98090_REG_SAMPLE_RATE: 341 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: 342 case M98090_REG_REVISION_ID: 343 return true; 344 default: 345 return false; 346 } 347 } 348 349 static int max98090_reset(struct max98090_priv *max98090) 350 { 351 int ret; 352 353 /* Reset the codec by writing to this write-only reset register */ 354 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 355 M98090_SWRESET_MASK); 356 if (ret < 0) { 357 dev_err(max98090->codec->dev, 358 "Failed to reset codec: %d\n", ret); 359 return ret; 360 } 361 362 msleep(20); 363 return ret; 364 } 365 366 static const unsigned int max98090_micboost_tlv[] = { 367 TLV_DB_RANGE_HEAD(2), 368 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 369 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 370 }; 371 372 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 373 374 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 375 -600, 600, 0); 376 377 static const unsigned int max98090_line_tlv[] = { 378 TLV_DB_RANGE_HEAD(2), 379 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 380 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), 381 }; 382 383 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 384 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 385 386 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 387 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 388 389 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0); 390 391 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0); 392 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 393 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 394 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 395 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0); 396 397 static const unsigned int max98090_mixout_tlv[] = { 398 TLV_DB_RANGE_HEAD(2), 399 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 400 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), 401 }; 402 403 static const unsigned int max98090_hp_tlv[] = { 404 TLV_DB_RANGE_HEAD(5), 405 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 406 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 407 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 408 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 409 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 410 }; 411 412 static const unsigned int max98090_spk_tlv[] = { 413 TLV_DB_RANGE_HEAD(5), 414 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 415 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 416 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 417 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 418 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0), 419 }; 420 421 static const unsigned int max98090_rcv_lout_tlv[] = { 422 TLV_DB_RANGE_HEAD(5), 423 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 424 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 425 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 426 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 427 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 428 }; 429 430 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 431 struct snd_ctl_elem_value *ucontrol) 432 { 433 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 434 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 435 struct soc_mixer_control *mc = 436 (struct soc_mixer_control *)kcontrol->private_value; 437 unsigned int mask = (1 << fls(mc->max)) - 1; 438 unsigned int val = snd_soc_read(codec, mc->reg); 439 unsigned int *select; 440 441 switch (mc->reg) { 442 case M98090_REG_MIC1_INPUT_LEVEL: 443 select = &(max98090->pa1en); 444 break; 445 case M98090_REG_MIC2_INPUT_LEVEL: 446 select = &(max98090->pa2en); 447 break; 448 case M98090_REG_ADC_SIDETONE: 449 select = &(max98090->sidetone); 450 break; 451 default: 452 return -EINVAL; 453 } 454 455 val = (val >> mc->shift) & mask; 456 457 if (val >= 1) { 458 /* If on, return the volume */ 459 val = val - 1; 460 *select = val; 461 } else { 462 /* If off, return last stored value */ 463 val = *select; 464 } 465 466 ucontrol->value.integer.value[0] = val; 467 return 0; 468 } 469 470 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 471 struct snd_ctl_elem_value *ucontrol) 472 { 473 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 474 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 475 struct soc_mixer_control *mc = 476 (struct soc_mixer_control *)kcontrol->private_value; 477 unsigned int mask = (1 << fls(mc->max)) - 1; 478 unsigned int sel = ucontrol->value.integer.value[0]; 479 unsigned int val = snd_soc_read(codec, mc->reg); 480 unsigned int *select; 481 482 switch (mc->reg) { 483 case M98090_REG_MIC1_INPUT_LEVEL: 484 select = &(max98090->pa1en); 485 break; 486 case M98090_REG_MIC2_INPUT_LEVEL: 487 select = &(max98090->pa2en); 488 break; 489 case M98090_REG_ADC_SIDETONE: 490 select = &(max98090->sidetone); 491 break; 492 default: 493 return -EINVAL; 494 } 495 496 val = (val >> mc->shift) & mask; 497 498 *select = sel; 499 500 /* Setting a volume is only valid if it is already On */ 501 if (val >= 1) { 502 sel = sel + 1; 503 } else { 504 /* Write what was already there */ 505 sel = val; 506 } 507 508 snd_soc_update_bits(codec, mc->reg, 509 mask << mc->shift, 510 sel << mc->shift); 511 512 return 0; 513 } 514 515 static const char *max98090_perf_pwr_text[] = 516 { "High Performance", "Low Power" }; 517 static const char *max98090_pwr_perf_text[] = 518 { "Low Power", "High Performance" }; 519 520 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, 521 M98090_REG_BIAS_CONTROL, 522 M98090_VCM_MODE_SHIFT, 523 max98090_pwr_perf_text); 524 525 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 526 527 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, 528 M98090_REG_ADC_CONTROL, 529 M98090_OSR128_SHIFT, 530 max98090_osr128_text); 531 532 static const char *max98090_mode_text[] = { "Voice", "Music" }; 533 534 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, 535 M98090_REG_FILTER_CONFIG, 536 M98090_MODE_SHIFT, 537 max98090_mode_text); 538 539 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, 540 M98090_REG_FILTER_CONFIG, 541 M98090_FLT_DMIC34MODE_SHIFT, 542 max98090_mode_text); 543 544 static const char *max98090_drcatk_text[] = 545 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 546 547 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, 548 M98090_REG_DRC_TIMING, 549 M98090_DRCATK_SHIFT, 550 max98090_drcatk_text); 551 552 static const char *max98090_drcrls_text[] = 553 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 554 555 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, 556 M98090_REG_DRC_TIMING, 557 M98090_DRCRLS_SHIFT, 558 max98090_drcrls_text); 559 560 static const char *max98090_alccmp_text[] = 561 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 562 563 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, 564 M98090_REG_DRC_COMPRESSOR, 565 M98090_DRCCMP_SHIFT, 566 max98090_alccmp_text); 567 568 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 569 570 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, 571 M98090_REG_DRC_EXPANDER, 572 M98090_DRCEXP_SHIFT, 573 max98090_drcexp_text); 574 575 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, 576 M98090_REG_DAC_CONTROL, 577 M98090_PERFMODE_SHIFT, 578 max98090_perf_pwr_text); 579 580 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, 581 M98090_REG_DAC_CONTROL, 582 M98090_DACHP_SHIFT, 583 max98090_pwr_perf_text); 584 585 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, 586 M98090_REG_ADC_CONTROL, 587 M98090_ADCHP_SHIFT, 588 max98090_pwr_perf_text); 589 590 static const struct snd_kcontrol_new max98090_snd_controls[] = { 591 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 592 593 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 594 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 595 596 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 597 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 598 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 599 max98090_put_enab_tlv, max98090_micboost_tlv), 600 601 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 602 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 603 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 604 max98090_put_enab_tlv, max98090_micboost_tlv), 605 606 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 607 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 608 max98090_mic_tlv), 609 610 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 611 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 612 max98090_mic_tlv), 613 614 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 615 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 616 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 617 618 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 619 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 620 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 621 622 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 623 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 624 max98090_line_tlv), 625 626 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 627 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 628 max98090_line_tlv), 629 630 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 631 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 632 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 633 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 634 635 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 636 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 637 max98090_avg_tlv), 638 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 639 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 640 max98090_avg_tlv), 641 642 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 643 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 644 max98090_av_tlv), 645 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 646 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 647 max98090_av_tlv), 648 649 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 650 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 651 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 652 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 653 654 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 655 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 656 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 657 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 658 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 659 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 660 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 661 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 662 SOC_ENUM("Filter Mode", max98090_mode_enum), 663 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 664 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 665 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 666 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 667 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 668 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 669 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 670 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 671 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 672 max98090_put_enab_tlv, max98090_sdg_tlv), 673 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 674 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 675 max98090_dvg_tlv), 676 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 677 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 678 max98090_dv_tlv), 679 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 680 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 681 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 682 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 683 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 684 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 685 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 686 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 687 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 688 1), 689 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 690 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 691 max98090_dv_tlv), 692 693 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 694 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 695 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 696 SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 697 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 698 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 699 max98090_alcmakeup_tlv), 700 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 701 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 702 SOC_SINGLE_TLV("ALC Compression Threshold Volume", 703 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 704 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 705 SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 706 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 707 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 708 709 SOC_ENUM("DAC HP Playback Performance Mode", 710 max98090_dac_perfmode_enum), 711 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 712 713 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 714 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 715 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 716 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 717 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 718 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 719 720 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 721 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 722 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 723 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 724 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 725 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 726 727 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 728 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 729 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 730 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 731 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 732 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 733 734 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 735 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 736 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 737 738 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 739 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 740 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 741 0, max98090_spk_tlv), 742 743 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 744 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 745 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 746 747 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 748 M98090_HPLM_SHIFT, 1, 1), 749 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 750 M98090_HPRM_SHIFT, 1, 1), 751 752 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 753 M98090_SPLM_SHIFT, 1, 1), 754 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 755 M98090_SPRM_SHIFT, 1, 1), 756 757 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 758 M98090_RCVLM_SHIFT, 1, 1), 759 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 760 M98090_RCVRM_SHIFT, 1, 1), 761 762 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 763 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 764 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 765 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 766 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 767 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 768 769 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 770 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 771 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 772 }; 773 774 static const struct snd_kcontrol_new max98091_snd_controls[] = { 775 776 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 777 M98090_DMIC34_ZEROPAD_SHIFT, 778 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 779 780 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 781 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 782 M98090_FLT_DMIC34HPF_SHIFT, 783 M98090_FLT_DMIC34HPF_NUM - 1, 0), 784 785 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 786 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 787 max98090_avg_tlv), 788 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 789 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 790 max98090_avg_tlv), 791 792 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 793 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 794 max98090_av_tlv), 795 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 796 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 797 max98090_av_tlv), 798 799 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 800 M98090_REG_DMIC34_BIQUAD_BASE, 15), 801 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 802 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 803 804 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 805 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 806 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 807 }; 808 809 static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 810 struct snd_kcontrol *kcontrol, int event) 811 { 812 struct snd_soc_codec *codec = w->codec; 813 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 814 815 unsigned int val = snd_soc_read(codec, w->reg); 816 817 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 818 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 819 else 820 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 821 822 823 if (val >= 1) { 824 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 825 max98090->pa1en = val - 1; /* Update for volatile */ 826 } else { 827 max98090->pa2en = val - 1; /* Update for volatile */ 828 } 829 } 830 831 switch (event) { 832 case SND_SOC_DAPM_POST_PMU: 833 /* If turning on, set to most recently selected volume */ 834 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 835 val = max98090->pa1en + 1; 836 else 837 val = max98090->pa2en + 1; 838 break; 839 case SND_SOC_DAPM_POST_PMD: 840 /* If turning off, turn off */ 841 val = 0; 842 break; 843 default: 844 return -EINVAL; 845 } 846 847 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 848 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK, 849 val << M98090_MIC_PA1EN_SHIFT); 850 else 851 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK, 852 val << M98090_MIC_PA2EN_SHIFT); 853 854 return 0; 855 } 856 857 static const char *mic1_mux_text[] = { "IN12", "IN56" }; 858 859 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, 860 M98090_REG_INPUT_MODE, 861 M98090_EXTMIC1_SHIFT, 862 mic1_mux_text); 863 864 static const struct snd_kcontrol_new max98090_mic1_mux = 865 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 866 867 static const char *mic2_mux_text[] = { "IN34", "IN56" }; 868 869 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, 870 M98090_REG_INPUT_MODE, 871 M98090_EXTMIC2_SHIFT, 872 mic2_mux_text); 873 874 static const struct snd_kcontrol_new max98090_mic2_mux = 875 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 876 877 static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 878 879 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 880 881 static const struct snd_kcontrol_new max98090_dmic_mux = 882 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum); 883 884 static const char *max98090_micpre_text[] = { "Off", "On" }; 885 886 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum, 887 M98090_REG_MIC1_INPUT_LEVEL, 888 M98090_MIC_PA1EN_SHIFT, 889 max98090_micpre_text); 890 891 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum, 892 M98090_REG_MIC2_INPUT_LEVEL, 893 M98090_MIC_PA2EN_SHIFT, 894 max98090_micpre_text); 895 896 /* LINEA mixer switch */ 897 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 898 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 899 M98090_IN1SEEN_SHIFT, 1, 0), 900 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 901 M98090_IN3SEEN_SHIFT, 1, 0), 902 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 903 M98090_IN5SEEN_SHIFT, 1, 0), 904 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 905 M98090_IN34DIFF_SHIFT, 1, 0), 906 }; 907 908 /* LINEB mixer switch */ 909 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 910 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 911 M98090_IN2SEEN_SHIFT, 1, 0), 912 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 913 M98090_IN4SEEN_SHIFT, 1, 0), 914 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 915 M98090_IN6SEEN_SHIFT, 1, 0), 916 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 917 M98090_IN56DIFF_SHIFT, 1, 0), 918 }; 919 920 /* Left ADC mixer switch */ 921 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 922 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 923 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 924 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 925 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 926 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 927 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 928 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 929 M98090_MIXADL_LINEA_SHIFT, 1, 0), 930 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 931 M98090_MIXADL_LINEB_SHIFT, 1, 0), 932 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 933 M98090_MIXADL_MIC1_SHIFT, 1, 0), 934 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 935 M98090_MIXADL_MIC2_SHIFT, 1, 0), 936 }; 937 938 /* Right ADC mixer switch */ 939 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 940 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 941 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 942 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 943 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 944 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 945 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 946 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 947 M98090_MIXADR_LINEA_SHIFT, 1, 0), 948 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 949 M98090_MIXADR_LINEB_SHIFT, 1, 0), 950 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 951 M98090_MIXADR_MIC1_SHIFT, 1, 0), 952 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 953 M98090_MIXADR_MIC2_SHIFT, 1, 0), 954 }; 955 956 static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 957 958 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, 959 M98090_REG_IO_CONFIGURATION, 960 M98090_LTEN_SHIFT, 961 lten_mux_text); 962 963 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, 964 M98090_REG_IO_CONFIGURATION, 965 M98090_LTEN_SHIFT, 966 lten_mux_text); 967 968 static const struct snd_kcontrol_new max98090_ltenl_mux = 969 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 970 971 static const struct snd_kcontrol_new max98090_ltenr_mux = 972 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 973 974 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 975 976 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, 977 M98090_REG_IO_CONFIGURATION, 978 M98090_LBEN_SHIFT, 979 lben_mux_text); 980 981 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, 982 M98090_REG_IO_CONFIGURATION, 983 M98090_LBEN_SHIFT, 984 lben_mux_text); 985 986 static const struct snd_kcontrol_new max98090_lbenl_mux = 987 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 988 989 static const struct snd_kcontrol_new max98090_lbenr_mux = 990 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 991 992 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 993 994 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 995 996 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, 997 M98090_REG_ADC_SIDETONE, 998 M98090_DSTSL_SHIFT, 999 stenl_mux_text); 1000 1001 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, 1002 M98090_REG_ADC_SIDETONE, 1003 M98090_DSTSR_SHIFT, 1004 stenr_mux_text); 1005 1006 static const struct snd_kcontrol_new max98090_stenl_mux = 1007 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 1008 1009 static const struct snd_kcontrol_new max98090_stenr_mux = 1010 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 1011 1012 /* Left speaker mixer switch */ 1013 static const struct 1014 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 1015 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1016 M98090_MIXSPL_DACL_SHIFT, 1, 0), 1017 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1018 M98090_MIXSPL_DACR_SHIFT, 1, 0), 1019 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 1020 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 1021 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 1022 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 1023 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 1024 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 1025 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 1026 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 1027 }; 1028 1029 /* Right speaker mixer switch */ 1030 static const struct 1031 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 1032 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1033 M98090_MIXSPR_DACL_SHIFT, 1, 0), 1034 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1035 M98090_MIXSPR_DACR_SHIFT, 1, 0), 1036 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 1037 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 1038 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 1039 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 1040 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 1041 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 1042 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 1043 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 1044 }; 1045 1046 /* Left headphone mixer switch */ 1047 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 1048 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 1049 M98090_MIXHPL_DACL_SHIFT, 1, 0), 1050 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 1051 M98090_MIXHPL_DACR_SHIFT, 1, 0), 1052 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 1053 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 1054 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 1055 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 1056 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 1057 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 1058 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 1059 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 1060 }; 1061 1062 /* Right headphone mixer switch */ 1063 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 1064 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1065 M98090_MIXHPR_DACL_SHIFT, 1, 0), 1066 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1067 M98090_MIXHPR_DACR_SHIFT, 1, 0), 1068 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 1069 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 1070 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 1071 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 1072 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 1073 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 1074 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 1075 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 1076 }; 1077 1078 /* Left receiver mixer switch */ 1079 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1080 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1081 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1082 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1083 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1084 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1085 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1086 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1087 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1088 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1089 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1090 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1091 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1092 }; 1093 1094 /* Right receiver mixer switch */ 1095 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1096 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1097 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1098 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1099 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1100 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1101 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1102 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1103 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1104 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1105 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1106 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1107 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1108 }; 1109 1110 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1111 1112 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, 1113 M98090_REG_LOUTR_MIXER, 1114 M98090_LINMOD_SHIFT, 1115 linmod_mux_text); 1116 1117 static const struct snd_kcontrol_new max98090_linmod_mux = 1118 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1119 1120 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1121 1122 /* 1123 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1124 */ 1125 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, 1126 M98090_REG_HP_CONTROL, 1127 M98090_MIXHPLSEL_SHIFT, 1128 mixhpsel_mux_text); 1129 1130 static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1131 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1132 1133 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, 1134 M98090_REG_HP_CONTROL, 1135 M98090_MIXHPRSEL_SHIFT, 1136 mixhpsel_mux_text); 1137 1138 static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1139 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1140 1141 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1142 1143 SND_SOC_DAPM_INPUT("MIC1"), 1144 SND_SOC_DAPM_INPUT("MIC2"), 1145 SND_SOC_DAPM_INPUT("DMICL"), 1146 SND_SOC_DAPM_INPUT("DMICR"), 1147 SND_SOC_DAPM_INPUT("IN1"), 1148 SND_SOC_DAPM_INPUT("IN2"), 1149 SND_SOC_DAPM_INPUT("IN3"), 1150 SND_SOC_DAPM_INPUT("IN4"), 1151 SND_SOC_DAPM_INPUT("IN5"), 1152 SND_SOC_DAPM_INPUT("IN6"), 1153 SND_SOC_DAPM_INPUT("IN12"), 1154 SND_SOC_DAPM_INPUT("IN34"), 1155 SND_SOC_DAPM_INPUT("IN56"), 1156 1157 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1158 M98090_MBEN_SHIFT, 0, NULL, 0), 1159 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1160 M98090_SHDNN_SHIFT, 0, NULL, 0), 1161 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1162 M98090_SDIEN_SHIFT, 0, NULL, 0), 1163 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1164 M98090_SDOEN_SHIFT, 0, NULL, 0), 1165 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1166 M98090_DIGMICL_SHIFT, 0, NULL, 0), 1167 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1168 M98090_DIGMICR_SHIFT, 0, NULL, 0), 1169 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1170 M98090_AHPF_SHIFT, 0, NULL, 0), 1171 1172 /* 1173 * Note: Sysclk and misc power supplies are taken care of by SHDN 1174 */ 1175 1176 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1177 0, 0, &max98090_mic1_mux), 1178 1179 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1180 0, 0, &max98090_mic2_mux), 1181 1182 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux), 1183 1184 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1185 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1186 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1187 1188 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1189 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1190 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1191 1192 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1193 &max98090_linea_mixer_controls[0], 1194 ARRAY_SIZE(max98090_linea_mixer_controls)), 1195 1196 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1197 &max98090_lineb_mixer_controls[0], 1198 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1199 1200 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1201 M98090_LINEAEN_SHIFT, 0, NULL, 0), 1202 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1203 M98090_LINEBEN_SHIFT, 0, NULL, 0), 1204 1205 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1206 &max98090_left_adc_mixer_controls[0], 1207 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1208 1209 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1210 &max98090_right_adc_mixer_controls[0], 1211 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1212 1213 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1214 M98090_ADLEN_SHIFT, 0), 1215 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1216 M98090_ADREN_SHIFT, 0), 1217 1218 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1219 SND_SOC_NOPM, 0, 0), 1220 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, 1221 SND_SOC_NOPM, 0, 0), 1222 1223 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1224 0, 0, &max98090_lbenl_mux), 1225 1226 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1227 0, 0, &max98090_lbenr_mux), 1228 1229 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1230 0, 0, &max98090_ltenl_mux), 1231 1232 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1233 0, 0, &max98090_ltenr_mux), 1234 1235 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1236 0, 0, &max98090_stenl_mux), 1237 1238 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1239 0, 0, &max98090_stenr_mux), 1240 1241 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1242 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1243 1244 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1245 M98090_DALEN_SHIFT, 0), 1246 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1247 M98090_DAREN_SHIFT, 0), 1248 1249 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1250 &max98090_left_hp_mixer_controls[0], 1251 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1252 1253 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1254 &max98090_right_hp_mixer_controls[0], 1255 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1256 1257 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1258 &max98090_left_speaker_mixer_controls[0], 1259 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1260 1261 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1262 &max98090_right_speaker_mixer_controls[0], 1263 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1264 1265 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1266 &max98090_left_rcv_mixer_controls[0], 1267 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1268 1269 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1270 &max98090_right_rcv_mixer_controls[0], 1271 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1272 1273 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER, 1274 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux), 1275 1276 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL, 1277 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux), 1278 1279 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL, 1280 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux), 1281 1282 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1283 M98090_HPLEN_SHIFT, 0, NULL, 0), 1284 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1285 M98090_HPREN_SHIFT, 0, NULL, 0), 1286 1287 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1288 M98090_SPLEN_SHIFT, 0, NULL, 0), 1289 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1290 M98090_SPREN_SHIFT, 0, NULL, 0), 1291 1292 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1293 M98090_RCVLEN_SHIFT, 0, NULL, 0), 1294 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1295 M98090_RCVREN_SHIFT, 0, NULL, 0), 1296 1297 SND_SOC_DAPM_OUTPUT("HPL"), 1298 SND_SOC_DAPM_OUTPUT("HPR"), 1299 SND_SOC_DAPM_OUTPUT("SPKL"), 1300 SND_SOC_DAPM_OUTPUT("SPKR"), 1301 SND_SOC_DAPM_OUTPUT("RCVL"), 1302 SND_SOC_DAPM_OUTPUT("RCVR"), 1303 }; 1304 1305 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1306 1307 SND_SOC_DAPM_INPUT("DMIC3"), 1308 SND_SOC_DAPM_INPUT("DMIC4"), 1309 1310 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1311 M98090_DIGMIC3_SHIFT, 0, NULL, 0), 1312 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1313 M98090_DIGMIC4_SHIFT, 0, NULL, 0), 1314 }; 1315 1316 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1317 1318 {"MIC1 Input", NULL, "MIC1"}, 1319 {"MIC2 Input", NULL, "MIC2"}, 1320 1321 {"DMICL", NULL, "DMICL_ENA"}, 1322 {"DMICR", NULL, "DMICR_ENA"}, 1323 {"DMICL", NULL, "AHPF"}, 1324 {"DMICR", NULL, "AHPF"}, 1325 1326 /* MIC1 input mux */ 1327 {"MIC1 Mux", "IN12", "IN12"}, 1328 {"MIC1 Mux", "IN56", "IN56"}, 1329 1330 /* MIC2 input mux */ 1331 {"MIC2 Mux", "IN34", "IN34"}, 1332 {"MIC2 Mux", "IN56", "IN56"}, 1333 1334 {"MIC1 Input", NULL, "MIC1 Mux"}, 1335 {"MIC2 Input", NULL, "MIC2 Mux"}, 1336 1337 /* Left ADC input mixer */ 1338 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1339 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1340 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1341 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1342 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1343 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1344 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1345 1346 /* Right ADC input mixer */ 1347 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1348 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1349 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1350 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1351 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1352 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1353 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1354 1355 /* Line A input mixer */ 1356 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1357 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1358 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1359 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1360 1361 /* Line B input mixer */ 1362 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1363 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1364 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1365 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1366 1367 {"LINEA Input", NULL, "LINEA Mixer"}, 1368 {"LINEB Input", NULL, "LINEB Mixer"}, 1369 1370 /* Inputs */ 1371 {"ADCL", NULL, "Left ADC Mixer"}, 1372 {"ADCR", NULL, "Right ADC Mixer"}, 1373 {"ADCL", NULL, "SHDN"}, 1374 {"ADCR", NULL, "SHDN"}, 1375 1376 {"DMIC Mux", "ADC", "ADCL"}, 1377 {"DMIC Mux", "ADC", "ADCR"}, 1378 {"DMIC Mux", "DMIC", "DMICL"}, 1379 {"DMIC Mux", "DMIC", "DMICR"}, 1380 1381 {"LBENL Mux", "Normal", "DMIC Mux"}, 1382 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1383 {"LBENR Mux", "Normal", "DMIC Mux"}, 1384 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1385 1386 {"AIFOUTL", NULL, "LBENL Mux"}, 1387 {"AIFOUTR", NULL, "LBENR Mux"}, 1388 {"AIFOUTL", NULL, "SHDN"}, 1389 {"AIFOUTR", NULL, "SHDN"}, 1390 {"AIFOUTL", NULL, "SDOEN"}, 1391 {"AIFOUTR", NULL, "SDOEN"}, 1392 1393 {"LTENL Mux", "Normal", "AIFINL"}, 1394 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1395 {"LTENR Mux", "Normal", "AIFINR"}, 1396 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1397 1398 {"DACL", NULL, "LTENL Mux"}, 1399 {"DACR", NULL, "LTENR Mux"}, 1400 1401 {"STENL Mux", "Sidetone Left", "ADCL"}, 1402 {"STENL Mux", "Sidetone Left", "DMICL"}, 1403 {"STENR Mux", "Sidetone Right", "ADCR"}, 1404 {"STENR Mux", "Sidetone Right", "DMICR"}, 1405 {"DACL", "NULL", "STENL Mux"}, 1406 {"DACR", "NULL", "STENL Mux"}, 1407 1408 {"AIFINL", NULL, "SHDN"}, 1409 {"AIFINR", NULL, "SHDN"}, 1410 {"AIFINL", NULL, "SDIEN"}, 1411 {"AIFINR", NULL, "SDIEN"}, 1412 {"DACL", NULL, "SHDN"}, 1413 {"DACR", NULL, "SHDN"}, 1414 1415 /* Left headphone output mixer */ 1416 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1417 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1418 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1419 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1420 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1421 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1422 1423 /* Right headphone output mixer */ 1424 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1425 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1426 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1427 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1428 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1429 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1430 1431 /* Left speaker output mixer */ 1432 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1433 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1434 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1435 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1436 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1437 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1438 1439 /* Right speaker output mixer */ 1440 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1441 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1442 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1443 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1444 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1445 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1446 1447 /* Left Receiver output mixer */ 1448 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1449 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1450 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1451 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1452 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1453 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1454 1455 /* Right Receiver output mixer */ 1456 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1457 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1458 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1459 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1460 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1461 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1462 1463 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1464 1465 /* 1466 * Disable this for lowest power if bypassing 1467 * the DAC with an analog signal 1468 */ 1469 {"HP Left Out", NULL, "DACL"}, 1470 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1471 1472 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1473 1474 /* 1475 * Disable this for lowest power if bypassing 1476 * the DAC with an analog signal 1477 */ 1478 {"HP Right Out", NULL, "DACR"}, 1479 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1480 1481 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1482 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1483 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1484 1485 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1486 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1487 {"RCV Right Out", NULL, "LINMOD Mux"}, 1488 1489 {"HPL", NULL, "HP Left Out"}, 1490 {"HPR", NULL, "HP Right Out"}, 1491 {"SPKL", NULL, "SPK Left Out"}, 1492 {"SPKR", NULL, "SPK Right Out"}, 1493 {"RCVL", NULL, "RCV Left Out"}, 1494 {"RCVR", NULL, "RCV Right Out"}, 1495 1496 }; 1497 1498 static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1499 1500 /* DMIC inputs */ 1501 {"DMIC3", NULL, "DMIC3_ENA"}, 1502 {"DMIC4", NULL, "DMIC4_ENA"}, 1503 {"DMIC3", NULL, "AHPF"}, 1504 {"DMIC4", NULL, "AHPF"}, 1505 1506 }; 1507 1508 static int max98090_add_widgets(struct snd_soc_codec *codec) 1509 { 1510 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1511 struct snd_soc_dapm_context *dapm = &codec->dapm; 1512 1513 snd_soc_add_codec_controls(codec, max98090_snd_controls, 1514 ARRAY_SIZE(max98090_snd_controls)); 1515 1516 if (max98090->devtype == MAX98091) { 1517 snd_soc_add_codec_controls(codec, max98091_snd_controls, 1518 ARRAY_SIZE(max98091_snd_controls)); 1519 } 1520 1521 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1522 ARRAY_SIZE(max98090_dapm_widgets)); 1523 1524 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1525 ARRAY_SIZE(max98090_dapm_routes)); 1526 1527 if (max98090->devtype == MAX98091) { 1528 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1529 ARRAY_SIZE(max98091_dapm_widgets)); 1530 1531 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1532 ARRAY_SIZE(max98091_dapm_routes)); 1533 1534 } 1535 1536 return 0; 1537 } 1538 1539 static const int pclk_rates[] = { 1540 12000000, 12000000, 13000000, 13000000, 1541 16000000, 16000000, 19200000, 19200000 1542 }; 1543 1544 static const int lrclk_rates[] = { 1545 8000, 16000, 8000, 16000, 1546 8000, 16000, 8000, 16000 1547 }; 1548 1549 static const int user_pclk_rates[] = { 1550 13000000, 13000000 1551 }; 1552 1553 static const int user_lrclk_rates[] = { 1554 44100, 48000 1555 }; 1556 1557 static const unsigned long long ni_value[] = { 1558 3528, 768 1559 }; 1560 1561 static const unsigned long long mi_value[] = { 1562 8125, 1625 1563 }; 1564 1565 static void max98090_configure_bclk(struct snd_soc_codec *codec) 1566 { 1567 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1568 unsigned long long ni; 1569 int i; 1570 1571 if (!max98090->sysclk) { 1572 dev_err(codec->dev, "No SYSCLK configured\n"); 1573 return; 1574 } 1575 1576 if (!max98090->bclk || !max98090->lrclk) { 1577 dev_err(codec->dev, "No audio clocks configured\n"); 1578 return; 1579 } 1580 1581 /* Skip configuration when operating as slave */ 1582 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) & 1583 M98090_MAS_MASK)) { 1584 return; 1585 } 1586 1587 /* Check for supported PCLK to LRCLK ratios */ 1588 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1589 if ((pclk_rates[i] == max98090->sysclk) && 1590 (lrclk_rates[i] == max98090->lrclk)) { 1591 dev_dbg(codec->dev, 1592 "Found supported PCLK to LRCLK rates 0x%x\n", 1593 i + 0x8); 1594 1595 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1596 M98090_FREQ_MASK, 1597 (i + 0x8) << M98090_FREQ_SHIFT); 1598 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1599 M98090_USE_M1_MASK, 0); 1600 return; 1601 } 1602 } 1603 1604 /* Check for user calculated MI and NI ratios */ 1605 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1606 if ((user_pclk_rates[i] == max98090->sysclk) && 1607 (user_lrclk_rates[i] == max98090->lrclk)) { 1608 dev_dbg(codec->dev, 1609 "Found user supported PCLK to LRCLK rates\n"); 1610 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n", 1611 i, ni_value[i], mi_value[i]); 1612 1613 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1614 M98090_FREQ_MASK, 0); 1615 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1616 M98090_USE_M1_MASK, 1617 1 << M98090_USE_M1_SHIFT); 1618 1619 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1620 (ni_value[i] >> 8) & 0x7F); 1621 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, 1622 ni_value[i] & 0xFF); 1623 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB, 1624 (mi_value[i] >> 8) & 0x7F); 1625 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB, 1626 mi_value[i] & 0xFF); 1627 1628 return; 1629 } 1630 } 1631 1632 /* 1633 * Calculate based on MI = 65536 (not as good as either method above) 1634 */ 1635 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1636 M98090_FREQ_MASK, 0); 1637 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1638 M98090_USE_M1_MASK, 0); 1639 1640 /* 1641 * Configure NI when operating as master 1642 * Note: There is a small, but significant audio quality improvement 1643 * by calculating ni and mi. 1644 */ 1645 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1646 * (unsigned long long int)max98090->lrclk; 1647 do_div(ni, (unsigned long long int)max98090->sysclk); 1648 dev_info(codec->dev, "No better method found\n"); 1649 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni); 1650 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1651 (ni >> 8) & 0x7F); 1652 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1653 } 1654 1655 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1656 unsigned int fmt) 1657 { 1658 struct snd_soc_codec *codec = codec_dai->codec; 1659 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1660 struct max98090_cdata *cdata; 1661 u8 regval; 1662 1663 max98090->dai_fmt = fmt; 1664 cdata = &max98090->dai[0]; 1665 1666 if (fmt != cdata->fmt) { 1667 cdata->fmt = fmt; 1668 1669 regval = 0; 1670 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1671 case SND_SOC_DAIFMT_CBS_CFS: 1672 /* Set to slave mode PLL - MAS mode off */ 1673 snd_soc_write(codec, 1674 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1675 snd_soc_write(codec, 1676 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1677 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1678 M98090_USE_M1_MASK, 0); 1679 max98090->master = false; 1680 break; 1681 case SND_SOC_DAIFMT_CBM_CFM: 1682 /* Set to master mode */ 1683 if (max98090->tdm_slots == 4) { 1684 /* TDM */ 1685 regval |= M98090_MAS_MASK | 1686 M98090_BSEL_64; 1687 } else if (max98090->tdm_slots == 3) { 1688 /* TDM */ 1689 regval |= M98090_MAS_MASK | 1690 M98090_BSEL_48; 1691 } else { 1692 /* Few TDM slots, or No TDM */ 1693 regval |= M98090_MAS_MASK | 1694 M98090_BSEL_32; 1695 } 1696 max98090->master = true; 1697 break; 1698 case SND_SOC_DAIFMT_CBS_CFM: 1699 case SND_SOC_DAIFMT_CBM_CFS: 1700 default: 1701 dev_err(codec->dev, "DAI clock mode unsupported"); 1702 return -EINVAL; 1703 } 1704 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval); 1705 1706 regval = 0; 1707 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1708 case SND_SOC_DAIFMT_I2S: 1709 regval |= M98090_DLY_MASK; 1710 break; 1711 case SND_SOC_DAIFMT_LEFT_J: 1712 break; 1713 case SND_SOC_DAIFMT_RIGHT_J: 1714 regval |= M98090_RJ_MASK; 1715 break; 1716 case SND_SOC_DAIFMT_DSP_A: 1717 /* Not supported mode */ 1718 default: 1719 dev_err(codec->dev, "DAI format unsupported"); 1720 return -EINVAL; 1721 } 1722 1723 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1724 case SND_SOC_DAIFMT_NB_NF: 1725 break; 1726 case SND_SOC_DAIFMT_NB_IF: 1727 regval |= M98090_WCI_MASK; 1728 break; 1729 case SND_SOC_DAIFMT_IB_NF: 1730 regval |= M98090_BCI_MASK; 1731 break; 1732 case SND_SOC_DAIFMT_IB_IF: 1733 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1734 break; 1735 default: 1736 dev_err(codec->dev, "DAI invert mode unsupported"); 1737 return -EINVAL; 1738 } 1739 1740 /* 1741 * This accommodates an inverted logic in the MAX98090 chip 1742 * for Bit Clock Invert (BCI). The inverted logic is only 1743 * seen for the case of TDM mode. The remaining cases have 1744 * normal logic. 1745 */ 1746 if (max98090->tdm_slots > 1) 1747 regval ^= M98090_BCI_MASK; 1748 1749 snd_soc_write(codec, 1750 M98090_REG_INTERFACE_FORMAT, regval); 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1757 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1758 { 1759 struct snd_soc_codec *codec = codec_dai->codec; 1760 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1761 struct max98090_cdata *cdata; 1762 cdata = &max98090->dai[0]; 1763 1764 if (slots < 0 || slots > 4) 1765 return -EINVAL; 1766 1767 max98090->tdm_slots = slots; 1768 max98090->tdm_width = slot_width; 1769 1770 if (max98090->tdm_slots > 1) { 1771 /* SLOTL SLOTR SLOTDLY */ 1772 snd_soc_write(codec, M98090_REG_TDM_FORMAT, 1773 0 << M98090_TDM_SLOTL_SHIFT | 1774 1 << M98090_TDM_SLOTR_SHIFT | 1775 0 << M98090_TDM_SLOTDLY_SHIFT); 1776 1777 /* FSW TDM */ 1778 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL, 1779 M98090_TDM_MASK, 1780 M98090_TDM_MASK); 1781 } 1782 1783 /* 1784 * Normally advisable to set TDM first, but this permits either order 1785 */ 1786 cdata->fmt = 0; 1787 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); 1788 1789 return 0; 1790 } 1791 1792 static int max98090_set_bias_level(struct snd_soc_codec *codec, 1793 enum snd_soc_bias_level level) 1794 { 1795 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1796 int ret; 1797 1798 switch (level) { 1799 case SND_SOC_BIAS_ON: 1800 break; 1801 1802 case SND_SOC_BIAS_PREPARE: 1803 break; 1804 1805 case SND_SOC_BIAS_STANDBY: 1806 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1807 ret = regcache_sync(max98090->regmap); 1808 if (ret != 0) { 1809 dev_err(codec->dev, 1810 "Failed to sync cache: %d\n", ret); 1811 return ret; 1812 } 1813 } 1814 break; 1815 1816 case SND_SOC_BIAS_OFF: 1817 /* Set internal pull-up to lowest power mode */ 1818 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1819 M98090_JDWK_MASK, M98090_JDWK_MASK); 1820 regcache_mark_dirty(max98090->regmap); 1821 break; 1822 } 1823 codec->dapm.bias_level = level; 1824 return 0; 1825 } 1826 1827 static const int comp_pclk_rates[] = { 1828 11289600, 12288000, 12000000, 13000000, 19200000 1829 }; 1830 1831 static const int dmic_micclk[] = { 1832 2, 2, 2, 2, 4, 2 1833 }; 1834 1835 static const int comp_lrclk_rates[] = { 1836 8000, 16000, 32000, 44100, 48000, 96000 1837 }; 1838 1839 static const int dmic_comp[6][6] = { 1840 {7, 8, 3, 3, 3, 3}, 1841 {7, 8, 3, 3, 3, 3}, 1842 {7, 8, 3, 3, 3, 3}, 1843 {7, 8, 3, 1, 1, 1}, 1844 {7, 8, 3, 1, 2, 2}, 1845 {7, 8, 3, 3, 3, 3} 1846 }; 1847 1848 static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1849 struct snd_pcm_hw_params *params, 1850 struct snd_soc_dai *dai) 1851 { 1852 struct snd_soc_codec *codec = dai->codec; 1853 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1854 struct max98090_cdata *cdata; 1855 int i, j; 1856 1857 cdata = &max98090->dai[0]; 1858 max98090->bclk = snd_soc_params_to_bclk(params); 1859 if (params_channels(params) == 1) 1860 max98090->bclk *= 2; 1861 1862 max98090->lrclk = params_rate(params); 1863 1864 switch (params_width(params)) { 1865 case 16: 1866 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT, 1867 M98090_WS_MASK, 0); 1868 break; 1869 default: 1870 return -EINVAL; 1871 } 1872 1873 if (max98090->master) 1874 max98090_configure_bclk(codec); 1875 1876 cdata->rate = max98090->lrclk; 1877 1878 /* Update filter mode */ 1879 if (max98090->lrclk < 24000) 1880 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1881 M98090_MODE_MASK, 0); 1882 else 1883 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1884 M98090_MODE_MASK, M98090_MODE_MASK); 1885 1886 /* Update sample rate mode */ 1887 if (max98090->lrclk < 50000) 1888 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1889 M98090_DHF_MASK, 0); 1890 else 1891 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1892 M98090_DHF_MASK, M98090_DHF_MASK); 1893 1894 /* Check for supported PCLK to LRCLK ratios */ 1895 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) { 1896 if (comp_pclk_rates[j] == max98090->sysclk) { 1897 break; 1898 } 1899 } 1900 1901 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 1902 if (max98090->lrclk <= (comp_lrclk_rates[i] + 1903 comp_lrclk_rates[i + 1]) / 2) { 1904 break; 1905 } 1906 } 1907 1908 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE, 1909 M98090_MICCLK_MASK, 1910 dmic_micclk[j] << M98090_MICCLK_SHIFT); 1911 1912 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG, 1913 M98090_DMIC_COMP_MASK, 1914 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT); 1915 1916 return 0; 1917 } 1918 1919 /* 1920 * PLL / Sysclk 1921 */ 1922 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1923 int clk_id, unsigned int freq, int dir) 1924 { 1925 struct snd_soc_codec *codec = dai->codec; 1926 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1927 1928 /* Requested clock frequency is already setup */ 1929 if (freq == max98090->sysclk) 1930 return 0; 1931 1932 /* Setup clocks for slave mode, and using the PLL 1933 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1934 * 0x02 (when master clk is 20MHz to 40MHz).. 1935 * 0x03 (when master clk is 40MHz to 60MHz).. 1936 */ 1937 if ((freq >= 10000000) && (freq < 20000000)) { 1938 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1939 M98090_PSCLK_DIV1); 1940 } else if ((freq >= 20000000) && (freq < 40000000)) { 1941 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1942 M98090_PSCLK_DIV2); 1943 } else if ((freq >= 40000000) && (freq < 60000000)) { 1944 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1945 M98090_PSCLK_DIV4); 1946 } else { 1947 dev_err(codec->dev, "Invalid master clock frequency\n"); 1948 return -EINVAL; 1949 } 1950 1951 max98090->sysclk = freq; 1952 1953 return 0; 1954 } 1955 1956 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1957 { 1958 struct snd_soc_codec *codec = codec_dai->codec; 1959 int regval; 1960 1961 regval = mute ? M98090_DVM_MASK : 0; 1962 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL, 1963 M98090_DVM_MASK, regval); 1964 1965 return 0; 1966 } 1967 1968 static void max98090_jack_work(struct work_struct *work) 1969 { 1970 struct max98090_priv *max98090 = container_of(work, 1971 struct max98090_priv, 1972 jack_work.work); 1973 struct snd_soc_codec *codec = max98090->codec; 1974 struct snd_soc_dapm_context *dapm = &codec->dapm; 1975 int status = 0; 1976 int reg; 1977 1978 /* Read a second time */ 1979 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 1980 1981 /* Strong pull up allows mic detection */ 1982 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1983 M98090_JDWK_MASK, 0); 1984 1985 msleep(50); 1986 1987 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1988 1989 /* Weak pull up allows only insertion detection */ 1990 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1991 M98090_JDWK_MASK, M98090_JDWK_MASK); 1992 } else { 1993 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1994 } 1995 1996 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1997 1998 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 1999 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 2000 dev_dbg(codec->dev, "No Headset Detected\n"); 2001 2002 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2003 2004 status |= 0; 2005 2006 break; 2007 2008 case 0: 2009 if (max98090->jack_state == 2010 M98090_JACK_STATE_HEADSET) { 2011 2012 dev_dbg(codec->dev, 2013 "Headset Button Down Detected\n"); 2014 2015 /* 2016 * max98090_headset_button_event(codec) 2017 * could be defined, then called here. 2018 */ 2019 2020 status |= SND_JACK_HEADSET; 2021 status |= SND_JACK_BTN_0; 2022 2023 break; 2024 } 2025 2026 /* Line is reported as Headphone */ 2027 /* Nokia Headset is reported as Headphone */ 2028 /* Mono Headphone is reported as Headphone */ 2029 dev_dbg(codec->dev, "Headphone Detected\n"); 2030 2031 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2032 2033 status |= SND_JACK_HEADPHONE; 2034 2035 break; 2036 2037 case M98090_JKSNS_MASK: 2038 dev_dbg(codec->dev, "Headset Detected\n"); 2039 2040 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2041 2042 status |= SND_JACK_HEADSET; 2043 2044 break; 2045 2046 default: 2047 dev_dbg(codec->dev, "Unrecognized Jack Status\n"); 2048 break; 2049 } 2050 2051 snd_soc_jack_report(max98090->jack, status, 2052 SND_JACK_HEADSET | SND_JACK_BTN_0); 2053 2054 snd_soc_dapm_sync(dapm); 2055 } 2056 2057 static irqreturn_t max98090_interrupt(int irq, void *data) 2058 { 2059 struct snd_soc_codec *codec = data; 2060 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2061 int ret; 2062 unsigned int mask; 2063 unsigned int active; 2064 2065 dev_dbg(codec->dev, "***** max98090_interrupt *****\n"); 2066 2067 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2068 2069 if (ret != 0) { 2070 dev_err(codec->dev, 2071 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2072 ret); 2073 return IRQ_NONE; 2074 } 2075 2076 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2077 2078 if (ret != 0) { 2079 dev_err(codec->dev, 2080 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2081 ret); 2082 return IRQ_NONE; 2083 } 2084 2085 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2086 active, mask, active & mask); 2087 2088 active &= mask; 2089 2090 if (!active) 2091 return IRQ_NONE; 2092 2093 if (active & M98090_CLD_MASK) 2094 dev_err(codec->dev, "M98090_CLD_MASK\n"); 2095 2096 if (active & M98090_SLD_MASK) 2097 dev_dbg(codec->dev, "M98090_SLD_MASK\n"); 2098 2099 if (active & M98090_ULK_MASK) 2100 dev_err(codec->dev, "M98090_ULK_MASK\n"); 2101 2102 if (active & M98090_JDET_MASK) { 2103 dev_dbg(codec->dev, "M98090_JDET_MASK\n"); 2104 2105 pm_wakeup_event(codec->dev, 100); 2106 2107 queue_delayed_work(system_power_efficient_wq, 2108 &max98090->jack_work, 2109 msecs_to_jiffies(100)); 2110 } 2111 2112 if (active & M98090_DRCACT_MASK) 2113 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n"); 2114 2115 if (active & M98090_DRCCLP_MASK) 2116 dev_err(codec->dev, "M98090_DRCCLP_MASK\n"); 2117 2118 return IRQ_HANDLED; 2119 } 2120 2121 /** 2122 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2123 * 2124 * @codec: MAX98090 codec 2125 * @jack: jack to report detection events on 2126 * 2127 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2128 * being used to bring out signals to the processor then only platform 2129 * data configuration is needed for MAX98090 and processor GPIOs should 2130 * be configured using snd_soc_jack_add_gpios() instead. 2131 * 2132 * If no jack is supplied detection will be disabled. 2133 */ 2134 int max98090_mic_detect(struct snd_soc_codec *codec, 2135 struct snd_soc_jack *jack) 2136 { 2137 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2138 2139 dev_dbg(codec->dev, "max98090_mic_detect\n"); 2140 2141 max98090->jack = jack; 2142 if (jack) { 2143 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2144 M98090_IJDET_MASK, 2145 1 << M98090_IJDET_SHIFT); 2146 } else { 2147 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2148 M98090_IJDET_MASK, 2149 0); 2150 } 2151 2152 /* Send an initial empty report */ 2153 snd_soc_jack_report(max98090->jack, 0, 2154 SND_JACK_HEADSET | SND_JACK_BTN_0); 2155 2156 queue_delayed_work(system_power_efficient_wq, 2157 &max98090->jack_work, 2158 msecs_to_jiffies(100)); 2159 2160 return 0; 2161 } 2162 EXPORT_SYMBOL_GPL(max98090_mic_detect); 2163 2164 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2165 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2166 2167 static struct snd_soc_dai_ops max98090_dai_ops = { 2168 .set_sysclk = max98090_dai_set_sysclk, 2169 .set_fmt = max98090_dai_set_fmt, 2170 .set_tdm_slot = max98090_set_tdm_slot, 2171 .hw_params = max98090_dai_hw_params, 2172 .digital_mute = max98090_dai_digital_mute, 2173 }; 2174 2175 static struct snd_soc_dai_driver max98090_dai[] = { 2176 { 2177 .name = "HiFi", 2178 .playback = { 2179 .stream_name = "HiFi Playback", 2180 .channels_min = 2, 2181 .channels_max = 2, 2182 .rates = MAX98090_RATES, 2183 .formats = MAX98090_FORMATS, 2184 }, 2185 .capture = { 2186 .stream_name = "HiFi Capture", 2187 .channels_min = 1, 2188 .channels_max = 2, 2189 .rates = MAX98090_RATES, 2190 .formats = MAX98090_FORMATS, 2191 }, 2192 .ops = &max98090_dai_ops, 2193 } 2194 }; 2195 2196 static void max98090_handle_pdata(struct snd_soc_codec *codec) 2197 { 2198 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2199 struct max98090_pdata *pdata = max98090->pdata; 2200 2201 if (!pdata) { 2202 dev_err(codec->dev, "No platform data\n"); 2203 return; 2204 } 2205 2206 } 2207 2208 static int max98090_probe(struct snd_soc_codec *codec) 2209 { 2210 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2211 struct max98090_cdata *cdata; 2212 int ret = 0; 2213 2214 dev_dbg(codec->dev, "max98090_probe\n"); 2215 2216 max98090->codec = codec; 2217 2218 /* Reset the codec, the DSP core, and disable all interrupts */ 2219 max98090_reset(max98090); 2220 2221 /* Initialize private data */ 2222 2223 max98090->sysclk = (unsigned)-1; 2224 max98090->master = false; 2225 2226 cdata = &max98090->dai[0]; 2227 cdata->rate = (unsigned)-1; 2228 cdata->fmt = (unsigned)-1; 2229 2230 max98090->lin_state = 0; 2231 max98090->pa1en = 0; 2232 max98090->pa2en = 0; 2233 max98090->extmic_mux = 0; 2234 2235 ret = snd_soc_read(codec, M98090_REG_REVISION_ID); 2236 if (ret < 0) { 2237 dev_err(codec->dev, "Failed to read device revision: %d\n", 2238 ret); 2239 goto err_access; 2240 } 2241 2242 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2243 max98090->devtype = MAX98090; 2244 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret); 2245 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2246 max98090->devtype = MAX98091; 2247 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret); 2248 } else { 2249 max98090->devtype = MAX98090; 2250 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret); 2251 } 2252 2253 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2254 2255 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2256 2257 /* Enable jack detection */ 2258 snd_soc_write(codec, M98090_REG_JACK_DETECT, 2259 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2260 2261 /* Register for interrupts */ 2262 dev_dbg(codec->dev, "irq = %d\n", max98090->irq); 2263 2264 ret = request_threaded_irq(max98090->irq, NULL, 2265 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2266 "max98090_interrupt", codec); 2267 if (ret < 0) { 2268 dev_err(codec->dev, "request_irq failed: %d\n", 2269 ret); 2270 } 2271 2272 /* 2273 * Clear any old interrupts. 2274 * An old interrupt ocurring prior to installing the ISR 2275 * can keep a new interrupt from generating a trigger. 2276 */ 2277 snd_soc_read(codec, M98090_REG_DEVICE_STATUS); 2278 2279 /* High Performance is default */ 2280 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2281 M98090_DACHP_MASK, 2282 1 << M98090_DACHP_SHIFT); 2283 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2284 M98090_PERFMODE_MASK, 2285 0 << M98090_PERFMODE_SHIFT); 2286 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL, 2287 M98090_ADCHP_MASK, 2288 1 << M98090_ADCHP_SHIFT); 2289 2290 /* Turn on VCM bandgap reference */ 2291 snd_soc_write(codec, M98090_REG_BIAS_CONTROL, 2292 M98090_VCM_MODE_MASK); 2293 2294 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE, 2295 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8); 2296 2297 max98090_handle_pdata(codec); 2298 2299 max98090_add_widgets(codec); 2300 2301 err_access: 2302 return ret; 2303 } 2304 2305 static int max98090_remove(struct snd_soc_codec *codec) 2306 { 2307 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2308 2309 cancel_delayed_work_sync(&max98090->jack_work); 2310 2311 return 0; 2312 } 2313 2314 static struct snd_soc_codec_driver soc_codec_dev_max98090 = { 2315 .probe = max98090_probe, 2316 .remove = max98090_remove, 2317 .set_bias_level = max98090_set_bias_level, 2318 }; 2319 2320 static const struct regmap_config max98090_regmap = { 2321 .reg_bits = 8, 2322 .val_bits = 8, 2323 2324 .max_register = MAX98090_MAX_REGISTER, 2325 .reg_defaults = max98090_reg, 2326 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2327 .volatile_reg = max98090_volatile_register, 2328 .readable_reg = max98090_readable_register, 2329 .cache_type = REGCACHE_RBTREE, 2330 }; 2331 2332 static int max98090_i2c_probe(struct i2c_client *i2c, 2333 const struct i2c_device_id *i2c_id) 2334 { 2335 struct max98090_priv *max98090; 2336 const struct acpi_device_id *acpi_id; 2337 kernel_ulong_t driver_data = 0; 2338 int ret; 2339 2340 pr_debug("max98090_i2c_probe\n"); 2341 2342 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2343 GFP_KERNEL); 2344 if (max98090 == NULL) 2345 return -ENOMEM; 2346 2347 if (ACPI_HANDLE(&i2c->dev)) { 2348 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, 2349 &i2c->dev); 2350 if (!acpi_id) { 2351 dev_err(&i2c->dev, "No driver data\n"); 2352 return -EINVAL; 2353 } 2354 driver_data = acpi_id->driver_data; 2355 } else if (i2c_id) { 2356 driver_data = i2c_id->driver_data; 2357 } 2358 2359 max98090->devtype = driver_data; 2360 i2c_set_clientdata(i2c, max98090); 2361 max98090->pdata = i2c->dev.platform_data; 2362 max98090->irq = i2c->irq; 2363 2364 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2365 if (IS_ERR(max98090->regmap)) { 2366 ret = PTR_ERR(max98090->regmap); 2367 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2368 goto err_enable; 2369 } 2370 2371 ret = snd_soc_register_codec(&i2c->dev, 2372 &soc_codec_dev_max98090, max98090_dai, 2373 ARRAY_SIZE(max98090_dai)); 2374 err_enable: 2375 return ret; 2376 } 2377 2378 static int max98090_i2c_remove(struct i2c_client *client) 2379 { 2380 snd_soc_unregister_codec(&client->dev); 2381 return 0; 2382 } 2383 2384 #ifdef CONFIG_PM_RUNTIME 2385 static int max98090_runtime_resume(struct device *dev) 2386 { 2387 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2388 2389 regcache_cache_only(max98090->regmap, false); 2390 2391 max98090_reset(max98090); 2392 2393 regcache_sync(max98090->regmap); 2394 2395 return 0; 2396 } 2397 2398 static int max98090_runtime_suspend(struct device *dev) 2399 { 2400 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2401 2402 regcache_cache_only(max98090->regmap, true); 2403 2404 return 0; 2405 } 2406 #endif 2407 2408 #ifdef CONFIG_PM 2409 static int max98090_resume(struct device *dev) 2410 { 2411 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2412 unsigned int status; 2413 2414 regcache_mark_dirty(max98090->regmap); 2415 2416 max98090_reset(max98090); 2417 2418 /* clear IRQ status */ 2419 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2420 2421 regcache_sync(max98090->regmap); 2422 2423 return 0; 2424 } 2425 2426 static int max98090_suspend(struct device *dev) 2427 { 2428 return 0; 2429 } 2430 #endif 2431 2432 static const struct dev_pm_ops max98090_pm = { 2433 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2434 max98090_runtime_resume, NULL) 2435 SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume) 2436 }; 2437 2438 static const struct i2c_device_id max98090_i2c_id[] = { 2439 { "max98090", MAX98090 }, 2440 { } 2441 }; 2442 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2443 2444 static const struct of_device_id max98090_of_match[] = { 2445 { .compatible = "maxim,max98090", }, 2446 { } 2447 }; 2448 MODULE_DEVICE_TABLE(of, max98090_of_match); 2449 2450 #ifdef CONFIG_ACPI 2451 static struct acpi_device_id max98090_acpi_match[] = { 2452 { "193C9890", MAX98090 }, 2453 { } 2454 }; 2455 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); 2456 #endif 2457 2458 static struct i2c_driver max98090_i2c_driver = { 2459 .driver = { 2460 .name = "max98090", 2461 .owner = THIS_MODULE, 2462 .pm = &max98090_pm, 2463 .of_match_table = of_match_ptr(max98090_of_match), 2464 .acpi_match_table = ACPI_PTR(max98090_acpi_match), 2465 }, 2466 .probe = max98090_i2c_probe, 2467 .remove = max98090_i2c_remove, 2468 .id_table = max98090_i2c_id, 2469 }; 2470 2471 module_i2c_driver(max98090_i2c_driver); 2472 2473 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2474 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2475 MODULE_LICENSE("GPL"); 2476